target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "sysemu/kvm.h"
  26
  27 /*****************************************************************************/
  28 /* Exceptions processing helpers */
  29
  30 QEMU_NORETURN
  31 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  32                                 int error_code)
  33 {
  34     do_raise_exception_err(env, exception, error_code, 0);
  35 }
  36
  37 QEMU_NORETURN
  38 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  39 {
  40     do_raise_exception(env, exception, GETPC());
  41 }
  42
  43 QEMU_NORETURN void helper_raise_exception_debug(CPUMIPSState *env)
  44 {
  45     do_raise_exception(env, EXCP_DEBUG, 0);
  46 }
  47
  48 static QEMU_NORETURN
  49 void raise_exception(CPUMIPSState *env, uint32_t exception)
  50 {
  51     do_raise_exception(env, exception, 0);
  52 }
  53
  54 #if defined(CONFIG_USER_ONLY)
  55 #define HELPER_LD(name, insn, type)                                     \
  56 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  57                              int mem_idx, uintptr_t retaddr)            \
  58 {                                                                       \
  59     return (type) cpu_##insn##_data_ra(env, addr, retaddr);             \
  60 }
  61 #else
  62 #define HELPER_LD(name, insn, type)                                     \
  63 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  64                              int mem_idx, uintptr_t retaddr)            \
  65 {                                                                       \
  66     switch (mem_idx)                                                    \
  67     {                                                                   \
  68     case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr);   \
  69     case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr);    \
  70     default:                                                            \
  71     case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr);     \
  72     }                                                                   \
  73 }
  74 #endif
  75 HELPER_LD(lw, ldl, int32_t)
  76 #if defined(TARGET_MIPS64)
  77 HELPER_LD(ld, ldq, int64_t)
  78 #endif
  79 #undef HELPER_LD
  80
  81 #if defined(CONFIG_USER_ONLY)
  82 #define HELPER_ST(name, insn, type)                                     \
  83 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  84                              type val, int mem_idx, uintptr_t retaddr)  \
  85 {                                                                       \
  86     cpu_##insn##_data_ra(env, addr, val, retaddr);                      \
  87 }
  88 #else
  89 #define HELPER_ST(name, insn, type)                                     \
  90 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  91                              type val, int mem_idx, uintptr_t retaddr)  \
  92 {                                                                       \
  93     switch (mem_idx)                                                    \
  94     {                                                                   \
  95     case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break;     \
  96     case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break;      \
  97     default:                                                            \
  98     case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break;       \
  99     }                                                                   \
 100 }
 101 #endif
 102 HELPER_ST(sb, stb, uint8_t)
 103 HELPER_ST(sw, stl, uint32_t)
 104 #if defined(TARGET_MIPS64)
 105 HELPER_ST(sd, stq, uint64_t)
 106 #endif
 107 #undef HELPER_ST
 108
 109 target_ulong helper_clo (target_ulong arg1)
 110 {
 111     return clo32(arg1);
 112 }
 113
 114 target_ulong helper_clz (target_ulong arg1)
 115 {
 116     return clz32(arg1);
 117 }
 118
 119 #if defined(TARGET_MIPS64)
 120 target_ulong helper_dclo (target_ulong arg1)
 121 {
 122     return clo64(arg1);
 123 }
 124
 125 target_ulong helper_dclz (target_ulong arg1)
 126 {
 127     return clz64(arg1);
 128 }
 129 #endif /* TARGET_MIPS64 */
 130
 131 /* 64 bits arithmetic for 32 bits hosts */
 132 static inline uint64_t get_HILO(CPUMIPSState *env)
 133 {
 134     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 135 }
 136
 137 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 138 {
 139     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 140     return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 141 }
 142
 143 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 144 {
 145     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 146     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 147     return tmp;
 148 }
 149
 150 /* Multiplication variants of the vr54xx. */
 151 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 152                          target_ulong arg2)
 153 {
 154     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 155                                  (int64_t)(int32_t)arg2));
 156 }
 157
 158 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 159                           target_ulong arg2)
 160 {
 161     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 162                        (uint64_t)(uint32_t)arg2);
 163 }
 164
 165 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 166                          target_ulong arg2)
 167 {
 168     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 169                        (int64_t)(int32_t)arg2);
 170 }
 171
 172 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 173                            target_ulong arg2)
 174 {
 175     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 176                        (int64_t)(int32_t)arg2);
 177 }
 178
 179 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 180                           target_ulong arg2)
 181 {
 182     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 183                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 184 }
 185
 186 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 187                             target_ulong arg2)
 188 {
 189     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 190                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 191 }
 192
 193 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 194                          target_ulong arg2)
 195 {
 196     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 197                        (int64_t)(int32_t)arg2);
 198 }
 199
 200 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 201                            target_ulong arg2)
 202 {
 203     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 204                        (int64_t)(int32_t)arg2);
 205 }
 206
 207 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 208                           target_ulong arg2)
 209 {
 210     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 211                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 212 }
 213
 214 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 215                             target_ulong arg2)
 216 {
 217     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 218                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 219 }
 220
 221 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 222                           target_ulong arg2)
 223 {
 224     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 228                            target_ulong arg2)
 229 {
 230     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 231                        (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 235                            target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 238                        (int64_t)(int32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 242                             target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 245                        (uint64_t)(uint32_t)arg2);
 246 }
 247
 248 static inline target_ulong bitswap(target_ulong v)
 249 {
 250     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 251               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 252     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 253               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 254     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 255               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 256     return v;
 257 }
 258
 259 #ifdef TARGET_MIPS64
 260 target_ulong helper_dbitswap(target_ulong rt)
 261 {
 262     return bitswap(rt);
 263 }
 264 #endif
 265
 266 target_ulong helper_bitswap(target_ulong rt)
 267 {
 268     return (int32_t)bitswap(rt);
 269 }
 270
 271 #ifndef CONFIG_USER_ONLY
 272
 273 static inline hwaddr do_translate_address(CPUMIPSState *env,
 274                                                       target_ulong address,
 275                                                       int rw, uintptr_t retaddr)
 276 {
 277     hwaddr lladdr;
 278     CPUState *cs = CPU(mips_env_get_cpu(env));
 279
 280     lladdr = cpu_mips_translate_address(env, address, rw);
 281
 282     if (lladdr == -1LL) {
 283         cpu_loop_exit_restore(cs, retaddr);
 284     } else {
 285         return lladdr;
 286     }
 287 }
 288
 289 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 290 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 291 {                                                                             \
 292     if (arg & almask) {                                                       \
 293         env->CP0_BadVAddr = arg;                                              \
 294         do_raise_exception(env, EXCP_AdEL, GETPC());                          \
 295     }                                                                         \
 296     env->lladdr = do_translate_address(env, arg, 0, GETPC());                 \
 297     env->llval = do_##insn(env, arg, mem_idx, GETPC());                       \
 298     return env->llval;                                                        \
 299 }
 300 HELPER_LD_ATOMIC(ll, lw, 0x3)
 301 #ifdef TARGET_MIPS64
 302 HELPER_LD_ATOMIC(lld, ld, 0x7)
 303 #endif
 304 #undef HELPER_LD_ATOMIC
 305
 306 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 307 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 308                            target_ulong arg2, int mem_idx)                    \
 309 {                                                                             \
 310     target_long tmp;                                                          \
 311                                                                               \
 312     if (arg2 & almask) {                                                      \
 313         env->CP0_BadVAddr = arg2;                                             \
 314         do_raise_exception(env, EXCP_AdES, GETPC());                          \
 315     }                                                                         \
 316     if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) {         \
 317         tmp = do_##ld_insn(env, arg2, mem_idx, GETPC());                      \
 318         if (tmp == env->llval) {                                              \
 319             do_##st_insn(env, arg2, arg1, mem_idx, GETPC());                  \
 320             return 1;                                                         \
 321         }                                                                     \
 322     }                                                                         \
 323     return 0;                                                                 \
 324 }
 325 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 326 #ifdef TARGET_MIPS64
 327 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 328 #endif
 329 #undef HELPER_ST_ATOMIC
 330 #endif
 331
 332 #ifdef TARGET_WORDS_BIGENDIAN
 333 #define GET_LMASK(v) ((v) & 3)
 334 #define GET_OFFSET(addr, offset) (addr + (offset))
 335 #else
 336 #define GET_LMASK(v) (((v) & 3) ^ 3)
 337 #define GET_OFFSET(addr, offset) (addr - (offset))
 338 #endif
 339
 340 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 341                 int mem_idx)
 342 {
 343     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
 344
 345     if (GET_LMASK(arg2) <= 2) {
 346         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
 347               GETPC());
 348     }
 349
 350     if (GET_LMASK(arg2) <= 1) {
 351         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
 352               GETPC());
 353     }
 354
 355     if (GET_LMASK(arg2) == 0) {
 356         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
 357               GETPC());
 358     }
 359 }
 360
 361 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 362                 int mem_idx)
 363 {
 364     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 365
 366     if (GET_LMASK(arg2) >= 1) {
 367         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 368               GETPC());
 369     }
 370
 371     if (GET_LMASK(arg2) >= 2) {
 372         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 373               GETPC());
 374     }
 375
 376     if (GET_LMASK(arg2) == 3) {
 377         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 378               GETPC());
 379     }
 380 }
 381
 382 #if defined(TARGET_MIPS64)
 383 /* "half" load and stores.  We must do the memory access inline,
 384    or fault handling won't work.  */
 385
 386 #ifdef TARGET_WORDS_BIGENDIAN
 387 #define GET_LMASK64(v) ((v) & 7)
 388 #else
 389 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 390 #endif
 391
 392 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 393                 int mem_idx)
 394 {
 395     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
 396
 397     if (GET_LMASK64(arg2) <= 6) {
 398         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
 399               GETPC());
 400     }
 401
 402     if (GET_LMASK64(arg2) <= 5) {
 403         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
 404               GETPC());
 405     }
 406
 407     if (GET_LMASK64(arg2) <= 4) {
 408         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
 409               GETPC());
 410     }
 411
 412     if (GET_LMASK64(arg2) <= 3) {
 413         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
 414               GETPC());
 415     }
 416
 417     if (GET_LMASK64(arg2) <= 2) {
 418         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
 419               GETPC());
 420     }
 421
 422     if (GET_LMASK64(arg2) <= 1) {
 423         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
 424               GETPC());
 425     }
 426
 427     if (GET_LMASK64(arg2) <= 0) {
 428         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
 429               GETPC());
 430     }
 431 }
 432
 433 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 434                 int mem_idx)
 435 {
 436     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 437
 438     if (GET_LMASK64(arg2) >= 1) {
 439         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 440               GETPC());
 441     }
 442
 443     if (GET_LMASK64(arg2) >= 2) {
 444         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 445               GETPC());
 446     }
 447
 448     if (GET_LMASK64(arg2) >= 3) {
 449         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 450               GETPC());
 451     }
 452
 453     if (GET_LMASK64(arg2) >= 4) {
 454         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
 455               GETPC());
 456     }
 457
 458     if (GET_LMASK64(arg2) >= 5) {
 459         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
 460               GETPC());
 461     }
 462
 463     if (GET_LMASK64(arg2) >= 6) {
 464         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
 465               GETPC());
 466     }
 467
 468     if (GET_LMASK64(arg2) == 7) {
 469         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
 470               GETPC());
 471     }
 472 }
 473 #endif /* TARGET_MIPS64 */
 474
 475 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 476
 477 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 478                 uint32_t mem_idx)
 479 {
 480     target_ulong base_reglist = reglist & 0xf;
 481     target_ulong do_r31 = reglist & 0x10;
 482
 483     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 484         target_ulong i;
 485
 486         for (i = 0; i < base_reglist; i++) {
 487             env->active_tc.gpr[multiple_regs[i]] =
 488                 (target_long)do_lw(env, addr, mem_idx, GETPC());
 489             addr += 4;
 490         }
 491     }
 492
 493     if (do_r31) {
 494         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
 495                                                     GETPC());
 496     }
 497 }
 498
 499 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 500                 uint32_t mem_idx)
 501 {
 502     target_ulong base_reglist = reglist & 0xf;
 503     target_ulong do_r31 = reglist & 0x10;
 504
 505     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 506         target_ulong i;
 507
 508         for (i = 0; i < base_reglist; i++) {
 509             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 510                   GETPC());
 511             addr += 4;
 512         }
 513     }
 514
 515     if (do_r31) {
 516         do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 517     }
 518 }
 519
 520 #if defined(TARGET_MIPS64)
 521 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 522                 uint32_t mem_idx)
 523 {
 524     target_ulong base_reglist = reglist & 0xf;
 525     target_ulong do_r31 = reglist & 0x10;
 526
 527     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 528         target_ulong i;
 529
 530         for (i = 0; i < base_reglist; i++) {
 531             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
 532                                                          GETPC());
 533             addr += 8;
 534         }
 535     }
 536
 537     if (do_r31) {
 538         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
 539     }
 540 }
 541
 542 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 543                 uint32_t mem_idx)
 544 {
 545     target_ulong base_reglist = reglist & 0xf;
 546     target_ulong do_r31 = reglist & 0x10;
 547
 548     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 549         target_ulong i;
 550
 551         for (i = 0; i < base_reglist; i++) {
 552             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 553                   GETPC());
 554             addr += 8;
 555         }
 556     }
 557
 558     if (do_r31) {
 559         do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 560     }
 561 }
 562 #endif
 563
 564 #ifndef CONFIG_USER_ONLY
 565 /* SMP helpers.  */
 566 static bool mips_vpe_is_wfi(MIPSCPU *c)
 567 {
 568     CPUState *cpu = CPU(c);
 569     CPUMIPSState *env = &c->env;
 570
 571     /* If the VPE is halted but otherwise active, it means it's waiting for
 572        an interrupt.  */
 573     return cpu->halted && mips_vpe_active(env);
 574 }
 575
 576 static bool mips_vp_is_wfi(MIPSCPU *c)
 577 {
 578     CPUState *cpu = CPU(c);
 579     CPUMIPSState *env = &c->env;
 580
 581     return cpu->halted && mips_vp_active(env);
 582 }
 583
 584 static inline void mips_vpe_wake(MIPSCPU *c)
 585 {
 586     /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
 587        because there might be other conditions that state that c should
 588        be sleeping.  */
 589     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 590 }
 591
 592 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 593 {
 594     CPUState *cs = CPU(cpu);
 595
 596     /* The VPE was shut off, really go to bed.
 597        Reset any old _WAKE requests.  */
 598     cs->halted = 1;
 599     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 600 }
 601
 602 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 603 {
 604     CPUMIPSState *c = &cpu->env;
 605
 606     /* FIXME: TC reschedule.  */
 607     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 608         mips_vpe_wake(cpu);
 609     }
 610 }
 611
 612 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 613 {
 614     CPUMIPSState *c = &cpu->env;
 615
 616     /* FIXME: TC reschedule.  */
 617     if (!mips_vpe_active(c)) {
 618         mips_vpe_sleep(cpu);
 619     }
 620 }
 621
 622 /**
 623  * mips_cpu_map_tc:
 624  * @env: CPU from which mapping is performed.
 625  * @tc: Should point to an int with the value of the global TC index.
 626  *
 627  * This function will transform @tc into a local index within the
 628  * returned #CPUMIPSState.
 629  */
 630 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 631           which depends on runtime setup. Can probably be fixed by
 632           walking the list of CPUMIPSStates.  */
 633 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 634 {
 635     MIPSCPU *cpu;
 636     CPUState *cs;
 637     CPUState *other_cs;
 638     int vpe_idx;
 639     int tc_idx = *tc;
 640
 641     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 642         /* Not allowed to address other CPUs.  */
 643         *tc = env->current_tc;
 644         return env;
 645     }
 646
 647     cs = CPU(mips_env_get_cpu(env));
 648     vpe_idx = tc_idx / cs->nr_threads;
 649     *tc = tc_idx % cs->nr_threads;
 650     other_cs = qemu_get_cpu(vpe_idx);
 651     if (other_cs == NULL) {
 652         return env;
 653     }
 654     cpu = MIPS_CPU(other_cs);
 655     return &cpu->env;
 656 }
 657
 658 /* The per VPE CP0_Status register shares some fields with the per TC
 659    CP0_TCStatus registers. These fields are wired to the same registers,
 660    so changes to either of them should be reflected on both registers.
 661
 662    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 663
 664    These helper call synchronizes the regs for a given cpu.  */
 665
 666 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 667 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 668                                      int tc);  */
 669
 670 /* Called for updates to CP0_TCStatus.  */
 671 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 672                              target_ulong v)
 673 {
 674     uint32_t status;
 675     uint32_t tcu, tmx, tasid, tksu;
 676     uint32_t mask = ((1U << CP0St_CU3)
 677                        | (1 << CP0St_CU2)
 678                        | (1 << CP0St_CU1)
 679                        | (1 << CP0St_CU0)
 680                        | (1 << CP0St_MX)
 681                        | (3 << CP0St_KSU));
 682
 683     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 684     tmx = (v >> CP0TCSt_TMX) & 0x1;
 685     tasid = v & cpu->CP0_EntryHi_ASID_mask;
 686     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 687
 688     status = tcu << CP0St_CU0;
 689     status |= tmx << CP0St_MX;
 690     status |= tksu << CP0St_KSU;
 691
 692     cpu->CP0_Status &= ~mask;
 693     cpu->CP0_Status |= status;
 694
 695     /* Sync the TASID with EntryHi.  */
 696     cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
 697     cpu->CP0_EntryHi |= tasid;
 698
 699     compute_hflags(cpu);
 700 }
 701
 702 /* Called for updates to CP0_EntryHi.  */
 703 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 704 {
 705     int32_t *tcst;
 706     uint32_t asid, v = cpu->CP0_EntryHi;
 707
 708     asid = v & cpu->CP0_EntryHi_ASID_mask;
 709
 710     if (tc == cpu->current_tc) {
 711         tcst = &cpu->active_tc.CP0_TCStatus;
 712     } else {
 713         tcst = &cpu->tcs[tc].CP0_TCStatus;
 714     }
 715
 716     *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
 717     *tcst |= asid;
 718 }
 719
 720 /* CP0 helpers */
 721 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 722 {
 723     return env->mvp->CP0_MVPControl;
 724 }
 725
 726 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 727 {
 728     return env->mvp->CP0_MVPConf0;
 729 }
 730
 731 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 732 {
 733     return env->mvp->CP0_MVPConf1;
 734 }
 735
 736 target_ulong helper_mfc0_random(CPUMIPSState *env)
 737 {
 738     return (int32_t)cpu_mips_get_random(env);
 739 }
 740
 741 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 742 {
 743     return env->active_tc.CP0_TCStatus;
 744 }
 745
 746 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 747 {
 748     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 749     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 750
 751     if (other_tc == other->current_tc)
 752         return other->active_tc.CP0_TCStatus;
 753     else
 754         return other->tcs[other_tc].CP0_TCStatus;
 755 }
 756
 757 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 758 {
 759     return env->active_tc.CP0_TCBind;
 760 }
 761
 762 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 763 {
 764     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 765     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 766
 767     if (other_tc == other->current_tc)
 768         return other->active_tc.CP0_TCBind;
 769     else
 770         return other->tcs[other_tc].CP0_TCBind;
 771 }
 772
 773 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 774 {
 775     return env->active_tc.PC;
 776 }
 777
 778 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 779 {
 780     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 781     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 782
 783     if (other_tc == other->current_tc)
 784         return other->active_tc.PC;
 785     else
 786         return other->tcs[other_tc].PC;
 787 }
 788
 789 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 790 {
 791     return env->active_tc.CP0_TCHalt;
 792 }
 793
 794 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 795 {
 796     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 797     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 798
 799     if (other_tc == other->current_tc)
 800         return other->active_tc.CP0_TCHalt;
 801     else
 802         return other->tcs[other_tc].CP0_TCHalt;
 803 }
 804
 805 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 806 {
 807     return env->active_tc.CP0_TCContext;
 808 }
 809
 810 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 811 {
 812     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 813     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 814
 815     if (other_tc == other->current_tc)
 816         return other->active_tc.CP0_TCContext;
 817     else
 818         return other->tcs[other_tc].CP0_TCContext;
 819 }
 820
 821 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 822 {
 823     return env->active_tc.CP0_TCSchedule;
 824 }
 825
 826 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 827 {
 828     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 829     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 830
 831     if (other_tc == other->current_tc)
 832         return other->active_tc.CP0_TCSchedule;
 833     else
 834         return other->tcs[other_tc].CP0_TCSchedule;
 835 }
 836
 837 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 838 {
 839     return env->active_tc.CP0_TCScheFBack;
 840 }
 841
 842 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 843 {
 844     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 845     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 846
 847     if (other_tc == other->current_tc)
 848         return other->active_tc.CP0_TCScheFBack;
 849     else
 850         return other->tcs[other_tc].CP0_TCScheFBack;
 851 }
 852
 853 target_ulong helper_mfc0_count(CPUMIPSState *env)
 854 {
 855     return (int32_t)cpu_mips_get_count(env);
 856 }
 857
 858 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 859 {
 860     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 861     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 862
 863     return other->CP0_EntryHi;
 864 }
 865
 866 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 867 {
 868     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 869     int32_t tccause;
 870     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 871
 872     if (other_tc == other->current_tc) {
 873         tccause = other->CP0_Cause;
 874     } else {
 875         tccause = other->CP0_Cause;
 876     }
 877
 878     return tccause;
 879 }
 880
 881 target_ulong helper_mftc0_status(CPUMIPSState *env)
 882 {
 883     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 884     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 885
 886     return other->CP0_Status;
 887 }
 888
 889 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 890 {
 891     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 892 }
 893
 894 target_ulong helper_mfc0_maar(CPUMIPSState *env)
 895 {
 896     return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
 897 }
 898
 899 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
 900 {
 901     return env->CP0_MAAR[env->CP0_MAARI] >> 32;
 902 }
 903
 904 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 905 {
 906     return (int32_t)env->CP0_WatchLo[sel];
 907 }
 908
 909 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 910 {
 911     return env->CP0_WatchHi[sel];
 912 }
 913
 914 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 915 {
 916     target_ulong t0 = env->CP0_Debug;
 917     if (env->hflags & MIPS_HFLAG_DM)
 918         t0 |= 1 << CP0DB_DM;
 919
 920     return t0;
 921 }
 922
 923 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 924 {
 925     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 926     int32_t tcstatus;
 927     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 928
 929     if (other_tc == other->current_tc)
 930         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 931     else
 932         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 933
 934     /* XXX: Might be wrong, check with EJTAG spec. */
 935     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 936             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 937 }
 938
 939 #if defined(TARGET_MIPS64)
 940 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 941 {
 942     return env->active_tc.PC;
 943 }
 944
 945 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 946 {
 947     return env->active_tc.CP0_TCHalt;
 948 }
 949
 950 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 951 {
 952     return env->active_tc.CP0_TCContext;
 953 }
 954
 955 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 956 {
 957     return env->active_tc.CP0_TCSchedule;
 958 }
 959
 960 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 961 {
 962     return env->active_tc.CP0_TCScheFBack;
 963 }
 964
 965 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 966 {
 967     return env->lladdr >> env->CP0_LLAddr_shift;
 968 }
 969
 970 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
 971 {
 972     return env->CP0_MAAR[env->CP0_MAARI];
 973 }
 974
 975 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 976 {
 977     return env->CP0_WatchLo[sel];
 978 }
 979 #endif /* TARGET_MIPS64 */
 980
 981 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 982 {
 983     uint32_t index_p = env->CP0_Index & 0x80000000;
 984     uint32_t tlb_index = arg1 & 0x7fffffff;
 985     if (tlb_index < env->tlb->nb_tlb) {
 986         if (env->insn_flags & ISA_MIPS32R6) {
 987             index_p |= arg1 & 0x80000000;
 988         }
 989         env->CP0_Index = index_p | tlb_index;
 990     }
 991 }
 992
 993 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 994 {
 995     uint32_t mask = 0;
 996     uint32_t newval;
 997
 998     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 999         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1000                 (1 << CP0MVPCo_EVP);
1001     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1002         mask |= (1 << CP0MVPCo_STLB);
1003     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1004
1005     // TODO: Enable/disable shared TLB, enable/disable VPEs.
1006
1007     env->mvp->CP0_MVPControl = newval;
1008 }
1009
1010 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1011 {
1012     uint32_t mask;
1013     uint32_t newval;
1014
1015     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1016            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1017     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1018
1019     /* Yield scheduler intercept not implemented. */
1020     /* Gating storage scheduler intercept not implemented. */
1021
1022     // TODO: Enable/disable TCs.
1023
1024     env->CP0_VPEControl = newval;
1025 }
1026
1027 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1028 {
1029     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1030     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1031     uint32_t mask;
1032     uint32_t newval;
1033
1034     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1035            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1036     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1037
1038     /* TODO: Enable/disable TCs.  */
1039
1040     other->CP0_VPEControl = newval;
1041 }
1042
1043 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1044 {
1045     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1046     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1047     /* FIXME: Mask away return zero on read bits.  */
1048     return other->CP0_VPEControl;
1049 }
1050
1051 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1052 {
1053     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1054     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1055
1056     return other->CP0_VPEConf0;
1057 }
1058
1059 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1060 {
1061     uint32_t mask = 0;
1062     uint32_t newval;
1063
1064     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1065         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1066             mask |= (0xff << CP0VPEC0_XTC);
1067         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1068     }
1069     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1070
1071     // TODO: TC exclusive handling due to ERL/EXL.
1072
1073     env->CP0_VPEConf0 = newval;
1074 }
1075
1076 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1077 {
1078     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1079     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1080     uint32_t mask = 0;
1081     uint32_t newval;
1082
1083     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1084     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1085
1086     /* TODO: TC exclusive handling due to ERL/EXL.  */
1087     other->CP0_VPEConf0 = newval;
1088 }
1089
1090 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1091 {
1092     uint32_t mask = 0;
1093     uint32_t newval;
1094
1095     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1096         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1097                 (0xff << CP0VPEC1_NCP1);
1098     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1099
1100     /* UDI not implemented. */
1101     /* CP2 not implemented. */
1102
1103     // TODO: Handle FPU (CP1) binding.
1104
1105     env->CP0_VPEConf1 = newval;
1106 }
1107
1108 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1109 {
1110     /* Yield qualifier inputs not implemented. */
1111     env->CP0_YQMask = 0x00000000;
1112 }
1113
1114 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1115 {
1116     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1117 }
1118
1119 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1120
1121 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1122 {
1123     /* 1k pages not implemented */
1124     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1125     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1126                         | (rxi << (CP0EnLo_XI - 30));
1127 }
1128
1129 #if defined(TARGET_MIPS64)
1130 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1131
1132 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1133 {
1134     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1135     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1136 }
1137 #endif
1138
1139 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1140 {
1141     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1142     uint32_t newval;
1143
1144     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1145
1146     env->active_tc.CP0_TCStatus = newval;
1147     sync_c0_tcstatus(env, env->current_tc, newval);
1148 }
1149
1150 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1151 {
1152     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1153     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1154
1155     if (other_tc == other->current_tc)
1156         other->active_tc.CP0_TCStatus = arg1;
1157     else
1158         other->tcs[other_tc].CP0_TCStatus = arg1;
1159     sync_c0_tcstatus(other, other_tc, arg1);
1160 }
1161
1162 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1163 {
1164     uint32_t mask = (1 << CP0TCBd_TBE);
1165     uint32_t newval;
1166
1167     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1168         mask |= (1 << CP0TCBd_CurVPE);
1169     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1170     env->active_tc.CP0_TCBind = newval;
1171 }
1172
1173 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1174 {
1175     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1176     uint32_t mask = (1 << CP0TCBd_TBE);
1177     uint32_t newval;
1178     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1179
1180     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1181         mask |= (1 << CP0TCBd_CurVPE);
1182     if (other_tc == other->current_tc) {
1183         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1184         other->active_tc.CP0_TCBind = newval;
1185     } else {
1186         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1187         other->tcs[other_tc].CP0_TCBind = newval;
1188     }
1189 }
1190
1191 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1192 {
1193     env->active_tc.PC = arg1;
1194     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1195     env->lladdr = 0ULL;
1196     /* MIPS16 not implemented. */
1197 }
1198
1199 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1200 {
1201     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1202     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1203
1204     if (other_tc == other->current_tc) {
1205         other->active_tc.PC = arg1;
1206         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1207         other->lladdr = 0ULL;
1208         /* MIPS16 not implemented. */
1209     } else {
1210         other->tcs[other_tc].PC = arg1;
1211         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1212         other->lladdr = 0ULL;
1213         /* MIPS16 not implemented. */
1214     }
1215 }
1216
1217 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1218 {
1219     MIPSCPU *cpu = mips_env_get_cpu(env);
1220
1221     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1222
1223     // TODO: Halt TC / Restart (if allocated+active) TC.
1224     if (env->active_tc.CP0_TCHalt & 1) {
1225         mips_tc_sleep(cpu, env->current_tc);
1226     } else {
1227         mips_tc_wake(cpu, env->current_tc);
1228     }
1229 }
1230
1231 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1232 {
1233     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1234     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1235     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1236
1237     // TODO: Halt TC / Restart (if allocated+active) TC.
1238
1239     if (other_tc == other->current_tc)
1240         other->active_tc.CP0_TCHalt = arg1;
1241     else
1242         other->tcs[other_tc].CP0_TCHalt = arg1;
1243
1244     if (arg1 & 1) {
1245         mips_tc_sleep(other_cpu, other_tc);
1246     } else {
1247         mips_tc_wake(other_cpu, other_tc);
1248     }
1249 }
1250
1251 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1252 {
1253     env->active_tc.CP0_TCContext = arg1;
1254 }
1255
1256 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1257 {
1258     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1259     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1260
1261     if (other_tc == other->current_tc)
1262         other->active_tc.CP0_TCContext = arg1;
1263     else
1264         other->tcs[other_tc].CP0_TCContext = arg1;
1265 }
1266
1267 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1268 {
1269     env->active_tc.CP0_TCSchedule = arg1;
1270 }
1271
1272 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1273 {
1274     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1275     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1276
1277     if (other_tc == other->current_tc)
1278         other->active_tc.CP0_TCSchedule = arg1;
1279     else
1280         other->tcs[other_tc].CP0_TCSchedule = arg1;
1281 }
1282
1283 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1284 {
1285     env->active_tc.CP0_TCScheFBack = arg1;
1286 }
1287
1288 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1289 {
1290     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1291     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1292
1293     if (other_tc == other->current_tc)
1294         other->active_tc.CP0_TCScheFBack = arg1;
1295     else
1296         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1297 }
1298
1299 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1300 {
1301     /* 1k pages not implemented */
1302     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1303     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1304                         | (rxi << (CP0EnLo_XI - 30));
1305 }
1306
1307 #if defined(TARGET_MIPS64)
1308 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1309 {
1310     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1311     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1312 }
1313 #endif
1314
1315 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1316 {
1317     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1318 }
1319
1320 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1321 {
1322     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1323     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1324         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1325          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1326          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1327         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1328     }
1329 }
1330
1331 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1332 {
1333     /* SmartMIPS not implemented */
1334     /* 1k pages not implemented */
1335     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1336                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1337     compute_hflags(env);
1338     restore_pamask(env);
1339 }
1340
1341 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1342 {
1343     if (env->insn_flags & ISA_MIPS32R6) {
1344         if (arg1 < env->tlb->nb_tlb) {
1345             env->CP0_Wired = arg1;
1346         }
1347     } else {
1348         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1349     }
1350 }
1351
1352 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1353 {
1354     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1355 }
1356
1357 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1358 {
1359     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1360 }
1361
1362 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1363 {
1364     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1365 }
1366
1367 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1368 {
1369     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1370 }
1371
1372 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1373 {
1374     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1375 }
1376
1377 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1378 {
1379     uint32_t mask = 0x0000000F;
1380
1381     if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1382         (env->insn_flags & ISA_MIPS32R6)) {
1383         mask |= (1 << 4);
1384     }
1385     if (env->insn_flags & ISA_MIPS32R6) {
1386         mask |= (1 << 5);
1387     }
1388     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1389         mask |= (1 << 29);
1390
1391         if (arg1 & (1 << 29)) {
1392             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1393         } else {
1394             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1395         }
1396     }
1397
1398     env->CP0_HWREna = arg1 & mask;
1399 }
1400
1401 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1402 {
1403     cpu_mips_store_count(env, arg1);
1404 }
1405
1406 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1407 {
1408     target_ulong old, val, mask;
1409     mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1410     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1411         mask |= 1 << CP0EnHi_EHINV;
1412     }
1413
1414     /* 1k pages not implemented */
1415 #if defined(TARGET_MIPS64)
1416     if (env->insn_flags & ISA_MIPS32R6) {
1417         int entryhi_r = extract64(arg1, 62, 2);
1418         int config0_at = extract32(env->CP0_Config0, 13, 2);
1419         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1420         if ((entryhi_r == 2) ||
1421             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1422             /* skip EntryHi.R field if new value is reserved */
1423             mask &= ~(0x3ull << 62);
1424         }
1425     }
1426     mask &= env->SEGMask;
1427 #endif
1428     old = env->CP0_EntryHi;
1429     val = (arg1 & mask) | (old & ~mask);
1430     env->CP0_EntryHi = val;
1431     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1432         sync_c0_entryhi(env, env->current_tc);
1433     }
1434     /* If the ASID changes, flush qemu's TLB.  */
1435     if ((old & env->CP0_EntryHi_ASID_mask) !=
1436         (val & env->CP0_EntryHi_ASID_mask)) {
1437         cpu_mips_tlb_flush(env, 1);
1438     }
1439 }
1440
1441 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1442 {
1443     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1444     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1445
1446     other->CP0_EntryHi = arg1;
1447     sync_c0_entryhi(other, other_tc);
1448 }
1449
1450 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1451 {
1452     cpu_mips_store_compare(env, arg1);
1453 }
1454
1455 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1456 {
1457     MIPSCPU *cpu = mips_env_get_cpu(env);
1458     uint32_t val, old;
1459
1460     old = env->CP0_Status;
1461     cpu_mips_store_status(env, arg1);
1462     val = env->CP0_Status;
1463
1464     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1465         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1466                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1467                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1468                 env->CP0_Cause);
1469         switch (env->hflags & MIPS_HFLAG_KSU) {
1470         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1471         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1472         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1473         default:
1474             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1475             break;
1476         }
1477     }
1478 }
1479
1480 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1481 {
1482     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1483     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1484     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1485
1486     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1487     sync_c0_status(env, other, other_tc);
1488 }
1489
1490 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1491 {
1492     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1493 }
1494
1495 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1496 {
1497     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1498     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1499 }
1500
1501 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1502 {
1503     cpu_mips_store_cause(env, arg1);
1504 }
1505
1506 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1507 {
1508     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1509     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1510
1511     cpu_mips_store_cause(other, arg1);
1512 }
1513
1514 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1515 {
1516     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1517     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1518
1519     return other->CP0_EPC;
1520 }
1521
1522 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1523 {
1524     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1525     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1526
1527     return other->CP0_EBase;
1528 }
1529
1530 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1531 {
1532     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1533 }
1534
1535 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1536 {
1537     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1538     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1539     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1540 }
1541
1542 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1543 {
1544     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1545     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1546
1547     switch (idx) {
1548     case 0: return other->CP0_Config0;
1549     case 1: return other->CP0_Config1;
1550     case 2: return other->CP0_Config2;
1551     case 3: return other->CP0_Config3;
1552     /* 4 and 5 are reserved.  */
1553     case 6: return other->CP0_Config6;
1554     case 7: return other->CP0_Config7;
1555     default:
1556         break;
1557     }
1558     return 0;
1559 }
1560
1561 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1562 {
1563     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1564 }
1565
1566 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1567 {
1568     /* tertiary/secondary caches not implemented */
1569     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1570 }
1571
1572 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1573 {
1574     if (env->insn_flags & ASE_MICROMIPS) {
1575         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1576                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1577     }
1578 }
1579
1580 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1581 {
1582     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1583                        (arg1 & env->CP0_Config4_rw_bitmask);
1584 }
1585
1586 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1587 {
1588     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1589                        (arg1 & env->CP0_Config5_rw_bitmask);
1590     compute_hflags(env);
1591 }
1592
1593 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1594 {
1595     target_long mask = env->CP0_LLAddr_rw_bitmask;
1596     arg1 = arg1 << env->CP0_LLAddr_shift;
1597     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1598 }
1599
1600 #define MTC0_MAAR_MASK(env) \
1601         ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1602
1603 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1604 {
1605     env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1606 }
1607
1608 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1609 {
1610     env->CP0_MAAR[env->CP0_MAARI] =
1611         (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1612         (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1613 }
1614
1615 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1616 {
1617     int index = arg1 & 0x3f;
1618     if (index == 0x3f) {
1619         /* Software may write all ones to INDEX to determine the
1620            maximum value supported. */
1621         env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1622     } else if (index < MIPS_MAAR_MAX) {
1623         env->CP0_MAARI = index;
1624     }
1625     /* Other than the all ones, if the
1626        value written is not supported, then INDEX is unchanged
1627        from its previous value. */
1628 }
1629
1630 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1631 {
1632     /* Watch exceptions for instructions, data loads, data stores
1633        not implemented. */
1634     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1635 }
1636
1637 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1638 {
1639     int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1640     env->CP0_WatchHi[sel] = arg1 & mask;
1641     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1642 }
1643
1644 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1645 {
1646     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1647     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1648 }
1649
1650 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1651 {
1652     env->CP0_Framemask = arg1; /* XXX */
1653 }
1654
1655 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1656 {
1657     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1658     if (arg1 & (1 << CP0DB_DM))
1659         env->hflags |= MIPS_HFLAG_DM;
1660     else
1661         env->hflags &= ~MIPS_HFLAG_DM;
1662 }
1663
1664 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1665 {
1666     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1667     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1668     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1669
1670     /* XXX: Might be wrong, check with EJTAG spec. */
1671     if (other_tc == other->current_tc)
1672         other->active_tc.CP0_Debug_tcstatus = val;
1673     else
1674         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1675     other->CP0_Debug = (other->CP0_Debug &
1676                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1677                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1678 }
1679
1680 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1681 {
1682     env->CP0_Performance0 = arg1 & 0x000007ff;
1683 }
1684
1685 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1686 {
1687     int32_t wst = arg1 & (1 << CP0EC_WST);
1688     int32_t spr = arg1 & (1 << CP0EC_SPR);
1689     int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1690
1691     env->CP0_ErrCtl = wst | spr | itc;
1692
1693     if (itc && !wst && !spr) {
1694         env->hflags |= MIPS_HFLAG_ITC_CACHE;
1695     } else {
1696         env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1697     }
1698 }
1699
1700 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1701 {
1702     if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1703         /* If CACHE instruction is configured for ITC tags then make all
1704            CP0.TagLo bits writable. The actual write to ITC Configuration
1705            Tag will take care of the read-only bits. */
1706         env->CP0_TagLo = arg1;
1707     } else {
1708         env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1709     }
1710 }
1711
1712 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1713 {
1714     env->CP0_DataLo = arg1; /* XXX */
1715 }
1716
1717 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1718 {
1719     env->CP0_TagHi = arg1; /* XXX */
1720 }
1721
1722 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1723 {
1724     env->CP0_DataHi = arg1; /* XXX */
1725 }
1726
1727 /* MIPS MT functions */
1728 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1729 {
1730     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1731     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1732
1733     if (other_tc == other->current_tc)
1734         return other->active_tc.gpr[sel];
1735     else
1736         return other->tcs[other_tc].gpr[sel];
1737 }
1738
1739 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1740 {
1741     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1742     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1743
1744     if (other_tc == other->current_tc)
1745         return other->active_tc.LO[sel];
1746     else
1747         return other->tcs[other_tc].LO[sel];
1748 }
1749
1750 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1751 {
1752     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1753     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1754
1755     if (other_tc == other->current_tc)
1756         return other->active_tc.HI[sel];
1757     else
1758         return other->tcs[other_tc].HI[sel];
1759 }
1760
1761 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1762 {
1763     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1764     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1765
1766     if (other_tc == other->current_tc)
1767         return other->active_tc.ACX[sel];
1768     else
1769         return other->tcs[other_tc].ACX[sel];
1770 }
1771
1772 target_ulong helper_mftdsp(CPUMIPSState *env)
1773 {
1774     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1775     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1776
1777     if (other_tc == other->current_tc)
1778         return other->active_tc.DSPControl;
1779     else
1780         return other->tcs[other_tc].DSPControl;
1781 }
1782
1783 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1784 {
1785     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1786     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1787
1788     if (other_tc == other->current_tc)
1789         other->active_tc.gpr[sel] = arg1;
1790     else
1791         other->tcs[other_tc].gpr[sel] = arg1;
1792 }
1793
1794 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1795 {
1796     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1797     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1798
1799     if (other_tc == other->current_tc)
1800         other->active_tc.LO[sel] = arg1;
1801     else
1802         other->tcs[other_tc].LO[sel] = arg1;
1803 }
1804
1805 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1806 {
1807     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1808     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1809
1810     if (other_tc == other->current_tc)
1811         other->active_tc.HI[sel] = arg1;
1812     else
1813         other->tcs[other_tc].HI[sel] = arg1;
1814 }
1815
1816 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1817 {
1818     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1819     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1820
1821     if (other_tc == other->current_tc)
1822         other->active_tc.ACX[sel] = arg1;
1823     else
1824         other->tcs[other_tc].ACX[sel] = arg1;
1825 }
1826
1827 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1828 {
1829     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1830     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1831
1832     if (other_tc == other->current_tc)
1833         other->active_tc.DSPControl = arg1;
1834     else
1835         other->tcs[other_tc].DSPControl = arg1;
1836 }
1837
1838 /* MIPS MT functions */
1839 target_ulong helper_dmt(void)
1840 {
1841     // TODO
1842      return 0;
1843 }
1844
1845 target_ulong helper_emt(void)
1846 {
1847     // TODO
1848     return 0;
1849 }
1850
1851 target_ulong helper_dvpe(CPUMIPSState *env)
1852 {
1853     CPUState *other_cs = first_cpu;
1854     target_ulong prev = env->mvp->CP0_MVPControl;
1855
1856     CPU_FOREACH(other_cs) {
1857         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1858         /* Turn off all VPEs except the one executing the dvpe.  */
1859         if (&other_cpu->env != env) {
1860             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1861             mips_vpe_sleep(other_cpu);
1862         }
1863     }
1864     return prev;
1865 }
1866
1867 target_ulong helper_evpe(CPUMIPSState *env)
1868 {
1869     CPUState *other_cs = first_cpu;
1870     target_ulong prev = env->mvp->CP0_MVPControl;
1871
1872     CPU_FOREACH(other_cs) {
1873         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1874
1875         if (&other_cpu->env != env
1876             /* If the VPE is WFI, don't disturb its sleep.  */
1877             && !mips_vpe_is_wfi(other_cpu)) {
1878             /* Enable the VPE.  */
1879             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1880             mips_vpe_wake(other_cpu); /* And wake it up.  */
1881         }
1882     }
1883     return prev;
1884 }
1885 #endif /* !CONFIG_USER_ONLY */
1886
1887 void helper_fork(target_ulong arg1, target_ulong arg2)
1888 {
1889     fprintf(stderr, "%s:%u - %s\n", __FILE__, __LINE__, __func__);
1890     // arg1 = rt, arg2 = rs
1891     // TODO: store to TC register, assert to detect test cases.
1892     g_assert_not_reached();
1893 }
1894
1895 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1896 {
1897     target_long arg1 = arg;
1898
1899     if (arg1 < 0) {
1900         /* No scheduling policy implemented. */
1901         if (arg1 != -2) {
1902             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1903                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1904                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1905                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1906                 do_raise_exception(env, EXCP_THREAD, GETPC());
1907             }
1908         }
1909     } else if (arg1 == 0) {
1910         if (0 /* TODO: TC underflow */) {
1911             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1912             do_raise_exception(env, EXCP_THREAD, GETPC());
1913         } else {
1914             // TODO: Deallocate TC
1915         }
1916     } else if (arg1 > 0) {
1917         /* Yield qualifier inputs not implemented. */
1918         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1919         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1920         do_raise_exception(env, EXCP_THREAD, GETPC());
1921     }
1922     return env->CP0_YQMask;
1923 }
1924
1925 /* R6 Multi-threading */
1926 #ifndef CONFIG_USER_ONLY
1927 target_ulong helper_dvp(CPUMIPSState *env)
1928 {
1929     CPUState *other_cs = first_cpu;
1930     target_ulong prev = env->CP0_VPControl;
1931
1932     if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1933         CPU_FOREACH(other_cs) {
1934             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1935             /* Turn off all VPs except the one executing the dvp. */
1936             if (&other_cpu->env != env) {
1937                 mips_vpe_sleep(other_cpu);
1938             }
1939         }
1940         env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1941     }
1942     return prev;
1943 }
1944
1945 target_ulong helper_evp(CPUMIPSState *env)
1946 {
1947     CPUState *other_cs = first_cpu;
1948     target_ulong prev = env->CP0_VPControl;
1949
1950     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1951         CPU_FOREACH(other_cs) {
1952             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1953             if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1954                 /* If the VP is WFI, don't disturb its sleep.
1955                  * Otherwise, wake it up. */
1956                 mips_vpe_wake(other_cpu);
1957             }
1958         }
1959         env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1960     }
1961     return prev;
1962 }
1963 #endif /* !CONFIG_USER_ONLY */
1964
1965 #ifndef CONFIG_USER_ONLY
1966 /* TLB management */
1967 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1968 {
1969     /* Discard entries from env->tlb[first] onwards.  */
1970     while (env->tlb->tlb_in_use > first) {
1971         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1972     }
1973 }
1974
1975 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1976 {
1977 #if defined(TARGET_MIPS64)
1978     return extract64(entrylo, 6, 54);
1979 #else
1980     return extract64(entrylo, 6, 24) | /* PFN */
1981            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1982 #endif
1983 }
1984
1985 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1986 {
1987     r4k_tlb_t *tlb;
1988
1989     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1990     tlb = &env->tlb->mmu.r4k.tlb[idx];
1991     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1992         tlb->EHINV = 1;
1993         return;
1994     }
1995     tlb->EHINV = 0;
1996     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1997 #if defined(TARGET_MIPS64)
1998     tlb->VPN &= env->SEGMask;
1999 #endif
2000     tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2001     tlb->PageMask = env->CP0_PageMask;
2002     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2003     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2004     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2005     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2006     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2007     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2008     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
2009     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2010     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2011     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2012     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2013     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2014     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
2015 }
2016
2017 void r4k_helper_tlbinv(CPUMIPSState *env)
2018 {
2019     int idx;
2020     r4k_tlb_t *tlb;
2021     uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2022
2023     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2024         tlb = &env->tlb->mmu.r4k.tlb[idx];
2025         if (!tlb->G && tlb->ASID == ASID) {
2026             tlb->EHINV = 1;
2027         }
2028     }
2029     cpu_mips_tlb_flush(env, 1);
2030 }
2031
2032 void r4k_helper_tlbinvf(CPUMIPSState *env)
2033 {
2034     int idx;
2035
2036     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2037         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2038     }
2039     cpu_mips_tlb_flush(env, 1);
2040 }
2041
2042 void r4k_helper_tlbwi(CPUMIPSState *env)
2043 {
2044     r4k_tlb_t *tlb;
2045     int idx;
2046     target_ulong VPN;
2047     uint16_t ASID;
2048     bool G, V0, D0, V1, D1;
2049
2050     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2051     tlb = &env->tlb->mmu.r4k.tlb[idx];
2052     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2053 #if defined(TARGET_MIPS64)
2054     VPN &= env->SEGMask;
2055 #endif
2056     ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2057     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2058     V0 = (env->CP0_EntryLo0 & 2) != 0;
2059     D0 = (env->CP0_EntryLo0 & 4) != 0;
2060     V1 = (env->CP0_EntryLo1 & 2) != 0;
2061     D1 = (env->CP0_EntryLo1 & 4) != 0;
2062
2063     /* Discard cached TLB entries, unless tlbwi is just upgrading access
2064        permissions on the current entry. */
2065     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2066         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2067         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
2068         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2069     }
2070
2071     r4k_invalidate_tlb(env, idx, 0);
2072     r4k_fill_tlb(env, idx);
2073 }
2074
2075 void r4k_helper_tlbwr(CPUMIPSState *env)
2076 {
2077     int r = cpu_mips_get_random(env);
2078
2079     r4k_invalidate_tlb(env, r, 1);
2080     r4k_fill_tlb(env, r);
2081 }
2082
2083 void r4k_helper_tlbp(CPUMIPSState *env)
2084 {
2085     r4k_tlb_t *tlb;
2086     target_ulong mask;
2087     target_ulong tag;
2088     target_ulong VPN;
2089     uint16_t ASID;
2090     int i;
2091
2092     ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2093     for (i = 0; i < env->tlb->nb_tlb; i++) {
2094         tlb = &env->tlb->mmu.r4k.tlb[i];
2095         /* 1k pages are not supported. */
2096         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2097         tag = env->CP0_EntryHi & ~mask;
2098         VPN = tlb->VPN & ~mask;
2099 #if defined(TARGET_MIPS64)
2100         tag &= env->SEGMask;
2101 #endif
2102         /* Check ASID, virtual page number & size */
2103         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2104             /* TLB match */
2105             env->CP0_Index = i;
2106             break;
2107         }
2108     }
2109     if (i == env->tlb->nb_tlb) {
2110         /* No match.  Discard any shadow entries, if any of them match.  */
2111         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2112             tlb = &env->tlb->mmu.r4k.tlb[i];
2113             /* 1k pages are not supported. */
2114             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2115             tag = env->CP0_EntryHi & ~mask;
2116             VPN = tlb->VPN & ~mask;
2117 #if defined(TARGET_MIPS64)
2118             tag &= env->SEGMask;
2119 #endif
2120             /* Check ASID, virtual page number & size */
2121             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2122                 r4k_mips_tlb_flush_extra (env, i);
2123                 break;
2124             }
2125         }
2126
2127         env->CP0_Index |= 0x80000000;
2128     }
2129 }
2130
2131 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2132 {
2133 #if defined(TARGET_MIPS64)
2134     return tlb_pfn << 6;
2135 #else
2136     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2137            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2138 #endif
2139 }
2140
2141 void r4k_helper_tlbr(CPUMIPSState *env)
2142 {
2143     r4k_tlb_t *tlb;
2144     uint16_t ASID;
2145     int idx;
2146
2147     ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2148     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2149     tlb = &env->tlb->mmu.r4k.tlb[idx];
2150
2151     /* If this will change the current ASID, flush qemu's TLB.  */
2152     if (ASID != tlb->ASID)
2153         cpu_mips_tlb_flush (env, 1);
2154
2155     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2156
2157     if (tlb->EHINV) {
2158         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2159         env->CP0_PageMask = 0;
2160         env->CP0_EntryLo0 = 0;
2161         env->CP0_EntryLo1 = 0;
2162     } else {
2163         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2164         env->CP0_PageMask = tlb->PageMask;
2165         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2166                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2167                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2168                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2169         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2170                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2171                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2172                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2173     }
2174 }
2175
2176 void helper_tlbwi(CPUMIPSState *env)
2177 {
2178     env->tlb->helper_tlbwi(env);
2179 }
2180
2181 void helper_tlbwr(CPUMIPSState *env)
2182 {
2183     env->tlb->helper_tlbwr(env);
2184 }
2185
2186 void helper_tlbp(CPUMIPSState *env)
2187 {
2188     env->tlb->helper_tlbp(env);
2189 }
2190
2191 void helper_tlbr(CPUMIPSState *env)
2192 {
2193     env->tlb->helper_tlbr(env);
2194 }
2195
2196 void helper_tlbinv(CPUMIPSState *env)
2197 {
2198     env->tlb->helper_tlbinv(env);
2199 }
2200
2201 void helper_tlbinvf(CPUMIPSState *env)
2202 {
2203     env->tlb->helper_tlbinvf(env);
2204 }
2205
2206 /* Specials */
2207 target_ulong helper_di(CPUMIPSState *env)
2208 {
2209     target_ulong t0 = env->CP0_Status;
2210
2211     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2212     return t0;
2213 }
2214
2215 target_ulong helper_ei(CPUMIPSState *env)
2216 {
2217     target_ulong t0 = env->CP0_Status;
2218
2219     env->CP0_Status = t0 | (1 << CP0St_IE);
2220     return t0;
2221 }
2222
2223 static void debug_pre_eret(CPUMIPSState *env)
2224 {
2225     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2226         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2227                 env->active_tc.PC, env->CP0_EPC);
2228         if (env->CP0_Status & (1 << CP0St_ERL))
2229             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2230         if (env->hflags & MIPS_HFLAG_DM)
2231             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2232         qemu_log("\n");
2233     }
2234 }
2235
2236 static void debug_post_eret(CPUMIPSState *env)
2237 {
2238     MIPSCPU *cpu = mips_env_get_cpu(env);
2239
2240     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2241         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2242                 env->active_tc.PC, env->CP0_EPC);
2243         if (env->CP0_Status & (1 << CP0St_ERL))
2244             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2245         if (env->hflags & MIPS_HFLAG_DM)
2246             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2247         switch (env->hflags & MIPS_HFLAG_KSU) {
2248         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2249         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2250         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2251         default:
2252             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2253             break;
2254         }
2255     }
2256 }
2257
2258 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2259 {
2260     env->active_tc.PC = error_pc & ~(target_ulong)1;
2261     if (error_pc & 1) {
2262         env->hflags |= MIPS_HFLAG_M16;
2263     } else {
2264         env->hflags &= ~(MIPS_HFLAG_M16);
2265     }
2266 }
2267
2268 static inline void exception_return(CPUMIPSState *env)
2269 {
2270     debug_pre_eret(env);
2271     if (env->CP0_Status & (1 << CP0St_ERL)) {
2272         set_pc(env, env->CP0_ErrorEPC);
2273         env->CP0_Status &= ~(1 << CP0St_ERL);
2274     } else {
2275         set_pc(env, env->CP0_EPC);
2276         env->CP0_Status &= ~(1 << CP0St_EXL);
2277     }
2278     compute_hflags(env);
2279     debug_post_eret(env);
2280 }
2281
2282 void helper_eret(CPUMIPSState *env)
2283 {
2284     exception_return(env);
2285     env->lladdr = 1;
2286 }
2287
2288 void helper_eretnc(CPUMIPSState *env)
2289 {
2290     exception_return(env);
2291 }
2292
2293 void helper_deret(CPUMIPSState *env)
2294 {
2295     debug_pre_eret(env);
2296     set_pc(env, env->CP0_DEPC);
2297
2298     env->hflags &= ~MIPS_HFLAG_DM;
2299     compute_hflags(env);
2300     debug_post_eret(env);
2301 }
2302 #endif /* !CONFIG_USER_ONLY */
2303
2304 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2305 {
2306     if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2307         return;
2308     }
2309     do_raise_exception(env, EXCP_RI, pc);
2310 }
2311
2312 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2313 {
2314     check_hwrena(env, 0, GETPC());
2315     return env->CP0_EBase & 0x3ff;
2316 }
2317
2318 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2319 {
2320     check_hwrena(env, 1, GETPC());
2321     return env->SYNCI_Step;
2322 }
2323
2324 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2325 {
2326     check_hwrena(env, 2, GETPC());
2327 #ifdef CONFIG_USER_ONLY
2328     return env->CP0_Count;
2329 #else
2330     return (int32_t)cpu_mips_get_count(env);
2331 #endif
2332 }
2333
2334 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2335 {
2336     check_hwrena(env, 3, GETPC());
2337     return env->CCRes;
2338 }
2339
2340 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2341 {
2342     check_hwrena(env, 4, GETPC());
2343     return env->CP0_Performance0;
2344 }
2345
2346 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2347 {
2348     check_hwrena(env, 5, GETPC());
2349     return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2350 }
2351
2352 void helper_pmon(CPUMIPSState *env, int function)
2353 {
2354     function /= 2;
2355     switch (function) {
2356     case 2: /* TODO: char inbyte(int waitflag); */
2357         if (env->active_tc.gpr[4] == 0)
2358             env->active_tc.gpr[2] = -1;
2359         /* Fall through */
2360     case 11: /* TODO: char inbyte (void); */
2361         env->active_tc.gpr[2] = -1;
2362         break;
2363     case 3:
2364     case 12:
2365         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2366         break;
2367     case 17:
2368         break;
2369 #ifndef CONFIG_USER_ONLY
2370     case 158:
2371         {
2372             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2373             printf("%s", fmt);
2374         }
2375         break;
2376 #endif
2377     }
2378 }
2379
2380 void QEMU_NORETURN helper_wait(CPUMIPSState *env)
2381 {
2382     CPUState *cs = CPU(mips_env_get_cpu(env));
2383
2384     cs->halted = 1;
2385     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2386     /* Last instruction in the block, PC was updated before
2387        - no need to recover PC and icount */
2388     raise_exception(env, EXCP_HLT);
2389 }
2390
2391 #if !defined(CONFIG_USER_ONLY)
2392
2393 void QEMU_NORETURN mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2394                                                 MMUAccessType access_type,
2395                                                 int mmu_idx, uintptr_t retaddr)
2396 {
2397     MIPSCPU *cpu = MIPS_CPU(cs);
2398     CPUMIPSState *env = &cpu->env;
2399     int error_code = 0;
2400     int excp;
2401
2402     env->CP0_BadVAddr = addr;
2403
2404     if (access_type == MMU_DATA_STORE) {
2405         excp = EXCP_AdES;
2406     } else {
2407         excp = EXCP_AdEL;
2408         if (access_type == MMU_INST_FETCH) {
2409             error_code |= EXCP_INST_NOTAVAIL;
2410         }
2411     }
2412
2413     do_raise_exception_err(env, excp, error_code, retaddr);
2414 }
2415
2416 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
2417               int mmu_idx, uintptr_t retaddr)
2418 {
2419     int ret;
2420
2421     ret = mips_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
2422     if (ret) {
2423         MIPSCPU *cpu = MIPS_CPU(cs);
2424         CPUMIPSState *env = &cpu->env;
2425
2426         do_raise_exception_err(env, cs->exception_index,
2427                                env->error_code, retaddr);
2428     }
2429 }
2430
2431 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2432                                 bool is_write, bool is_exec, int unused,
2433                                 unsigned size)
2434 {
2435     MIPSCPU *cpu = MIPS_CPU(cs);
2436     CPUMIPSState *env = &cpu->env;
2437
2438     /*
2439      * Raising an exception with KVM enabled will crash because it won't be from
2440      * the main execution loop so the longjmp won't have a matching setjmp.
2441      * Until we can trigger a bus error exception through KVM lets just ignore
2442      * the access.
2443      */
2444     if (kvm_enabled()) {
2445         /* TODO: here a return was replaced by an assertion. */
2446         g_assert_not_reached();
2447     }
2448
2449     if (is_exec) {
2450         raise_exception(env, EXCP_IBE);
2451     } else {
2452         raise_exception(env, EXCP_DBE);
2453     }
2454 }
2455 #endif /* !CONFIG_USER_ONLY */
2456
2457 /* Complex FPU operations which may need stack space. */
2458
2459 #define FLOAT_TWO32 make_float32(1 << 30)
2460 #define FLOAT_TWO64 make_float64(1ULL << 62)
2461
2462 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2463 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2464
2465 /* convert MIPS rounding mode in FCR31 to IEEE library */
2466 unsigned int ieee_rm[] = {
2467     float_round_nearest_even,
2468     float_round_to_zero,
2469     float_round_up,
2470     float_round_down
2471 };
2472
2473 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2474 {
2475     target_ulong arg1 = 0;
2476
2477     switch (reg) {
2478     case 0:
2479         arg1 = (int32_t)env->active_fpu.fcr0;
2480         break;
2481     case 1:
2482         /* UFR Support - Read Status FR */
2483         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2484             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2485                 arg1 = (int32_t)
2486                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2487             } else {
2488                 do_raise_exception(env, EXCP_RI, GETPC());
2489             }
2490         }
2491         break;
2492     case 5:
2493         /* FRE Support - read Config5.FRE bit */
2494         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2495             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2496                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2497             } else {
2498                 helper_raise_exception(env, EXCP_RI);
2499             }
2500         }
2501         break;
2502     case 25:
2503         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2504         break;
2505     case 26:
2506         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2507         break;
2508     case 28:
2509         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2510         break;
2511     default:
2512         arg1 = (int32_t)env->active_fpu.fcr31;
2513         break;
2514     }
2515
2516     return arg1;
2517 }
2518
2519 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2520 {
2521     switch (fs) {
2522     case 1:
2523         /* UFR Alias - Reset Status FR */
2524         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2525             return;
2526         }
2527         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2528             env->CP0_Status &= ~(1 << CP0St_FR);
2529             compute_hflags(env);
2530         } else {
2531             do_raise_exception(env, EXCP_RI, GETPC());
2532         }
2533         break;
2534     case 4:
2535         /* UNFR Alias - Set Status FR */
2536         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2537             return;
2538         }
2539         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2540             env->CP0_Status |= (1 << CP0St_FR);
2541             compute_hflags(env);
2542         } else {
2543             do_raise_exception(env, EXCP_RI, GETPC());
2544         }
2545         break;
2546     case 5:
2547         /* FRE Support - clear Config5.FRE bit */
2548         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2549             return;
2550         }
2551         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2552             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2553             compute_hflags(env);
2554         } else {
2555             helper_raise_exception(env, EXCP_RI);
2556         }
2557         break;
2558     case 6:
2559         /* FRE Support - set Config5.FRE bit */
2560         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2561             return;
2562         }
2563         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2564             env->CP0_Config5 |= (1 << CP0C5_FRE);
2565             compute_hflags(env);
2566         } else {
2567             helper_raise_exception(env, EXCP_RI);
2568         }
2569         break;
2570     case 25:
2571         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2572             return;
2573         }
2574         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2575                      ((arg1 & 0x1) << 23);
2576         break;
2577     case 26:
2578         if (arg1 & 0x007c0000)
2579             return;
2580         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2581         break;
2582     case 28:
2583         if (arg1 & 0x007c0000)
2584             return;
2585         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2586                      ((arg1 & 0x4) << 22);
2587         break;
2588     case 31:
2589         env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2590                (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2591         break;
2592     default:
2593         return;
2594     }
2595     restore_fp_status(env);
2596     set_float_exception_flags(0, &env->active_fpu.fp_status);
2597     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) {
2598         do_raise_exception(env, EXCP_FPE, GETPC());
2599     }
2600 }
2601
2602 int ieee_ex_to_mips(int xcpt)
2603 {
2604     int ret = 0;
2605     if (xcpt) {
2606         if (xcpt & float_flag_invalid) {
2607             ret |= FP_INVALID;
2608         }
2609         if (xcpt & float_flag_overflow) {
2610             ret |= FP_OVERFLOW;
2611         }
2612         if (xcpt & float_flag_underflow) {
2613             ret |= FP_UNDERFLOW;
2614         }
2615         if (xcpt & float_flag_divbyzero) {
2616             ret |= FP_DIV0;
2617         }
2618         if (xcpt & float_flag_inexact) {
2619             ret |= FP_INEXACT;
2620         }
2621     }
2622     return ret;
2623 }
2624
2625 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2626 {
2627     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2628
2629     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2630
2631     if (tmp) {
2632         set_float_exception_flags(0, &env->active_fpu.fp_status);
2633
2634         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2635             do_raise_exception(env, EXCP_FPE, pc);
2636         } else {
2637             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2638         }
2639     }
2640 }
2641
2642 /* Float support.
2643    Single precition routines have a "s" suffix, double precision a
2644    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2645    paired single lower "pl", paired single upper "pu".  */
2646
2647 /* unary operations, modifying fp status  */
2648 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2649 {
2650     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2651     update_fcr31(env, GETPC());
2652     return fdt0;
2653 }
2654
2655 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2656 {
2657     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2658     update_fcr31(env, GETPC());
2659     return fst0;
2660 }
2661
2662 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2663 {
2664     uint64_t fdt2;
2665
2666     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2667     fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status);
2668     update_fcr31(env, GETPC());
2669     return fdt2;
2670 }
2671
2672 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2673 {
2674     uint64_t fdt2;
2675
2676     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2677     update_fcr31(env, GETPC());
2678     return fdt2;
2679 }
2680
2681 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2682 {
2683     uint64_t fdt2;
2684
2685     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2686     update_fcr31(env, GETPC());
2687     return fdt2;
2688 }
2689
2690 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2691 {
2692     uint64_t dt2;
2693
2694     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2695     if (get_float_exception_flags(&env->active_fpu.fp_status)
2696         & (float_flag_invalid | float_flag_overflow)) {
2697         dt2 = FP_TO_INT64_OVERFLOW;
2698     }
2699     update_fcr31(env, GETPC());
2700     return dt2;
2701 }
2702
2703 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2704 {
2705     uint64_t dt2;
2706
2707     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2708     if (get_float_exception_flags(&env->active_fpu.fp_status)
2709         & (float_flag_invalid | float_flag_overflow)) {
2710         dt2 = FP_TO_INT64_OVERFLOW;
2711     }
2712     update_fcr31(env, GETPC());
2713     return dt2;
2714 }
2715
2716 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2717 {
2718     uint32_t fst2;
2719     uint32_t fsth2;
2720
2721     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2722     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2723     update_fcr31(env, GETPC());
2724     return ((uint64_t)fsth2 << 32) | fst2;
2725 }
2726
2727 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2728 {
2729     uint32_t wt2;
2730     uint32_t wth2;
2731     int excp, excph;
2732
2733     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2734     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2735     if (excp & (float_flag_overflow | float_flag_invalid)) {
2736         wt2 = FP_TO_INT32_OVERFLOW;
2737     }
2738
2739     set_float_exception_flags(0, &env->active_fpu.fp_status);
2740     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2741     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2742     if (excph & (float_flag_overflow | float_flag_invalid)) {
2743         wth2 = FP_TO_INT32_OVERFLOW;
2744     }
2745
2746     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2747     update_fcr31(env, GETPC());
2748
2749     return ((uint64_t)wth2 << 32) | wt2;
2750 }
2751
2752 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2753 {
2754     uint32_t fst2;
2755
2756     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2757     fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status);
2758     update_fcr31(env, GETPC());
2759     return fst2;
2760 }
2761
2762 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2763 {
2764     uint32_t fst2;
2765
2766     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2767     update_fcr31(env, GETPC());
2768     return fst2;
2769 }
2770
2771 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2772 {
2773     uint32_t fst2;
2774
2775     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2776     update_fcr31(env, GETPC());
2777     return fst2;
2778 }
2779
2780 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2781 {
2782     uint32_t wt2;
2783
2784     wt2 = wt0;
2785     update_fcr31(env, GETPC());
2786     return wt2;
2787 }
2788
2789 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2790 {
2791     uint32_t wt2;
2792
2793     wt2 = wth0;
2794     update_fcr31(env, GETPC());
2795     return wt2;
2796 }
2797
2798 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
2799 {
2800     uint32_t wt2;
2801
2802     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2803     if (get_float_exception_flags(&env->active_fpu.fp_status)
2804         & (float_flag_invalid | float_flag_overflow)) {
2805         wt2 = FP_TO_INT32_OVERFLOW;
2806     }
2807     update_fcr31(env, GETPC());
2808     return wt2;
2809 }
2810
2811 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
2812 {
2813     uint32_t wt2;
2814
2815     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2816     if (get_float_exception_flags(&env->active_fpu.fp_status)
2817         & (float_flag_invalid | float_flag_overflow)) {
2818         wt2 = FP_TO_INT32_OVERFLOW;
2819     }
2820     update_fcr31(env, GETPC());
2821     return wt2;
2822 }
2823
2824 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
2825 {
2826     uint64_t dt2;
2827
2828     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2829     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2830     restore_rounding_mode(env);
2831     if (get_float_exception_flags(&env->active_fpu.fp_status)
2832         & (float_flag_invalid | float_flag_overflow)) {
2833         dt2 = FP_TO_INT64_OVERFLOW;
2834     }
2835     update_fcr31(env, GETPC());
2836     return dt2;
2837 }
2838
2839 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
2840 {
2841     uint64_t dt2;
2842
2843     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2844     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2845     restore_rounding_mode(env);
2846     if (get_float_exception_flags(&env->active_fpu.fp_status)
2847         & (float_flag_invalid | float_flag_overflow)) {
2848         dt2 = FP_TO_INT64_OVERFLOW;
2849     }
2850     update_fcr31(env, GETPC());
2851     return dt2;
2852 }
2853
2854 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
2855 {
2856     uint32_t wt2;
2857
2858     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2859     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2860     restore_rounding_mode(env);
2861     if (get_float_exception_flags(&env->active_fpu.fp_status)
2862         & (float_flag_invalid | float_flag_overflow)) {
2863         wt2 = FP_TO_INT32_OVERFLOW;
2864     }
2865     update_fcr31(env, GETPC());
2866     return wt2;
2867 }
2868
2869 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
2870 {
2871     uint32_t wt2;
2872
2873     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2874     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2875     restore_rounding_mode(env);
2876     if (get_float_exception_flags(&env->active_fpu.fp_status)
2877         & (float_flag_invalid | float_flag_overflow)) {
2878         wt2 = FP_TO_INT32_OVERFLOW;
2879     }
2880     update_fcr31(env, GETPC());
2881     return wt2;
2882 }
2883
2884 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
2885 {
2886     uint64_t dt2;
2887
2888     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2889     if (get_float_exception_flags(&env->active_fpu.fp_status)
2890         & (float_flag_invalid | float_flag_overflow)) {
2891         dt2 = FP_TO_INT64_OVERFLOW;
2892     }
2893     update_fcr31(env, GETPC());
2894     return dt2;
2895 }
2896
2897 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
2898 {
2899     uint64_t dt2;
2900
2901     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2902     if (get_float_exception_flags(&env->active_fpu.fp_status)
2903         & (float_flag_invalid | float_flag_overflow)) {
2904         dt2 = FP_TO_INT64_OVERFLOW;
2905     }
2906     update_fcr31(env, GETPC());
2907     return dt2;
2908 }
2909
2910 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
2911 {
2912     uint32_t wt2;
2913
2914     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2915     if (get_float_exception_flags(&env->active_fpu.fp_status)
2916         & (float_flag_invalid | float_flag_overflow)) {
2917         wt2 = FP_TO_INT32_OVERFLOW;
2918     }
2919     update_fcr31(env, GETPC());
2920     return wt2;
2921 }
2922
2923 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
2924 {
2925     uint32_t wt2;
2926
2927     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2928     if (get_float_exception_flags(&env->active_fpu.fp_status)
2929         & (float_flag_invalid | float_flag_overflow)) {
2930         wt2 = FP_TO_INT32_OVERFLOW;
2931     }
2932     update_fcr31(env, GETPC());
2933     return wt2;
2934 }
2935
2936 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
2937 {
2938     uint64_t dt2;
2939
2940     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2941     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2942     restore_rounding_mode(env);
2943     if (get_float_exception_flags(&env->active_fpu.fp_status)
2944         & (float_flag_invalid | float_flag_overflow)) {
2945         dt2 = FP_TO_INT64_OVERFLOW;
2946     }
2947     update_fcr31(env, GETPC());
2948     return dt2;
2949 }
2950
2951 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
2952 {
2953     uint64_t dt2;
2954
2955     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2956     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2957     restore_rounding_mode(env);
2958     if (get_float_exception_flags(&env->active_fpu.fp_status)
2959         & (float_flag_invalid | float_flag_overflow)) {
2960         dt2 = FP_TO_INT64_OVERFLOW;
2961     }
2962     update_fcr31(env, GETPC());
2963     return dt2;
2964 }
2965
2966 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
2967 {
2968     uint32_t wt2;
2969
2970     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2971     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2972     restore_rounding_mode(env);
2973     if (get_float_exception_flags(&env->active_fpu.fp_status)
2974         & (float_flag_invalid | float_flag_overflow)) {
2975         wt2 = FP_TO_INT32_OVERFLOW;
2976     }
2977     update_fcr31(env, GETPC());
2978     return wt2;
2979 }
2980
2981 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
2982 {
2983     uint32_t wt2;
2984
2985     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2986     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2987     restore_rounding_mode(env);
2988     if (get_float_exception_flags(&env->active_fpu.fp_status)
2989         & (float_flag_invalid | float_flag_overflow)) {
2990         wt2 = FP_TO_INT32_OVERFLOW;
2991     }
2992     update_fcr31(env, GETPC());
2993     return wt2;
2994 }
2995
2996 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
2997 {
2998     uint64_t dt2;
2999
3000     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3001     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3002     restore_rounding_mode(env);
3003     if (get_float_exception_flags(&env->active_fpu.fp_status)
3004         & (float_flag_invalid | float_flag_overflow)) {
3005         dt2 = FP_TO_INT64_OVERFLOW;
3006     }
3007     update_fcr31(env, GETPC());
3008     return dt2;
3009 }
3010
3011 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3012 {
3013     uint64_t dt2;
3014
3015     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3016     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3017     restore_rounding_mode(env);
3018     if (get_float_exception_flags(&env->active_fpu.fp_status)
3019         & (float_flag_invalid | float_flag_overflow)) {
3020         dt2 = FP_TO_INT64_OVERFLOW;
3021     }
3022     update_fcr31(env, GETPC());
3023     return dt2;
3024 }
3025
3026 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3027 {
3028     uint32_t wt2;
3029
3030     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3031     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3032     restore_rounding_mode(env);
3033     if (get_float_exception_flags(&env->active_fpu.fp_status)
3034         & (float_flag_invalid | float_flag_overflow)) {
3035         wt2 = FP_TO_INT32_OVERFLOW;
3036     }
3037     update_fcr31(env, GETPC());
3038     return wt2;
3039 }
3040
3041 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3042 {
3043     uint32_t wt2;
3044
3045     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3046     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3047     restore_rounding_mode(env);
3048     if (get_float_exception_flags(&env->active_fpu.fp_status)
3049         & (float_flag_invalid | float_flag_overflow)) {
3050         wt2 = FP_TO_INT32_OVERFLOW;
3051     }
3052     update_fcr31(env, GETPC());
3053     return wt2;
3054 }
3055
3056 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3057 {
3058     uint64_t dt2;
3059
3060     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3061     if (get_float_exception_flags(&env->active_fpu.fp_status)
3062             & float_flag_invalid) {
3063         if (float64_is_any_nan(fdt0)) {
3064             dt2 = 0;
3065         }
3066     }
3067     update_fcr31(env, GETPC());
3068     return dt2;
3069 }
3070
3071 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3072 {
3073     uint64_t dt2;
3074
3075     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3076     if (get_float_exception_flags(&env->active_fpu.fp_status)
3077             & float_flag_invalid) {
3078         if (float32_is_any_nan(fst0)) {
3079             dt2 = 0;
3080         }
3081     }
3082     update_fcr31(env, GETPC());
3083     return dt2;
3084 }
3085
3086 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3087 {
3088     uint32_t wt2;
3089
3090     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3091     if (get_float_exception_flags(&env->active_fpu.fp_status)
3092             & float_flag_invalid) {
3093         if (float64_is_any_nan(fdt0)) {
3094             wt2 = 0;
3095         }
3096     }
3097     update_fcr31(env, GETPC());
3098     return wt2;
3099 }
3100
3101 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3102 {
3103     uint32_t wt2;
3104
3105     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3106     if (get_float_exception_flags(&env->active_fpu.fp_status)
3107             & float_flag_invalid) {
3108         if (float32_is_any_nan(fst0)) {
3109             wt2 = 0;
3110         }
3111     }
3112     update_fcr31(env, GETPC());
3113     return wt2;
3114 }
3115
3116 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3117 {
3118     uint64_t dt2;
3119
3120     set_float_rounding_mode(float_round_nearest_even,
3121             &env->active_fpu.fp_status);
3122     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3123     restore_rounding_mode(env);
3124     if (get_float_exception_flags(&env->active_fpu.fp_status)
3125             & float_flag_invalid) {
3126         if (float64_is_any_nan(fdt0)) {
3127             dt2 = 0;
3128         }
3129     }
3130     update_fcr31(env, GETPC());
3131     return dt2;
3132 }
3133
3134 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3135 {
3136     uint64_t dt2;
3137
3138     set_float_rounding_mode(float_round_nearest_even,
3139             &env->active_fpu.fp_status);
3140     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3141     restore_rounding_mode(env);
3142     if (get_float_exception_flags(&env->active_fpu.fp_status)
3143             & float_flag_invalid) {
3144         if (float32_is_any_nan(fst0)) {
3145             dt2 = 0;
3146         }
3147     }
3148     update_fcr31(env, GETPC());
3149     return dt2;
3150 }
3151
3152 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3153 {
3154     uint32_t wt2;
3155
3156     set_float_rounding_mode(float_round_nearest_even,
3157             &env->active_fpu.fp_status);
3158     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3159     restore_rounding_mode(env);
3160     if (get_float_exception_flags(&env->active_fpu.fp_status)
3161             & float_flag_invalid) {
3162         if (float64_is_any_nan(fdt0)) {
3163             wt2 = 0;
3164         }
3165     }
3166     update_fcr31(env, GETPC());
3167     return wt2;
3168 }
3169
3170 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3171 {
3172     uint32_t wt2;
3173
3174     set_float_rounding_mode(float_round_nearest_even,
3175             &env->active_fpu.fp_status);
3176     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3177     restore_rounding_mode(env);
3178     if (get_float_exception_flags(&env->active_fpu.fp_status)
3179             & float_flag_invalid) {
3180         if (float32_is_any_nan(fst0)) {
3181             wt2 = 0;
3182         }
3183     }
3184     update_fcr31(env, GETPC());
3185     return wt2;
3186 }
3187
3188 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3189 {
3190     uint64_t dt2;
3191
3192     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3193     if (get_float_exception_flags(&env->active_fpu.fp_status)
3194             & float_flag_invalid) {
3195         if (float64_is_any_nan(fdt0)) {
3196             dt2 = 0;
3197         }
3198     }
3199     update_fcr31(env, GETPC());
3200     return dt2;
3201 }
3202
3203 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3204 {
3205     uint64_t dt2;
3206
3207     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3208     if (get_float_exception_flags(&env->active_fpu.fp_status)
3209             & float_flag_invalid) {
3210         if (float32_is_any_nan(fst0)) {
3211             dt2 = 0;
3212         }
3213     }
3214     update_fcr31(env, GETPC());
3215     return dt2;
3216 }
3217
3218 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3219 {
3220     uint32_t wt2;
3221
3222     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3223     if (get_float_exception_flags(&env->active_fpu.fp_status)
3224             & float_flag_invalid) {
3225         if (float64_is_any_nan(fdt0)) {
3226             wt2 = 0;
3227         }
3228     }
3229     update_fcr31(env, GETPC());
3230     return wt2;
3231 }
3232
3233 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3234 {
3235     uint32_t wt2;
3236
3237     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3238     if (get_float_exception_flags(&env->active_fpu.fp_status)
3239             & float_flag_invalid) {
3240         if (float32_is_any_nan(fst0)) {
3241             wt2 = 0;
3242         }
3243     }
3244     update_fcr31(env, GETPC());
3245     return wt2;
3246 }
3247
3248 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3249 {
3250     uint64_t dt2;
3251
3252     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3253     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3254     restore_rounding_mode(env);
3255     if (get_float_exception_flags(&env->active_fpu.fp_status)
3256             & float_flag_invalid) {
3257         if (float64_is_any_nan(fdt0)) {
3258             dt2 = 0;
3259         }
3260     }
3261     update_fcr31(env, GETPC());
3262     return dt2;
3263 }
3264
3265 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3266 {
3267     uint64_t dt2;
3268
3269     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3270     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3271     restore_rounding_mode(env);
3272     if (get_float_exception_flags(&env->active_fpu.fp_status)
3273             & float_flag_invalid) {
3274         if (float32_is_any_nan(fst0)) {
3275             dt2 = 0;
3276         }
3277     }
3278     update_fcr31(env, GETPC());
3279     return dt2;
3280 }
3281
3282 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3283 {
3284     uint32_t wt2;
3285
3286     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3287     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3288     restore_rounding_mode(env);
3289     if (get_float_exception_flags(&env->active_fpu.fp_status)
3290             & float_flag_invalid) {
3291         if (float64_is_any_nan(fdt0)) {
3292             wt2 = 0;
3293         }
3294     }
3295     update_fcr31(env, GETPC());
3296     return wt2;
3297 }
3298
3299 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3300 {
3301     uint32_t wt2;
3302
3303     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3304     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3305     restore_rounding_mode(env);
3306     if (get_float_exception_flags(&env->active_fpu.fp_status)
3307             & float_flag_invalid) {
3308         if (float32_is_any_nan(fst0)) {
3309             wt2 = 0;
3310         }
3311     }
3312     update_fcr31(env, GETPC());
3313     return wt2;
3314 }
3315
3316 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3317 {
3318     uint64_t dt2;
3319
3320     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3321     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3322     restore_rounding_mode(env);
3323     if (get_float_exception_flags(&env->active_fpu.fp_status)
3324             & float_flag_invalid) {
3325         if (float64_is_any_nan(fdt0)) {
3326             dt2 = 0;
3327         }
3328     }
3329     update_fcr31(env, GETPC());
3330     return dt2;
3331 }
3332
3333 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3334 {
3335     uint64_t dt2;
3336
3337     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3338     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3339     restore_rounding_mode(env);
3340     if (get_float_exception_flags(&env->active_fpu.fp_status)
3341             & float_flag_invalid) {
3342         if (float32_is_any_nan(fst0)) {
3343             dt2 = 0;
3344         }
3345     }
3346     update_fcr31(env, GETPC());
3347     return dt2;
3348 }
3349
3350 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3351 {
3352     uint32_t wt2;
3353
3354     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3355     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3356     restore_rounding_mode(env);
3357     if (get_float_exception_flags(&env->active_fpu.fp_status)
3358             & float_flag_invalid) {
3359         if (float64_is_any_nan(fdt0)) {
3360             wt2 = 0;
3361         }
3362     }
3363     update_fcr31(env, GETPC());
3364     return wt2;
3365 }
3366
3367 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3368 {
3369     uint32_t wt2;
3370
3371     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3372     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3373     restore_rounding_mode(env);
3374     if (get_float_exception_flags(&env->active_fpu.fp_status)
3375             & float_flag_invalid) {
3376         if (float32_is_any_nan(fst0)) {
3377             wt2 = 0;
3378         }
3379     }
3380     update_fcr31(env, GETPC());
3381     return wt2;
3382 }
3383
3384 /* unary operations, not modifying fp status  */
3385 #define FLOAT_UNOP(name)                                       \
3386 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
3387 {                                                              \
3388     return float64_ ## name(fdt0);                             \
3389 }                                                              \
3390 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
3391 {                                                              \
3392     return float32_ ## name(fst0);                             \
3393 }                                                              \
3394 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
3395 {                                                              \
3396     uint32_t wt0;                                              \
3397     uint32_t wth0;                                             \
3398                                                                \
3399     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
3400     wth0 = float32_ ## name(fdt0 >> 32);                       \
3401     return ((uint64_t)wth0 << 32) | wt0;                       \
3402 }
3403 FLOAT_UNOP(abs)
3404 FLOAT_UNOP(chs)
3405 #undef FLOAT_UNOP
3406
3407 /* MIPS specific unary operations */
3408 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3409 {
3410     uint64_t fdt2;
3411
3412     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3413     update_fcr31(env, GETPC());
3414     return fdt2;
3415 }
3416
3417 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3418 {
3419     uint32_t fst2;
3420
3421     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3422     update_fcr31(env, GETPC());
3423     return fst2;
3424 }
3425
3426 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3427 {
3428     uint64_t fdt2;
3429
3430     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3431     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3432     update_fcr31(env, GETPC());
3433     return fdt2;
3434 }
3435
3436 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3437 {
3438     uint32_t fst2;
3439
3440     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3441     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3442     update_fcr31(env, GETPC());
3443     return fst2;
3444 }
3445
3446 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3447 {
3448     uint64_t fdt2;
3449
3450     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3451     update_fcr31(env, GETPC());
3452     return fdt2;
3453 }
3454
3455 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3456 {
3457     uint32_t fst2;
3458
3459     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3460     update_fcr31(env, GETPC());
3461     return fst2;
3462 }
3463
3464 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3465 {
3466     uint32_t fst2;
3467     uint32_t fsth2;
3468
3469     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3470     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3471     update_fcr31(env, GETPC());
3472     return ((uint64_t)fsth2 << 32) | fst2;
3473 }
3474
3475 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3476 {
3477     uint64_t fdt2;
3478
3479     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3480     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3481     update_fcr31(env, GETPC());
3482     return fdt2;
3483 }
3484
3485 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3486 {
3487     uint32_t fst2;
3488
3489     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3490     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3491     update_fcr31(env, GETPC());
3492     return fst2;
3493 }
3494
3495 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3496 {
3497     uint32_t fst2;
3498     uint32_t fsth2;
3499
3500     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3501     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3502     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3503     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3504     update_fcr31(env, GETPC());
3505     return ((uint64_t)fsth2 << 32) | fst2;
3506 }
3507
3508 #define FLOAT_RINT(name, bits)                                              \
3509 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3510                                           uint ## bits ## _t fs)            \
3511 {                                                                           \
3512     uint ## bits ## _t fdret;                                               \
3513                                                                             \
3514     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3515     update_fcr31(env, GETPC());                                             \
3516     return fdret;                                                           \
3517 }
3518
3519 FLOAT_RINT(rint_s, 32)
3520 FLOAT_RINT(rint_d, 64)
3521 #undef FLOAT_RINT
3522
3523 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3524 #define FLOAT_CLASS_QUIET_NAN          0x002
3525 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3526 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3527 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3528 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3529 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3530 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3531 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3532 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3533
3534 #define FLOAT_CLASS(name, bits)                                      \
3535 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg,           \
3536                                    float_status *status)             \
3537 {                                                                    \
3538     if (float ## bits ## _is_signaling_nan(arg, status)) {           \
3539         return FLOAT_CLASS_SIGNALING_NAN;                            \
3540     } else if (float ## bits ## _is_quiet_nan(arg, status)) {        \
3541         return FLOAT_CLASS_QUIET_NAN;                                \
3542     } else if (float ## bits ## _is_neg(arg)) {                      \
3543         if (float ## bits ## _is_infinity(arg)) {                    \
3544             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3545         } else if (float ## bits ## _is_zero(arg)) {                 \
3546             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3547         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3548             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3549         } else {                                                     \
3550             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3551         }                                                            \
3552     } else {                                                         \
3553         if (float ## bits ## _is_infinity(arg)) {                    \
3554             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3555         } else if (float ## bits ## _is_zero(arg)) {                 \
3556             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3557         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3558             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3559         } else {                                                     \
3560             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3561         }                                                            \
3562     }                                                                \
3563 }                                                                    \
3564                                                                      \
3565 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,         \
3566                                           uint ## bits ## _t arg)    \
3567 {                                                                    \
3568     return float_ ## name(arg, &env->active_fpu.fp_status);          \
3569 }
3570
3571 FLOAT_CLASS(class_s, 32)
3572 FLOAT_CLASS(class_d, 64)
3573 #undef FLOAT_CLASS
3574
3575 /* binary operations */
3576 #define FLOAT_BINOP(name)                                          \
3577 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3578                                      uint64_t fdt0, uint64_t fdt1) \
3579 {                                                                  \
3580     uint64_t dt2;                                                  \
3581                                                                    \
3582     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3583     update_fcr31(env, GETPC());                                    \
3584     return dt2;                                                    \
3585 }                                                                  \
3586                                                                    \
3587 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3588                                      uint32_t fst0, uint32_t fst1) \
3589 {                                                                  \
3590     uint32_t wt2;                                                  \
3591                                                                    \
3592     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3593     update_fcr31(env, GETPC());                                    \
3594     return wt2;                                                    \
3595 }                                                                  \
3596                                                                    \
3597 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3598                                       uint64_t fdt0,               \
3599                                       uint64_t fdt1)               \
3600 {                                                                  \
3601     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3602     uint32_t fsth0 = fdt0 >> 32;                                   \
3603     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3604     uint32_t fsth1 = fdt1 >> 32;                                   \
3605     uint32_t wt2;                                                  \
3606     uint32_t wth2;                                                 \
3607                                                                    \
3608     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3609     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3610     update_fcr31(env, GETPC());                                    \
3611     return ((uint64_t)wth2 << 32) | wt2;                           \
3612 }
3613
3614 FLOAT_BINOP(add)
3615 FLOAT_BINOP(sub)
3616 FLOAT_BINOP(mul)
3617 FLOAT_BINOP(div)
3618 #undef FLOAT_BINOP
3619
3620 /* MIPS specific binary operations */
3621 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3622 {
3623     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3624     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3625     update_fcr31(env, GETPC());
3626     return fdt2;
3627 }
3628
3629 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3630 {
3631     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3632     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3633     update_fcr31(env, GETPC());
3634     return fst2;
3635 }
3636
3637 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3638 {
3639     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3640     uint32_t fsth0 = fdt0 >> 32;
3641     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3642     uint32_t fsth2 = fdt2 >> 32;
3643
3644     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3645     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3646     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3647     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3648     update_fcr31(env, GETPC());
3649     return ((uint64_t)fsth2 << 32) | fst2;
3650 }
3651
3652 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3653 {
3654     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3655     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3656     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3657     update_fcr31(env, GETPC());
3658     return fdt2;
3659 }
3660
3661 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3662 {
3663     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3664     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3665     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3666     update_fcr31(env, GETPC());
3667     return fst2;
3668 }
3669
3670 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3671 {
3672     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3673     uint32_t fsth0 = fdt0 >> 32;
3674     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3675     uint32_t fsth2 = fdt2 >> 32;
3676
3677     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3678     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3679     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3680     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3681     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3682     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3683     update_fcr31(env, GETPC());
3684     return ((uint64_t)fsth2 << 32) | fst2;
3685 }
3686
3687 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3688 {
3689     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3690     uint32_t fsth0 = fdt0 >> 32;
3691     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3692     uint32_t fsth1 = fdt1 >> 32;
3693     uint32_t fst2;
3694     uint32_t fsth2;
3695
3696     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3697     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3698     update_fcr31(env, GETPC());
3699     return ((uint64_t)fsth2 << 32) | fst2;
3700 }
3701
3702 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3703 {
3704     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3705     uint32_t fsth0 = fdt0 >> 32;
3706     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3707     uint32_t fsth1 = fdt1 >> 32;
3708     uint32_t fst2;
3709     uint32_t fsth2;
3710
3711     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3712     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3713     update_fcr31(env, GETPC());
3714     return ((uint64_t)fsth2 << 32) | fst2;
3715 }
3716
3717 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3718 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3719                                           uint ## bits ## _t fs,        \
3720                                           uint ## bits ## _t ft)        \
3721 {                                                                       \
3722     uint ## bits ## _t fdret;                                           \
3723                                                                         \
3724     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3725                                            &env->active_fpu.fp_status); \
3726     update_fcr31(env, GETPC());                                         \
3727     return fdret;                                                       \
3728 }
3729
3730 FLOAT_MINMAX(max_s, 32, maxnum)
3731 FLOAT_MINMAX(max_d, 64, maxnum)
3732 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3733 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3734
3735 FLOAT_MINMAX(min_s, 32, minnum)
3736 FLOAT_MINMAX(min_d, 64, minnum)
3737 FLOAT_MINMAX(mina_s, 32, minnummag)
3738 FLOAT_MINMAX(mina_d, 64, minnummag)
3739 #undef FLOAT_MINMAX
3740
3741 /* ternary operations */
3742 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3743 {                                                                    \
3744     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3745     if ((flags) & float_muladd_negate_c) {                           \
3746         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3747     } else {                                                         \
3748         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3749     }                                                                \
3750     if ((flags) & float_muladd_negate_result) {                      \
3751         a = prefix##_chs(a);                                         \
3752     }                                                                \
3753 }
3754
3755 /* FMA based operations */
3756 #define FLOAT_FMA(name, type)                                        \
3757 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3758                                      uint64_t fdt0, uint64_t fdt1,   \
3759                                      uint64_t fdt2)                  \
3760 {                                                                    \
3761     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3762     update_fcr31(env, GETPC());                                      \
3763     return fdt0;                                                     \
3764 }                                                                    \
3765                                                                      \
3766 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3767                                      uint32_t fst0, uint32_t fst1,   \
3768                                      uint32_t fst2)                  \
3769 {                                                                    \
3770     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3771     update_fcr31(env, GETPC());                                      \
3772     return fst0;                                                     \
3773 }                                                                    \
3774                                                                      \
3775 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3776                                       uint64_t fdt0, uint64_t fdt1,  \
3777                                       uint64_t fdt2)                 \
3778 {                                                                    \
3779     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3780     uint32_t fsth0 = fdt0 >> 32;                                     \
3781     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3782     uint32_t fsth1 = fdt1 >> 32;                                     \
3783     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3784     uint32_t fsth2 = fdt2 >> 32;                                     \
3785                                                                      \
3786     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3787     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3788     update_fcr31(env, GETPC());                                      \
3789     return ((uint64_t)fsth0 << 32) | fst0;                           \
3790 }
3791 FLOAT_FMA(madd, 0)
3792 FLOAT_FMA(msub, float_muladd_negate_c)
3793 FLOAT_FMA(nmadd, float_muladd_negate_result)
3794 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3795 #undef FLOAT_FMA
3796
3797 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3798 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3799                                           uint ## bits ## _t fs,        \
3800                                           uint ## bits ## _t ft,        \
3801                                           uint ## bits ## _t fd)        \
3802 {                                                                       \
3803     uint ## bits ## _t fdret;                                           \
3804                                                                         \
3805     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3806                                      &env->active_fpu.fp_status);       \
3807     update_fcr31(env, GETPC());                                         \
3808     return fdret;                                                       \
3809 }
3810
3811 FLOAT_FMADDSUB(maddf_s, 32, 0)
3812 FLOAT_FMADDSUB(maddf_d, 64, 0)
3813 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3814 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3815 #undef FLOAT_FMADDSUB
3816
3817 /* compare operations */
3818 #define FOP_COND_D(op, cond)                                   \
3819 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3820                          uint64_t fdt1, int cc)                \
3821 {                                                              \
3822     int c;                                                     \
3823     c = cond;                                                  \
3824     update_fcr31(env, GETPC());                                \
3825     if (c)                                                     \
3826         SET_FP_COND(cc, env->active_fpu);                      \
3827     else                                                       \
3828         CLEAR_FP_COND(cc, env->active_fpu);                    \
3829 }                                                              \
3830 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3831                             uint64_t fdt1, int cc)             \
3832 {                                                              \
3833     int c;                                                     \
3834     fdt0 = float64_abs(fdt0);                                  \
3835     fdt1 = float64_abs(fdt1);                                  \
3836     c = cond;                                                  \
3837     update_fcr31(env, GETPC());                                \
3838     if (c)                                                     \
3839         SET_FP_COND(cc, env->active_fpu);                      \
3840     else                                                       \
3841         CLEAR_FP_COND(cc, env->active_fpu);                    \
3842 }
3843
3844 /* NOTE: the comma operator will make "cond" to eval to false,
3845  * but float64_unordered_quiet() is still called. */
3846 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3847 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3848 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3849 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3850 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3851 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3852 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3853 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3854 /* NOTE: the comma operator will make "cond" to eval to false,
3855  * but float64_unordered() is still called. */
3856 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3857 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3858 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3859 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3860 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3861 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3862 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3863 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3864
3865 #define FOP_COND_S(op, cond)                                   \
3866 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3867                          uint32_t fst1, int cc)                \
3868 {                                                              \
3869     int c;                                                     \
3870     c = cond;                                                  \
3871     update_fcr31(env, GETPC());                                \
3872     if (c)                                                     \
3873         SET_FP_COND(cc, env->active_fpu);                      \
3874     else                                                       \
3875         CLEAR_FP_COND(cc, env->active_fpu);                    \
3876 }                                                              \
3877 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3878                             uint32_t fst1, int cc)             \
3879 {                                                              \
3880     int c;                                                     \
3881     fst0 = float32_abs(fst0);                                  \
3882     fst1 = float32_abs(fst1);                                  \
3883     c = cond;                                                  \
3884     update_fcr31(env, GETPC());                                \
3885     if (c)                                                     \
3886         SET_FP_COND(cc, env->active_fpu);                      \
3887     else                                                       \
3888         CLEAR_FP_COND(cc, env->active_fpu);                    \
3889 }
3890
3891 /* NOTE: the comma operator will make "cond" to eval to false,
3892  * but float32_unordered_quiet() is still called. */
3893 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3894 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3895 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3896 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3897 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3898 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3899 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3900 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3901 /* NOTE: the comma operator will make "cond" to eval to false,
3902  * but float32_unordered() is still called. */
3903 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3904 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3905 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3906 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3907 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3908 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3909 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3910 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3911
3912 #define FOP_COND_PS(op, condl, condh)                           \
3913 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3914                           uint64_t fdt1, int cc)                \
3915 {                                                               \
3916     uint32_t fst0, fsth0, fst1, fsth1;                          \
3917     int ch, cl;                                                 \
3918     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3919     fsth0 = fdt0 >> 32;                                         \
3920     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3921     fsth1 = fdt1 >> 32;                                         \
3922     cl = condl;                                                 \
3923     ch = condh;                                                 \
3924     update_fcr31(env, GETPC());                                 \
3925     if (cl)                                                     \
3926         SET_FP_COND(cc, env->active_fpu);                       \
3927     else                                                        \
3928         CLEAR_FP_COND(cc, env->active_fpu);                     \
3929     if (ch)                                                     \
3930         SET_FP_COND(cc + 1, env->active_fpu);                   \
3931     else                                                        \
3932         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3933 }                                                               \
3934 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3935                              uint64_t fdt1, int cc)             \
3936 {                                                               \
3937     uint32_t fst0, fsth0, fst1, fsth1;                          \
3938     int ch, cl;                                                 \
3939     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3940     fsth0 = float32_abs(fdt0 >> 32);                            \
3941     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3942     fsth1 = float32_abs(fdt1 >> 32);                            \
3943     cl = condl;                                                 \
3944     ch = condh;                                                 \
3945     update_fcr31(env, GETPC());                                 \
3946     if (cl)                                                     \
3947         SET_FP_COND(cc, env->active_fpu);                       \
3948     else                                                        \
3949         CLEAR_FP_COND(cc, env->active_fpu);                     \
3950     if (ch)                                                     \
3951         SET_FP_COND(cc + 1, env->active_fpu);                   \
3952     else                                                        \
3953         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3954 }
3955
3956 /* NOTE: the comma operator will make "cond" to eval to false,
3957  * but float32_unordered_quiet() is still called. */
3958 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3959                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3960 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3961                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3962 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3963                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3964 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3965                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3966 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3967                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3968 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3969                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3970 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3971                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3972 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3973                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3974 /* NOTE: the comma operator will make "cond" to eval to false,
3975  * but float32_unordered() is still called. */
3976 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3977                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3978 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3979                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3980 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3981                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3982 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3983                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3984 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3985                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3986 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3987                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3988 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3989                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3990 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3991                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3992
3993 /* R6 compare operations */
3994 #define FOP_CONDN_D(op, cond)                                       \
3995 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3996                          uint64_t fdt1)                             \
3997 {                                                                   \
3998     uint64_t c;                                                     \
3999     c = cond;                                                       \
4000     update_fcr31(env, GETPC());                                     \
4001     if (c) {                                                        \
4002         return -1;                                                  \
4003     } else {                                                        \
4004         return 0;                                                   \
4005     }                                                               \
4006 }
4007
4008 /* NOTE: the comma operator will make "cond" to eval to false,
4009  * but float64_unordered_quiet() is still called. */
4010 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4011 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4012 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4013 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4014                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4015 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4016 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4017                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4018 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4019 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4020                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4021 /* NOTE: the comma operator will make "cond" to eval to false,
4022  * but float64_unordered() is still called. */
4023 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4024 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4025 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4026 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4027                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4028 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4029 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4030                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4031 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4032 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4033                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4034 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4035                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4036 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4037                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4038                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4039 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4040                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4041 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4042                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4043 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4044                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4045                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4046 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4047                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4048
4049 #define FOP_CONDN_S(op, cond)                                       \
4050 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
4051                          uint32_t fst1)                             \
4052 {                                                                   \
4053     uint64_t c;                                                     \
4054     c = cond;                                                       \
4055     update_fcr31(env, GETPC());                                     \
4056     if (c) {                                                        \
4057         return -1;                                                  \
4058     } else {                                                        \
4059         return 0;                                                   \
4060     }                                                               \
4061 }
4062
4063 /* NOTE: the comma operator will make "cond" to eval to false,
4064  * but float32_unordered_quiet() is still called. */
4065 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4066 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4067 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4068 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4069                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4070 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4071 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4072                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4073 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4074 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4075                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4076 /* NOTE: the comma operator will make "cond" to eval to false,
4077  * but float32_unordered() is still called. */
4078 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4079 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4080 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4081 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4082                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4083 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4084 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4085                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4086 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4087 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4088                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4089 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4090                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4091 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4092                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4093                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4094 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4095                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4096 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4097                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4098 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4099                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4100                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4101 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4102                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4103
4104 /* MSA */
4105 /* Data format min and max values */
4106 #define DF_BITS(df) (1 << ((df) + 3))
4107
4108 /* Element-by-element access macros */
4109 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4110
4111 #if !defined(CONFIG_USER_ONLY)
4112 #define MEMOP_IDX(DF)                                           \
4113         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
4114                                         cpu_mmu_index(env, false));
4115 #else
4116 #define MEMOP_IDX(DF)
4117 #endif
4118
4119 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
4120 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
4121                             target_ulong addr)                          \
4122 {                                                                       \
4123     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
4124     wr_t wx;                                                            \
4125     int i;                                                              \
4126     MEMOP_IDX(DF)                                                       \
4127     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
4128         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
4129     }                                                                   \
4130     memcpy(pwd, &wx, sizeof(wr_t));                                     \
4131 }
4132
4133 #if !defined(CONFIG_USER_ONLY)
4134 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
4135 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
4136 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
4137 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
4138 #else
4139 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
4140 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
4141 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
4142 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
4143 #endif
4144
4145 #define MSA_PAGESPAN(x) \
4146         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4147
4148 static inline void ensure_writable_pages(CPUMIPSState *env,
4149                                          target_ulong addr,
4150                                          int mmu_idx,
4151                                          uintptr_t retaddr)
4152 {
4153 #if !defined(CONFIG_USER_ONLY)
4154     target_ulong page_addr;
4155     if (unlikely(MSA_PAGESPAN(addr))) {
4156         /* first page */
4157         probe_write(env, addr, mmu_idx, retaddr);
4158         /* second page */
4159         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4160         probe_write(env, page_addr, mmu_idx, retaddr);
4161     }
4162 #endif
4163 }
4164
4165 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
4166 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
4167                             target_ulong addr)                          \
4168 {                                                                       \
4169     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
4170     int mmu_idx = cpu_mmu_index(env, false);                            \
4171     int i;                                                              \
4172     MEMOP_IDX(DF)                                                       \
4173     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
4174     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
4175         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
4176     }                                                                   \
4177 }
4178
4179 #if !defined(CONFIG_USER_ONLY)
4180 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
4181 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
4182 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
4183 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
4184 #else
4185 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
4186 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
4187 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
4188 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
4189 #endif
4190
4191 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4192 {
4193 #ifndef CONFIG_USER_ONLY
4194     target_ulong index = addr & 0x1fffffff;
4195     if (op == 9) {
4196         /* Index Store Tag */
4197         memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4198                                      8, MEMTXATTRS_UNSPECIFIED);
4199     } else if (op == 5) {
4200         /* Index Load Tag */
4201         memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4202                                     8, MEMTXATTRS_UNSPECIFIED);
4203     }
4204 #endif
4205 }