target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20
  21 #include "cpu.h"
  22 #include "sysemu/kvm.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "exec/log.h"
  26
  27 enum {
  28     TLBRET_XI = -6,
  29     TLBRET_RI = -5,
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ;
  45     if (rw) {
  46         *prot |= PAGE_WRITE;
  47     }
  48     return TLBRET_MATCH;
  49 }
  50
  51 /* fixed mapping MMU emulation */
  52 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  53                            target_ulong address, int rw, int access_type)
  54 {
  55     if (address <= (int32_t)0x7FFFFFFFUL) {
  56         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  57             *physical = address + 0x40000000UL;
  58         else
  59             *physical = address;
  60     } else if (address <= (int32_t)0xBFFFFFFFUL)
  61         *physical = address & 0x1FFFFFFF;
  62     else
  63         *physical = address;
  64
  65     *prot = PAGE_READ;
  66     if (rw) {
  67         *prot |= PAGE_WRITE;
  68     }
  69     return TLBRET_MATCH;
  70 }
  71
  72 /* MIPS32/MIPS64 R4000-style MMU emulation */
  73 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  74                      target_ulong address, int rw, int access_type)
  75 {
  76     uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
  77     int i;
  78
  79     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  80         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  81         /* 1k pages are not supported. */
  82         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  83         target_ulong tag = address & ~mask;
  84         target_ulong VPN = tlb->VPN & ~mask;
  85 #if defined(TARGET_MIPS64)
  86         tag &= env->SEGMask;
  87 #endif
  88
  89         /* Check ASID, virtual page number & size */
  90         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
  91             /* TLB match */
  92             int n = !!(address & mask & ~(mask >> 1));
  93             /* Check access rights */
  94             if (!(n ? tlb->V1 : tlb->V0)) {
  95                 return TLBRET_INVALID;
  96             }
  97             if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
  98                 return TLBRET_XI;
  99             }
 100             if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
 101                 return TLBRET_RI;
 102             }
 103             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
 104                 *physical = tlb->PFN[n] | (address & (mask >> 1));
 105                 *prot = PAGE_READ;
 106                 if (n ? tlb->D1 : tlb->D0)
 107                     *prot |= PAGE_WRITE;
 108                 return TLBRET_MATCH;
 109             }
 110             return TLBRET_DIRTY;
 111         }
 112     }
 113     return TLBRET_NOMATCH;
 114 }
 115
 116 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 117                                 int *prot, target_ulong real_address,
 118                                 int rw, int access_type)
 119 {
 120     /* User mode can only access useg/xuseg */
 121     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 122     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 123     int kernel_mode = !user_mode && !supervisor_mode;
 124 #if defined(TARGET_MIPS64)
 125     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 126     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 127     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 128 #endif
 129     int ret = TLBRET_MATCH;
 130     /* effective address (modified for KVM T&E kernel segments) */
 131     target_ulong address = real_address;
 132
 133 #define USEG_LIMIT      0x7FFFFFFFUL
 134 #define KSEG0_BASE      0x80000000UL
 135 #define KSEG1_BASE      0xA0000000UL
 136 #define KSEG2_BASE      0xC0000000UL
 137 #define KSEG3_BASE      0xE0000000UL
 138
 139 #define KVM_KSEG0_BASE  0x40000000UL
 140 #define KVM_KSEG2_BASE  0x60000000UL
 141
 142     if (kvm_enabled()) {
 143         /* KVM T&E adds guest kernel segments in useg */
 144         if (real_address >= KVM_KSEG0_BASE) {
 145             if (real_address < KVM_KSEG2_BASE) {
 146                 /* kseg0 */
 147                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 148             } else if (real_address <= USEG_LIMIT) {
 149                 /* kseg2/3 */
 150                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 151             }
 152         }
 153     }
 154
 155     if (address <= USEG_LIMIT) {
 156         /* useg */
 157         if (env->CP0_Status & (1 << CP0St_ERL)) {
 158             *physical = address & 0xFFFFFFFF;
 159             *prot = PAGE_READ;
 160             if (rw) {
 161                 *prot |= PAGE_WRITE;
 162             }
 163         } else {
 164             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 165         }
 166 #if defined(TARGET_MIPS64)
 167     } else if (address < 0x4000000000000000ULL) {
 168         /* xuseg */
 169         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 170             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 171         } else {
 172             ret = TLBRET_BADADDR;
 173         }
 174     } else if (address < 0x8000000000000000ULL) {
 175         /* xsseg */
 176         if ((supervisor_mode || kernel_mode) &&
 177             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 178             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 179         } else {
 180             ret = TLBRET_BADADDR;
 181         }
 182     } else if (address < 0xC000000000000000ULL) {
 183         /* xkphys */
 184         if (kernel_mode && KX &&
 185             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 186             *physical = address & env->PAMask;
 187             *prot = PAGE_READ;
 188             if (rw) {
 189                 *prot |= PAGE_WRITE;
 190             }
 191         } else {
 192             ret = TLBRET_BADADDR;
 193         }
 194     } else if (address < 0xFFFFFFFF80000000ULL) {
 195         /* xkseg */
 196         if (kernel_mode && KX &&
 197             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 198             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 199         } else {
 200             ret = TLBRET_BADADDR;
 201         }
 202 #endif
 203     } else if (address < (int32_t)KSEG1_BASE) {
 204         /* kseg0 */
 205         if (kernel_mode) {
 206             *physical = address - (int32_t)KSEG0_BASE;
 207             *prot = PAGE_READ;
 208             if (rw) {
 209                 *prot |= PAGE_WRITE;
 210             }
 211         } else {
 212             ret = TLBRET_BADADDR;
 213         }
 214     } else if (address < (int32_t)KSEG2_BASE) {
 215         /* kseg1 */
 216         if (kernel_mode) {
 217             *physical = address - (int32_t)KSEG1_BASE;
 218             *prot = PAGE_READ;
 219             if (rw) {
 220                 *prot |= PAGE_WRITE;
 221             }
 222         } else {
 223             ret = TLBRET_BADADDR;
 224         }
 225     } else if (address < (int32_t)KSEG3_BASE) {
 226         /* sseg (kseg2) */
 227         if (supervisor_mode || kernel_mode) {
 228             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 229         } else {
 230             ret = TLBRET_BADADDR;
 231         }
 232     } else {
 233         /* kseg3 */
 234         /* XXX: debug segment is not emulated */
 235         if (kernel_mode) {
 236             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 237         } else {
 238             ret = TLBRET_BADADDR;
 239         }
 240     }
 241     return ret;
 242 }
 243
 244 void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
 245 {
 246     MIPSCPU *cpu = mips_env_get_cpu(env);
 247
 248     /* Flush qemu's TLB and discard all shadowed entries.  */
 249     tlb_flush(CPU(cpu), flush_global);
 250     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 251 }
 252
 253 /* Called for updates to CP0_Status.  */
 254 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 255 {
 256     int32_t tcstatus, *tcst;
 257     uint32_t v = cpu->CP0_Status;
 258     uint32_t cu, mx, asid, ksu;
 259     uint32_t mask = ((1 << CP0TCSt_TCU3)
 260                        | (1 << CP0TCSt_TCU2)
 261                        | (1 << CP0TCSt_TCU1)
 262                        | (1 << CP0TCSt_TCU0)
 263                        | (1 << CP0TCSt_TMX)
 264                        | (3 << CP0TCSt_TKSU)
 265                        | (0xff << CP0TCSt_TASID));
 266
 267     cu = (v >> CP0St_CU0) & 0xf;
 268     mx = (v >> CP0St_MX) & 0x1;
 269     ksu = (v >> CP0St_KSU) & 0x3;
 270     asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 271
 272     tcstatus = cu << CP0TCSt_TCU0;
 273     tcstatus |= mx << CP0TCSt_TMX;
 274     tcstatus |= ksu << CP0TCSt_TKSU;
 275     tcstatus |= asid;
 276
 277     if (tc == cpu->current_tc) {
 278         tcst = &cpu->active_tc.CP0_TCStatus;
 279     } else {
 280         tcst = &cpu->tcs[tc].CP0_TCStatus;
 281     }
 282
 283     *tcst &= ~mask;
 284     *tcst |= tcstatus;
 285     compute_hflags(cpu);
 286 }
 287
 288 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
 289 {
 290     uint32_t mask = env->CP0_Status_rw_bitmask;
 291     target_ulong old = env->CP0_Status;
 292
 293     if (env->insn_flags & ISA_MIPS32R6) {
 294         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
 295 #if defined(TARGET_MIPS64)
 296         uint32_t ksux = (1 << CP0St_KX) & val;
 297         ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
 298         ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
 299         val = (val & ~(7 << CP0St_UX)) | ksux;
 300 #endif
 301         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
 302             mask &= ~(3 << CP0St_KSU);
 303         }
 304         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
 305     }
 306
 307     env->CP0_Status = (old & ~mask) | (val & mask);
 308 #if defined(TARGET_MIPS64)
 309     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
 310         /* Access to at least one of the 64-bit segments has been disabled */
 311         cpu_mips_tlb_flush(env, 1);
 312     }
 313 #endif
 314     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
 315         sync_c0_status(env, env, env->current_tc);
 316     } else {
 317         compute_hflags(env);
 318     }
 319 }
 320
 321 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
 322 {
 323     uint32_t mask = 0x00C00300;
 324     uint32_t old = env->CP0_Cause;
 325     int i;
 326
 327     if (env->insn_flags & ISA_MIPS32R2) {
 328         mask |= 1 << CP0Ca_DC;
 329     }
 330     if (env->insn_flags & ISA_MIPS32R6) {
 331         mask &= ~((1 << CP0Ca_WP) & val);
 332     }
 333
 334     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
 335
 336     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
 337         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 338             cpu_mips_stop_count(env);
 339         } else {
 340             cpu_mips_start_count(env);
 341         }
 342     }
 343
 344     /* Set/reset software interrupts */
 345     for (i = 0 ; i < 2 ; i++) {
 346         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
 347             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
 348         }
 349     }
 350 }
 351 #endif
 352
 353 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 354                                 int rw, int tlb_error)
 355 {
 356     CPUState *cs = CPU(mips_env_get_cpu(env));
 357     int exception = 0, error_code = 0;
 358
 359     if (rw == MMU_INST_FETCH) {
 360         error_code |= EXCP_INST_NOTAVAIL;
 361     }
 362
 363     switch (tlb_error) {
 364     default:
 365     case TLBRET_BADADDR:
 366         /* Reference to kernel address from user mode or supervisor mode */
 367         /* Reference to supervisor address from user mode */
 368         if (rw == MMU_DATA_STORE) {
 369             exception = EXCP_AdES;
 370         } else {
 371             exception = EXCP_AdEL;
 372         }
 373         break;
 374     case TLBRET_NOMATCH:
 375         /* No TLB match for a mapped address */
 376         if (rw == MMU_DATA_STORE) {
 377             exception = EXCP_TLBS;
 378         } else {
 379             exception = EXCP_TLBL;
 380         }
 381         error_code |= EXCP_TLB_NOMATCH;
 382         break;
 383     case TLBRET_INVALID:
 384         /* TLB match with no valid bit */
 385         if (rw == MMU_DATA_STORE) {
 386             exception = EXCP_TLBS;
 387         } else {
 388             exception = EXCP_TLBL;
 389         }
 390         break;
 391     case TLBRET_DIRTY:
 392         /* TLB match but 'D' bit is cleared */
 393         exception = EXCP_LTLBL;
 394         break;
 395     case TLBRET_XI:
 396         /* Execute-Inhibit Exception */
 397         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 398             exception = EXCP_TLBXI;
 399         } else {
 400             exception = EXCP_TLBL;
 401         }
 402         break;
 403     case TLBRET_RI:
 404         /* Read-Inhibit Exception */
 405         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 406             exception = EXCP_TLBRI;
 407         } else {
 408             exception = EXCP_TLBL;
 409         }
 410         break;
 411     }
 412     /* Raise exception */
 413     env->CP0_BadVAddr = address;
 414     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 415                        ((address >> 9) & 0x007ffff0);
 416     env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
 417                        (address & (TARGET_PAGE_MASK << 1));
 418 #if defined(TARGET_MIPS64)
 419     env->CP0_EntryHi &= env->SEGMask;
 420     env->CP0_XContext =
 421         /* PTEBase */   (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 422         /* R */         (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
 423         /* BadVPN2 */   (extract64(address, 13, env->SEGBITS - 13) << 4);
 424 #endif
 425     cs->exception_index = exception;
 426     env->error_code = error_code;
 427 }
 428
 429 #if !defined(CONFIG_USER_ONLY)
 430 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 431 {
 432     MIPSCPU *cpu = MIPS_CPU(cs);
 433     hwaddr phys_addr;
 434     int prot;
 435
 436     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 437                              ACCESS_INT) != 0) {
 438         return -1;
 439     }
 440     return phys_addr;
 441 }
 442 #endif
 443
 444 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 445                               int mmu_idx)
 446 {
 447     MIPSCPU *cpu = MIPS_CPU(cs);
 448     CPUMIPSState *env = &cpu->env;
 449 #if !defined(CONFIG_USER_ONLY)
 450     hwaddr physical;
 451     int prot;
 452     int access_type;
 453 #endif
 454     int ret = 0;
 455
 456 #if 0
 457     log_cpu_state(cs, 0);
 458 #endif
 459     qemu_log_mask(CPU_LOG_MMU,
 460               "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 461               __func__, env->active_tc.PC, address, rw, mmu_idx);
 462
 463     /* data access */
 464 #if !defined(CONFIG_USER_ONLY)
 465     /* XXX: put correct access by using cpu_restore_state()
 466        correctly */
 467     access_type = ACCESS_INT;
 468     ret = get_physical_address(env, &physical, &prot,
 469                                address, rw, access_type);
 470     qemu_log_mask(CPU_LOG_MMU,
 471              "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 472              " prot %d\n",
 473              __func__, address, ret, physical, prot);
 474     if (ret == TLBRET_MATCH) {
 475         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 476                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 477                      mmu_idx, TARGET_PAGE_SIZE);
 478         ret = 0;
 479     } else if (ret < 0)
 480 #endif
 481     {
 482         raise_mmu_exception(env, address, rw, ret);
 483         ret = 1;
 484     }
 485
 486     return ret;
 487 }
 488
 489 #if !defined(CONFIG_USER_ONLY)
 490 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 491 {
 492     hwaddr physical;
 493     int prot;
 494     int access_type;
 495     int ret = 0;
 496
 497     /* data access */
 498     access_type = ACCESS_INT;
 499     ret = get_physical_address(env, &physical, &prot,
 500                                address, rw, access_type);
 501     if (ret != TLBRET_MATCH) {
 502         raise_mmu_exception(env, address, rw, ret);
 503         return -1LL;
 504     } else {
 505         return physical;
 506     }
 507 }
 508
 509 static const char * const excp_names[EXCP_LAST + 1] = {
 510     [EXCP_RESET] = "reset",
 511     [EXCP_SRESET] = "soft reset",
 512     [EXCP_DSS] = "debug single step",
 513     [EXCP_DINT] = "debug interrupt",
 514     [EXCP_NMI] = "non-maskable interrupt",
 515     [EXCP_MCHECK] = "machine check",
 516     [EXCP_EXT_INTERRUPT] = "interrupt",
 517     [EXCP_DFWATCH] = "deferred watchpoint",
 518     [EXCP_DIB] = "debug instruction breakpoint",
 519     [EXCP_IWATCH] = "instruction fetch watchpoint",
 520     [EXCP_AdEL] = "address error load",
 521     [EXCP_AdES] = "address error store",
 522     [EXCP_TLBF] = "TLB refill",
 523     [EXCP_IBE] = "instruction bus error",
 524     [EXCP_DBp] = "debug breakpoint",
 525     [EXCP_SYSCALL] = "syscall",
 526     [EXCP_BREAK] = "break",
 527     [EXCP_CpU] = "coprocessor unusable",
 528     [EXCP_RI] = "reserved instruction",
 529     [EXCP_OVERFLOW] = "arithmetic overflow",
 530     [EXCP_TRAP] = "trap",
 531     [EXCP_FPE] = "floating point",
 532     [EXCP_DDBS] = "debug data break store",
 533     [EXCP_DWATCH] = "data watchpoint",
 534     [EXCP_LTLBL] = "TLB modify",
 535     [EXCP_TLBL] = "TLB load",
 536     [EXCP_TLBS] = "TLB store",
 537     [EXCP_DBE] = "data bus error",
 538     [EXCP_DDBL] = "debug data break load",
 539     [EXCP_THREAD] = "thread",
 540     [EXCP_MDMX] = "MDMX",
 541     [EXCP_C2E] = "precise coprocessor 2",
 542     [EXCP_CACHE] = "cache error",
 543     [EXCP_TLBXI] = "TLB execute-inhibit",
 544     [EXCP_TLBRI] = "TLB read-inhibit",
 545     [EXCP_MSADIS] = "MSA disabled",
 546     [EXCP_MSAFPE] = "MSA floating point",
 547 };
 548 #endif
 549
 550 target_ulong exception_resume_pc (CPUMIPSState *env)
 551 {
 552     target_ulong bad_pc;
 553     target_ulong isa_mode;
 554
 555     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 556     bad_pc = env->active_tc.PC | isa_mode;
 557     if (env->hflags & MIPS_HFLAG_BMASK) {
 558         /* If the exception was raised from a delay slot, come back to
 559            the jump.  */
 560         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 561     }
 562
 563     return bad_pc;
 564 }
 565
 566 #if !defined(CONFIG_USER_ONLY)
 567 static void set_hflags_for_handler (CPUMIPSState *env)
 568 {
 569     /* Exception handlers are entered in 32-bit mode.  */
 570     env->hflags &= ~(MIPS_HFLAG_M16);
 571     /* ...except that microMIPS lets you choose.  */
 572     if (env->insn_flags & ASE_MICROMIPS) {
 573         env->hflags |= (!!(env->CP0_Config3
 574                            & (1 << CP0C3_ISA_ON_EXC))
 575                         << MIPS_HFLAG_M16_SHIFT);
 576     }
 577 }
 578
 579 static inline void set_badinstr_registers(CPUMIPSState *env)
 580 {
 581     if (env->hflags & MIPS_HFLAG_M16) {
 582         /* TODO: add BadInstr support for microMIPS */
 583         return;
 584     }
 585     if (env->CP0_Config3 & (1 << CP0C3_BI)) {
 586         env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
 587     }
 588     if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
 589         (env->hflags & MIPS_HFLAG_BMASK)) {
 590         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
 591     }
 592 }
 593 #endif
 594
 595 void mips_cpu_do_interrupt(CPUState *cs)
 596 {
 597 #if !defined(CONFIG_USER_ONLY)
 598     MIPSCPU *cpu = MIPS_CPU(cs);
 599     CPUMIPSState *env = &cpu->env;
 600     bool update_badinstr = 0;
 601     target_ulong offset;
 602     int cause = -1;
 603     const char *name;
 604
 605     if (qemu_loglevel_mask(CPU_LOG_INT)
 606         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 607         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 608             name = "unknown";
 609         } else {
 610             name = excp_names[cs->exception_index];
 611         }
 612
 613         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
 614                  " %s exception\n",
 615                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 616     }
 617     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 618         (env->hflags & MIPS_HFLAG_DM)) {
 619         cs->exception_index = EXCP_DINT;
 620     }
 621     offset = 0x180;
 622     switch (cs->exception_index) {
 623     case EXCP_DSS:
 624         env->CP0_Debug |= 1 << CP0DB_DSS;
 625         /* Debug single step cannot be raised inside a delay slot and
 626            resume will always occur on the next instruction
 627            (but we assume the pc has always been updated during
 628            code translation). */
 629         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 630         goto enter_debug_mode;
 631     case EXCP_DINT:
 632         env->CP0_Debug |= 1 << CP0DB_DINT;
 633         goto set_DEPC;
 634     case EXCP_DIB:
 635         env->CP0_Debug |= 1 << CP0DB_DIB;
 636         goto set_DEPC;
 637     case EXCP_DBp:
 638         env->CP0_Debug |= 1 << CP0DB_DBp;
 639         goto set_DEPC;
 640     case EXCP_DDBS:
 641         env->CP0_Debug |= 1 << CP0DB_DDBS;
 642         goto set_DEPC;
 643     case EXCP_DDBL:
 644         env->CP0_Debug |= 1 << CP0DB_DDBL;
 645     set_DEPC:
 646         env->CP0_DEPC = exception_resume_pc(env);
 647         env->hflags &= ~MIPS_HFLAG_BMASK;
 648  enter_debug_mode:
 649         if (env->insn_flags & ISA_MIPS3) {
 650             env->hflags |= MIPS_HFLAG_64;
 651             if (!(env->insn_flags & ISA_MIPS64R6) ||
 652                 env->CP0_Status & (1 << CP0St_KX)) {
 653                 env->hflags &= ~MIPS_HFLAG_AWRAP;
 654             }
 655         }
 656         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
 657         env->hflags &= ~(MIPS_HFLAG_KSU);
 658         /* EJTAG probe trap enable is not implemented... */
 659         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 660             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 661         env->active_tc.PC = env->exception_base + 0x480;
 662         set_hflags_for_handler(env);
 663         break;
 664     case EXCP_RESET:
 665         cpu_reset(CPU(cpu));
 666         break;
 667     case EXCP_SRESET:
 668         env->CP0_Status |= (1 << CP0St_SR);
 669         memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
 670         goto set_error_EPC;
 671     case EXCP_NMI:
 672         env->CP0_Status |= (1 << CP0St_NMI);
 673  set_error_EPC:
 674         env->CP0_ErrorEPC = exception_resume_pc(env);
 675         env->hflags &= ~MIPS_HFLAG_BMASK;
 676         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 677         if (env->insn_flags & ISA_MIPS3) {
 678             env->hflags |= MIPS_HFLAG_64;
 679             if (!(env->insn_flags & ISA_MIPS64R6) ||
 680                 env->CP0_Status & (1 << CP0St_KX)) {
 681                 env->hflags &= ~MIPS_HFLAG_AWRAP;
 682             }
 683         }
 684         env->hflags |= MIPS_HFLAG_CP0;
 685         env->hflags &= ~(MIPS_HFLAG_KSU);
 686         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 687             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 688         env->active_tc.PC = env->exception_base;
 689         set_hflags_for_handler(env);
 690         break;
 691     case EXCP_EXT_INTERRUPT:
 692         cause = 0;
 693         if (env->CP0_Cause & (1 << CP0Ca_IV)) {
 694             uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
 695
 696             if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
 697                 offset = 0x200;
 698             } else {
 699                 uint32_t vector = 0;
 700                 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
 701
 702                 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 703                     /* For VEIC mode, the external interrupt controller feeds
 704                      * the vector through the CP0Cause IP lines.  */
 705                     vector = pending;
 706                 } else {
 707                     /* Vectored Interrupts
 708                      * Mask with Status.IM7-IM0 to get enabled interrupts. */
 709                     pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
 710                     /* Find the highest-priority interrupt. */
 711                     while (pending >>= 1) {
 712                         vector++;
 713                     }
 714                 }
 715                 offset = 0x200 + (vector * (spacing << 5));
 716             }
 717         }
 718         goto set_EPC;
 719     case EXCP_LTLBL:
 720         cause = 1;
 721         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 722         goto set_EPC;
 723     case EXCP_TLBL:
 724         cause = 2;
 725         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 726         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 727             !(env->CP0_Status & (1 << CP0St_EXL))) {
 728 #if defined(TARGET_MIPS64)
 729             int R = env->CP0_BadVAddr >> 62;
 730             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 731             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 732             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 733
 734             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 735                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 736                 offset = 0x080;
 737             else
 738 #endif
 739                 offset = 0x000;
 740         }
 741         goto set_EPC;
 742     case EXCP_TLBS:
 743         cause = 3;
 744         update_badinstr = 1;
 745         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 746             !(env->CP0_Status & (1 << CP0St_EXL))) {
 747 #if defined(TARGET_MIPS64)
 748             int R = env->CP0_BadVAddr >> 62;
 749             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 750             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 751             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 752
 753             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 754                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 755                 offset = 0x080;
 756             else
 757 #endif
 758                 offset = 0x000;
 759         }
 760         goto set_EPC;
 761     case EXCP_AdEL:
 762         cause = 4;
 763         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 764         goto set_EPC;
 765     case EXCP_AdES:
 766         cause = 5;
 767         update_badinstr = 1;
 768         goto set_EPC;
 769     case EXCP_IBE:
 770         cause = 6;
 771         goto set_EPC;
 772     case EXCP_DBE:
 773         cause = 7;
 774         goto set_EPC;
 775     case EXCP_SYSCALL:
 776         cause = 8;
 777         update_badinstr = 1;
 778         goto set_EPC;
 779     case EXCP_BREAK:
 780         cause = 9;
 781         update_badinstr = 1;
 782         goto set_EPC;
 783     case EXCP_RI:
 784         cause = 10;
 785         update_badinstr = 1;
 786         goto set_EPC;
 787     case EXCP_CpU:
 788         cause = 11;
 789         update_badinstr = 1;
 790         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 791                          (env->error_code << CP0Ca_CE);
 792         goto set_EPC;
 793     case EXCP_OVERFLOW:
 794         cause = 12;
 795         update_badinstr = 1;
 796         goto set_EPC;
 797     case EXCP_TRAP:
 798         cause = 13;
 799         update_badinstr = 1;
 800         goto set_EPC;
 801     case EXCP_MSAFPE:
 802         cause = 14;
 803         update_badinstr = 1;
 804         goto set_EPC;
 805     case EXCP_FPE:
 806         cause = 15;
 807         update_badinstr = 1;
 808         goto set_EPC;
 809     case EXCP_C2E:
 810         cause = 18;
 811         goto set_EPC;
 812     case EXCP_TLBRI:
 813         cause = 19;
 814         update_badinstr = 1;
 815         goto set_EPC;
 816     case EXCP_TLBXI:
 817         cause = 20;
 818         goto set_EPC;
 819     case EXCP_MSADIS:
 820         cause = 21;
 821         update_badinstr = 1;
 822         goto set_EPC;
 823     case EXCP_MDMX:
 824         cause = 22;
 825         goto set_EPC;
 826     case EXCP_DWATCH:
 827         cause = 23;
 828         /* XXX: TODO: manage deferred watch exceptions */
 829         goto set_EPC;
 830     case EXCP_MCHECK:
 831         cause = 24;
 832         goto set_EPC;
 833     case EXCP_THREAD:
 834         cause = 25;
 835         goto set_EPC;
 836     case EXCP_DSPDIS:
 837         cause = 26;
 838         goto set_EPC;
 839     case EXCP_CACHE:
 840         cause = 30;
 841         if (env->CP0_Status & (1 << CP0St_BEV)) {
 842             offset = 0x100;
 843         } else {
 844             offset = 0x20000100;
 845         }
 846  set_EPC:
 847         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 848             env->CP0_EPC = exception_resume_pc(env);
 849             if (update_badinstr) {
 850                 set_badinstr_registers(env);
 851             }
 852             if (env->hflags & MIPS_HFLAG_BMASK) {
 853                 env->CP0_Cause |= (1U << CP0Ca_BD);
 854             } else {
 855                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 856             }
 857             env->CP0_Status |= (1 << CP0St_EXL);
 858             if (env->insn_flags & ISA_MIPS3) {
 859                 env->hflags |= MIPS_HFLAG_64;
 860                 if (!(env->insn_flags & ISA_MIPS64R6) ||
 861                     env->CP0_Status & (1 << CP0St_KX)) {
 862                     env->hflags &= ~MIPS_HFLAG_AWRAP;
 863                 }
 864             }
 865             env->hflags |= MIPS_HFLAG_CP0;
 866             env->hflags &= ~(MIPS_HFLAG_KSU);
 867         }
 868         env->hflags &= ~MIPS_HFLAG_BMASK;
 869         if (env->CP0_Status & (1 << CP0St_BEV)) {
 870             env->active_tc.PC = env->exception_base + 0x200;
 871         } else {
 872             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 873         }
 874         env->active_tc.PC += offset;
 875         set_hflags_for_handler(env);
 876         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 877         break;
 878     default:
 879         abort();
 880     }
 881     if (qemu_loglevel_mask(CPU_LOG_INT)
 882         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 883         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 884                  "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 885                  __func__, env->active_tc.PC, env->CP0_EPC, cause,
 886                  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 887                  env->CP0_DEPC);
 888     }
 889 #endif
 890     cs->exception_index = EXCP_NONE;
 891 }
 892
 893 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 894 {
 895     if (interrupt_request & CPU_INTERRUPT_HARD) {
 896         MIPSCPU *cpu = MIPS_CPU(cs);
 897         CPUMIPSState *env = &cpu->env;
 898
 899         if (cpu_mips_hw_interrupts_enabled(env) &&
 900             cpu_mips_hw_interrupts_pending(env)) {
 901             /* Raise it */
 902             cs->exception_index = EXCP_EXT_INTERRUPT;
 903             env->error_code = 0;
 904             mips_cpu_do_interrupt(cs);
 905             return true;
 906         }
 907     }
 908     return false;
 909 }
 910
 911 #if !defined(CONFIG_USER_ONLY)
 912 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 913 {
 914     MIPSCPU *cpu = mips_env_get_cpu(env);
 915     CPUState *cs;
 916     r4k_tlb_t *tlb;
 917     target_ulong addr;
 918     target_ulong end;
 919     uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 920     target_ulong mask;
 921
 922     tlb = &env->tlb->mmu.r4k.tlb[idx];
 923     /* The qemu TLB is flushed when the ASID changes, so no need to
 924        flush these entries again.  */
 925     if (tlb->G == 0 && tlb->ASID != ASID) {
 926         return;
 927     }
 928
 929     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 930         /* For tlbwr, we can shadow the discarded entry into
 931            a new (fake) TLB entry, as long as the guest can not
 932            tell that it's there.  */
 933         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 934         env->tlb->tlb_in_use++;
 935         return;
 936     }
 937
 938     /* 1k pages are not supported. */
 939     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 940     if (tlb->V0) {
 941         cs = CPU(cpu);
 942         addr = tlb->VPN & ~mask;
 943 #if defined(TARGET_MIPS64)
 944         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 945             addr |= 0x3FFFFF0000000000ULL;
 946         }
 947 #endif
 948         end = addr | (mask >> 1);
 949         while (addr < end) {
 950             // optimize memset in tlb_flush_page!!!
 951             tlb_flush_page(cs, addr);
 952             addr += TARGET_PAGE_SIZE;
 953         }
 954     }
 955     if (tlb->V1) {
 956         cs = CPU(cpu);
 957         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 958 #if defined(TARGET_MIPS64)
 959         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 960             addr |= 0x3FFFFF0000000000ULL;
 961         }
 962 #endif
 963         end = addr | mask;
 964         while (addr - 1 < end) {
 965             // optimize memset in tlb_flush_page!!!
 966             tlb_flush_page(cs, addr);
 967             addr += TARGET_PAGE_SIZE;
 968         }
 969     }
 970 }
 971 #endif
 972
 973 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
 974                                           uint32_t exception,
 975                                           int error_code,
 976                                           uintptr_t pc)
 977 {
 978     CPUState *cs = CPU(mips_env_get_cpu(env));
 979
 980     if (exception < EXCP_SC) {
 981         qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
 982                       __func__, exception, error_code);
 983     }
 984     cs->exception_index = exception;
 985     env->error_code = error_code;
 986
 987     cpu_loop_exit_restore(cs, pc);
 988 }