2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "dyngen-exec.h"
23 #include "host-utils.h"
27 #if !defined(CONFIG_USER_ONLY)
28 #include "softmmu_exec.h"
29 #endif /* !defined(CONFIG_USER_ONLY) */
31 #ifndef CONFIG_USER_ONLY
32 static inline void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
);
35 /*****************************************************************************/
36 /* Exceptions processing helpers */
38 void helper_raise_exception_err (uint32_t exception
, int error_code
)
41 if (exception
< 0x100)
42 qemu_log("%s: %d %d\n", __func__
, exception
, error_code
);
44 env
->exception_index
= exception
;
45 env
->error_code
= error_code
;
49 void helper_raise_exception (uint32_t exception
)
51 helper_raise_exception_err(exception
, 0);
54 #if !defined(CONFIG_USER_ONLY)
55 static void do_restore_state(uintptr_t pc
)
61 cpu_restore_state(tb
, env
, pc
);
66 #if defined(CONFIG_USER_ONLY)
67 #define HELPER_LD(name, insn, type) \
68 static inline type do_##name(target_ulong addr, int mem_idx) \
70 return (type) insn##_raw(addr); \
73 #define HELPER_LD(name, insn, type) \
74 static inline type do_##name(target_ulong addr, int mem_idx) \
78 case 0: return (type) insn##_kernel(addr); break; \
79 case 1: return (type) insn##_super(addr); break; \
81 case 2: return (type) insn##_user(addr); break; \
85 HELPER_LD(lbu
, ldub
, uint8_t)
86 HELPER_LD(lw
, ldl
, int32_t)
88 HELPER_LD(ld
, ldq
, int64_t)
92 #if defined(CONFIG_USER_ONLY)
93 #define HELPER_ST(name, insn, type) \
94 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
96 insn##_raw(addr, val); \
99 #define HELPER_ST(name, insn, type) \
100 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
104 case 0: insn##_kernel(addr, val); break; \
105 case 1: insn##_super(addr, val); break; \
107 case 2: insn##_user(addr, val); break; \
111 HELPER_ST(sb
, stb
, uint8_t)
112 HELPER_ST(sw
, stl
, uint32_t)
114 HELPER_ST(sd
, stq
, uint64_t)
118 target_ulong
helper_clo (target_ulong arg1
)
123 target_ulong
helper_clz (target_ulong arg1
)
128 #if defined(TARGET_MIPS64)
129 target_ulong
helper_dclo (target_ulong arg1
)
134 target_ulong
helper_dclz (target_ulong arg1
)
138 #endif /* TARGET_MIPS64 */
140 /* 64 bits arithmetic for 32 bits hosts */
141 static inline uint64_t get_HILO (void)
143 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
146 static inline target_ulong
set_HIT0_LO(uint64_t HILO
)
149 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
150 tmp
= env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
154 static inline target_ulong
set_HI_LOT0(uint64_t HILO
)
156 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
157 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
161 /* Multiplication variants of the vr54xx. */
162 target_ulong
helper_muls (target_ulong arg1
, target_ulong arg2
)
164 return set_HI_LOT0(0 - ((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
));
167 target_ulong
helper_mulsu (target_ulong arg1
, target_ulong arg2
)
169 return set_HI_LOT0(0 - (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
172 target_ulong
helper_macc (target_ulong arg1
, target_ulong arg2
)
174 return set_HI_LOT0((int64_t)get_HILO() + (int64_t)(int32_t)arg1
*
175 (int64_t)(int32_t)arg2
);
178 target_ulong
helper_macchi (target_ulong arg1
, target_ulong arg2
)
180 return set_HIT0_LO((int64_t)get_HILO() + (int64_t)(int32_t)arg1
*
181 (int64_t)(int32_t)arg2
);
184 target_ulong
helper_maccu (target_ulong arg1
, target_ulong arg2
)
186 return set_HI_LOT0((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1
*
187 (uint64_t)(uint32_t)arg2
);
190 target_ulong
helper_macchiu (target_ulong arg1
, target_ulong arg2
)
192 return set_HIT0_LO((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1
*
193 (uint64_t)(uint32_t)arg2
);
196 target_ulong
helper_msac (target_ulong arg1
, target_ulong arg2
)
198 return set_HI_LOT0((int64_t)get_HILO() - (int64_t)(int32_t)arg1
*
199 (int64_t)(int32_t)arg2
);
202 target_ulong
helper_msachi (target_ulong arg1
, target_ulong arg2
)
204 return set_HIT0_LO((int64_t)get_HILO() - (int64_t)(int32_t)arg1
*
205 (int64_t)(int32_t)arg2
);
208 target_ulong
helper_msacu (target_ulong arg1
, target_ulong arg2
)
210 return set_HI_LOT0((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1
*
211 (uint64_t)(uint32_t)arg2
);
214 target_ulong
helper_msachiu (target_ulong arg1
, target_ulong arg2
)
216 return set_HIT0_LO((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1
*
217 (uint64_t)(uint32_t)arg2
);
220 target_ulong
helper_mulhi (target_ulong arg1
, target_ulong arg2
)
222 return set_HIT0_LO((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
225 target_ulong
helper_mulhiu (target_ulong arg1
, target_ulong arg2
)
227 return set_HIT0_LO((uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
230 target_ulong
helper_mulshi (target_ulong arg1
, target_ulong arg2
)
232 return set_HIT0_LO(0 - (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
235 target_ulong
helper_mulshiu (target_ulong arg1
, target_ulong arg2
)
237 return set_HIT0_LO(0 - (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
241 void helper_dmult (target_ulong arg1
, target_ulong arg2
)
243 muls64(&(env
->active_tc
.LO
[0]), &(env
->active_tc
.HI
[0]), arg1
, arg2
);
246 void helper_dmultu (target_ulong arg1
, target_ulong arg2
)
248 mulu64(&(env
->active_tc
.LO
[0]), &(env
->active_tc
.HI
[0]), arg1
, arg2
);
252 #ifndef CONFIG_USER_ONLY
254 static inline target_phys_addr_t
do_translate_address(target_ulong address
, int rw
)
256 target_phys_addr_t lladdr
;
258 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
260 if (lladdr
== -1LL) {
267 #define HELPER_LD_ATOMIC(name, insn) \
268 target_ulong helper_##name(target_ulong arg, int mem_idx) \
270 env->lladdr = do_translate_address(arg, 0); \
271 env->llval = do_##insn(arg, mem_idx); \
274 HELPER_LD_ATOMIC(ll
, lw
)
276 HELPER_LD_ATOMIC(lld
, ld
)
278 #undef HELPER_LD_ATOMIC
280 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
281 target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
285 if (arg2 & almask) { \
286 env->CP0_BadVAddr = arg2; \
287 helper_raise_exception(EXCP_AdES); \
289 if (do_translate_address(arg2, 1) == env->lladdr) { \
290 tmp = do_##ld_insn(arg2, mem_idx); \
291 if (tmp == env->llval) { \
292 do_##st_insn(arg2, arg1, mem_idx); \
298 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
300 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
302 #undef HELPER_ST_ATOMIC
305 #ifdef TARGET_WORDS_BIGENDIAN
306 #define GET_LMASK(v) ((v) & 3)
307 #define GET_OFFSET(addr, offset) (addr + (offset))
309 #define GET_LMASK(v) (((v) & 3) ^ 3)
310 #define GET_OFFSET(addr, offset) (addr - (offset))
313 target_ulong
helper_lwl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
317 tmp
= do_lbu(arg2
, mem_idx
);
318 arg1
= (arg1
& 0x00FFFFFF) | (tmp
<< 24);
320 if (GET_LMASK(arg2
) <= 2) {
321 tmp
= do_lbu(GET_OFFSET(arg2
, 1), mem_idx
);
322 arg1
= (arg1
& 0xFF00FFFF) | (tmp
<< 16);
325 if (GET_LMASK(arg2
) <= 1) {
326 tmp
= do_lbu(GET_OFFSET(arg2
, 2), mem_idx
);
327 arg1
= (arg1
& 0xFFFF00FF) | (tmp
<< 8);
330 if (GET_LMASK(arg2
) == 0) {
331 tmp
= do_lbu(GET_OFFSET(arg2
, 3), mem_idx
);
332 arg1
= (arg1
& 0xFFFFFF00) | tmp
;
334 return (int32_t)arg1
;
337 target_ulong
helper_lwr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
341 tmp
= do_lbu(arg2
, mem_idx
);
342 arg1
= (arg1
& 0xFFFFFF00) | tmp
;
344 if (GET_LMASK(arg2
) >= 1) {
345 tmp
= do_lbu(GET_OFFSET(arg2
, -1), mem_idx
);
346 arg1
= (arg1
& 0xFFFF00FF) | (tmp
<< 8);
349 if (GET_LMASK(arg2
) >= 2) {
350 tmp
= do_lbu(GET_OFFSET(arg2
, -2), mem_idx
);
351 arg1
= (arg1
& 0xFF00FFFF) | (tmp
<< 16);
354 if (GET_LMASK(arg2
) == 3) {
355 tmp
= do_lbu(GET_OFFSET(arg2
, -3), mem_idx
);
356 arg1
= (arg1
& 0x00FFFFFF) | (tmp
<< 24);
358 return (int32_t)arg1
;
361 void helper_swl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
363 do_sb(arg2
, (uint8_t)(arg1
>> 24), mem_idx
);
365 if (GET_LMASK(arg2
) <= 2)
366 do_sb(GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
);
368 if (GET_LMASK(arg2
) <= 1)
369 do_sb(GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
);
371 if (GET_LMASK(arg2
) == 0)
372 do_sb(GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
);
375 void helper_swr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
377 do_sb(arg2
, (uint8_t)arg1
, mem_idx
);
379 if (GET_LMASK(arg2
) >= 1)
380 do_sb(GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
382 if (GET_LMASK(arg2
) >= 2)
383 do_sb(GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
385 if (GET_LMASK(arg2
) == 3)
386 do_sb(GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
389 #if defined(TARGET_MIPS64)
390 /* "half" load and stores. We must do the memory access inline,
391 or fault handling won't work. */
393 #ifdef TARGET_WORDS_BIGENDIAN
394 #define GET_LMASK64(v) ((v) & 7)
396 #define GET_LMASK64(v) (((v) & 7) ^ 7)
399 target_ulong
helper_ldl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
403 tmp
= do_lbu(arg2
, mem_idx
);
404 arg1
= (arg1
& 0x00FFFFFFFFFFFFFFULL
) | (tmp
<< 56);
406 if (GET_LMASK64(arg2
) <= 6) {
407 tmp
= do_lbu(GET_OFFSET(arg2
, 1), mem_idx
);
408 arg1
= (arg1
& 0xFF00FFFFFFFFFFFFULL
) | (tmp
<< 48);
411 if (GET_LMASK64(arg2
) <= 5) {
412 tmp
= do_lbu(GET_OFFSET(arg2
, 2), mem_idx
);
413 arg1
= (arg1
& 0xFFFF00FFFFFFFFFFULL
) | (tmp
<< 40);
416 if (GET_LMASK64(arg2
) <= 4) {
417 tmp
= do_lbu(GET_OFFSET(arg2
, 3), mem_idx
);
418 arg1
= (arg1
& 0xFFFFFF00FFFFFFFFULL
) | (tmp
<< 32);
421 if (GET_LMASK64(arg2
) <= 3) {
422 tmp
= do_lbu(GET_OFFSET(arg2
, 4), mem_idx
);
423 arg1
= (arg1
& 0xFFFFFFFF00FFFFFFULL
) | (tmp
<< 24);
426 if (GET_LMASK64(arg2
) <= 2) {
427 tmp
= do_lbu(GET_OFFSET(arg2
, 5), mem_idx
);
428 arg1
= (arg1
& 0xFFFFFFFFFF00FFFFULL
) | (tmp
<< 16);
431 if (GET_LMASK64(arg2
) <= 1) {
432 tmp
= do_lbu(GET_OFFSET(arg2
, 6), mem_idx
);
433 arg1
= (arg1
& 0xFFFFFFFFFFFF00FFULL
) | (tmp
<< 8);
436 if (GET_LMASK64(arg2
) == 0) {
437 tmp
= do_lbu(GET_OFFSET(arg2
, 7), mem_idx
);
438 arg1
= (arg1
& 0xFFFFFFFFFFFFFF00ULL
) | tmp
;
444 target_ulong
helper_ldr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
448 tmp
= do_lbu(arg2
, mem_idx
);
449 arg1
= (arg1
& 0xFFFFFFFFFFFFFF00ULL
) | tmp
;
451 if (GET_LMASK64(arg2
) >= 1) {
452 tmp
= do_lbu(GET_OFFSET(arg2
, -1), mem_idx
);
453 arg1
= (arg1
& 0xFFFFFFFFFFFF00FFULL
) | (tmp
<< 8);
456 if (GET_LMASK64(arg2
) >= 2) {
457 tmp
= do_lbu(GET_OFFSET(arg2
, -2), mem_idx
);
458 arg1
= (arg1
& 0xFFFFFFFFFF00FFFFULL
) | (tmp
<< 16);
461 if (GET_LMASK64(arg2
) >= 3) {
462 tmp
= do_lbu(GET_OFFSET(arg2
, -3), mem_idx
);
463 arg1
= (arg1
& 0xFFFFFFFF00FFFFFFULL
) | (tmp
<< 24);
466 if (GET_LMASK64(arg2
) >= 4) {
467 tmp
= do_lbu(GET_OFFSET(arg2
, -4), mem_idx
);
468 arg1
= (arg1
& 0xFFFFFF00FFFFFFFFULL
) | (tmp
<< 32);
471 if (GET_LMASK64(arg2
) >= 5) {
472 tmp
= do_lbu(GET_OFFSET(arg2
, -5), mem_idx
);
473 arg1
= (arg1
& 0xFFFF00FFFFFFFFFFULL
) | (tmp
<< 40);
476 if (GET_LMASK64(arg2
) >= 6) {
477 tmp
= do_lbu(GET_OFFSET(arg2
, -6), mem_idx
);
478 arg1
= (arg1
& 0xFF00FFFFFFFFFFFFULL
) | (tmp
<< 48);
481 if (GET_LMASK64(arg2
) == 7) {
482 tmp
= do_lbu(GET_OFFSET(arg2
, -7), mem_idx
);
483 arg1
= (arg1
& 0x00FFFFFFFFFFFFFFULL
) | (tmp
<< 56);
489 void helper_sdl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
491 do_sb(arg2
, (uint8_t)(arg1
>> 56), mem_idx
);
493 if (GET_LMASK64(arg2
) <= 6)
494 do_sb(GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
);
496 if (GET_LMASK64(arg2
) <= 5)
497 do_sb(GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
);
499 if (GET_LMASK64(arg2
) <= 4)
500 do_sb(GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
);
502 if (GET_LMASK64(arg2
) <= 3)
503 do_sb(GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
);
505 if (GET_LMASK64(arg2
) <= 2)
506 do_sb(GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
);
508 if (GET_LMASK64(arg2
) <= 1)
509 do_sb(GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
);
511 if (GET_LMASK64(arg2
) <= 0)
512 do_sb(GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
);
515 void helper_sdr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
517 do_sb(arg2
, (uint8_t)arg1
, mem_idx
);
519 if (GET_LMASK64(arg2
) >= 1)
520 do_sb(GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
522 if (GET_LMASK64(arg2
) >= 2)
523 do_sb(GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
525 if (GET_LMASK64(arg2
) >= 3)
526 do_sb(GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
528 if (GET_LMASK64(arg2
) >= 4)
529 do_sb(GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
);
531 if (GET_LMASK64(arg2
) >= 5)
532 do_sb(GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
);
534 if (GET_LMASK64(arg2
) >= 6)
535 do_sb(GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
);
537 if (GET_LMASK64(arg2
) == 7)
538 do_sb(GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
);
540 #endif /* TARGET_MIPS64 */
542 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
544 void helper_lwm (target_ulong addr
, target_ulong reglist
, uint32_t mem_idx
)
546 target_ulong base_reglist
= reglist
& 0xf;
547 target_ulong do_r31
= reglist
& 0x10;
548 #ifdef CONFIG_USER_ONLY
550 #define ldfun ldl_raw
552 uint32_t (*ldfun
)(target_ulong
);
556 case 0: ldfun
= ldl_kernel
; break;
557 case 1: ldfun
= ldl_super
; break;
559 case 2: ldfun
= ldl_user
; break;
563 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
566 for (i
= 0; i
< base_reglist
; i
++) {
567 env
->active_tc
.gpr
[multiple_regs
[i
]] = (target_long
) ldfun(addr
);
573 env
->active_tc
.gpr
[31] = (target_long
) ldfun(addr
);
577 void helper_swm (target_ulong addr
, target_ulong reglist
, uint32_t mem_idx
)
579 target_ulong base_reglist
= reglist
& 0xf;
580 target_ulong do_r31
= reglist
& 0x10;
581 #ifdef CONFIG_USER_ONLY
583 #define stfun stl_raw
585 void (*stfun
)(target_ulong
, uint32_t);
589 case 0: stfun
= stl_kernel
; break;
590 case 1: stfun
= stl_super
; break;
592 case 2: stfun
= stl_user
; break;
596 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
599 for (i
= 0; i
< base_reglist
; i
++) {
600 stfun(addr
, env
->active_tc
.gpr
[multiple_regs
[i
]]);
606 stfun(addr
, env
->active_tc
.gpr
[31]);
610 #if defined(TARGET_MIPS64)
611 void helper_ldm (target_ulong addr
, target_ulong reglist
, uint32_t mem_idx
)
613 target_ulong base_reglist
= reglist
& 0xf;
614 target_ulong do_r31
= reglist
& 0x10;
615 #ifdef CONFIG_USER_ONLY
617 #define ldfun ldq_raw
619 uint64_t (*ldfun
)(target_ulong
);
623 case 0: ldfun
= ldq_kernel
; break;
624 case 1: ldfun
= ldq_super
; break;
626 case 2: ldfun
= ldq_user
; break;
630 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
633 for (i
= 0; i
< base_reglist
; i
++) {
634 env
->active_tc
.gpr
[multiple_regs
[i
]] = ldfun(addr
);
640 env
->active_tc
.gpr
[31] = ldfun(addr
);
644 void helper_sdm (target_ulong addr
, target_ulong reglist
, uint32_t mem_idx
)
646 target_ulong base_reglist
= reglist
& 0xf;
647 target_ulong do_r31
= reglist
& 0x10;
648 #ifdef CONFIG_USER_ONLY
650 #define stfun stq_raw
652 void (*stfun
)(target_ulong
, uint64_t);
656 case 0: stfun
= stq_kernel
; break;
657 case 1: stfun
= stq_super
; break;
659 case 2: stfun
= stq_user
; break;
663 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
666 for (i
= 0; i
< base_reglist
; i
++) {
667 stfun(addr
, env
->active_tc
.gpr
[multiple_regs
[i
]]);
673 stfun(addr
, env
->active_tc
.gpr
[31]);
678 #ifndef CONFIG_USER_ONLY
680 static int mips_vpe_is_wfi(CPUMIPSState
*c
)
682 /* If the VPE is halted but otherwise active, it means it's waiting for
684 return c
->halted
&& mips_vpe_active(c
);
687 static inline void mips_vpe_wake(CPUMIPSState
*c
)
689 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
690 because there might be other conditions that state that c should
692 cpu_interrupt(c
, CPU_INTERRUPT_WAKE
);
695 static inline void mips_vpe_sleep(CPUMIPSState
*c
)
697 /* The VPE was shut off, really go to bed.
698 Reset any old _WAKE requests. */
700 cpu_reset_interrupt(c
, CPU_INTERRUPT_WAKE
);
703 static inline void mips_tc_wake(CPUMIPSState
*c
, int tc
)
705 /* FIXME: TC reschedule. */
706 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(c
)) {
711 static inline void mips_tc_sleep(CPUMIPSState
*c
, int tc
)
713 /* FIXME: TC reschedule. */
714 if (!mips_vpe_active(c
)) {
719 /* tc should point to an int with the value of the global TC index.
720 This function will transform it into a local index within the
721 returned CPUMIPSState.
723 FIXME: This code assumes that all VPEs have the same number of TCs,
724 which depends on runtime setup. Can probably be fixed by
725 walking the list of CPUMIPSStates. */
726 static CPUMIPSState
*mips_cpu_map_tc(int *tc
)
729 int vpe_idx
, nr_threads
= env
->nr_threads
;
732 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
733 /* Not allowed to address other CPUs. */
734 *tc
= env
->current_tc
;
738 vpe_idx
= tc_idx
/ nr_threads
;
739 *tc
= tc_idx
% nr_threads
;
740 other
= qemu_get_cpu(vpe_idx
);
741 return other
? other
: env
;
744 /* The per VPE CP0_Status register shares some fields with the per TC
745 CP0_TCStatus registers. These fields are wired to the same registers,
746 so changes to either of them should be reflected on both registers.
748 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
750 These helper call synchronizes the regs for a given cpu. */
752 /* Called for updates to CP0_Status. */
753 static void sync_c0_status(CPUMIPSState
*cpu
, int tc
)
755 int32_t tcstatus
, *tcst
;
756 uint32_t v
= cpu
->CP0_Status
;
757 uint32_t cu
, mx
, asid
, ksu
;
758 uint32_t mask
= ((1 << CP0TCSt_TCU3
)
759 | (1 << CP0TCSt_TCU2
)
760 | (1 << CP0TCSt_TCU1
)
761 | (1 << CP0TCSt_TCU0
)
763 | (3 << CP0TCSt_TKSU
)
764 | (0xff << CP0TCSt_TASID
));
766 cu
= (v
>> CP0St_CU0
) & 0xf;
767 mx
= (v
>> CP0St_MX
) & 0x1;
768 ksu
= (v
>> CP0St_KSU
) & 0x3;
769 asid
= env
->CP0_EntryHi
& 0xff;
771 tcstatus
= cu
<< CP0TCSt_TCU0
;
772 tcstatus
|= mx
<< CP0TCSt_TMX
;
773 tcstatus
|= ksu
<< CP0TCSt_TKSU
;
776 if (tc
== cpu
->current_tc
) {
777 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
779 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
787 /* Called for updates to CP0_TCStatus. */
788 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
, target_ulong v
)
791 uint32_t tcu
, tmx
, tasid
, tksu
;
792 uint32_t mask
= ((1 << CP0St_CU3
)
799 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
800 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
802 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
804 status
= tcu
<< CP0St_CU0
;
805 status
|= tmx
<< CP0St_MX
;
806 status
|= tksu
<< CP0St_KSU
;
808 cpu
->CP0_Status
&= ~mask
;
809 cpu
->CP0_Status
|= status
;
811 /* Sync the TASID with EntryHi. */
812 cpu
->CP0_EntryHi
&= ~0xff;
813 cpu
->CP0_EntryHi
= tasid
;
818 /* Called for updates to CP0_EntryHi. */
819 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
822 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
826 if (tc
== cpu
->current_tc
) {
827 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
829 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
837 target_ulong
helper_mfc0_mvpcontrol (void)
839 return env
->mvp
->CP0_MVPControl
;
842 target_ulong
helper_mfc0_mvpconf0 (void)
844 return env
->mvp
->CP0_MVPConf0
;
847 target_ulong
helper_mfc0_mvpconf1 (void)
849 return env
->mvp
->CP0_MVPConf1
;
852 target_ulong
helper_mfc0_random (void)
854 return (int32_t)cpu_mips_get_random(env
);
857 target_ulong
helper_mfc0_tcstatus (void)
859 return env
->active_tc
.CP0_TCStatus
;
862 target_ulong
helper_mftc0_tcstatus(void)
864 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
865 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
867 if (other_tc
== other
->current_tc
)
868 return other
->active_tc
.CP0_TCStatus
;
870 return other
->tcs
[other_tc
].CP0_TCStatus
;
873 target_ulong
helper_mfc0_tcbind (void)
875 return env
->active_tc
.CP0_TCBind
;
878 target_ulong
helper_mftc0_tcbind(void)
880 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
881 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
883 if (other_tc
== other
->current_tc
)
884 return other
->active_tc
.CP0_TCBind
;
886 return other
->tcs
[other_tc
].CP0_TCBind
;
889 target_ulong
helper_mfc0_tcrestart (void)
891 return env
->active_tc
.PC
;
894 target_ulong
helper_mftc0_tcrestart(void)
896 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
897 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
899 if (other_tc
== other
->current_tc
)
900 return other
->active_tc
.PC
;
902 return other
->tcs
[other_tc
].PC
;
905 target_ulong
helper_mfc0_tchalt (void)
907 return env
->active_tc
.CP0_TCHalt
;
910 target_ulong
helper_mftc0_tchalt(void)
912 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
913 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
915 if (other_tc
== other
->current_tc
)
916 return other
->active_tc
.CP0_TCHalt
;
918 return other
->tcs
[other_tc
].CP0_TCHalt
;
921 target_ulong
helper_mfc0_tccontext (void)
923 return env
->active_tc
.CP0_TCContext
;
926 target_ulong
helper_mftc0_tccontext(void)
928 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
929 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
931 if (other_tc
== other
->current_tc
)
932 return other
->active_tc
.CP0_TCContext
;
934 return other
->tcs
[other_tc
].CP0_TCContext
;
937 target_ulong
helper_mfc0_tcschedule (void)
939 return env
->active_tc
.CP0_TCSchedule
;
942 target_ulong
helper_mftc0_tcschedule(void)
944 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
945 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
947 if (other_tc
== other
->current_tc
)
948 return other
->active_tc
.CP0_TCSchedule
;
950 return other
->tcs
[other_tc
].CP0_TCSchedule
;
953 target_ulong
helper_mfc0_tcschefback (void)
955 return env
->active_tc
.CP0_TCScheFBack
;
958 target_ulong
helper_mftc0_tcschefback(void)
960 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
961 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
963 if (other_tc
== other
->current_tc
)
964 return other
->active_tc
.CP0_TCScheFBack
;
966 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
969 target_ulong
helper_mfc0_count (void)
971 return (int32_t)cpu_mips_get_count(env
);
974 target_ulong
helper_mftc0_entryhi(void)
976 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
977 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
979 return other
->CP0_EntryHi
;
982 target_ulong
helper_mftc0_cause(void)
984 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
986 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
988 if (other_tc
== other
->current_tc
) {
989 tccause
= other
->CP0_Cause
;
991 tccause
= other
->CP0_Cause
;
997 target_ulong
helper_mftc0_status(void)
999 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1000 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1002 return other
->CP0_Status
;
1005 target_ulong
helper_mfc0_lladdr (void)
1007 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
1010 target_ulong
helper_mfc0_watchlo (uint32_t sel
)
1012 return (int32_t)env
->CP0_WatchLo
[sel
];
1015 target_ulong
helper_mfc0_watchhi (uint32_t sel
)
1017 return env
->CP0_WatchHi
[sel
];
1020 target_ulong
helper_mfc0_debug (void)
1022 target_ulong t0
= env
->CP0_Debug
;
1023 if (env
->hflags
& MIPS_HFLAG_DM
)
1024 t0
|= 1 << CP0DB_DM
;
1029 target_ulong
helper_mftc0_debug(void)
1031 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1033 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1035 if (other_tc
== other
->current_tc
)
1036 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
1038 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
1040 /* XXX: Might be wrong, check with EJTAG spec. */
1041 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1042 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1045 #if defined(TARGET_MIPS64)
1046 target_ulong
helper_dmfc0_tcrestart (void)
1048 return env
->active_tc
.PC
;
1051 target_ulong
helper_dmfc0_tchalt (void)
1053 return env
->active_tc
.CP0_TCHalt
;
1056 target_ulong
helper_dmfc0_tccontext (void)
1058 return env
->active_tc
.CP0_TCContext
;
1061 target_ulong
helper_dmfc0_tcschedule (void)
1063 return env
->active_tc
.CP0_TCSchedule
;
1066 target_ulong
helper_dmfc0_tcschefback (void)
1068 return env
->active_tc
.CP0_TCScheFBack
;
1071 target_ulong
helper_dmfc0_lladdr (void)
1073 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
1076 target_ulong
helper_dmfc0_watchlo (uint32_t sel
)
1078 return env
->CP0_WatchLo
[sel
];
1080 #endif /* TARGET_MIPS64 */
1082 void helper_mtc0_index (target_ulong arg1
)
1085 unsigned int tmp
= env
->tlb
->nb_tlb
;
1091 env
->CP0_Index
= (env
->CP0_Index
& 0x80000000) | (arg1
& (num
- 1));
1094 void helper_mtc0_mvpcontrol (target_ulong arg1
)
1099 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
1100 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
1101 (1 << CP0MVPCo_EVP
);
1102 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1103 mask
|= (1 << CP0MVPCo_STLB
);
1104 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
1106 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1108 env
->mvp
->CP0_MVPControl
= newval
;
1111 void helper_mtc0_vpecontrol (target_ulong arg1
)
1116 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1117 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1118 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1120 /* Yield scheduler intercept not implemented. */
1121 /* Gating storage scheduler intercept not implemented. */
1123 // TODO: Enable/disable TCs.
1125 env
->CP0_VPEControl
= newval
;
1128 void helper_mttc0_vpecontrol(target_ulong arg1
)
1130 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1131 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1135 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1136 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1137 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1139 /* TODO: Enable/disable TCs. */
1141 other
->CP0_VPEControl
= newval
;
1144 target_ulong
helper_mftc0_vpecontrol(void)
1146 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1147 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1148 /* FIXME: Mask away return zero on read bits. */
1149 return other
->CP0_VPEControl
;
1152 target_ulong
helper_mftc0_vpeconf0(void)
1154 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1155 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1157 return other
->CP0_VPEConf0
;
1160 void helper_mtc0_vpeconf0 (target_ulong arg1
)
1165 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1166 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1167 mask
|= (0xff << CP0VPEC0_XTC
);
1168 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1170 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1172 // TODO: TC exclusive handling due to ERL/EXL.
1174 env
->CP0_VPEConf0
= newval
;
1177 void helper_mttc0_vpeconf0(target_ulong arg1
)
1179 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1180 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1184 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1185 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1187 /* TODO: TC exclusive handling due to ERL/EXL. */
1188 other
->CP0_VPEConf0
= newval
;
1191 void helper_mtc0_vpeconf1 (target_ulong arg1
)
1196 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1197 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1198 (0xff << CP0VPEC1_NCP1
);
1199 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1201 /* UDI not implemented. */
1202 /* CP2 not implemented. */
1204 // TODO: Handle FPU (CP1) binding.
1206 env
->CP0_VPEConf1
= newval
;
1209 void helper_mtc0_yqmask (target_ulong arg1
)
1211 /* Yield qualifier inputs not implemented. */
1212 env
->CP0_YQMask
= 0x00000000;
1215 void helper_mtc0_vpeopt (target_ulong arg1
)
1217 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1220 void helper_mtc0_entrylo0 (target_ulong arg1
)
1222 /* Large physaddr (PABITS) not implemented */
1223 /* 1k pages not implemented */
1224 env
->CP0_EntryLo0
= arg1
& 0x3FFFFFFF;
1227 void helper_mtc0_tcstatus (target_ulong arg1
)
1229 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1232 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1234 env
->active_tc
.CP0_TCStatus
= newval
;
1235 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1238 void helper_mttc0_tcstatus (target_ulong arg1
)
1240 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1241 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1243 if (other_tc
== other
->current_tc
)
1244 other
->active_tc
.CP0_TCStatus
= arg1
;
1246 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1247 sync_c0_tcstatus(other
, other_tc
, arg1
);
1250 void helper_mtc0_tcbind (target_ulong arg1
)
1252 uint32_t mask
= (1 << CP0TCBd_TBE
);
1255 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1256 mask
|= (1 << CP0TCBd_CurVPE
);
1257 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1258 env
->active_tc
.CP0_TCBind
= newval
;
1261 void helper_mttc0_tcbind (target_ulong arg1
)
1263 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1264 uint32_t mask
= (1 << CP0TCBd_TBE
);
1266 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1268 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1269 mask
|= (1 << CP0TCBd_CurVPE
);
1270 if (other_tc
== other
->current_tc
) {
1271 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1272 other
->active_tc
.CP0_TCBind
= newval
;
1274 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1275 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1279 void helper_mtc0_tcrestart (target_ulong arg1
)
1281 env
->active_tc
.PC
= arg1
;
1282 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1284 /* MIPS16 not implemented. */
1287 void helper_mttc0_tcrestart (target_ulong arg1
)
1289 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1290 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1292 if (other_tc
== other
->current_tc
) {
1293 other
->active_tc
.PC
= arg1
;
1294 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1295 other
->lladdr
= 0ULL;
1296 /* MIPS16 not implemented. */
1298 other
->tcs
[other_tc
].PC
= arg1
;
1299 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1300 other
->lladdr
= 0ULL;
1301 /* MIPS16 not implemented. */
1305 void helper_mtc0_tchalt (target_ulong arg1
)
1307 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1309 // TODO: Halt TC / Restart (if allocated+active) TC.
1310 if (env
->active_tc
.CP0_TCHalt
& 1) {
1311 mips_tc_sleep(env
, env
->current_tc
);
1313 mips_tc_wake(env
, env
->current_tc
);
1317 void helper_mttc0_tchalt (target_ulong arg1
)
1319 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1320 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1322 // TODO: Halt TC / Restart (if allocated+active) TC.
1324 if (other_tc
== other
->current_tc
)
1325 other
->active_tc
.CP0_TCHalt
= arg1
;
1327 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1330 mips_tc_sleep(other
, other_tc
);
1332 mips_tc_wake(other
, other_tc
);
1336 void helper_mtc0_tccontext (target_ulong arg1
)
1338 env
->active_tc
.CP0_TCContext
= arg1
;
1341 void helper_mttc0_tccontext (target_ulong arg1
)
1343 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1344 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1346 if (other_tc
== other
->current_tc
)
1347 other
->active_tc
.CP0_TCContext
= arg1
;
1349 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1352 void helper_mtc0_tcschedule (target_ulong arg1
)
1354 env
->active_tc
.CP0_TCSchedule
= arg1
;
1357 void helper_mttc0_tcschedule (target_ulong arg1
)
1359 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1360 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1362 if (other_tc
== other
->current_tc
)
1363 other
->active_tc
.CP0_TCSchedule
= arg1
;
1365 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1368 void helper_mtc0_tcschefback (target_ulong arg1
)
1370 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1373 void helper_mttc0_tcschefback (target_ulong arg1
)
1375 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1376 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1378 if (other_tc
== other
->current_tc
)
1379 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1381 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1384 void helper_mtc0_entrylo1 (target_ulong arg1
)
1386 /* Large physaddr (PABITS) not implemented */
1387 /* 1k pages not implemented */
1388 env
->CP0_EntryLo1
= arg1
& 0x3FFFFFFF;
1391 void helper_mtc0_context (target_ulong arg1
)
1393 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1396 void helper_mtc0_pagemask (target_ulong arg1
)
1398 /* 1k pages not implemented */
1399 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1402 void helper_mtc0_pagegrain (target_ulong arg1
)
1404 /* SmartMIPS not implemented */
1405 /* Large physaddr (PABITS) not implemented */
1406 /* 1k pages not implemented */
1407 env
->CP0_PageGrain
= 0;
1410 void helper_mtc0_wired (target_ulong arg1
)
1412 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1415 void helper_mtc0_srsconf0 (target_ulong arg1
)
1417 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1420 void helper_mtc0_srsconf1 (target_ulong arg1
)
1422 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1425 void helper_mtc0_srsconf2 (target_ulong arg1
)
1427 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1430 void helper_mtc0_srsconf3 (target_ulong arg1
)
1432 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1435 void helper_mtc0_srsconf4 (target_ulong arg1
)
1437 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1440 void helper_mtc0_hwrena (target_ulong arg1
)
1442 env
->CP0_HWREna
= arg1
& 0x0000000F;
1445 void helper_mtc0_count (target_ulong arg1
)
1447 cpu_mips_store_count(env
, arg1
);
1450 void helper_mtc0_entryhi (target_ulong arg1
)
1452 target_ulong old
, val
;
1454 /* 1k pages not implemented */
1455 val
= arg1
& ((TARGET_PAGE_MASK
<< 1) | 0xFF);
1456 #if defined(TARGET_MIPS64)
1457 val
&= env
->SEGMask
;
1459 old
= env
->CP0_EntryHi
;
1460 env
->CP0_EntryHi
= val
;
1461 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1462 sync_c0_entryhi(env
, env
->current_tc
);
1464 /* If the ASID changes, flush qemu's TLB. */
1465 if ((old
& 0xFF) != (val
& 0xFF))
1466 cpu_mips_tlb_flush(env
, 1);
1469 void helper_mttc0_entryhi(target_ulong arg1
)
1471 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1472 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1474 other
->CP0_EntryHi
= arg1
;
1475 sync_c0_entryhi(other
, other_tc
);
1478 void helper_mtc0_compare (target_ulong arg1
)
1480 cpu_mips_store_compare(env
, arg1
);
1483 void helper_mtc0_status (target_ulong arg1
)
1486 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
1489 old
= env
->CP0_Status
;
1490 env
->CP0_Status
= (env
->CP0_Status
& ~mask
) | val
;
1491 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1492 sync_c0_status(env
, env
->current_tc
);
1494 compute_hflags(env
);
1497 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1498 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1499 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1500 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1502 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1503 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1504 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1505 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1506 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
1511 void helper_mttc0_status(target_ulong arg1
)
1513 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1514 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1516 other
->CP0_Status
= arg1
& ~0xf1000018;
1517 sync_c0_status(other
, other_tc
);
1520 void helper_mtc0_intctl (target_ulong arg1
)
1522 /* vectored interrupts not implemented, no performance counters. */
1523 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1526 void helper_mtc0_srsctl (target_ulong arg1
)
1528 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1529 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1532 static void mtc0_cause(CPUMIPSState
*cpu
, target_ulong arg1
)
1534 uint32_t mask
= 0x00C00300;
1535 uint32_t old
= cpu
->CP0_Cause
;
1538 if (cpu
->insn_flags
& ISA_MIPS32R2
) {
1539 mask
|= 1 << CP0Ca_DC
;
1542 cpu
->CP0_Cause
= (cpu
->CP0_Cause
& ~mask
) | (arg1
& mask
);
1544 if ((old
^ cpu
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
1545 if (cpu
->CP0_Cause
& (1 << CP0Ca_DC
)) {
1546 cpu_mips_stop_count(cpu
);
1548 cpu_mips_start_count(cpu
);
1552 /* Set/reset software interrupts */
1553 for (i
= 0 ; i
< 2 ; i
++) {
1554 if ((old
^ cpu
->CP0_Cause
) & (1 << (CP0Ca_IP
+ i
))) {
1555 cpu_mips_soft_irq(cpu
, i
, cpu
->CP0_Cause
& (1 << (CP0Ca_IP
+ i
)));
1560 void helper_mtc0_cause(target_ulong arg1
)
1562 mtc0_cause(env
, arg1
);
1565 void helper_mttc0_cause(target_ulong arg1
)
1567 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1568 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1570 mtc0_cause(other
, arg1
);
1573 target_ulong
helper_mftc0_epc(void)
1575 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1576 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1578 return other
->CP0_EPC
;
1581 target_ulong
helper_mftc0_ebase(void)
1583 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1584 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1586 return other
->CP0_EBase
;
1589 void helper_mtc0_ebase (target_ulong arg1
)
1591 /* vectored interrupts not implemented */
1592 env
->CP0_EBase
= (env
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1595 void helper_mttc0_ebase(target_ulong arg1
)
1597 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1598 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1599 other
->CP0_EBase
= (other
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1602 target_ulong
helper_mftc0_configx(target_ulong idx
)
1604 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1605 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1608 case 0: return other
->CP0_Config0
;
1609 case 1: return other
->CP0_Config1
;
1610 case 2: return other
->CP0_Config2
;
1611 case 3: return other
->CP0_Config3
;
1612 /* 4 and 5 are reserved. */
1613 case 6: return other
->CP0_Config6
;
1614 case 7: return other
->CP0_Config7
;
1621 void helper_mtc0_config0 (target_ulong arg1
)
1623 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1626 void helper_mtc0_config2 (target_ulong arg1
)
1628 /* tertiary/secondary caches not implemented */
1629 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1632 void helper_mtc0_lladdr (target_ulong arg1
)
1634 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1635 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1636 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1639 void helper_mtc0_watchlo (target_ulong arg1
, uint32_t sel
)
1641 /* Watch exceptions for instructions, data loads, data stores
1643 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1646 void helper_mtc0_watchhi (target_ulong arg1
, uint32_t sel
)
1648 env
->CP0_WatchHi
[sel
] = (arg1
& 0x40FF0FF8);
1649 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1652 void helper_mtc0_xcontext (target_ulong arg1
)
1654 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1655 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1658 void helper_mtc0_framemask (target_ulong arg1
)
1660 env
->CP0_Framemask
= arg1
; /* XXX */
1663 void helper_mtc0_debug (target_ulong arg1
)
1665 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1666 if (arg1
& (1 << CP0DB_DM
))
1667 env
->hflags
|= MIPS_HFLAG_DM
;
1669 env
->hflags
&= ~MIPS_HFLAG_DM
;
1672 void helper_mttc0_debug(target_ulong arg1
)
1674 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1675 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1676 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1678 /* XXX: Might be wrong, check with EJTAG spec. */
1679 if (other_tc
== other
->current_tc
)
1680 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1682 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1683 other
->CP0_Debug
= (other
->CP0_Debug
&
1684 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1685 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1688 void helper_mtc0_performance0 (target_ulong arg1
)
1690 env
->CP0_Performance0
= arg1
& 0x000007ff;
1693 void helper_mtc0_taglo (target_ulong arg1
)
1695 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1698 void helper_mtc0_datalo (target_ulong arg1
)
1700 env
->CP0_DataLo
= arg1
; /* XXX */
1703 void helper_mtc0_taghi (target_ulong arg1
)
1705 env
->CP0_TagHi
= arg1
; /* XXX */
1708 void helper_mtc0_datahi (target_ulong arg1
)
1710 env
->CP0_DataHi
= arg1
; /* XXX */
1713 /* MIPS MT functions */
1714 target_ulong
helper_mftgpr(uint32_t sel
)
1716 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1717 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1719 if (other_tc
== other
->current_tc
)
1720 return other
->active_tc
.gpr
[sel
];
1722 return other
->tcs
[other_tc
].gpr
[sel
];
1725 target_ulong
helper_mftlo(uint32_t sel
)
1727 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1728 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1730 if (other_tc
== other
->current_tc
)
1731 return other
->active_tc
.LO
[sel
];
1733 return other
->tcs
[other_tc
].LO
[sel
];
1736 target_ulong
helper_mfthi(uint32_t sel
)
1738 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1739 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1741 if (other_tc
== other
->current_tc
)
1742 return other
->active_tc
.HI
[sel
];
1744 return other
->tcs
[other_tc
].HI
[sel
];
1747 target_ulong
helper_mftacx(uint32_t sel
)
1749 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1750 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1752 if (other_tc
== other
->current_tc
)
1753 return other
->active_tc
.ACX
[sel
];
1755 return other
->tcs
[other_tc
].ACX
[sel
];
1758 target_ulong
helper_mftdsp(void)
1760 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1761 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1763 if (other_tc
== other
->current_tc
)
1764 return other
->active_tc
.DSPControl
;
1766 return other
->tcs
[other_tc
].DSPControl
;
1769 void helper_mttgpr(target_ulong arg1
, uint32_t sel
)
1771 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1772 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1774 if (other_tc
== other
->current_tc
)
1775 other
->active_tc
.gpr
[sel
] = arg1
;
1777 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1780 void helper_mttlo(target_ulong arg1
, uint32_t sel
)
1782 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1783 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1785 if (other_tc
== other
->current_tc
)
1786 other
->active_tc
.LO
[sel
] = arg1
;
1788 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1791 void helper_mtthi(target_ulong arg1
, uint32_t sel
)
1793 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1794 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1796 if (other_tc
== other
->current_tc
)
1797 other
->active_tc
.HI
[sel
] = arg1
;
1799 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1802 void helper_mttacx(target_ulong arg1
, uint32_t sel
)
1804 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1805 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1807 if (other_tc
== other
->current_tc
)
1808 other
->active_tc
.ACX
[sel
] = arg1
;
1810 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1813 void helper_mttdsp(target_ulong arg1
)
1815 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1816 CPUMIPSState
*other
= mips_cpu_map_tc(&other_tc
);
1818 if (other_tc
== other
->current_tc
)
1819 other
->active_tc
.DSPControl
= arg1
;
1821 other
->tcs
[other_tc
].DSPControl
= arg1
;
1824 /* MIPS MT functions */
1825 target_ulong
helper_dmt(void)
1831 target_ulong
helper_emt(void)
1837 target_ulong
helper_dvpe(void)
1839 CPUMIPSState
*other_cpu
= first_cpu
;
1840 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1843 /* Turn off all VPEs except the one executing the dvpe. */
1844 if (other_cpu
!= env
) {
1845 other_cpu
->mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1846 mips_vpe_sleep(other_cpu
);
1848 other_cpu
= other_cpu
->next_cpu
;
1849 } while (other_cpu
);
1853 target_ulong
helper_evpe(void)
1855 CPUMIPSState
*other_cpu
= first_cpu
;
1856 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1859 if (other_cpu
!= env
1860 /* If the VPE is WFI, don't disturb its sleep. */
1861 && !mips_vpe_is_wfi(other_cpu
)) {
1862 /* Enable the VPE. */
1863 other_cpu
->mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1864 mips_vpe_wake(other_cpu
); /* And wake it up. */
1866 other_cpu
= other_cpu
->next_cpu
;
1867 } while (other_cpu
);
1870 #endif /* !CONFIG_USER_ONLY */
1872 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1874 // arg1 = rt, arg2 = rs
1876 // TODO: store to TC register
1879 target_ulong
helper_yield(target_ulong arg
)
1881 target_long arg1
= arg
;
1884 /* No scheduling policy implemented. */
1886 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1887 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1888 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1889 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1890 helper_raise_exception(EXCP_THREAD
);
1893 } else if (arg1
== 0) {
1894 if (0 /* TODO: TC underflow */) {
1895 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1896 helper_raise_exception(EXCP_THREAD
);
1898 // TODO: Deallocate TC
1900 } else if (arg1
> 0) {
1901 /* Yield qualifier inputs not implemented. */
1902 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1903 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1904 helper_raise_exception(EXCP_THREAD
);
1906 return env
->CP0_YQMask
;
1909 #ifndef CONFIG_USER_ONLY
1910 /* TLB management */
1911 static void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
)
1913 /* Flush qemu's TLB and discard all shadowed entries. */
1914 tlb_flush (env
, flush_global
);
1915 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
1918 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1920 /* Discard entries from env->tlb[first] onwards. */
1921 while (env
->tlb
->tlb_in_use
> first
) {
1922 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1926 static void r4k_fill_tlb (int idx
)
1930 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1931 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1932 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1933 #if defined(TARGET_MIPS64)
1934 tlb
->VPN
&= env
->SEGMask
;
1936 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1937 tlb
->PageMask
= env
->CP0_PageMask
;
1938 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1939 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1940 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1941 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1942 tlb
->PFN
[0] = (env
->CP0_EntryLo0
>> 6) << 12;
1943 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
1944 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
1945 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
1946 tlb
->PFN
[1] = (env
->CP0_EntryLo1
>> 6) << 12;
1949 void r4k_helper_tlbwi (void)
1953 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
1955 /* Discard cached TLB entries. We could avoid doing this if the
1956 tlbwi is just upgrading access permissions on the current entry;
1957 that might be a further win. */
1958 r4k_mips_tlb_flush_extra (env
, env
->tlb
->nb_tlb
);
1960 r4k_invalidate_tlb(env
, idx
, 0);
1964 void r4k_helper_tlbwr (void)
1966 int r
= cpu_mips_get_random(env
);
1968 r4k_invalidate_tlb(env
, r
, 1);
1972 void r4k_helper_tlbp (void)
1981 ASID
= env
->CP0_EntryHi
& 0xFF;
1982 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
1983 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1984 /* 1k pages are not supported. */
1985 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1986 tag
= env
->CP0_EntryHi
& ~mask
;
1987 VPN
= tlb
->VPN
& ~mask
;
1988 /* Check ASID, virtual page number & size */
1989 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1995 if (i
== env
->tlb
->nb_tlb
) {
1996 /* No match. Discard any shadow entries, if any of them match. */
1997 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
1998 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1999 /* 1k pages are not supported. */
2000 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2001 tag
= env
->CP0_EntryHi
& ~mask
;
2002 VPN
= tlb
->VPN
& ~mask
;
2003 /* Check ASID, virtual page number & size */
2004 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2005 r4k_mips_tlb_flush_extra (env
, i
);
2010 env
->CP0_Index
|= 0x80000000;
2014 void r4k_helper_tlbr (void)
2020 ASID
= env
->CP0_EntryHi
& 0xFF;
2021 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2022 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2024 /* If this will change the current ASID, flush qemu's TLB. */
2025 if (ASID
!= tlb
->ASID
)
2026 cpu_mips_tlb_flush (env
, 1);
2028 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2030 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2031 env
->CP0_PageMask
= tlb
->PageMask
;
2032 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2033 (tlb
->C0
<< 3) | (tlb
->PFN
[0] >> 6);
2034 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2035 (tlb
->C1
<< 3) | (tlb
->PFN
[1] >> 6);
2038 void helper_tlbwi(void)
2040 env
->tlb
->helper_tlbwi();
2043 void helper_tlbwr(void)
2045 env
->tlb
->helper_tlbwr();
2048 void helper_tlbp(void)
2050 env
->tlb
->helper_tlbp();
2053 void helper_tlbr(void)
2055 env
->tlb
->helper_tlbr();
2059 target_ulong
helper_di (void)
2061 target_ulong t0
= env
->CP0_Status
;
2063 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2067 target_ulong
helper_ei (void)
2069 target_ulong t0
= env
->CP0_Status
;
2071 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2075 static void debug_pre_eret (void)
2077 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2078 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2079 env
->active_tc
.PC
, env
->CP0_EPC
);
2080 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2081 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2082 if (env
->hflags
& MIPS_HFLAG_DM
)
2083 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2088 static void debug_post_eret (void)
2090 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2091 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2092 env
->active_tc
.PC
, env
->CP0_EPC
);
2093 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2094 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2095 if (env
->hflags
& MIPS_HFLAG_DM
)
2096 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2097 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
2098 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2099 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2100 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2101 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
2106 static void set_pc (target_ulong error_pc
)
2108 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2110 env
->hflags
|= MIPS_HFLAG_M16
;
2112 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2116 void helper_eret (void)
2119 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2120 set_pc(env
->CP0_ErrorEPC
);
2121 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2123 set_pc(env
->CP0_EPC
);
2124 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2126 compute_hflags(env
);
2131 void helper_deret (void)
2134 set_pc(env
->CP0_DEPC
);
2136 env
->hflags
&= MIPS_HFLAG_DM
;
2137 compute_hflags(env
);
2141 #endif /* !CONFIG_USER_ONLY */
2143 target_ulong
helper_rdhwr_cpunum(void)
2145 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2146 (env
->CP0_HWREna
& (1 << 0)))
2147 return env
->CP0_EBase
& 0x3ff;
2149 helper_raise_exception(EXCP_RI
);
2154 target_ulong
helper_rdhwr_synci_step(void)
2156 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2157 (env
->CP0_HWREna
& (1 << 1)))
2158 return env
->SYNCI_Step
;
2160 helper_raise_exception(EXCP_RI
);
2165 target_ulong
helper_rdhwr_cc(void)
2167 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2168 (env
->CP0_HWREna
& (1 << 2)))
2169 return env
->CP0_Count
;
2171 helper_raise_exception(EXCP_RI
);
2176 target_ulong
helper_rdhwr_ccres(void)
2178 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2179 (env
->CP0_HWREna
& (1 << 3)))
2182 helper_raise_exception(EXCP_RI
);
2187 void helper_pmon (int function
)
2191 case 2: /* TODO: char inbyte(int waitflag); */
2192 if (env
->active_tc
.gpr
[4] == 0)
2193 env
->active_tc
.gpr
[2] = -1;
2195 case 11: /* TODO: char inbyte (void); */
2196 env
->active_tc
.gpr
[2] = -1;
2200 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2206 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2213 void helper_wait (void)
2216 cpu_reset_interrupt(env
, CPU_INTERRUPT_WAKE
);
2217 helper_raise_exception(EXCP_HLT
);
2220 #if !defined(CONFIG_USER_ONLY)
2222 static void QEMU_NORETURN
do_unaligned_access(target_ulong addr
, int is_write
,
2223 int is_user
, uintptr_t retaddr
);
2225 #define MMUSUFFIX _mmu
2226 #define ALIGNED_ONLY
2229 #include "softmmu_template.h"
2232 #include "softmmu_template.h"
2235 #include "softmmu_template.h"
2238 #include "softmmu_template.h"
2240 static void do_unaligned_access(target_ulong addr
, int is_write
,
2241 int is_user
, uintptr_t retaddr
)
2243 env
->CP0_BadVAddr
= addr
;
2244 do_restore_state (retaddr
);
2245 helper_raise_exception ((is_write
== 1) ? EXCP_AdES
: EXCP_AdEL
);
2248 void tlb_fill(CPUMIPSState
*env1
, target_ulong addr
, int is_write
, int mmu_idx
,
2251 TranslationBlock
*tb
;
2252 CPUMIPSState
*saved_env
;
2257 ret
= cpu_mips_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
);
2260 /* now we have a real cpu fault */
2261 tb
= tb_find_pc(retaddr
);
2263 /* the PC is inside the translated code. It means that we have
2264 a virtual CPU fault */
2265 cpu_restore_state(tb
, env
, retaddr
);
2268 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
2273 void cpu_unassigned_access(CPUMIPSState
*env1
, target_phys_addr_t addr
,
2274 int is_write
, int is_exec
, int unused
, int size
)
2279 helper_raise_exception(EXCP_IBE
);
2281 helper_raise_exception(EXCP_DBE
);
2283 #endif /* !CONFIG_USER_ONLY */
2285 /* Complex FPU operations which may need stack space. */
2287 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
2288 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
2289 #define FLOAT_TWO32 make_float32(1 << 30)
2290 #define FLOAT_TWO64 make_float64(1ULL << 62)
2291 #define FLOAT_QNAN32 0x7fbfffff
2292 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
2293 #define FLOAT_SNAN32 0x7fffffff
2294 #define FLOAT_SNAN64 0x7fffffffffffffffULL
2296 /* convert MIPS rounding mode in FCR31 to IEEE library */
2297 static unsigned int ieee_rm
[] = {
2298 float_round_nearest_even
,
2299 float_round_to_zero
,
2304 #define RESTORE_ROUNDING_MODE \
2305 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2307 #define RESTORE_FLUSH_MODE \
2308 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2310 target_ulong
helper_cfc1 (uint32_t reg
)
2316 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2319 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2322 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2325 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2328 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2335 void helper_ctc1 (target_ulong arg1
, uint32_t reg
)
2339 if (arg1
& 0xffffff00)
2341 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2342 ((arg1
& 0x1) << 23);
2345 if (arg1
& 0x007c0000)
2347 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2350 if (arg1
& 0x007c0000)
2352 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2353 ((arg1
& 0x4) << 22);
2356 if (arg1
& 0x007c0000)
2358 env
->active_fpu
.fcr31
= arg1
;
2363 /* set rounding mode */
2364 RESTORE_ROUNDING_MODE
;
2365 /* set flush-to-zero mode */
2367 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2368 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2369 helper_raise_exception(EXCP_FPE
);
2372 static inline int ieee_ex_to_mips(int xcpt
)
2376 if (xcpt
& float_flag_invalid
) {
2379 if (xcpt
& float_flag_overflow
) {
2382 if (xcpt
& float_flag_underflow
) {
2383 ret
|= FP_UNDERFLOW
;
2385 if (xcpt
& float_flag_divbyzero
) {
2388 if (xcpt
& float_flag_inexact
) {
2395 static inline void update_fcr31(void)
2397 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2399 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2400 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
)
2401 helper_raise_exception(EXCP_FPE
);
2403 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2407 Single precition routines have a "s" suffix, double precision a
2408 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2409 paired single lower "pl", paired single upper "pu". */
2411 /* unary operations, modifying fp status */
2412 uint64_t helper_float_sqrt_d(uint64_t fdt0
)
2414 return float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2417 uint32_t helper_float_sqrt_s(uint32_t fst0
)
2419 return float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2422 uint64_t helper_float_cvtd_s(uint32_t fst0
)
2426 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2427 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2432 uint64_t helper_float_cvtd_w(uint32_t wt0
)
2436 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2437 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2442 uint64_t helper_float_cvtd_l(uint64_t dt0
)
2446 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2447 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2452 uint64_t helper_float_cvtl_d(uint64_t fdt0
)
2456 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2457 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2459 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2464 uint64_t helper_float_cvtl_s(uint32_t fst0
)
2468 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2469 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2471 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2476 uint64_t helper_float_cvtps_pw(uint64_t dt0
)
2481 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2482 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2483 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2485 return ((uint64_t)fsth2
<< 32) | fst2
;
2488 uint64_t helper_float_cvtpw_ps(uint64_t fdt0
)
2493 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2494 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2495 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2497 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
)) {
2499 wth2
= FLOAT_SNAN32
;
2501 return ((uint64_t)wth2
<< 32) | wt2
;
2504 uint32_t helper_float_cvts_d(uint64_t fdt0
)
2508 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2509 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2514 uint32_t helper_float_cvts_w(uint32_t wt0
)
2518 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2519 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2524 uint32_t helper_float_cvts_l(uint64_t dt0
)
2528 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2529 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2534 uint32_t helper_float_cvts_pl(uint32_t wt0
)
2538 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2544 uint32_t helper_float_cvts_pu(uint32_t wth0
)
2548 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2554 uint32_t helper_float_cvtw_s(uint32_t fst0
)
2558 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2559 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2561 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2566 uint32_t helper_float_cvtw_d(uint64_t fdt0
)
2570 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2571 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2573 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2578 uint64_t helper_float_roundl_d(uint64_t fdt0
)
2582 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2583 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2584 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2585 RESTORE_ROUNDING_MODE
;
2587 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2592 uint64_t helper_float_roundl_s(uint32_t fst0
)
2596 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2597 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2598 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2599 RESTORE_ROUNDING_MODE
;
2601 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2606 uint32_t helper_float_roundw_d(uint64_t fdt0
)
2610 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2611 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2612 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2613 RESTORE_ROUNDING_MODE
;
2615 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2620 uint32_t helper_float_roundw_s(uint32_t fst0
)
2624 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2625 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2626 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2627 RESTORE_ROUNDING_MODE
;
2629 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2634 uint64_t helper_float_truncl_d(uint64_t fdt0
)
2638 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2639 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2641 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2646 uint64_t helper_float_truncl_s(uint32_t fst0
)
2650 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2651 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2653 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2658 uint32_t helper_float_truncw_d(uint64_t fdt0
)
2662 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2663 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2665 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2670 uint32_t helper_float_truncw_s(uint32_t fst0
)
2674 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2675 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2677 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2682 uint64_t helper_float_ceill_d(uint64_t fdt0
)
2686 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2687 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2688 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2689 RESTORE_ROUNDING_MODE
;
2691 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2696 uint64_t helper_float_ceill_s(uint32_t fst0
)
2700 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2701 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2702 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2703 RESTORE_ROUNDING_MODE
;
2705 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2710 uint32_t helper_float_ceilw_d(uint64_t fdt0
)
2714 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2715 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2716 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2717 RESTORE_ROUNDING_MODE
;
2719 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2724 uint32_t helper_float_ceilw_s(uint32_t fst0
)
2728 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2729 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2730 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2731 RESTORE_ROUNDING_MODE
;
2733 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2738 uint64_t helper_float_floorl_d(uint64_t fdt0
)
2742 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2743 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2744 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2745 RESTORE_ROUNDING_MODE
;
2747 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2752 uint64_t helper_float_floorl_s(uint32_t fst0
)
2756 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2757 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2758 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2759 RESTORE_ROUNDING_MODE
;
2761 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2766 uint32_t helper_float_floorw_d(uint64_t fdt0
)
2770 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2771 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2772 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2773 RESTORE_ROUNDING_MODE
;
2775 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2780 uint32_t helper_float_floorw_s(uint32_t fst0
)
2784 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2785 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2786 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2787 RESTORE_ROUNDING_MODE
;
2789 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2794 /* unary operations, not modifying fp status */
2795 #define FLOAT_UNOP(name) \
2796 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2798 return float64_ ## name(fdt0); \
2800 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2802 return float32_ ## name(fst0); \
2804 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2809 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2810 wth0 = float32_ ## name(fdt0 >> 32); \
2811 return ((uint64_t)wth0 << 32) | wt0; \
2817 /* MIPS specific unary operations */
2818 uint64_t helper_float_recip_d(uint64_t fdt0
)
2822 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2823 fdt2
= float64_div(FLOAT_ONE64
, fdt0
, &env
->active_fpu
.fp_status
);
2828 uint32_t helper_float_recip_s(uint32_t fst0
)
2832 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2833 fst2
= float32_div(FLOAT_ONE32
, fst0
, &env
->active_fpu
.fp_status
);
2838 uint64_t helper_float_rsqrt_d(uint64_t fdt0
)
2842 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2843 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2844 fdt2
= float64_div(FLOAT_ONE64
, fdt2
, &env
->active_fpu
.fp_status
);
2849 uint32_t helper_float_rsqrt_s(uint32_t fst0
)
2853 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2854 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2855 fst2
= float32_div(FLOAT_ONE32
, fst2
, &env
->active_fpu
.fp_status
);
2860 uint64_t helper_float_recip1_d(uint64_t fdt0
)
2864 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2865 fdt2
= float64_div(FLOAT_ONE64
, fdt0
, &env
->active_fpu
.fp_status
);
2870 uint32_t helper_float_recip1_s(uint32_t fst0
)
2874 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2875 fst2
= float32_div(FLOAT_ONE32
, fst0
, &env
->active_fpu
.fp_status
);
2880 uint64_t helper_float_recip1_ps(uint64_t fdt0
)
2885 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2886 fst2
= float32_div(FLOAT_ONE32
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2887 fsth2
= float32_div(FLOAT_ONE32
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
2889 return ((uint64_t)fsth2
<< 32) | fst2
;
2892 uint64_t helper_float_rsqrt1_d(uint64_t fdt0
)
2896 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2897 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2898 fdt2
= float64_div(FLOAT_ONE64
, fdt2
, &env
->active_fpu
.fp_status
);
2903 uint32_t helper_float_rsqrt1_s(uint32_t fst0
)
2907 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2908 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2909 fst2
= float32_div(FLOAT_ONE32
, fst2
, &env
->active_fpu
.fp_status
);
2914 uint64_t helper_float_rsqrt1_ps(uint64_t fdt0
)
2919 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2920 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2921 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2922 fst2
= float32_div(FLOAT_ONE32
, fst2
, &env
->active_fpu
.fp_status
);
2923 fsth2
= float32_div(FLOAT_ONE32
, fsth2
, &env
->active_fpu
.fp_status
);
2925 return ((uint64_t)fsth2
<< 32) | fst2
;
2928 #define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2930 /* binary operations */
2931 #define FLOAT_BINOP(name) \
2932 uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2936 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2937 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2939 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2940 dt2 = FLOAT_QNAN64; \
2944 uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2948 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2949 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2951 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2952 wt2 = FLOAT_QNAN32; \
2956 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2958 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2959 uint32_t fsth0 = fdt0 >> 32; \
2960 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2961 uint32_t fsth1 = fdt1 >> 32; \
2965 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2966 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2967 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2969 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2970 wt2 = FLOAT_QNAN32; \
2971 wth2 = FLOAT_QNAN32; \
2973 return ((uint64_t)wth2 << 32) | wt2; \
2982 /* ternary operations */
2983 #define FLOAT_TERNOP(name1, name2) \
2984 uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2987 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2988 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2991 uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2994 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2995 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2998 uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
3001 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3002 uint32_t fsth0 = fdt0 >> 32; \
3003 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3004 uint32_t fsth1 = fdt1 >> 32; \
3005 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3006 uint32_t fsth2 = fdt2 >> 32; \
3008 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
3009 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
3010 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
3011 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
3012 return ((uint64_t)fsth2 << 32) | fst2; \
3015 FLOAT_TERNOP(mul
, add
)
3016 FLOAT_TERNOP(mul
, sub
)
3019 /* negated ternary operations */
3020 #define FLOAT_NTERNOP(name1, name2) \
3021 uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
3024 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
3025 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
3026 return float64_chs(fdt2); \
3029 uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
3032 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
3033 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
3034 return float32_chs(fst2); \
3037 uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
3040 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3041 uint32_t fsth0 = fdt0 >> 32; \
3042 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3043 uint32_t fsth1 = fdt1 >> 32; \
3044 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3045 uint32_t fsth2 = fdt2 >> 32; \
3047 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
3048 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
3049 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
3050 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
3051 fst2 = float32_chs(fst2); \
3052 fsth2 = float32_chs(fsth2); \
3053 return ((uint64_t)fsth2 << 32) | fst2; \
3056 FLOAT_NTERNOP(mul
, add
)
3057 FLOAT_NTERNOP(mul
, sub
)
3058 #undef FLOAT_NTERNOP
3060 /* MIPS specific binary operations */
3061 uint64_t helper_float_recip2_d(uint64_t fdt0
, uint64_t fdt2
)
3063 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3064 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3065 fdt2
= float64_chs(float64_sub(fdt2
, FLOAT_ONE64
, &env
->active_fpu
.fp_status
));
3070 uint32_t helper_float_recip2_s(uint32_t fst0
, uint32_t fst2
)
3072 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3073 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3074 fst2
= float32_chs(float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
));
3079 uint64_t helper_float_recip2_ps(uint64_t fdt0
, uint64_t fdt2
)
3081 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3082 uint32_t fsth0
= fdt0
>> 32;
3083 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3084 uint32_t fsth2
= fdt2
>> 32;
3086 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3087 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3088 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3089 fst2
= float32_chs(float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
));
3090 fsth2
= float32_chs(float32_sub(fsth2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
));
3092 return ((uint64_t)fsth2
<< 32) | fst2
;
3095 uint64_t helper_float_rsqrt2_d(uint64_t fdt0
, uint64_t fdt2
)
3097 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3098 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3099 fdt2
= float64_sub(fdt2
, FLOAT_ONE64
, &env
->active_fpu
.fp_status
);
3100 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3105 uint32_t helper_float_rsqrt2_s(uint32_t fst0
, uint32_t fst2
)
3107 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3108 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3109 fst2
= float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
);
3110 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3115 uint64_t helper_float_rsqrt2_ps(uint64_t fdt0
, uint64_t fdt2
)
3117 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3118 uint32_t fsth0
= fdt0
>> 32;
3119 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3120 uint32_t fsth2
= fdt2
>> 32;
3122 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3123 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3124 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3125 fst2
= float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
);
3126 fsth2
= float32_sub(fsth2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
);
3127 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3128 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3130 return ((uint64_t)fsth2
<< 32) | fst2
;
3133 uint64_t helper_float_addr_ps(uint64_t fdt0
, uint64_t fdt1
)
3135 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3136 uint32_t fsth0
= fdt0
>> 32;
3137 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3138 uint32_t fsth1
= fdt1
>> 32;
3142 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3143 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3144 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3146 return ((uint64_t)fsth2
<< 32) | fst2
;
3149 uint64_t helper_float_mulr_ps(uint64_t fdt0
, uint64_t fdt1
)
3151 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3152 uint32_t fsth0
= fdt0
>> 32;
3153 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3154 uint32_t fsth1
= fdt1
>> 32;
3158 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3159 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3160 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3162 return ((uint64_t)fsth2
<< 32) | fst2
;
3165 /* compare operations */
3166 #define FOP_COND_D(op, cond) \
3167 void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
3170 set_float_exception_flags(0, &env->active_fpu.fp_status); \
3174 SET_FP_COND(cc, env->active_fpu); \
3176 CLEAR_FP_COND(cc, env->active_fpu); \
3178 void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
3181 set_float_exception_flags(0, &env->active_fpu.fp_status); \
3182 fdt0 = float64_abs(fdt0); \
3183 fdt1 = float64_abs(fdt1); \
3187 SET_FP_COND(cc, env->active_fpu); \
3189 CLEAR_FP_COND(cc, env->active_fpu); \
3192 /* NOTE: the comma operator will make "cond" to eval to false,
3193 * but float64_unordered_quiet() is still called. */
3194 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3195 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3196 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3197 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3198 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3199 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3200 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3201 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3202 /* NOTE: the comma operator will make "cond" to eval to false,
3203 * but float64_unordered() is still called. */
3204 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3205 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3206 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3207 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3208 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3209 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3210 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3211 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3213 #define FOP_COND_S(op, cond) \
3214 void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
3217 set_float_exception_flags(0, &env->active_fpu.fp_status); \
3221 SET_FP_COND(cc, env->active_fpu); \
3223 CLEAR_FP_COND(cc, env->active_fpu); \
3225 void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
3228 set_float_exception_flags(0, &env->active_fpu.fp_status); \
3229 fst0 = float32_abs(fst0); \
3230 fst1 = float32_abs(fst1); \
3234 SET_FP_COND(cc, env->active_fpu); \
3236 CLEAR_FP_COND(cc, env->active_fpu); \
3239 /* NOTE: the comma operator will make "cond" to eval to false,
3240 * but float32_unordered_quiet() is still called. */
3241 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3242 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3243 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3244 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3245 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3246 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3247 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3248 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3249 /* NOTE: the comma operator will make "cond" to eval to false,
3250 * but float32_unordered() is still called. */
3251 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3252 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3253 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3254 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3255 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3256 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3257 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3258 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3260 #define FOP_COND_PS(op, condl, condh) \
3261 void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
3263 uint32_t fst0, fsth0, fst1, fsth1; \
3265 set_float_exception_flags(0, &env->active_fpu.fp_status); \
3266 fst0 = fdt0 & 0XFFFFFFFF; \
3267 fsth0 = fdt0 >> 32; \
3268 fst1 = fdt1 & 0XFFFFFFFF; \
3269 fsth1 = fdt1 >> 32; \
3274 SET_FP_COND(cc, env->active_fpu); \
3276 CLEAR_FP_COND(cc, env->active_fpu); \
3278 SET_FP_COND(cc + 1, env->active_fpu); \
3280 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3282 void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
3284 uint32_t fst0, fsth0, fst1, fsth1; \
3286 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3287 fsth0 = float32_abs(fdt0 >> 32); \
3288 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3289 fsth1 = float32_abs(fdt1 >> 32); \
3294 SET_FP_COND(cc, env->active_fpu); \
3296 CLEAR_FP_COND(cc, env->active_fpu); \
3298 SET_FP_COND(cc + 1, env->active_fpu); \
3300 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3303 /* NOTE: the comma operator will make "cond" to eval to false,
3304 * but float32_unordered_quiet() is still called. */
3305 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3306 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3307 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3308 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3309 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3310 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3311 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3312 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3313 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3314 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3315 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3316 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3317 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3318 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3319 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3320 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3321 /* NOTE: the comma operator will make "cond" to eval to false,
3322 * but float32_unordered() is still called. */
3323 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3324 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3325 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3326 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3327 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3328 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3329 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3330 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3331 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3332 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3333 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3334 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3335 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3336 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3337 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3338 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))