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ppc: parse cpu features once
[qemu/ar7.git] / target-mips / translate_init.c
blob39ed5c4c1b129b88f82555181d04b6e8714e43df
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t CP1_fcr31_rw_bitmask;
88 int32_t CP1_fcr31;
89 int32_t MSAIR;
90 int32_t SEGBITS;
91 int32_t PABITS;
92 int32_t CP0_SRSConf0_rw_bitmask;
93 int32_t CP0_SRSConf0;
94 int32_t CP0_SRSConf1_rw_bitmask;
95 int32_t CP0_SRSConf1;
96 int32_t CP0_SRSConf2_rw_bitmask;
97 int32_t CP0_SRSConf2;
98 int32_t CP0_SRSConf3_rw_bitmask;
99 int32_t CP0_SRSConf3;
100 int32_t CP0_SRSConf4_rw_bitmask;
101 int32_t CP0_SRSConf4;
102 int32_t CP0_PageGrain_rw_bitmask;
103 int32_t CP0_PageGrain;
104 int insn_flags;
105 enum mips_mmu_types mmu_type;
106 };
107
108 /*****************************************************************************/
109 /* MIPS CPU definitions */
110 static const mips_def_t mips_defs[] =
111 {
112 {
113 .name = "4Kc",
114 .CP0_PRid = 0x00018000,
115 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
116 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
117 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
118 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
119 (0 << CP0C1_CA),
120 .CP0_Config2 = MIPS_CONFIG2,
121 .CP0_Config3 = MIPS_CONFIG3,
122 .CP0_LLAddr_rw_bitmask = 0,
123 .CP0_LLAddr_shift = 4,
124 .SYNCI_Step = 32,
125 .CCRes = 2,
126 .CP0_Status_rw_bitmask = 0x1278FF17,
127 .SEGBITS = 32,
128 .PABITS = 32,
129 .insn_flags = CPU_MIPS32,
130 .mmu_type = MMU_TYPE_R4000,
131 },
132 {
133 .name = "4Km",
134 .CP0_PRid = 0x00018300,
135 /* Config1 implemented, fixed mapping MMU,
136 no virtual icache, uncached coherency. */
137 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
138 .CP0_Config1 = MIPS_CONFIG1 |
139 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
140 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
141 (1 << CP0C1_CA),
142 .CP0_Config2 = MIPS_CONFIG2,
143 .CP0_Config3 = MIPS_CONFIG3,
144 .CP0_LLAddr_rw_bitmask = 0,
145 .CP0_LLAddr_shift = 4,
146 .SYNCI_Step = 32,
147 .CCRes = 2,
148 .CP0_Status_rw_bitmask = 0x1258FF17,
149 .SEGBITS = 32,
150 .PABITS = 32,
151 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
152 .mmu_type = MMU_TYPE_FMT,
153 },
154 {
155 .name = "4KEcR1",
156 .CP0_PRid = 0x00018400,
157 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
158 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
159 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
160 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
161 (0 << CP0C1_CA),
162 .CP0_Config2 = MIPS_CONFIG2,
163 .CP0_Config3 = MIPS_CONFIG3,
164 .CP0_LLAddr_rw_bitmask = 0,
165 .CP0_LLAddr_shift = 4,
166 .SYNCI_Step = 32,
167 .CCRes = 2,
168 .CP0_Status_rw_bitmask = 0x1278FF17,
169 .SEGBITS = 32,
170 .PABITS = 32,
171 .insn_flags = CPU_MIPS32,
172 .mmu_type = MMU_TYPE_R4000,
173 },
174 {
175 .name = "4KEmR1",
176 .CP0_PRid = 0x00018500,
177 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
178 .CP0_Config1 = MIPS_CONFIG1 |
179 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
180 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
181 (1 << CP0C1_CA),
182 .CP0_Config2 = MIPS_CONFIG2,
183 .CP0_Config3 = MIPS_CONFIG3,
184 .CP0_LLAddr_rw_bitmask = 0,
185 .CP0_LLAddr_shift = 4,
186 .SYNCI_Step = 32,
187 .CCRes = 2,
188 .CP0_Status_rw_bitmask = 0x1258FF17,
189 .SEGBITS = 32,
190 .PABITS = 32,
191 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
192 .mmu_type = MMU_TYPE_FMT,
193 },
194 {
195 .name = "4KEc",
196 .CP0_PRid = 0x00019000,
197 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
198 (MMU_TYPE_R4000 << CP0C0_MT),
199 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
200 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
201 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
202 (0 << CP0C1_CA),
203 .CP0_Config2 = MIPS_CONFIG2,
204 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
205 .CP0_LLAddr_rw_bitmask = 0,
206 .CP0_LLAddr_shift = 4,
207 .SYNCI_Step = 32,
208 .CCRes = 2,
209 .CP0_Status_rw_bitmask = 0x1278FF17,
210 .SEGBITS = 32,
211 .PABITS = 32,
212 .insn_flags = CPU_MIPS32R2,
213 .mmu_type = MMU_TYPE_R4000,
214 },
215 {
216 .name = "4KEm",
217 .CP0_PRid = 0x00019100,
218 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
219 (MMU_TYPE_FMT << CP0C0_MT),
220 .CP0_Config1 = MIPS_CONFIG1 |
221 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
222 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
223 (1 << CP0C1_CA),
224 .CP0_Config2 = MIPS_CONFIG2,
225 .CP0_Config3 = MIPS_CONFIG3,
226 .CP0_LLAddr_rw_bitmask = 0,
227 .CP0_LLAddr_shift = 4,
228 .SYNCI_Step = 32,
229 .CCRes = 2,
230 .CP0_Status_rw_bitmask = 0x1258FF17,
231 .SEGBITS = 32,
232 .PABITS = 32,
233 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
234 .mmu_type = MMU_TYPE_FMT,
235 },
236 {
237 .name = "24Kc",
238 .CP0_PRid = 0x00019300,
239 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
240 (MMU_TYPE_R4000 << CP0C0_MT),
241 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
242 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
243 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
244 (1 << CP0C1_CA),
245 .CP0_Config2 = MIPS_CONFIG2,
246 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
247 .CP0_LLAddr_rw_bitmask = 0,
248 .CP0_LLAddr_shift = 4,
249 .SYNCI_Step = 32,
250 .CCRes = 2,
251 /* No DSP implemented. */
252 .CP0_Status_rw_bitmask = 0x1278FF1F,
253 .SEGBITS = 32,
254 .PABITS = 32,
255 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
256 .mmu_type = MMU_TYPE_R4000,
257 },
258 {
259 .name = "24Kf",
260 .CP0_PRid = 0x00019300,
261 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
262 (MMU_TYPE_R4000 << CP0C0_MT),
263 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
264 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
265 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
266 (1 << CP0C1_CA),
267 .CP0_Config2 = MIPS_CONFIG2,
268 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
269 .CP0_LLAddr_rw_bitmask = 0,
270 .CP0_LLAddr_shift = 4,
271 .SYNCI_Step = 32,
272 .CCRes = 2,
273 /* No DSP implemented. */
274 .CP0_Status_rw_bitmask = 0x3678FF1F,
275 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
277 .CP1_fcr31 = 0,
278 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
279 .SEGBITS = 32,
280 .PABITS = 32,
281 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
282 .mmu_type = MMU_TYPE_R4000,
283 },
284 {
285 .name = "34Kf",
286 .CP0_PRid = 0x00019500,
287 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
288 (MMU_TYPE_R4000 << CP0C0_MT),
289 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
290 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
291 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
292 (1 << CP0C1_CA),
293 .CP0_Config2 = MIPS_CONFIG2,
294 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
295 (1 << CP0C3_DSPP),
296 .CP0_LLAddr_rw_bitmask = 0,
297 .CP0_LLAddr_shift = 0,
298 .SYNCI_Step = 32,
299 .CCRes = 2,
300 .CP0_Status_rw_bitmask = 0x3778FF1F,
301 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
302 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
303 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
304 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
305 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
306 (0xff << CP0TCSt_TASID),
307 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
308 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
309 .CP1_fcr31 = 0,
310 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
311 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
312 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
313 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
314 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
315 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
316 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
317 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
318 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
319 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
320 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
321 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
322 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
323 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
324 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
325 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
326 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
327 .SEGBITS = 32,
328 .PABITS = 32,
329 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
330 .mmu_type = MMU_TYPE_R4000,
331 },
332 {
333 .name = "74Kf",
334 .CP0_PRid = 0x00019700,
335 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
336 (MMU_TYPE_R4000 << CP0C0_MT),
337 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
338 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
339 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
340 (1 << CP0C1_CA),
341 .CP0_Config2 = MIPS_CONFIG2,
342 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
343 (1 << CP0C3_VInt),
344 .CP0_LLAddr_rw_bitmask = 0,
345 .CP0_LLAddr_shift = 4,
346 .SYNCI_Step = 32,
347 .CCRes = 2,
348 .CP0_Status_rw_bitmask = 0x3778FF1F,
349 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
350 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
351 .CP1_fcr31 = 0,
352 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
353 .SEGBITS = 32,
354 .PABITS = 32,
355 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
356 .mmu_type = MMU_TYPE_R4000,
357 },
358 {
359 .name = "M14K",
360 .CP0_PRid = 0x00019b00,
361 /* Config1 implemented, fixed mapping MMU,
362 no virtual icache, uncached coherency. */
363 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
364 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
365 .CP0_Config1 = MIPS_CONFIG1,
366 .CP0_Config2 = MIPS_CONFIG2,
367 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
368 .CP0_LLAddr_rw_bitmask = 0,
369 .CP0_LLAddr_shift = 4,
370 .SYNCI_Step = 32,
371 .CCRes = 2,
372 .CP0_Status_rw_bitmask = 0x1258FF17,
373 .SEGBITS = 32,
374 .PABITS = 32,
375 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
376 .mmu_type = MMU_TYPE_FMT,
377 },
378 {
379 .name = "M14Kc",
380 /* This is the TLB-based MMU core. */
381 .CP0_PRid = 0x00019c00,
382 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
383 (MMU_TYPE_R4000 << CP0C0_MT),
384 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
385 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
386 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
387 .CP0_Config2 = MIPS_CONFIG2,
388 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
389 .CP0_LLAddr_rw_bitmask = 0,
390 .CP0_LLAddr_shift = 4,
391 .SYNCI_Step = 32,
392 .CCRes = 2,
393 .CP0_Status_rw_bitmask = 0x1278FF17,
394 .SEGBITS = 32,
395 .PABITS = 32,
396 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
397 .mmu_type = MMU_TYPE_R4000,
398 },
399 {
400 /* FIXME:
401 * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
402 * Config4: MMUExtDef
403 * Config5: EVA, MRP
404 * FIR(FCR0): Has2008
405 * */
406 .name = "P5600",
407 .CP0_PRid = 0x0001A800,
408 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
409 (MMU_TYPE_R4000 << CP0C0_MT),
410 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
411 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
412 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
413 (1 << CP0C1_PC) | (1 << CP0C1_FP),
414 .CP0_Config2 = MIPS_CONFIG2,
415 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
416 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
417 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
418 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
419 (0x1c << CP0C4_KScrExist),
420 .CP0_Config4_rw_bitmask = 0,
421 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) |
422 (1 << CP0C5_MRP),
423 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
424 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
425 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
426 .CP0_LLAddr_rw_bitmask = 0,
427 .CP0_LLAddr_shift = 0,
428 .SYNCI_Step = 32,
429 .CCRes = 2,
430 .CP0_Status_rw_bitmask = 0x3C68FF1F,
431 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
432 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
433 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
434 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
435 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
436 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
437 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
438 .SEGBITS = 32,
439 .PABITS = 40,
440 .insn_flags = CPU_MIPS32R5 | ASE_MSA,
441 .mmu_type = MMU_TYPE_R4000,
442 },
443 {
444 /* A generic CPU supporting MIPS32 Release 6 ISA.
445 FIXME: Support IEEE 754-2008 FP.
446 Eventually this should be replaced by a real CPU model. */
447 .name = "mips32r6-generic",
448 .CP0_PRid = 0x00010000,
449 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
450 (MMU_TYPE_R4000 << CP0C0_MT),
451 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
452 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
453 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
454 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
455 .CP0_Config2 = MIPS_CONFIG2,
456 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
457 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
458 (1 << CP0C3_RXI) | (1U << CP0C3_M),
459 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
460 (3 << CP0C4_IE) | (1U << CP0C4_M),
461 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
462 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
463 (1 << CP0C5_UFE),
464 .CP0_LLAddr_rw_bitmask = 0,
465 .CP0_LLAddr_shift = 0,
466 .SYNCI_Step = 32,
467 .CCRes = 2,
468 .CP0_Status_rw_bitmask = 0x3058FF1F,
469 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
470 (1U << CP0PG_RIE),
471 .CP0_PageGrain_rw_bitmask = 0,
472 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
473 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
474 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
475 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
476 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
477 .SEGBITS = 32,
478 .PABITS = 32,
479 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
480 .mmu_type = MMU_TYPE_R4000,
481 },
482 #if defined(TARGET_MIPS64)
483 {
484 .name = "R4000",
485 .CP0_PRid = 0x00000400,
486 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
487 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
488 /* Note: Config1 is only used internally, the R4000 has only Config0. */
489 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
490 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
491 .CP0_LLAddr_shift = 4,
492 .SYNCI_Step = 16,
493 .CCRes = 2,
494 .CP0_Status_rw_bitmask = 0x3678FFFF,
495 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
496 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
497 .CP1_fcr31 = 0,
498 .CP1_fcr31_rw_bitmask = 0x0183FFFF,
499 .SEGBITS = 40,
500 .PABITS = 36,
501 .insn_flags = CPU_MIPS3,
502 .mmu_type = MMU_TYPE_R4000,
503 },
504 {
505 .name = "VR5432",
506 .CP0_PRid = 0x00005400,
507 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
508 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
509 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
510 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
511 .CP0_LLAddr_shift = 4,
512 .SYNCI_Step = 16,
513 .CCRes = 2,
514 .CP0_Status_rw_bitmask = 0x3678FFFF,
515 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
516 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
517 .CP1_fcr31 = 0,
518 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
519 .SEGBITS = 40,
520 .PABITS = 32,
521 .insn_flags = CPU_VR54XX,
522 .mmu_type = MMU_TYPE_R4000,
523 },
524 {
525 .name = "5Kc",
526 .CP0_PRid = 0x00018100,
527 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
528 (MMU_TYPE_R4000 << CP0C0_MT),
529 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
530 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
531 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
532 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
533 .CP0_Config2 = MIPS_CONFIG2,
534 .CP0_Config3 = MIPS_CONFIG3,
535 .CP0_LLAddr_rw_bitmask = 0,
536 .CP0_LLAddr_shift = 4,
537 .SYNCI_Step = 32,
538 .CCRes = 2,
539 .CP0_Status_rw_bitmask = 0x12F8FFFF,
540 .SEGBITS = 42,
541 .PABITS = 36,
542 .insn_flags = CPU_MIPS64,
543 .mmu_type = MMU_TYPE_R4000,
544 },
545 {
546 .name = "5Kf",
547 .CP0_PRid = 0x00018100,
548 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
549 (MMU_TYPE_R4000 << CP0C0_MT),
550 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
551 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
552 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
553 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
554 .CP0_Config2 = MIPS_CONFIG2,
555 .CP0_Config3 = MIPS_CONFIG3,
556 .CP0_LLAddr_rw_bitmask = 0,
557 .CP0_LLAddr_shift = 4,
558 .SYNCI_Step = 32,
559 .CCRes = 2,
560 .CP0_Status_rw_bitmask = 0x36F8FFFF,
561 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
562 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
563 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
564 .CP1_fcr31 = 0,
565 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
566 .SEGBITS = 42,
567 .PABITS = 36,
568 .insn_flags = CPU_MIPS64,
569 .mmu_type = MMU_TYPE_R4000,
570 },
571 {
572 .name = "20Kc",
573 /* We emulate a later version of the 20Kc, earlier ones had a broken
574 WAIT instruction. */
575 .CP0_PRid = 0x000182a0,
576 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
577 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
578 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
579 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
580 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
581 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
582 .CP0_Config2 = MIPS_CONFIG2,
583 .CP0_Config3 = MIPS_CONFIG3,
584 .CP0_LLAddr_rw_bitmask = 0,
585 .CP0_LLAddr_shift = 0,
586 .SYNCI_Step = 32,
587 .CCRes = 1,
588 .CP0_Status_rw_bitmask = 0x36FBFFFF,
589 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
590 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
591 (1 << FCR0_D) | (1 << FCR0_S) |
592 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
593 .CP1_fcr31 = 0,
594 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
595 .SEGBITS = 40,
596 .PABITS = 36,
597 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
598 .mmu_type = MMU_TYPE_R4000,
599 },
600 {
601 /* A generic CPU providing MIPS64 Release 2 features.
602 FIXME: Eventually this should be replaced by a real CPU model. */
603 .name = "MIPS64R2-generic",
604 .CP0_PRid = 0x00010000,
605 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
606 (MMU_TYPE_R4000 << CP0C0_MT),
607 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
608 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
609 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
610 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
611 .CP0_Config2 = MIPS_CONFIG2,
612 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
613 .CP0_LLAddr_rw_bitmask = 0,
614 .CP0_LLAddr_shift = 0,
615 .SYNCI_Step = 32,
616 .CCRes = 2,
617 .CP0_Status_rw_bitmask = 0x36FBFFFF,
618 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
619 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
620 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
621 .CP1_fcr31 = 0,
622 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
623 .SEGBITS = 42,
624 .PABITS = 36,
625 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
626 .mmu_type = MMU_TYPE_R4000,
627 },
628 {
629 .name = "5KEc",
630 .CP0_PRid = 0x00018900,
631 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
632 (MMU_TYPE_R4000 << CP0C0_MT),
633 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
634 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
635 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
636 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
637 .CP0_Config2 = MIPS_CONFIG2,
638 .CP0_Config3 = MIPS_CONFIG3,
639 .CP0_LLAddr_rw_bitmask = 0,
640 .CP0_LLAddr_shift = 4,
641 .SYNCI_Step = 32,
642 .CCRes = 2,
643 .CP0_Status_rw_bitmask = 0x12F8FFFF,
644 .SEGBITS = 42,
645 .PABITS = 36,
646 .insn_flags = CPU_MIPS64R2,
647 .mmu_type = MMU_TYPE_R4000,
648 },
649 {
650 .name = "5KEf",
651 .CP0_PRid = 0x00018900,
652 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
653 (MMU_TYPE_R4000 << CP0C0_MT),
654 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
655 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
656 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
657 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
658 .CP0_Config2 = MIPS_CONFIG2,
659 .CP0_Config3 = MIPS_CONFIG3,
660 .CP0_LLAddr_rw_bitmask = 0,
661 .CP0_LLAddr_shift = 4,
662 .SYNCI_Step = 32,
663 .CCRes = 2,
664 .CP0_Status_rw_bitmask = 0x36F8FFFF,
665 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
666 (1 << FCR0_D) | (1 << FCR0_S) |
667 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
668 .SEGBITS = 42,
669 .PABITS = 36,
670 .insn_flags = CPU_MIPS64R2,
671 .mmu_type = MMU_TYPE_R4000,
672 },
673 {
674 .name = "I6400",
675 .CP0_PRid = 0x1A900,
676 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
677 (MMU_TYPE_R4000 << CP0C0_MT),
678 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
679 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
680 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
681 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
682 .CP0_Config2 = MIPS_CONFIG2,
683 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
684 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
685 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
686 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
687 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
688 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
689 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
690 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
691 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
692 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
693 .CP0_LLAddr_rw_bitmask = 0,
694 .CP0_LLAddr_shift = 0,
695 .SYNCI_Step = 32,
696 .CCRes = 2,
697 .CP0_Status_rw_bitmask = 0x30D8FFFF,
698 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
699 (1U << CP0PG_RIE),
700 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
701 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
702 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
703 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
704 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
705 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
706 .MSAIR = 0x03 << MSAIR_ProcID,
707 .SEGBITS = 48,
708 .PABITS = 48,
709 .insn_flags = CPU_MIPS64R6 | ASE_MSA,
710 .mmu_type = MMU_TYPE_R4000,
711 },
712 {
713 .name = "Loongson-2E",
714 .CP0_PRid = 0x6302,
715 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
716 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
717 (0x1<<5) | (0x1<<4) | (0x1<<1),
718 /* Note: Config1 is only used internally,
719 Loongson-2E has only Config0. */
720 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
721 .SYNCI_Step = 16,
722 .CCRes = 2,
723 .CP0_Status_rw_bitmask = 0x35D0FFFF,
724 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
725 .CP1_fcr31 = 0,
726 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
727 .SEGBITS = 40,
728 .PABITS = 40,
729 .insn_flags = CPU_LOONGSON2E,
730 .mmu_type = MMU_TYPE_R4000,
731 },
732 {
733 .name = "Loongson-2F",
734 .CP0_PRid = 0x6303,
735 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
736 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
737 (0x1<<5) | (0x1<<4) | (0x1<<1),
738 /* Note: Config1 is only used internally,
739 Loongson-2F has only Config0. */
740 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
741 .SYNCI_Step = 16,
742 .CCRes = 2,
743 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
744 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
745 .CP1_fcr31 = 0,
746 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
747 .SEGBITS = 40,
748 .PABITS = 40,
749 .insn_flags = CPU_LOONGSON2F,
750 .mmu_type = MMU_TYPE_R4000,
751 },
752 {
753 /* A generic CPU providing MIPS64 ASE DSP 2 features.
754 FIXME: Eventually this should be replaced by a real CPU model. */
755 .name = "mips64dspr2",
756 .CP0_PRid = 0x00010000,
757 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
758 (MMU_TYPE_R4000 << CP0C0_MT),
759 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
760 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
761 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
762 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
763 .CP0_Config2 = MIPS_CONFIG2,
764 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
765 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
766 .CP0_LLAddr_rw_bitmask = 0,
767 .CP0_LLAddr_shift = 0,
768 .SYNCI_Step = 32,
769 .CCRes = 2,
770 .CP0_Status_rw_bitmask = 0x37FBFFFF,
771 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
772 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
773 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
774 .CP1_fcr31 = 0,
775 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
776 .SEGBITS = 42,
777 .PABITS = 36,
778 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
779 .mmu_type = MMU_TYPE_R4000,
780 },
781
782 #endif
783 };
784
785 static const mips_def_t *cpu_mips_find_by_name (const char *name)
786 {
787 int i;
788
789 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
790 if (strcasecmp(name, mips_defs[i].name) == 0) {
791 return &mips_defs[i];
792 }
793 }
794 return NULL;
795 }
796
797 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
798 {
799 int i;
800
801 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
802 (*cpu_fprintf)(f, "MIPS '%s'\n",
803 mips_defs[i].name);
804 }
805 }
806
807 #ifndef CONFIG_USER_ONLY
808 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
809 {
810 env->tlb->nb_tlb = 1;
811 env->tlb->map_address = &no_mmu_map_address;
812 }
813
814 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
815 {
816 env->tlb->nb_tlb = 1;
817 env->tlb->map_address = &fixed_mmu_map_address;
818 }
819
820 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
821 {
822 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
823 env->tlb->map_address = &r4k_map_address;
824 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
825 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
826 env->tlb->helper_tlbp = r4k_helper_tlbp;
827 env->tlb->helper_tlbr = r4k_helper_tlbr;
828 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
829 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
830 }
831
832 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
833 {
834 MIPSCPU *cpu = mips_env_get_cpu(env);
835
836 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
837
838 switch (def->mmu_type) {
839 case MMU_TYPE_NONE:
840 no_mmu_init(env, def);
841 break;
842 case MMU_TYPE_R4000:
843 r4k_mmu_init(env, def);
844 break;
845 case MMU_TYPE_FMT:
846 fixed_mmu_init(env, def);
847 break;
848 case MMU_TYPE_R3000:
849 case MMU_TYPE_R6000:
850 case MMU_TYPE_R8000:
851 default:
852 cpu_abort(CPU(cpu), "MMU type not supported\n");
853 }
854 }
855 #endif /* CONFIG_USER_ONLY */
856
857 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
858 {
859 int i;
860
861 for (i = 0; i < MIPS_FPU_MAX; i++)
862 env->fpus[i].fcr0 = def->CP1_fcr0;
863
864 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
865 }
866
867 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
868 {
869 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
870
871 /* MVPConf1 implemented, TLB sharable, no gating storage support,
872 programmable cache partitioning implemented, number of allocatable
873 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
874 implemented, 5 TCs implemented. */
875 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
876 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
877 // TODO: actually do 2 VPEs.
878 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
879 // (0x04 << CP0MVPC0_PTC);
880 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
881 (0x00 << CP0MVPC0_PTC);
882 #if !defined(CONFIG_USER_ONLY)
883 /* Usermode has no TLB support */
884 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
885 #endif
886
887 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
888 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
889 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
890 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
891 (0x1 << CP0MVPC1_PCP1);
892 }
893
894 static void msa_reset(CPUMIPSState *env)
895 {
896 #ifdef CONFIG_USER_ONLY
897 /* MSA access enabled */
898 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
899 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
900 #endif
901
902 /* MSA CSR:
903 - non-signaling floating point exception mode off (NX bit is 0)
904 - Cause, Enables, and Flags are all 0
905 - round to nearest / ties to even (RM bits are 0) */
906 env->active_tc.msacsr = 0;
907
908 restore_msa_fp_status(env);
909
910 /* tininess detected after rounding.*/
911 set_float_detect_tininess(float_tininess_after_rounding,
912 &env->active_tc.msa_fp_status);
913
914 /* clear float_status exception flags */
915 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
916
917 /* clear float_status nan mode */
918 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
919
920 /* set proper signanling bit meaning ("1" means "quiet") */
921 set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
922 }
AR7 emulation for QEMU