hw/dma/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Modifications:
   7  *  2010-Feb-14 Artyom Tarasenko : reworked irq generation
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/hw.h"
  30 #include "hw/sparc/sparc32_dma.h"
  31 #include "hw/sparc/sun4m.h"
  32 #include "hw/sysbus.h"
  33 #include "trace.h"
  34
  35 /*
  36  * This is the DMA controller part of chip STP2000 (Master I/O), also
  37  * produced as NCR89C100. See
  38  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  39  * and
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  41  */
  42
  43 #define DMA_SIZE (4 * sizeof(uint32_t))
  44 /* We need the mask, because one instance of the device is not page
  45    aligned (ledma, start address 0x0010) */
  46 #define DMA_MASK (DMA_SIZE - 1)
  47 /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
  48 #define DMA_ETH_SIZE (8 * sizeof(uint32_t))
  49 #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
  50
  51 #define DMA_VER 0xa0000000
  52 #define DMA_INTR 1
  53 #define DMA_INTREN 0x10
  54 #define DMA_WRITE_MEM 0x100
  55 #define DMA_EN 0x200
  56 #define DMA_LOADED 0x04000000
  57 #define DMA_DRAIN_FIFO 0x40
  58 #define DMA_RESET 0x80
  59
  60 /* XXX SCSI and ethernet should have different read-only bit masks */
  61 #define DMA_CSR_RO_MASK 0xfe000007
  62
  63 enum {
  64     GPIO_RESET = 0,
  65     GPIO_DMA,
  66 };
  67
  68 /* Note: on sparc, the lance 16 bit bus is swapped */
  69 void ledma_memory_read(void *opaque, hwaddr addr,
  70                        uint8_t *buf, int len, int do_bswap)
  71 {
  72     DMADeviceState *s = opaque;
  73     int i;
  74
  75     addr |= s->dmaregs[3];
  76     trace_ledma_memory_read(addr);
  77     if (do_bswap) {
  78         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  79     } else {
  80         addr &= ~1;
  81         len &= ~1;
  82         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  83         for(i = 0; i < len; i += 2) {
  84             bswap16s((uint16_t *)(buf + i));
  85         }
  86     }
  87 }
  88
  89 void ledma_memory_write(void *opaque, hwaddr addr,
  90                         uint8_t *buf, int len, int do_bswap)
  91 {
  92     DMADeviceState *s = opaque;
  93     int l, i;
  94     uint16_t tmp_buf[32];
  95
  96     addr |= s->dmaregs[3];
  97     trace_ledma_memory_write(addr);
  98     if (do_bswap) {
  99         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 100     } else {
 101         addr &= ~1;
 102         len &= ~1;
 103         while (len > 0) {
 104             l = len;
 105             if (l > sizeof(tmp_buf))
 106                 l = sizeof(tmp_buf);
 107             for(i = 0; i < l; i += 2) {
 108                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 109             }
 110             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 111             len -= l;
 112             buf += l;
 113             addr += l;
 114         }
 115     }
 116 }
 117
 118 static void dma_set_irq(void *opaque, int irq, int level)
 119 {
 120     DMADeviceState *s = opaque;
 121     if (level) {
 122         s->dmaregs[0] |= DMA_INTR;
 123         if (s->dmaregs[0] & DMA_INTREN) {
 124             trace_sparc32_dma_set_irq_raise();
 125             qemu_irq_raise(s->irq);
 126         }
 127     } else {
 128         if (s->dmaregs[0] & DMA_INTR) {
 129             s->dmaregs[0] &= ~DMA_INTR;
 130             if (s->dmaregs[0] & DMA_INTREN) {
 131                 trace_sparc32_dma_set_irq_lower();
 132                 qemu_irq_lower(s->irq);
 133             }
 134         }
 135     }
 136 }
 137
 138 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 139 {
 140     DMADeviceState *s = opaque;
 141
 142     trace_espdma_memory_read(s->dmaregs[1]);
 143     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 144     s->dmaregs[1] += len;
 145 }
 146
 147 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 148 {
 149     DMADeviceState *s = opaque;
 150
 151     trace_espdma_memory_write(s->dmaregs[1]);
 152     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 153     s->dmaregs[1] += len;
 154 }
 155
 156 static uint64_t dma_mem_read(void *opaque, hwaddr addr,
 157                              unsigned size)
 158 {
 159     DMADeviceState *s = opaque;
 160     uint32_t saddr;
 161
 162     if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
 163         /* aliased to espdma, but we can't get there from here */
 164         /* buggy driver if using undocumented behavior, just return 0 */
 165         trace_sparc32_dma_mem_readl(addr, 0);
 166         return 0;
 167     }
 168     saddr = (addr & DMA_MASK) >> 2;
 169     trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
 170     return s->dmaregs[saddr];
 171 }
 172
 173 static void dma_mem_write(void *opaque, hwaddr addr,
 174                           uint64_t val, unsigned size)
 175 {
 176     DMADeviceState *s = opaque;
 177     uint32_t saddr;
 178
 179     if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
 180         /* aliased to espdma, but we can't get there from here */
 181         trace_sparc32_dma_mem_writel(addr, 0, val);
 182         return;
 183     }
 184     saddr = (addr & DMA_MASK) >> 2;
 185     trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
 186     switch (saddr) {
 187     case 0:
 188         if (val & DMA_INTREN) {
 189             if (s->dmaregs[0] & DMA_INTR) {
 190                 trace_sparc32_dma_set_irq_raise();
 191                 qemu_irq_raise(s->irq);
 192             }
 193         } else {
 194             if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
 195                 trace_sparc32_dma_set_irq_lower();
 196                 qemu_irq_lower(s->irq);
 197             }
 198         }
 199         if (val & DMA_RESET) {
 200             qemu_irq_raise(s->gpio[GPIO_RESET]);
 201             qemu_irq_lower(s->gpio[GPIO_RESET]);
 202         } else if (val & DMA_DRAIN_FIFO) {
 203             val &= ~DMA_DRAIN_FIFO;
 204         } else if (val == 0)
 205             val = DMA_DRAIN_FIFO;
 206
 207         if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
 208             trace_sparc32_dma_enable_raise();
 209             qemu_irq_raise(s->gpio[GPIO_DMA]);
 210         } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
 211             trace_sparc32_dma_enable_lower();
 212             qemu_irq_lower(s->gpio[GPIO_DMA]);
 213         }
 214
 215         val &= ~DMA_CSR_RO_MASK;
 216         val |= DMA_VER;
 217         s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
 218         break;
 219     case 1:
 220         s->dmaregs[0] |= DMA_LOADED;
 221         /* fall through */
 222     default:
 223         s->dmaregs[saddr] = val;
 224         break;
 225     }
 226 }
 227
 228 static const MemoryRegionOps dma_mem_ops = {
 229     .read = dma_mem_read,
 230     .write = dma_mem_write,
 231     .endianness = DEVICE_NATIVE_ENDIAN,
 232     .valid = {
 233         .min_access_size = 4,
 234         .max_access_size = 4,
 235     },
 236 };
 237
 238 static void sparc32_dma_device_reset(DeviceState *d)
 239 {
 240     DMADeviceState *s = SPARC32_DMA_DEVICE(d);
 241
 242     memset(s->dmaregs, 0, DMA_SIZE);
 243     s->dmaregs[0] = DMA_VER;
 244 }
 245
 246 static const VMStateDescription vmstate_sparc32_dma_device = {
 247     .name ="sparc32_dma",
 248     .version_id = 2,
 249     .minimum_version_id = 2,
 250     .fields = (VMStateField[]) {
 251         VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
 252         VMSTATE_END_OF_LIST()
 253     }
 254 };
 255
 256 static void sparc32_dma_device_init(Object *obj)
 257 {
 258     DeviceState *dev = DEVICE(obj);
 259     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 260     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 261
 262     sysbus_init_irq(sbd, &s->irq);
 263
 264     sysbus_init_mmio(sbd, &s->iomem);
 265
 266     object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
 267                              (Object **) &s->iommu,
 268                              qdev_prop_allow_set_link_before_realize,
 269                              0, NULL);
 270
 271     qdev_init_gpio_in(dev, dma_set_irq, 1);
 272     qdev_init_gpio_out(dev, s->gpio, 2);
 273 }
 274
 275 static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
 276 {
 277     DeviceClass *dc = DEVICE_CLASS(klass);
 278
 279     dc->reset = sparc32_dma_device_reset;
 280     dc->vmsd = &vmstate_sparc32_dma_device;
 281 }
 282
 283 static const TypeInfo sparc32_dma_device_info = {
 284     .name          = TYPE_SPARC32_DMA_DEVICE,
 285     .parent        = TYPE_SYS_BUS_DEVICE,
 286     .abstract      = true,
 287     .instance_size = sizeof(DMADeviceState),
 288     .instance_init = sparc32_dma_device_init,
 289     .class_init    = sparc32_dma_device_class_init,
 290 };
 291
 292 static void sparc32_espdma_device_init(Object *obj)
 293 {
 294     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 295
 296     memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
 297                           "espdma-mmio", DMA_SIZE);
 298     s->is_ledma = 0;
 299 }
 300
 301 static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
 302 {
 303     DeviceState *d;
 304     SysBusESPState *sysbus;
 305     ESPState *esp;
 306
 307     d = qdev_create(NULL, TYPE_ESP);
 308     object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp);
 309     sysbus = ESP_STATE(d);
 310     esp = &sysbus->esp;
 311     esp->dma_memory_read = espdma_memory_read;
 312     esp->dma_memory_write = espdma_memory_write;
 313     esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
 314     sysbus->it_shift = 2;
 315     esp->dma_enabled = 1;
 316     qdev_init_nofail(d);
 317 }
 318
 319 static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
 320 {
 321     DeviceClass *dc = DEVICE_CLASS(klass);
 322
 323     dc->realize = sparc32_espdma_device_realize;
 324 }
 325
 326 static const TypeInfo sparc32_espdma_device_info = {
 327     .name          = TYPE_SPARC32_ESPDMA_DEVICE,
 328     .parent        = TYPE_SPARC32_DMA_DEVICE,
 329     .instance_size = sizeof(ESPDMADeviceState),
 330     .instance_init = sparc32_espdma_device_init,
 331     .class_init    = sparc32_espdma_device_class_init,
 332 };
 333
 334 static void sparc32_ledma_device_init(Object *obj)
 335 {
 336     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 337
 338     memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
 339                           "ledma-mmio", DMA_ETH_SIZE);
 340     s->is_ledma = 1;
 341 }
 342
 343 static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
 344 {
 345     DeviceState *d;
 346     NICInfo *nd = &nd_table[0];
 347
 348     qemu_check_nic_model(nd, TYPE_LANCE);
 349
 350     d = qdev_create(NULL, TYPE_LANCE);
 351     object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);
 352     qdev_set_nic_properties(d, nd);
 353     qdev_prop_set_ptr(d, "dma", dev);
 354     qdev_init_nofail(d);
 355 }
 356
 357 static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
 358 {
 359     DeviceClass *dc = DEVICE_CLASS(klass);
 360
 361     dc->realize = sparc32_ledma_device_realize;
 362 }
 363
 364 static const TypeInfo sparc32_ledma_device_info = {
 365     .name          = TYPE_SPARC32_LEDMA_DEVICE,
 366     .parent        = TYPE_SPARC32_DMA_DEVICE,
 367     .instance_size = sizeof(LEDMADeviceState),
 368     .instance_init = sparc32_ledma_device_init,
 369     .class_init    = sparc32_ledma_device_class_init,
 370 };
 371
 372 static void sparc32_dma_register_types(void)
 373 {
 374     type_register_static(&sparc32_dma_device_info);
 375     type_register_static(&sparc32_espdma_device_info);
 376     type_register_static(&sparc32_ledma_device_info);
 377 }
 378
 379 type_init(sparc32_dma_register_types)