2 * QEMU IDE Emulation: PCI PIIX3/4 support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/pci/pci.h"
28 #include "migration/vmstate.h"
29 #include "qemu/module.h"
30 #include "sysemu/block-backend.h"
31 #include "sysemu/blockdev.h"
32 #include "sysemu/dma.h"
34 #include "hw/ide/pci.h"
37 static uint64_t bmdma_read(void *opaque
, hwaddr addr
, unsigned size
)
39 BMDMAState
*bm
= opaque
;
43 return ((uint64_t)1 << (size
* 8)) - 1;
58 trace_bmdma_read(addr
, val
);
62 static void bmdma_write(void *opaque
, hwaddr addr
,
63 uint64_t val
, unsigned size
)
65 BMDMAState
*bm
= opaque
;
71 trace_bmdma_write(addr
, val
);
75 bmdma_cmd_writeb(bm
, val
);
78 bm
->status
= (val
& 0x60) | (bm
->status
& 1) | (bm
->status
& ~val
& 0x06);
83 static const MemoryRegionOps piix_bmdma_ops
= {
88 static void bmdma_setup_bar(PCIIDEState
*d
)
92 memory_region_init(&d
->bmdma_bar
, OBJECT(d
), "piix-bmdma-container", 16);
93 for(i
= 0;i
< 2; i
++) {
94 BMDMAState
*bm
= &d
->bmdma
[i
];
96 memory_region_init_io(&bm
->extra_io
, OBJECT(d
), &piix_bmdma_ops
, bm
,
98 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8, &bm
->extra_io
);
99 memory_region_init_io(&bm
->addr_ioport
, OBJECT(d
),
100 &bmdma_addr_ioport_ops
, bm
, "bmdma", 4);
101 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8 + 4, &bm
->addr_ioport
);
105 static void piix_ide_reset(DeviceState
*dev
)
107 PCIIDEState
*d
= PCI_IDE(dev
);
108 PCIDevice
*pd
= PCI_DEVICE(d
);
109 uint8_t *pci_conf
= pd
->config
;
112 for (i
= 0; i
< 2; i
++) {
113 ide_bus_reset(&d
->bus
[i
]);
116 /* TODO: this is the default. do not override. */
117 pci_conf
[PCI_COMMAND
] = 0x00;
118 /* TODO: this is the default. do not override. */
119 pci_conf
[PCI_COMMAND
+ 1] = 0x00;
120 /* TODO: use pci_set_word */
121 pci_conf
[PCI_STATUS
] = PCI_STATUS_FAST_BACK
;
122 pci_conf
[PCI_STATUS
+ 1] = PCI_STATUS_DEVSEL_MEDIUM
>> 8;
123 pci_conf
[0x20] = 0x01; /* BMIBA: 20-23h */
126 static void pci_piix_init_ports(PCIIDEState
*d
) {
127 static const struct {
137 for (i
= 0; i
< 2; i
++) {
138 ide_bus_new(&d
->bus
[i
], sizeof(d
->bus
[i
]), DEVICE(d
), i
, 2);
139 ide_init_ioport(&d
->bus
[i
], NULL
, port_info
[i
].iobase
,
140 port_info
[i
].iobase2
);
141 ide_init2(&d
->bus
[i
], isa_get_irq(NULL
, port_info
[i
].isairq
));
143 bmdma_init(&d
->bus
[i
], &d
->bmdma
[i
], d
);
144 d
->bmdma
[i
].bus
= &d
->bus
[i
];
145 ide_register_restart_cb(&d
->bus
[i
]);
149 static void pci_piix_ide_realize(PCIDevice
*dev
, Error
**errp
)
151 PCIIDEState
*d
= PCI_IDE(dev
);
152 uint8_t *pci_conf
= dev
->config
;
154 pci_conf
[PCI_CLASS_PROG
] = 0x80; // legacy ATA mode
157 pci_register_bar(dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &d
->bmdma_bar
);
159 vmstate_register(DEVICE(dev
), 0, &vmstate_ide_pci
, d
);
161 pci_piix_init_ports(d
);
164 int pci_piix3_xen_ide_unplug(DeviceState
*dev
, bool aux
)
166 PCIIDEState
*pci_ide
;
171 pci_ide
= PCI_IDE(dev
);
173 for (i
= aux
? 1 : 0; i
< 4; i
++) {
174 di
= drive_get_by_index(IF_IDE
, i
);
175 if (di
!= NULL
&& !di
->media_cd
) {
176 BlockBackend
*blk
= blk_by_legacy_dinfo(di
);
177 DeviceState
*ds
= blk_get_attached_dev(blk
);
183 blk_detach_dev(blk
, ds
);
185 pci_ide
->bus
[di
->bus
].ifs
[di
->unit
].blk
= NULL
;
187 idedev
= pci_ide
->bus
[di
->bus
].master
;
189 idedev
= pci_ide
->bus
[di
->bus
].slave
;
191 idedev
->conf
.blk
= NULL
;
192 monitor_remove_blk(blk
);
196 qdev_reset_all(DEVICE(dev
));
200 PCIDevice
*pci_piix3_xen_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
, int devfn
)
204 dev
= pci_create_simple(bus
, devfn
, "piix3-ide-xen");
205 pci_ide_create_devs(dev
, hd_table
);
209 static void pci_piix_ide_exitfn(PCIDevice
*dev
)
211 PCIIDEState
*d
= PCI_IDE(dev
);
214 for (i
= 0; i
< 2; ++i
) {
215 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].extra_io
);
216 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].addr_ioport
);
220 /* hd_table must contain 4 block drivers */
221 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
222 PCIDevice
*pci_piix3_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
, int devfn
)
226 dev
= pci_create_simple(bus
, devfn
, "piix3-ide");
227 pci_ide_create_devs(dev
, hd_table
);
231 /* hd_table must contain 4 block drivers */
232 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
233 PCIDevice
*pci_piix4_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
, int devfn
)
237 dev
= pci_create_simple(bus
, devfn
, "piix4-ide");
238 pci_ide_create_devs(dev
, hd_table
);
242 static void piix3_ide_class_init(ObjectClass
*klass
, void *data
)
244 DeviceClass
*dc
= DEVICE_CLASS(klass
);
245 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
247 dc
->reset
= piix_ide_reset
;
248 k
->realize
= pci_piix_ide_realize
;
249 k
->exit
= pci_piix_ide_exitfn
;
250 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
251 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_1
;
252 k
->class_id
= PCI_CLASS_STORAGE_IDE
;
253 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
254 dc
->hotpluggable
= false;
257 static const TypeInfo piix3_ide_info
= {
259 .parent
= TYPE_PCI_IDE
,
260 .class_init
= piix3_ide_class_init
,
263 static const TypeInfo piix3_ide_xen_info
= {
264 .name
= "piix3-ide-xen",
265 .parent
= TYPE_PCI_IDE
,
266 .class_init
= piix3_ide_class_init
,
269 static void piix4_ide_class_init(ObjectClass
*klass
, void *data
)
271 DeviceClass
*dc
= DEVICE_CLASS(klass
);
272 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
274 dc
->reset
= piix_ide_reset
;
275 k
->realize
= pci_piix_ide_realize
;
276 k
->exit
= pci_piix_ide_exitfn
;
277 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
278 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB
;
279 k
->class_id
= PCI_CLASS_STORAGE_IDE
;
280 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
281 dc
->hotpluggable
= false;
284 static const TypeInfo piix4_ide_info
= {
286 .parent
= TYPE_PCI_IDE
,
287 .class_init
= piix4_ide_class_init
,
290 static void piix_ide_register_types(void)
292 type_register_static(&piix3_ide_info
);
293 type_register_static(&piix3_ide_xen_info
);
294 type_register_static(&piix4_ide_info
);
297 type_init(piix_ide_register_types
)