2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
38 #include "hw/fw-path-provider.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "mmu-hash64.h"
50 #include "mmu-book3s-v3.h"
51 #include "cpu-models.h"
52 #include "hw/core/cpu.h"
54 #include "hw/boards.h"
55 #include "hw/ppc/ppc.h"
56 #include "hw/loader.h"
58 #include "hw/ppc/fdt.h"
59 #include "hw/ppc/spapr.h"
60 #include "hw/ppc/spapr_vio.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/pci-host/spapr.h"
63 #include "hw/pci/msi.h"
65 #include "hw/pci/pci.h"
66 #include "hw/scsi/scsi.h"
67 #include "hw/virtio/virtio-scsi.h"
68 #include "hw/virtio/vhost-scsi-common.h"
70 #include "exec/address-spaces.h"
71 #include "exec/ram_addr.h"
73 #include "qemu/config-file.h"
74 #include "qemu/error-report.h"
77 #include "hw/intc/intc.h"
79 #include "qemu/cutils.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
84 #include "monitor/monitor.h"
88 /* SLOF memory layout:
90 * SLOF raw image loaded at 0, copies its romfs right below the flat
91 * device-tree, then position SLOF itself 31M below that
93 * So we set FW_OVERHEAD to 40MB which should account for all of that
96 * We load our kernel at 4M, leaving space for SLOF initial image
98 #define FDT_MAX_SIZE 0x100000
99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
100 #define FW_MAX_SIZE 0x400000
101 #define FW_FILE_NAME "slof.bin"
102 #define FW_OVERHEAD 0x2800000
103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
105 #define MIN_RMA_SLOF 128UL
107 #define PHANDLE_INTC 0x00001111
109 /* These two functions implement the VCPU id numbering: one to compute them
110 * all and one to identify thread 0 of a VCORE. Any change to the first one
111 * is likely to have an impact on the second one, so let's keep them close.
113 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
115 MachineState
*ms
= MACHINE(spapr
);
116 unsigned int smp_threads
= ms
->smp
.threads
;
120 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
122 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
126 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
131 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
132 * and newer QEMUs don't even have them. In both cases, we don't want
133 * to send anything on the wire.
138 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
139 .name
= "icp/server",
141 .minimum_version_id
= 1,
142 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
143 .fields
= (VMStateField
[]) {
144 VMSTATE_UNUSED(4), /* uint32_t xirr */
145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
146 VMSTATE_UNUSED(1), /* uint8_t mfrr */
147 VMSTATE_END_OF_LIST()
151 static void pre_2_10_vmstate_register_dummy_icp(int i
)
153 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
154 (void *)(uintptr_t) i
);
157 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
159 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
160 (void *)(uintptr_t) i
);
163 int spapr_max_server_number(SpaprMachineState
*spapr
)
165 MachineState
*ms
= MACHINE(spapr
);
168 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
171 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
175 uint32_t servers_prop
[smt_threads
];
176 uint32_t gservers_prop
[smt_threads
* 2];
177 int index
= spapr_get_vcpu_id(cpu
);
179 if (cpu
->compat_pvr
) {
180 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
186 /* Build interrupt servers and gservers properties */
187 for (i
= 0; i
< smt_threads
; i
++) {
188 servers_prop
[i
] = cpu_to_be32(index
+ i
);
189 /* Hack, direct the group queues back to cpu 0 */
190 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
191 gservers_prop
[i
*2 + 1] = 0;
193 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
194 servers_prop
, sizeof(servers_prop
));
198 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
199 gservers_prop
, sizeof(gservers_prop
));
204 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
206 int index
= spapr_get_vcpu_id(cpu
);
207 uint32_t associativity
[] = {cpu_to_be32(0x5),
211 cpu_to_be32(cpu
->node_id
),
214 /* Advertise NUMA via ibm,associativity */
215 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
216 sizeof(associativity
));
219 /* Populate the "ibm,pa-features" property */
220 static void spapr_populate_pa_features(SpaprMachineState
*spapr
,
222 void *fdt
, int offset
)
224 uint8_t pa_features_206
[] = { 6, 0,
225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
226 uint8_t pa_features_207
[] = { 24, 0,
227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
231 uint8_t pa_features_300
[] = { 66, 0,
232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
247 /* 42: PM, 44: PC RA, 46: SC vec'd */
248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
249 /* 48: SIMD, 50: QP BFP, 52: String */
250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
251 /* 54: DecFP, 56: DecI, 58: SHA */
252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
253 /* 60: NM atomic, 62: RNG */
254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
256 uint8_t *pa_features
= NULL
;
259 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
260 pa_features
= pa_features_206
;
261 pa_size
= sizeof(pa_features_206
);
263 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
264 pa_features
= pa_features_207
;
265 pa_size
= sizeof(pa_features_207
);
267 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
268 pa_features
= pa_features_300
;
269 pa_size
= sizeof(pa_features_300
);
275 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
277 * Note: we keep CI large pages off by default because a 64K capable
278 * guest provisioned with large pages might otherwise try to map a qemu
279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
280 * even if that qemu runs on a 4k host.
281 * We dd this bit back here if we are confident this is not an issue
283 pa_features
[3] |= 0x20;
285 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
286 pa_features
[24] |= 0x80; /* Transactional memory support */
288 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
289 /* Workaround for broken kernels that attempt (guest) radix
290 * mode when they can't handle it, if they see the radix bit set
291 * in pa-features. So hide it from them. */
292 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
295 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
298 static hwaddr
spapr_node0_size(MachineState
*machine
)
300 if (machine
->numa_state
->num_nodes
) {
302 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
303 if (machine
->numa_state
->nodes
[i
].node_mem
) {
304 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
309 return machine
->ram_size
;
312 static void add_str(GString
*s
, const gchar
*s1
)
314 g_string_append_len(s
, s1
, strlen(s1
) + 1);
317 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
320 uint32_t associativity
[] = {
321 cpu_to_be32(0x4), /* length */
322 cpu_to_be32(0x0), cpu_to_be32(0x0),
323 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
326 uint64_t mem_reg_property
[2];
329 mem_reg_property
[0] = cpu_to_be64(start
);
330 mem_reg_property
[1] = cpu_to_be64(size
);
332 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
333 off
= fdt_add_subnode(fdt
, 0, mem_name
);
335 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
336 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
337 sizeof(mem_reg_property
))));
338 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
339 sizeof(associativity
))));
343 static int spapr_populate_memory(SpaprMachineState
*spapr
, void *fdt
)
345 MachineState
*machine
= MACHINE(spapr
);
346 hwaddr mem_start
, node_size
;
347 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
348 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
351 /* No NUMA nodes, assume there is just one node with whole RAM */
354 ramnode
.node_mem
= machine
->ram_size
;
358 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
359 if (!nodes
[i
].node_mem
) {
362 if (mem_start
>= machine
->ram_size
) {
365 node_size
= nodes
[i
].node_mem
;
366 if (node_size
> machine
->ram_size
- mem_start
) {
367 node_size
= machine
->ram_size
- mem_start
;
371 /* spapr_machine_init() checks for rma_size <= node0_size
373 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
374 mem_start
+= spapr
->rma_size
;
375 node_size
-= spapr
->rma_size
;
377 for ( ; node_size
; ) {
378 hwaddr sizetmp
= pow2floor(node_size
);
380 /* mem_start != 0 here */
381 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
382 sizetmp
= 1ULL << ctzl(mem_start
);
385 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
386 node_size
-= sizetmp
;
387 mem_start
+= sizetmp
;
394 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
395 SpaprMachineState
*spapr
)
397 MachineState
*ms
= MACHINE(spapr
);
398 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
399 CPUPPCState
*env
= &cpu
->env
;
400 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
401 int index
= spapr_get_vcpu_id(cpu
);
402 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
403 0xffffffff, 0xffffffff};
404 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
405 : SPAPR_TIMEBASE_FREQ
;
406 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
407 uint32_t page_sizes_prop
[64];
408 size_t page_sizes_prop_size
;
409 unsigned int smp_threads
= ms
->smp
.threads
;
410 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
411 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
412 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
415 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
418 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
420 drc_index
= spapr_drc_index(drc
);
421 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
424 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
425 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
427 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
428 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
429 env
->dcache_line_size
)));
430 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
431 env
->dcache_line_size
)));
432 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
433 env
->icache_line_size
)));
434 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
435 env
->icache_line_size
)));
437 if (pcc
->l1_dcache_size
) {
438 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
439 pcc
->l1_dcache_size
)));
441 warn_report("Unknown L1 dcache size for cpu");
443 if (pcc
->l1_icache_size
) {
444 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
445 pcc
->l1_icache_size
)));
447 warn_report("Unknown L1 icache size for cpu");
450 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
451 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
452 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
453 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
454 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
455 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
457 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
458 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
460 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
461 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
464 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
465 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
466 segs
, sizeof(segs
))));
469 /* Advertise VSX (vector extensions) if available
470 * 1 == VMX / Altivec available
473 * Only CPUs for which we create core types in spapr_cpu_core.c
474 * are possible, and all of those have VMX */
475 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
476 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
478 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
481 /* Advertise DFP (Decimal Floating Point) if available
482 * 0 / no property == no DFP
483 * 1 == DFP available */
484 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
485 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
488 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
489 sizeof(page_sizes_prop
));
490 if (page_sizes_prop_size
) {
491 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
492 page_sizes_prop
, page_sizes_prop_size
)));
495 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
);
497 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
498 cs
->cpu_index
/ vcpus_per_socket
)));
500 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
501 pft_size_prop
, sizeof(pft_size_prop
))));
503 if (ms
->numa_state
->num_nodes
> 1) {
504 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
507 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
509 if (pcc
->radix_page_info
) {
510 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
511 radix_AP_encodings
[i
] =
512 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
514 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
516 pcc
->radix_page_info
->count
*
517 sizeof(radix_AP_encodings
[0]))));
521 * We set this property to let the guest know that it can use the large
522 * decrementer and its width in bits.
524 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
525 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
526 pcc
->lrg_decr_bits
)));
529 static void spapr_populate_cpus_dt_node(void *fdt
, SpaprMachineState
*spapr
)
538 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
540 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
541 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
544 * We walk the CPUs in reverse order to ensure that CPU DT nodes
545 * created by fdt_add_subnode() end up in the right order in FDT
546 * for the guest kernel the enumerate the CPUs correctly.
548 * The CPU list cannot be traversed in reverse order, so we need
554 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
558 for (i
= n_cpus
- 1; i
>= 0; i
--) {
559 CPUState
*cs
= rev
[i
];
560 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
561 int index
= spapr_get_vcpu_id(cpu
);
562 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
565 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
569 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
570 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
573 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
579 static int spapr_rng_populate_dt(void *fdt
)
584 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
588 ret
= fdt_setprop_string(fdt
, node
, "device_type",
589 "ibm,platform-facilities");
590 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
591 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
593 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
597 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
602 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
604 MemoryDeviceInfoList
*info
;
606 for (info
= list
; info
; info
= info
->next
) {
607 MemoryDeviceInfo
*value
= info
->value
;
609 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
610 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
612 if (addr
>= pcdimm_info
->addr
&&
613 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
614 return pcdimm_info
->node
;
622 struct sPAPRDrconfCellV2
{
630 typedef struct DrconfCellQueue
{
631 struct sPAPRDrconfCellV2 cell
;
632 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
635 static DrconfCellQueue
*
636 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
637 uint32_t drc_index
, uint32_t aa_index
,
640 DrconfCellQueue
*elem
;
642 elem
= g_malloc0(sizeof(*elem
));
643 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
644 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
645 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
646 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
647 elem
->cell
.flags
= cpu_to_be32(flags
);
652 /* ibm,dynamic-memory-v2 */
653 static int spapr_populate_drmem_v2(SpaprMachineState
*spapr
, void *fdt
,
654 int offset
, MemoryDeviceInfoList
*dimms
)
656 MachineState
*machine
= MACHINE(spapr
);
657 uint8_t *int_buf
, *cur_index
;
659 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
660 uint64_t addr
, cur_addr
, size
;
661 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
662 uint64_t mem_end
= machine
->device_memory
->base
+
663 memory_region_size(&machine
->device_memory
->mr
);
664 uint32_t node
, buf_len
, nr_entries
= 0;
666 DrconfCellQueue
*elem
, *next
;
667 MemoryDeviceInfoList
*info
;
668 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
669 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
671 /* Entry to cover RAM and the gap area */
672 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
673 SPAPR_LMB_FLAGS_RESERVED
|
674 SPAPR_LMB_FLAGS_DRC_INVALID
);
675 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
678 cur_addr
= machine
->device_memory
->base
;
679 for (info
= dimms
; info
; info
= info
->next
) {
680 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
686 /* Entry for hot-pluggable area */
687 if (cur_addr
< addr
) {
688 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
690 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
691 cur_addr
, spapr_drc_index(drc
), -1, 0);
692 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
697 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
699 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
700 spapr_drc_index(drc
), node
,
701 SPAPR_LMB_FLAGS_ASSIGNED
);
702 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
704 cur_addr
= addr
+ size
;
707 /* Entry for remaining hotpluggable area */
708 if (cur_addr
< mem_end
) {
709 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
711 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
712 cur_addr
, spapr_drc_index(drc
), -1, 0);
713 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
717 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
718 int_buf
= cur_index
= g_malloc0(buf_len
);
719 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
720 cur_index
+= sizeof(nr_entries
);
722 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
723 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
724 cur_index
+= sizeof(elem
->cell
);
725 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
729 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
737 /* ibm,dynamic-memory */
738 static int spapr_populate_drmem_v1(SpaprMachineState
*spapr
, void *fdt
,
739 int offset
, MemoryDeviceInfoList
*dimms
)
741 MachineState
*machine
= MACHINE(spapr
);
743 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
744 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
745 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
746 memory_region_size(&machine
->device_memory
->mr
)) /
748 uint32_t *int_buf
, *cur_index
, buf_len
;
751 * Allocate enough buffer size to fit in ibm,dynamic-memory
753 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
754 cur_index
= int_buf
= g_malloc0(buf_len
);
755 int_buf
[0] = cpu_to_be32(nr_lmbs
);
757 for (i
= 0; i
< nr_lmbs
; i
++) {
758 uint64_t addr
= i
* lmb_size
;
759 uint32_t *dynamic_memory
= cur_index
;
761 if (i
>= device_lmb_start
) {
764 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
767 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
768 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
769 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
770 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
771 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
772 if (memory_region_present(get_system_memory(), addr
)) {
773 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
775 dynamic_memory
[5] = cpu_to_be32(0);
779 * LMB information for RMA, boot time RAM and gap b/n RAM and
780 * device memory region -- all these are marked as reserved
781 * and as having no valid DRC.
783 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
784 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
785 dynamic_memory
[2] = cpu_to_be32(0);
786 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
787 dynamic_memory
[4] = cpu_to_be32(-1);
788 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
789 SPAPR_LMB_FLAGS_DRC_INVALID
);
792 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
794 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
803 * Adds ibm,dynamic-reconfiguration-memory node.
804 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
805 * of this device tree node.
807 static int spapr_populate_drconf_memory(SpaprMachineState
*spapr
, void *fdt
)
809 MachineState
*machine
= MACHINE(spapr
);
810 int nb_numa_nodes
= machine
->numa_state
->num_nodes
;
812 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
813 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
814 uint32_t *int_buf
, *cur_index
, buf_len
;
815 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
816 MemoryDeviceInfoList
*dimms
= NULL
;
819 * Don't create the node if there is no device memory
821 if (machine
->ram_size
== machine
->maxram_size
) {
825 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
827 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
828 sizeof(prop_lmb_size
));
833 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
838 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
843 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
844 dimms
= qmp_memory_device_list();
845 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
846 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
848 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
850 qapi_free_MemoryDeviceInfoList(dimms
);
856 /* ibm,associativity-lookup-arrays */
857 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
858 cur_index
= int_buf
= g_malloc0(buf_len
);
859 int_buf
[0] = cpu_to_be32(nr_nodes
);
860 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
862 for (i
= 0; i
< nr_nodes
; i
++) {
863 uint32_t associativity
[] = {
869 memcpy(cur_index
, associativity
, sizeof(associativity
));
872 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
873 (cur_index
- int_buf
) * sizeof(uint32_t));
879 static int spapr_dt_cas_updates(SpaprMachineState
*spapr
, void *fdt
,
880 SpaprOptionVector
*ov5_updates
)
882 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
885 /* Generate ibm,dynamic-reconfiguration-memory node if required */
886 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
887 g_assert(smc
->dr_lmb_enabled
);
888 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
894 offset
= fdt_path_offset(fdt
, "/chosen");
896 offset
= fdt_add_subnode(fdt
, 0, "chosen");
901 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
902 "ibm,architecture-vec-5");
908 static bool spapr_hotplugged_dev_before_cas(void)
910 Object
*drc_container
, *obj
;
911 ObjectProperty
*prop
;
912 ObjectPropertyIterator iter
;
914 drc_container
= container_get(object_get_root(), "/dr-connector");
915 object_property_iter_init(&iter
, drc_container
);
916 while ((prop
= object_property_iter_next(&iter
))) {
917 if (!strstart(prop
->type
, "link<", NULL
)) {
920 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
921 if (spapr_drc_needed(obj
)) {
928 static void *spapr_build_fdt(SpaprMachineState
*spapr
);
930 int spapr_h_cas_compose_response(SpaprMachineState
*spapr
,
931 target_ulong addr
, target_ulong size
,
932 SpaprOptionVector
*ov5_updates
)
935 SpaprDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
937 if (spapr_hotplugged_dev_before_cas()) {
941 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
942 error_report("SLOF provided an unexpected CAS buffer size "
943 TARGET_FMT_lu
" (min: %zu, max: %u)",
944 size
, sizeof(hdr
), FW_MAX_SIZE
);
950 fdt
= spapr_build_fdt(spapr
);
951 _FDT((fdt_pack(fdt
)));
953 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
955 trace_spapr_cas_failed(size
);
959 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
960 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
961 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
963 g_free(spapr
->fdt_blob
);
964 spapr
->fdt_size
= fdt_totalsize(fdt
);
965 spapr
->fdt_initial_size
= spapr
->fdt_size
;
966 spapr
->fdt_blob
= fdt
;
971 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
973 MachineState
*ms
= MACHINE(spapr
);
975 GString
*hypertas
= g_string_sized_new(256);
976 GString
*qemu_hypertas
= g_string_sized_new(256);
977 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
978 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
979 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
980 uint32_t lrdr_capacity
[] = {
981 cpu_to_be32(max_device_addr
>> 32),
982 cpu_to_be32(max_device_addr
& 0xffffffff),
983 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
984 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
986 uint32_t maxdomain
= cpu_to_be32(spapr
->gpu_numa_id
> 1 ? 1 : 0);
987 uint32_t maxdomains
[] = {
992 cpu_to_be32(spapr
->gpu_numa_id
),
995 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
998 add_str(hypertas
, "hcall-pft");
999 add_str(hypertas
, "hcall-term");
1000 add_str(hypertas
, "hcall-dabr");
1001 add_str(hypertas
, "hcall-interrupt");
1002 add_str(hypertas
, "hcall-tce");
1003 add_str(hypertas
, "hcall-vio");
1004 add_str(hypertas
, "hcall-splpar");
1005 add_str(hypertas
, "hcall-join");
1006 add_str(hypertas
, "hcall-bulk");
1007 add_str(hypertas
, "hcall-set-mode");
1008 add_str(hypertas
, "hcall-sprg0");
1009 add_str(hypertas
, "hcall-copy");
1010 add_str(hypertas
, "hcall-debug");
1011 add_str(hypertas
, "hcall-vphn");
1012 add_str(qemu_hypertas
, "hcall-memop1");
1014 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1015 add_str(hypertas
, "hcall-multi-tce");
1018 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1019 add_str(hypertas
, "hcall-hpt-resize");
1022 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1023 hypertas
->str
, hypertas
->len
));
1024 g_string_free(hypertas
, TRUE
);
1025 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1026 qemu_hypertas
->str
, qemu_hypertas
->len
));
1027 g_string_free(qemu_hypertas
, TRUE
);
1029 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1030 refpoints
, sizeof(refpoints
)));
1032 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1033 maxdomains
, sizeof(maxdomains
)));
1035 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1036 RTAS_ERROR_LOG_MAX
));
1037 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1038 RTAS_EVENT_SCAN_RATE
));
1040 g_assert(msi_nonbroken
);
1041 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1044 * According to PAPR, rtas ibm,os-term does not guarantee a return
1045 * back to the guest cpu.
1047 * While an additional ibm,extended-os-term property indicates
1048 * that rtas call return will always occur. Set this property.
1050 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1052 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1053 lrdr_capacity
, sizeof(lrdr_capacity
)));
1055 spapr_dt_rtas_tokens(fdt
, rtas
);
1059 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1060 * and the XIVE features that the guest may request and thus the valid
1061 * values for bytes 23..26 of option vector 5:
1063 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
1066 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1069 23, spapr
->irq
->ov5
, /* Xive mode. */
1070 24, 0x00, /* Hash/Radix, filled in below. */
1071 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1072 26, 0x40, /* Radix options: GTSE == yes. */
1075 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1076 first_ppc_cpu
->compat_pvr
)) {
1078 * If we're in a pre POWER9 compat mode then the guest should
1079 * do hash and use the legacy interrupt mode
1081 val
[1] = 0x00; /* XICS */
1082 val
[3] = 0x00; /* Hash */
1083 } else if (kvm_enabled()) {
1084 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1085 val
[3] = 0x80; /* OV5_MMU_BOTH */
1086 } else if (kvmppc_has_cap_mmu_radix()) {
1087 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1089 val
[3] = 0x00; /* Hash */
1092 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1095 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1099 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
)
1101 MachineState
*machine
= MACHINE(spapr
);
1102 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1104 const char *boot_device
= machine
->boot_order
;
1105 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1107 char *bootlist
= get_boot_devices_list(&cb
);
1109 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1111 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1112 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1113 machine
->kernel_cmdline
));
1115 if (spapr
->initrd_size
) {
1116 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1117 spapr
->initrd_base
));
1118 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1119 spapr
->initrd_base
+ spapr
->initrd_size
));
1122 if (spapr
->kernel_size
) {
1123 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1124 cpu_to_be64(spapr
->kernel_size
) };
1126 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1127 &kprop
, sizeof(kprop
)));
1128 if (spapr
->kernel_le
) {
1129 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1133 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1135 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1136 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1137 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1139 if (cb
&& bootlist
) {
1142 for (i
= 0; i
< cb
; i
++) {
1143 if (bootlist
[i
] == '\n') {
1147 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1150 if (boot_device
&& strlen(boot_device
)) {
1151 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1154 if (!spapr
->has_graphics
&& stdout_path
) {
1156 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1157 * kernel. New platforms should only use the "stdout-path" property. Set
1158 * the new property and continue using older property to remain
1159 * compatible with the existing firmware.
1161 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1162 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1165 /* We can deal with BAR reallocation just fine, advertise it to the guest */
1166 if (smc
->linux_pci_probe
) {
1167 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1170 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1172 g_free(stdout_path
);
1176 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1178 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1179 * KVM to work under pHyp with some guest co-operation */
1181 uint8_t hypercall
[16];
1183 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1184 /* indicate KVM hypercall interface */
1185 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1186 if (kvmppc_has_cap_fixup_hcalls()) {
1188 * Older KVM versions with older guest kernels were broken
1189 * with the magic page, don't allow the guest to map it.
1191 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1192 sizeof(hypercall
))) {
1193 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1194 hypercall
, sizeof(hypercall
)));
1199 static void *spapr_build_fdt(SpaprMachineState
*spapr
)
1201 MachineState
*machine
= MACHINE(spapr
);
1202 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1203 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1209 fdt
= g_malloc0(FDT_MAX_SIZE
);
1210 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1213 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1214 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1215 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1217 /* Guest UUID & Name*/
1218 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1219 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1220 if (qemu_uuid_set
) {
1221 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1225 if (qemu_get_vm_name()) {
1226 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1227 qemu_get_vm_name()));
1230 /* Host Model & Serial Number */
1231 if (spapr
->host_model
) {
1232 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1233 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1234 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1238 if (spapr
->host_serial
) {
1239 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1240 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1241 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1245 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1246 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1248 /* /interrupt controller */
1249 spapr
->irq
->dt_populate(spapr
, spapr_max_server_number(spapr
), fdt
,
1252 ret
= spapr_populate_memory(spapr
, fdt
);
1254 error_report("couldn't setup memory nodes in fdt");
1259 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1261 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1262 ret
= spapr_rng_populate_dt(fdt
);
1264 error_report("could not set up rng device in the fdt");
1269 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1270 ret
= spapr_dt_phb(phb
, PHANDLE_INTC
, fdt
, spapr
->irq
->nr_msis
, NULL
);
1272 error_report("couldn't setup PCI devices in fdt");
1278 spapr_populate_cpus_dt_node(fdt
, spapr
);
1280 if (smc
->dr_lmb_enabled
) {
1281 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1284 if (mc
->has_hotpluggable_cpus
) {
1285 int offset
= fdt_path_offset(fdt
, "/cpus");
1286 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1288 error_report("Couldn't set up CPU DR device tree properties");
1293 /* /event-sources */
1294 spapr_dt_events(spapr
, fdt
);
1297 spapr_dt_rtas(spapr
, fdt
);
1300 spapr_dt_chosen(spapr
, fdt
);
1303 if (kvm_enabled()) {
1304 spapr_dt_hypervisor(spapr
, fdt
);
1307 /* Build memory reserve map */
1308 if (spapr
->kernel_size
) {
1309 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1311 if (spapr
->initrd_size
) {
1312 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1315 /* ibm,client-architecture-support updates */
1316 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1318 error_report("couldn't setup CAS properties fdt");
1322 if (smc
->dr_phb_enabled
) {
1323 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1325 error_report("Couldn't set up PHB DR device tree properties");
1333 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1335 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1338 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1341 CPUPPCState
*env
= &cpu
->env
;
1343 /* The TCG path should also be holding the BQL at this point */
1344 g_assert(qemu_mutex_iothread_locked());
1347 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1348 env
->gpr
[3] = H_PRIVILEGE
;
1350 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1354 struct LPCRSyncState
{
1359 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1361 struct LPCRSyncState
*s
= arg
.host_ptr
;
1362 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1363 CPUPPCState
*env
= &cpu
->env
;
1366 cpu_synchronize_state(cs
);
1367 lpcr
= env
->spr
[SPR_LPCR
];
1370 ppc_store_lpcr(cpu
, lpcr
);
1373 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1376 struct LPCRSyncState s
= {
1381 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1385 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1387 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1389 /* Copy PATE1:GR into PATE0:HR */
1390 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1391 entry
->dw1
= spapr
->patb_entry
;
1394 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1395 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1396 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1397 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1398 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1401 * Get the fd to access the kernel htab, re-opening it if necessary
1403 static int get_htab_fd(SpaprMachineState
*spapr
)
1405 Error
*local_err
= NULL
;
1407 if (spapr
->htab_fd
>= 0) {
1408 return spapr
->htab_fd
;
1411 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1412 if (spapr
->htab_fd
< 0) {
1413 error_report_err(local_err
);
1416 return spapr
->htab_fd
;
1419 void close_htab_fd(SpaprMachineState
*spapr
)
1421 if (spapr
->htab_fd
>= 0) {
1422 close(spapr
->htab_fd
);
1424 spapr
->htab_fd
= -1;
1427 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1429 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1431 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1434 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1436 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1438 assert(kvm_enabled());
1444 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1447 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1450 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1451 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1455 * HTAB is controlled by KVM. Fetch into temporary buffer
1457 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1458 kvmppc_read_hptes(hptes
, ptex
, n
);
1463 * HTAB is controlled by QEMU. Just point to the internally
1466 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1469 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1470 const ppc_hash_pte64_t
*hptes
,
1473 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1476 g_free((void *)hptes
);
1479 /* Nothing to do for qemu managed HPT */
1482 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1483 uint64_t pte0
, uint64_t pte1
)
1485 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1486 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1489 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1491 if (pte0
& HPTE64_V_VALID
) {
1492 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1494 * When setting valid, we write PTE1 first. This ensures
1495 * proper synchronization with the reading code in
1496 * ppc_hash64_pteg_search()
1499 stq_p(spapr
->htab
+ offset
, pte0
);
1501 stq_p(spapr
->htab
+ offset
, pte0
);
1503 * When clearing it we set PTE0 first. This ensures proper
1504 * synchronization with the reading code in
1505 * ppc_hash64_pteg_search()
1508 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1513 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1516 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1517 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1520 /* There should always be a hash table when this is called */
1521 error_report("spapr_hpte_set_c called with no hash table !");
1525 /* The HW performs a non-atomic byte update */
1526 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1529 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1532 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1533 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1536 /* There should always be a hash table when this is called */
1537 error_report("spapr_hpte_set_r called with no hash table !");
1541 /* The HW performs a non-atomic byte update */
1542 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1545 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1549 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1550 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1551 * that's much more than is needed for Linux guests */
1552 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1553 shift
= MAX(shift
, 18); /* Minimum architected size */
1554 shift
= MIN(shift
, 46); /* Maximum architected size */
1558 void spapr_free_hpt(SpaprMachineState
*spapr
)
1560 g_free(spapr
->htab
);
1562 spapr
->htab_shift
= 0;
1563 close_htab_fd(spapr
);
1566 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1571 /* Clean up any HPT info from a previous boot */
1572 spapr_free_hpt(spapr
);
1574 rc
= kvmppc_reset_htab(shift
);
1576 /* kernel-side HPT needed, but couldn't allocate one */
1577 error_setg_errno(errp
, errno
,
1578 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1580 /* This is almost certainly fatal, but if the caller really
1581 * wants to carry on with shift == 0, it's welcome to try */
1582 } else if (rc
> 0) {
1583 /* kernel-side HPT allocated */
1586 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1590 spapr
->htab_shift
= shift
;
1593 /* kernel-side HPT not needed, allocate in userspace instead */
1594 size_t size
= 1ULL << shift
;
1597 spapr
->htab
= qemu_memalign(size
, size
);
1599 error_setg_errno(errp
, errno
,
1600 "Could not allocate HPT of order %d", shift
);
1604 memset(spapr
->htab
, 0, size
);
1605 spapr
->htab_shift
= shift
;
1607 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1608 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1611 /* We're setting up a hash table, so that means we're not radix */
1612 spapr
->patb_entry
= 0;
1613 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1616 void spapr_setup_hpt_and_vrma(SpaprMachineState
*spapr
)
1620 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1621 || (spapr
->cas_reboot
1622 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1623 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1625 uint64_t current_ram_size
;
1627 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1628 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1630 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1632 if (spapr
->vrma_adjust
) {
1633 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1638 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1641 (SpaprDrc
*) object_dynamic_cast(child
,
1642 TYPE_SPAPR_DR_CONNECTOR
);
1645 spapr_drc_reset(drc
);
1651 static void spapr_machine_reset(MachineState
*machine
)
1653 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1654 PowerPCCPU
*first_ppc_cpu
;
1659 spapr_caps_apply(spapr
);
1661 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1662 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1663 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1664 spapr
->max_compat_pvr
)) {
1666 * If using KVM with radix mode available, VCPUs can be started
1667 * without a HPT because KVM will start them in radix mode.
1668 * Set the GR bit in PATE so that we know there is no HPT.
1670 spapr
->patb_entry
= PATE1_GR
;
1671 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1673 spapr_setup_hpt_and_vrma(spapr
);
1676 qemu_devices_reset();
1679 * If this reset wasn't generated by CAS, we should reset our
1680 * negotiated options and start from scratch
1682 if (!spapr
->cas_reboot
) {
1683 spapr_ovec_cleanup(spapr
->ov5_cas
);
1684 spapr
->ov5_cas
= spapr_ovec_new();
1686 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1690 * This is fixing some of the default configuration of the XIVE
1691 * devices. To be called after the reset of the machine devices.
1693 spapr_irq_reset(spapr
, &error_fatal
);
1696 * There is no CAS under qtest. Simulate one to please the code that
1697 * depends on spapr->ov5_cas. This is especially needed to test device
1698 * unplug, so we do that before resetting the DRCs.
1700 if (qtest_enabled()) {
1701 spapr_ovec_cleanup(spapr
->ov5_cas
);
1702 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1705 /* DRC reset may cause a device to be unplugged. This will cause troubles
1706 * if this device is used by another device (eg, a running vhost backend
1707 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1708 * situations, we reset DRCs after all devices have been reset.
1710 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1712 spapr_clear_pending_events(spapr
);
1715 * We place the device tree and RTAS just below either the top of the RMA,
1716 * or just below 2GB, whichever is lower, so that it can be
1717 * processed with 32-bit real mode code if necessary
1719 fdt_addr
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FDT_MAX_SIZE
;
1721 fdt
= spapr_build_fdt(spapr
);
1725 /* Should only fail if we've built a corrupted tree */
1728 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1729 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1730 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1735 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1736 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1737 g_free(spapr
->fdt_blob
);
1738 spapr
->fdt_size
= fdt_totalsize(fdt
);
1739 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1740 spapr
->fdt_blob
= fdt
;
1742 /* Set up the entry state */
1743 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1744 first_ppc_cpu
->env
.gpr
[5] = 0;
1746 spapr
->cas_reboot
= false;
1749 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1751 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1752 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1755 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1759 qdev_init_nofail(dev
);
1761 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1764 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1766 object_initialize_child(OBJECT(spapr
), "rtc",
1767 &spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1768 &error_fatal
, NULL
);
1769 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1771 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1772 "date", &error_fatal
);
1775 /* Returns whether we want to use VGA or not */
1776 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1778 switch (vga_interface_type
) {
1786 return pci_vga_init(pci_bus
) != NULL
;
1789 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1794 static int spapr_pre_load(void *opaque
)
1798 rc
= spapr_caps_pre_load(opaque
);
1806 static int spapr_post_load(void *opaque
, int version_id
)
1808 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1811 err
= spapr_caps_post_migration(spapr
);
1817 * In earlier versions, there was no separate qdev for the PAPR
1818 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1819 * So when migrating from those versions, poke the incoming offset
1820 * value into the RTC device
1822 if (version_id
< 3) {
1823 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1829 if (kvm_enabled() && spapr
->patb_entry
) {
1830 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1831 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1832 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1835 * Update LPCR:HR and UPRT as they may not be set properly in
1838 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1839 LPCR_HR
| LPCR_UPRT
);
1841 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1843 error_report("Process table config unsupported by the host");
1848 err
= spapr_irq_post_load(spapr
, version_id
);
1856 static int spapr_pre_save(void *opaque
)
1860 rc
= spapr_caps_pre_save(opaque
);
1868 static bool version_before_3(void *opaque
, int version_id
)
1870 return version_id
< 3;
1873 static bool spapr_pending_events_needed(void *opaque
)
1875 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1876 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1879 static const VMStateDescription vmstate_spapr_event_entry
= {
1880 .name
= "spapr_event_log_entry",
1882 .minimum_version_id
= 1,
1883 .fields
= (VMStateField
[]) {
1884 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1885 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1886 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1887 NULL
, extended_length
),
1888 VMSTATE_END_OF_LIST()
1892 static const VMStateDescription vmstate_spapr_pending_events
= {
1893 .name
= "spapr_pending_events",
1895 .minimum_version_id
= 1,
1896 .needed
= spapr_pending_events_needed
,
1897 .fields
= (VMStateField
[]) {
1898 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1899 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1900 VMSTATE_END_OF_LIST()
1904 static bool spapr_ov5_cas_needed(void *opaque
)
1906 SpaprMachineState
*spapr
= opaque
;
1907 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1908 SpaprOptionVector
*ov5_legacy
= spapr_ovec_new();
1909 SpaprOptionVector
*ov5_removed
= spapr_ovec_new();
1912 /* Prior to the introduction of SpaprOptionVector, we had two option
1913 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1914 * Both of these options encode machine topology into the device-tree
1915 * in such a way that the now-booted OS should still be able to interact
1916 * appropriately with QEMU regardless of what options were actually
1917 * negotiatied on the source side.
1919 * As such, we can avoid migrating the CAS-negotiated options if these
1920 * are the only options available on the current machine/platform.
1921 * Since these are the only options available for pseries-2.7 and
1922 * earlier, this allows us to maintain old->new/new->old migration
1925 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1926 * via default pseries-2.8 machines and explicit command-line parameters.
1927 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1928 * of the actual CAS-negotiated values to continue working properly. For
1929 * example, availability of memory unplug depends on knowing whether
1930 * OV5_HP_EVT was negotiated via CAS.
1932 * Thus, for any cases where the set of available CAS-negotiatable
1933 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1934 * include the CAS-negotiated options in the migration stream, unless
1935 * if they affect boot time behaviour only.
1937 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1938 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1939 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1941 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1942 * the mask itself since in the future it's possible "legacy" bits may be
1943 * removed via machine options, which could generate a false positive
1944 * that breaks migration.
1946 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1947 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1949 spapr_ovec_cleanup(ov5_mask
);
1950 spapr_ovec_cleanup(ov5_legacy
);
1951 spapr_ovec_cleanup(ov5_removed
);
1956 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1957 .name
= "spapr_option_vector_ov5_cas",
1959 .minimum_version_id
= 1,
1960 .needed
= spapr_ov5_cas_needed
,
1961 .fields
= (VMStateField
[]) {
1962 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1963 vmstate_spapr_ovec
, SpaprOptionVector
),
1964 VMSTATE_END_OF_LIST()
1968 static bool spapr_patb_entry_needed(void *opaque
)
1970 SpaprMachineState
*spapr
= opaque
;
1972 return !!spapr
->patb_entry
;
1975 static const VMStateDescription vmstate_spapr_patb_entry
= {
1976 .name
= "spapr_patb_entry",
1978 .minimum_version_id
= 1,
1979 .needed
= spapr_patb_entry_needed
,
1980 .fields
= (VMStateField
[]) {
1981 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1982 VMSTATE_END_OF_LIST()
1986 static bool spapr_irq_map_needed(void *opaque
)
1988 SpaprMachineState
*spapr
= opaque
;
1990 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1993 static const VMStateDescription vmstate_spapr_irq_map
= {
1994 .name
= "spapr_irq_map",
1996 .minimum_version_id
= 1,
1997 .needed
= spapr_irq_map_needed
,
1998 .fields
= (VMStateField
[]) {
1999 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
2000 VMSTATE_END_OF_LIST()
2004 static bool spapr_dtb_needed(void *opaque
)
2006 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
2008 return smc
->update_dt_enabled
;
2011 static int spapr_dtb_pre_load(void *opaque
)
2013 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2015 g_free(spapr
->fdt_blob
);
2016 spapr
->fdt_blob
= NULL
;
2017 spapr
->fdt_size
= 0;
2022 static const VMStateDescription vmstate_spapr_dtb
= {
2023 .name
= "spapr_dtb",
2025 .minimum_version_id
= 1,
2026 .needed
= spapr_dtb_needed
,
2027 .pre_load
= spapr_dtb_pre_load
,
2028 .fields
= (VMStateField
[]) {
2029 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
2030 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
2031 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
2033 VMSTATE_END_OF_LIST()
2037 static const VMStateDescription vmstate_spapr
= {
2040 .minimum_version_id
= 1,
2041 .pre_load
= spapr_pre_load
,
2042 .post_load
= spapr_post_load
,
2043 .pre_save
= spapr_pre_save
,
2044 .fields
= (VMStateField
[]) {
2045 /* used to be @next_irq */
2046 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2049 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2051 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2052 VMSTATE_END_OF_LIST()
2054 .subsections
= (const VMStateDescription
*[]) {
2055 &vmstate_spapr_ov5_cas
,
2056 &vmstate_spapr_patb_entry
,
2057 &vmstate_spapr_pending_events
,
2058 &vmstate_spapr_cap_htm
,
2059 &vmstate_spapr_cap_vsx
,
2060 &vmstate_spapr_cap_dfp
,
2061 &vmstate_spapr_cap_cfpc
,
2062 &vmstate_spapr_cap_sbbc
,
2063 &vmstate_spapr_cap_ibs
,
2064 &vmstate_spapr_cap_hpt_maxpagesize
,
2065 &vmstate_spapr_irq_map
,
2066 &vmstate_spapr_cap_nested_kvm_hv
,
2068 &vmstate_spapr_cap_large_decr
,
2069 &vmstate_spapr_cap_ccf_assist
,
2074 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2076 SpaprMachineState
*spapr
= opaque
;
2078 /* "Iteration" header */
2079 if (!spapr
->htab_shift
) {
2080 qemu_put_be32(f
, -1);
2082 qemu_put_be32(f
, spapr
->htab_shift
);
2086 spapr
->htab_save_index
= 0;
2087 spapr
->htab_first_pass
= true;
2089 if (spapr
->htab_shift
) {
2090 assert(kvm_enabled());
2098 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2099 int chunkstart
, int n_valid
, int n_invalid
)
2101 qemu_put_be32(f
, chunkstart
);
2102 qemu_put_be16(f
, n_valid
);
2103 qemu_put_be16(f
, n_invalid
);
2104 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2105 HASH_PTE_SIZE_64
* n_valid
);
2108 static void htab_save_end_marker(QEMUFile
*f
)
2110 qemu_put_be32(f
, 0);
2111 qemu_put_be16(f
, 0);
2112 qemu_put_be16(f
, 0);
2115 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2118 bool has_timeout
= max_ns
!= -1;
2119 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2120 int index
= spapr
->htab_save_index
;
2121 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2123 assert(spapr
->htab_first_pass
);
2128 /* Consume invalid HPTEs */
2129 while ((index
< htabslots
)
2130 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2131 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2135 /* Consume valid HPTEs */
2137 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2138 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2139 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2143 if (index
> chunkstart
) {
2144 int n_valid
= index
- chunkstart
;
2146 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2149 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2153 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2155 if (index
>= htabslots
) {
2156 assert(index
== htabslots
);
2158 spapr
->htab_first_pass
= false;
2160 spapr
->htab_save_index
= index
;
2163 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2166 bool final
= max_ns
< 0;
2167 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2168 int examined
= 0, sent
= 0;
2169 int index
= spapr
->htab_save_index
;
2170 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2172 assert(!spapr
->htab_first_pass
);
2175 int chunkstart
, invalidstart
;
2177 /* Consume non-dirty HPTEs */
2178 while ((index
< htabslots
)
2179 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2185 /* Consume valid dirty HPTEs */
2186 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2187 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2188 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2189 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2194 invalidstart
= index
;
2195 /* Consume invalid dirty HPTEs */
2196 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2197 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2198 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2199 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2204 if (index
> chunkstart
) {
2205 int n_valid
= invalidstart
- chunkstart
;
2206 int n_invalid
= index
- invalidstart
;
2208 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2209 sent
+= index
- chunkstart
;
2211 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2216 if (examined
>= htabslots
) {
2220 if (index
>= htabslots
) {
2221 assert(index
== htabslots
);
2224 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2226 if (index
>= htabslots
) {
2227 assert(index
== htabslots
);
2231 spapr
->htab_save_index
= index
;
2233 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2236 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2237 #define MAX_KVM_BUF_SIZE 2048
2239 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2241 SpaprMachineState
*spapr
= opaque
;
2245 /* Iteration header */
2246 if (!spapr
->htab_shift
) {
2247 qemu_put_be32(f
, -1);
2250 qemu_put_be32(f
, 0);
2254 assert(kvm_enabled());
2256 fd
= get_htab_fd(spapr
);
2261 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2265 } else if (spapr
->htab_first_pass
) {
2266 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2268 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2271 htab_save_end_marker(f
);
2276 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2278 SpaprMachineState
*spapr
= opaque
;
2281 /* Iteration header */
2282 if (!spapr
->htab_shift
) {
2283 qemu_put_be32(f
, -1);
2286 qemu_put_be32(f
, 0);
2292 assert(kvm_enabled());
2294 fd
= get_htab_fd(spapr
);
2299 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2304 if (spapr
->htab_first_pass
) {
2305 htab_save_first_pass(f
, spapr
, -1);
2307 htab_save_later_pass(f
, spapr
, -1);
2311 htab_save_end_marker(f
);
2316 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2318 SpaprMachineState
*spapr
= opaque
;
2319 uint32_t section_hdr
;
2321 Error
*local_err
= NULL
;
2323 if (version_id
< 1 || version_id
> 1) {
2324 error_report("htab_load() bad version");
2328 section_hdr
= qemu_get_be32(f
);
2330 if (section_hdr
== -1) {
2331 spapr_free_hpt(spapr
);
2336 /* First section gives the htab size */
2337 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2339 error_report_err(local_err
);
2346 assert(kvm_enabled());
2348 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2350 error_report_err(local_err
);
2357 uint16_t n_valid
, n_invalid
;
2359 index
= qemu_get_be32(f
);
2360 n_valid
= qemu_get_be16(f
);
2361 n_invalid
= qemu_get_be16(f
);
2363 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2368 if ((index
+ n_valid
+ n_invalid
) >
2369 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2370 /* Bad index in stream */
2372 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2373 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2379 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2380 HASH_PTE_SIZE_64
* n_valid
);
2383 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2384 HASH_PTE_SIZE_64
* n_invalid
);
2391 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2406 static void htab_save_cleanup(void *opaque
)
2408 SpaprMachineState
*spapr
= opaque
;
2410 close_htab_fd(spapr
);
2413 static SaveVMHandlers savevm_htab_handlers
= {
2414 .save_setup
= htab_save_setup
,
2415 .save_live_iterate
= htab_save_iterate
,
2416 .save_live_complete_precopy
= htab_save_complete
,
2417 .save_cleanup
= htab_save_cleanup
,
2418 .load_state
= htab_load
,
2421 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2424 MachineState
*machine
= MACHINE(opaque
);
2425 machine
->boot_order
= g_strdup(boot_device
);
2428 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2430 MachineState
*machine
= MACHINE(spapr
);
2431 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2432 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2435 for (i
= 0; i
< nr_lmbs
; i
++) {
2438 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2439 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2445 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2446 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2447 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2449 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2453 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2454 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2455 " is not aligned to %" PRIu64
" MiB",
2457 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2461 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2462 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2463 " is not aligned to %" PRIu64
" MiB",
2465 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2469 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2470 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2472 "Node %d memory size 0x%" PRIx64
2473 " is not aligned to %" PRIu64
" MiB",
2474 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2475 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2481 /* find cpu slot in machine->possible_cpus by core_id */
2482 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2484 int index
= id
/ ms
->smp
.threads
;
2486 if (index
>= ms
->possible_cpus
->len
) {
2492 return &ms
->possible_cpus
->cpus
[index
];
2495 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2497 MachineState
*ms
= MACHINE(spapr
);
2498 Error
*local_err
= NULL
;
2499 bool vsmt_user
= !!spapr
->vsmt
;
2500 int kvm_smt
= kvmppc_smt_threads();
2502 unsigned int smp_threads
= ms
->smp
.threads
;
2504 if (!kvm_enabled() && (smp_threads
> 1)) {
2505 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2506 "on a pseries machine");
2509 if (!is_power_of_2(smp_threads
)) {
2510 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2511 "machine because it must be a power of 2", smp_threads
);
2515 /* Detemine the VSMT mode to use: */
2517 if (spapr
->vsmt
< smp_threads
) {
2518 error_setg(&local_err
, "Cannot support VSMT mode %d"
2519 " because it must be >= threads/core (%d)",
2520 spapr
->vsmt
, smp_threads
);
2523 /* In this case, spapr->vsmt has been set by the command line */
2526 * Default VSMT value is tricky, because we need it to be as
2527 * consistent as possible (for migration), but this requires
2528 * changing it for at least some existing cases. We pick 8 as
2529 * the value that we'd get with KVM on POWER8, the
2530 * overwhelmingly common case in production systems.
2532 spapr
->vsmt
= MAX(8, smp_threads
);
2535 /* KVM: If necessary, set the SMT mode: */
2536 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2537 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2539 /* Looks like KVM isn't able to change VSMT mode */
2540 error_setg(&local_err
,
2541 "Failed to set KVM's VSMT mode to %d (errno %d)",
2543 /* We can live with that if the default one is big enough
2544 * for the number of threads, and a submultiple of the one
2545 * we want. In this case we'll waste some vcpu ids, but
2546 * behaviour will be correct */
2547 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2548 warn_report_err(local_err
);
2553 error_append_hint(&local_err
,
2554 "On PPC, a VM with %d threads/core"
2555 " on a host with %d threads/core"
2556 " requires the use of VSMT mode %d.\n",
2557 smp_threads
, kvm_smt
, spapr
->vsmt
);
2559 kvmppc_hint_smt_possible(&local_err
);
2564 /* else TCG: nothing to do currently */
2566 error_propagate(errp
, local_err
);
2569 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2571 MachineState
*machine
= MACHINE(spapr
);
2572 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2573 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2574 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2575 const CPUArchIdList
*possible_cpus
;
2576 unsigned int smp_cpus
= machine
->smp
.cpus
;
2577 unsigned int smp_threads
= machine
->smp
.threads
;
2578 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2579 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2582 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2583 if (mc
->has_hotpluggable_cpus
) {
2584 if (smp_cpus
% smp_threads
) {
2585 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2586 smp_cpus
, smp_threads
);
2589 if (max_cpus
% smp_threads
) {
2590 error_report("max_cpus (%u) must be multiple of threads (%u)",
2591 max_cpus
, smp_threads
);
2595 if (max_cpus
!= smp_cpus
) {
2596 error_report("This machine version does not support CPU hotplug");
2599 boot_cores_nr
= possible_cpus
->len
;
2602 if (smc
->pre_2_10_has_unused_icps
) {
2605 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2606 /* Dummy entries get deregistered when real ICPState objects
2607 * are registered during CPU core hotplug.
2609 pre_2_10_vmstate_register_dummy_icp(i
);
2613 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2614 int core_id
= i
* smp_threads
;
2616 if (mc
->has_hotpluggable_cpus
) {
2617 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2618 spapr_vcpu_id(spapr
, core_id
));
2621 if (i
< boot_cores_nr
) {
2622 Object
*core
= object_new(type
);
2623 int nr_threads
= smp_threads
;
2625 /* Handle the partially filled core for older machine types */
2626 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2627 nr_threads
= smp_cpus
- i
* smp_threads
;
2630 object_property_set_int(core
, nr_threads
, "nr-threads",
2632 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2634 object_property_set_bool(core
, true, "realized", &error_fatal
);
2641 static PCIHostState
*spapr_create_default_phb(void)
2645 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2646 qdev_prop_set_uint32(dev
, "index", 0);
2647 qdev_init_nofail(dev
);
2649 return PCI_HOST_BRIDGE(dev
);
2652 /* pSeries LPAR / sPAPR hardware init */
2653 static void spapr_machine_init(MachineState
*machine
)
2655 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2656 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2657 const char *kernel_filename
= machine
->kernel_filename
;
2658 const char *initrd_filename
= machine
->initrd_filename
;
2661 MemoryRegion
*sysmem
= get_system_memory();
2662 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2663 hwaddr node0_size
= spapr_node0_size(machine
);
2664 long load_limit
, fw_size
;
2666 Error
*resize_hpt_err
= NULL
;
2668 msi_nonbroken
= true;
2670 QLIST_INIT(&spapr
->phbs
);
2671 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2673 /* Determine capabilities to run with */
2674 spapr_caps_init(spapr
);
2676 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2677 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2679 * If the user explicitly requested a mode we should either
2680 * supply it, or fail completely (which we do below). But if
2681 * it's not set explicitly, we reset our mode to something
2684 if (resize_hpt_err
) {
2685 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2686 error_free(resize_hpt_err
);
2687 resize_hpt_err
= NULL
;
2689 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2693 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2695 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2697 * User requested HPT resize, but this host can't supply it. Bail out
2699 error_report_err(resize_hpt_err
);
2703 spapr
->rma_size
= node0_size
;
2705 /* With KVM, we don't actually know whether KVM supports an
2706 * unbounded RMA (PR KVM) or is limited by the hash table size
2707 * (HV KVM using VRMA), so we always assume the latter
2709 * In that case, we also limit the initial allocations for RTAS
2710 * etc... to 256M since we have no way to know what the VRMA size
2711 * is going to be as it depends on the size of the hash table
2712 * which isn't determined yet.
2714 if (kvm_enabled()) {
2715 spapr
->vrma_adjust
= 1;
2716 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2719 /* Actually we don't support unbounded RMA anymore since we added
2720 * proper emulation of HV mode. The max we can get is 16G which
2721 * also happens to be what we configure for PAPR mode so make sure
2722 * we don't do anything bigger than that
2724 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2726 if (spapr
->rma_size
> node0_size
) {
2727 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2732 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2733 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2736 * VSMT must be set in order to be able to compute VCPU ids, ie to
2737 * call spapr_max_server_number() or spapr_vcpu_id().
2739 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2741 /* Set up Interrupt Controller before we create the VCPUs */
2742 spapr_irq_init(spapr
, &error_fatal
);
2744 /* Set up containers for ibm,client-architecture-support negotiated options
2746 spapr
->ov5
= spapr_ovec_new();
2747 spapr
->ov5_cas
= spapr_ovec_new();
2749 if (smc
->dr_lmb_enabled
) {
2750 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2751 spapr_validate_node_memory(machine
, &error_fatal
);
2754 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2756 /* advertise support for dedicated HP event source to guests */
2757 if (spapr
->use_hotplug_event_source
) {
2758 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2761 /* advertise support for HPT resizing */
2762 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2763 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2766 /* advertise support for ibm,dyamic-memory-v2 */
2767 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2769 /* advertise XIVE on POWER9 machines */
2770 if (spapr
->irq
->ov5
& (SPAPR_OV5_XIVE_EXPLOIT
| SPAPR_OV5_XIVE_BOTH
)) {
2771 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2775 spapr_init_cpus(spapr
);
2778 * check we don't have a memory-less/cpu-less NUMA node
2779 * Firmware relies on the existing memory/cpu topology to provide the
2780 * NUMA topology to the kernel.
2781 * And the linux kernel needs to know the NUMA topology at start
2782 * to be able to hotplug CPUs later.
2784 if (machine
->numa_state
->num_nodes
) {
2785 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2786 /* check for memory-less node */
2787 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2790 /* check for cpu-less node */
2792 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2793 if (cpu
->node_id
== i
) {
2798 /* memory-less and cpu-less node */
2801 "Memory-less/cpu-less nodes are not supported (node %d)",
2811 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2812 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2813 * called from vPHB reset handler so we initialize the counter here.
2814 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2815 * must be equally distant from any other node.
2816 * The final value of spapr->gpu_numa_id is going to be written to
2817 * max-associativity-domains in spapr_build_fdt().
2819 spapr
->gpu_numa_id
= MAX(1, machine
->numa_state
->num_nodes
);
2821 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2822 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2823 spapr
->max_compat_pvr
)) {
2824 /* KVM and TCG always allow GTSE with radix... */
2825 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2827 /* ... but not with hash (currently). */
2829 if (kvm_enabled()) {
2830 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2831 kvmppc_enable_logical_ci_hcalls();
2832 kvmppc_enable_set_mode_hcall();
2834 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2835 kvmppc_enable_clear_ref_mod_hcalls();
2837 /* Enable H_PAGE_INIT */
2838 kvmppc_enable_h_page_init();
2842 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2844 memory_region_add_subregion(sysmem
, 0, ram
);
2846 /* always allocate the device memory information */
2847 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2849 /* initialize hotplug memory address space */
2850 if (machine
->ram_size
< machine
->maxram_size
) {
2851 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2853 * Limit the number of hotpluggable memory slots to half the number
2854 * slots that KVM supports, leaving the other half for PCI and other
2855 * devices. However ensure that number of slots doesn't drop below 32.
2857 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2858 SPAPR_MAX_RAM_SLOTS
;
2860 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2861 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2863 if (machine
->ram_slots
> max_memslots
) {
2864 error_report("Specified number of memory slots %"
2865 PRIu64
" exceeds max supported %d",
2866 machine
->ram_slots
, max_memslots
);
2870 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2871 SPAPR_DEVICE_MEM_ALIGN
);
2872 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2873 "device-memory", device_mem_size
);
2874 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2875 &machine
->device_memory
->mr
);
2878 if (smc
->dr_lmb_enabled
) {
2879 spapr_create_lmb_dr_connectors(spapr
);
2882 /* Set up RTAS event infrastructure */
2883 spapr_events_init(spapr
);
2885 /* Set up the RTC RTAS interfaces */
2886 spapr_rtc_create(spapr
);
2888 /* Set up VIO bus */
2889 spapr
->vio_bus
= spapr_vio_bus_init();
2891 for (i
= 0; i
< serial_max_hds(); i
++) {
2893 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2897 /* We always have at least the nvram device on VIO */
2898 spapr_create_nvram(spapr
);
2901 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2902 * connectors (described in root DT node's "ibm,drc-types" property)
2903 * are pre-initialized here. additional child connectors (such as
2904 * connectors for a PHBs PCI slots) are added as needed during their
2905 * parent's realization.
2907 if (smc
->dr_phb_enabled
) {
2908 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2909 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2914 spapr_pci_rtas_init();
2916 phb
= spapr_create_default_phb();
2918 for (i
= 0; i
< nb_nics
; i
++) {
2919 NICInfo
*nd
= &nd_table
[i
];
2922 nd
->model
= g_strdup("spapr-vlan");
2925 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2926 g_str_equal(nd
->model
, "ibmveth")) {
2927 spapr_vlan_create(spapr
->vio_bus
, nd
);
2929 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2933 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2934 spapr_vscsi_create(spapr
->vio_bus
);
2938 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2939 spapr
->has_graphics
= true;
2940 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2944 if (smc
->use_ohci_by_default
) {
2945 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2947 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2950 if (spapr
->has_graphics
) {
2951 USBBus
*usb_bus
= usb_bus_find(-1);
2953 usb_create_simple(usb_bus
, "usb-kbd");
2954 usb_create_simple(usb_bus
, "usb-mouse");
2958 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
2960 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2965 if (kernel_filename
) {
2966 uint64_t lowaddr
= 0;
2968 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2969 translate_kernel_address
, NULL
,
2970 NULL
, &lowaddr
, NULL
, 1,
2971 PPC_ELF_MACHINE
, 0, 0);
2972 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2973 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2974 translate_kernel_address
, NULL
, NULL
,
2975 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2977 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2979 if (spapr
->kernel_size
< 0) {
2980 error_report("error loading %s: %s", kernel_filename
,
2981 load_elf_strerror(spapr
->kernel_size
));
2986 if (initrd_filename
) {
2987 /* Try to locate the initrd in the gap between the kernel
2988 * and the firmware. Add a bit of space just in case
2990 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
2991 + 0x1ffff) & ~0xffff;
2992 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2995 - spapr
->initrd_base
);
2996 if (spapr
->initrd_size
< 0) {
2997 error_report("could not load initial ram disk '%s'",
3004 if (bios_name
== NULL
) {
3005 bios_name
= FW_FILE_NAME
;
3007 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
3009 error_report("Could not find LPAR firmware '%s'", bios_name
);
3012 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
3014 error_report("Could not load LPAR firmware '%s'", filename
);
3019 /* FIXME: Should register things through the MachineState's qdev
3020 * interface, this is a legacy from the sPAPREnvironment structure
3021 * which predated MachineState but had a similar function */
3022 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3023 register_savevm_live("spapr/htab", -1, 1,
3024 &savevm_htab_handlers
, spapr
);
3026 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
),
3029 qemu_register_boot_set(spapr_boot_set
, spapr
);
3032 * Nothing needs to be done to resume a suspended guest because
3033 * suspending does not change the machine state, so no need for
3034 * a ->wakeup method.
3036 qemu_register_wakeup_support();
3038 if (kvm_enabled()) {
3039 /* to stop and start vmclock */
3040 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3043 kvmppc_spapr_enable_inkernel_multitce();
3047 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3053 if (!strcmp(vm_type
, "HV")) {
3057 if (!strcmp(vm_type
, "PR")) {
3061 error_report("Unknown kvm-type specified '%s'", vm_type
);
3066 * Implementation of an interface to adjust firmware path
3067 * for the bootindex property handling.
3069 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3072 #define CAST(type, obj, name) \
3073 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3074 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3075 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3076 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3079 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3080 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3081 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3085 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3086 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3087 * 0x8000 | (target << 8) | (bus << 5) | lun
3088 * (see the "Logical unit addressing format" table in SAM5)
3090 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3091 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3092 (uint64_t)id
<< 48);
3093 } else if (virtio
) {
3095 * We use SRP luns of the form 01000000 | (target << 8) | lun
3096 * in the top 32 bits of the 64-bit LUN
3097 * Note: the quote above is from SLOF and it is wrong,
3098 * the actual binding is:
3099 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3101 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3102 if (d
->lun
>= 256) {
3103 /* Use the LUN "flat space addressing method" */
3106 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3107 (uint64_t)id
<< 32);
3110 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3111 * in the top 32 bits of the 64-bit LUN
3113 unsigned usb_port
= atoi(usb
->port
->path
);
3114 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3115 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3116 (uint64_t)id
<< 32);
3121 * SLOF probes the USB devices, and if it recognizes that the device is a
3122 * storage device, it changes its name to "storage" instead of "usb-host",
3123 * and additionally adds a child node for the SCSI LUN, so the correct
3124 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3126 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3127 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3128 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3129 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3134 /* Replace "pci" with "pci@800000020000000" */
3135 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3139 /* Same logic as virtio above */
3140 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3141 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3144 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3145 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3146 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3147 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3153 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3155 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3157 return g_strdup(spapr
->kvm_type
);
3160 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3162 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3164 g_free(spapr
->kvm_type
);
3165 spapr
->kvm_type
= g_strdup(value
);
3168 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3170 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3172 return spapr
->use_hotplug_event_source
;
3175 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3178 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3180 spapr
->use_hotplug_event_source
= value
;
3183 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3188 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3190 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3192 switch (spapr
->resize_hpt
) {
3193 case SPAPR_RESIZE_HPT_DEFAULT
:
3194 return g_strdup("default");
3195 case SPAPR_RESIZE_HPT_DISABLED
:
3196 return g_strdup("disabled");
3197 case SPAPR_RESIZE_HPT_ENABLED
:
3198 return g_strdup("enabled");
3199 case SPAPR_RESIZE_HPT_REQUIRED
:
3200 return g_strdup("required");
3202 g_assert_not_reached();
3205 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3207 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3209 if (strcmp(value
, "default") == 0) {
3210 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3211 } else if (strcmp(value
, "disabled") == 0) {
3212 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3213 } else if (strcmp(value
, "enabled") == 0) {
3214 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3215 } else if (strcmp(value
, "required") == 0) {
3216 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3218 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3222 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3223 void *opaque
, Error
**errp
)
3225 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3228 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3229 void *opaque
, Error
**errp
)
3231 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3234 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3236 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3238 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3239 return g_strdup("legacy");
3240 } else if (spapr
->irq
== &spapr_irq_xics
) {
3241 return g_strdup("xics");
3242 } else if (spapr
->irq
== &spapr_irq_xive
) {
3243 return g_strdup("xive");
3244 } else if (spapr
->irq
== &spapr_irq_dual
) {
3245 return g_strdup("dual");
3247 g_assert_not_reached();
3250 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3252 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3254 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3255 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3259 /* The legacy IRQ backend can not be set */
3260 if (strcmp(value
, "xics") == 0) {
3261 spapr
->irq
= &spapr_irq_xics
;
3262 } else if (strcmp(value
, "xive") == 0) {
3263 spapr
->irq
= &spapr_irq_xive
;
3264 } else if (strcmp(value
, "dual") == 0) {
3265 spapr
->irq
= &spapr_irq_dual
;
3267 error_setg(errp
, "Bad value for \"ic-mode\" property");
3271 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3273 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3275 return g_strdup(spapr
->host_model
);
3278 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3280 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3282 g_free(spapr
->host_model
);
3283 spapr
->host_model
= g_strdup(value
);
3286 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3288 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3290 return g_strdup(spapr
->host_serial
);
3293 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3295 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3297 g_free(spapr
->host_serial
);
3298 spapr
->host_serial
= g_strdup(value
);
3301 static void spapr_instance_init(Object
*obj
)
3303 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3304 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3306 spapr
->htab_fd
= -1;
3307 spapr
->use_hotplug_event_source
= true;
3308 object_property_add_str(obj
, "kvm-type",
3309 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3310 object_property_set_description(obj
, "kvm-type",
3311 "Specifies the KVM virtualization mode (HV, PR)",
3313 object_property_add_bool(obj
, "modern-hotplug-events",
3314 spapr_get_modern_hotplug_events
,
3315 spapr_set_modern_hotplug_events
,
3317 object_property_set_description(obj
, "modern-hotplug-events",
3318 "Use dedicated hotplug event mechanism in"
3319 " place of standard EPOW events when possible"
3320 " (required for memory hot-unplug support)",
3322 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3323 "Maximum permitted CPU compatibility mode",
3326 object_property_add_str(obj
, "resize-hpt",
3327 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3328 object_property_set_description(obj
, "resize-hpt",
3329 "Resizing of the Hash Page Table (enabled, disabled, required)",
3331 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3332 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3333 object_property_set_description(obj
, "vsmt",
3334 "Virtual SMT: KVM behaves as if this were"
3335 " the host's SMT mode", &error_abort
);
3336 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3337 spapr_get_msix_emulation
, NULL
, NULL
);
3339 /* The machine class defines the default interrupt controller mode */
3340 spapr
->irq
= smc
->irq
;
3341 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3342 spapr_set_ic_mode
, NULL
);
3343 object_property_set_description(obj
, "ic-mode",
3344 "Specifies the interrupt controller mode (xics, xive, dual)",
3347 object_property_add_str(obj
, "host-model",
3348 spapr_get_host_model
, spapr_set_host_model
,
3350 object_property_set_description(obj
, "host-model",
3351 "Host model to advertise in guest device tree", &error_abort
);
3352 object_property_add_str(obj
, "host-serial",
3353 spapr_get_host_serial
, spapr_set_host_serial
,
3355 object_property_set_description(obj
, "host-serial",
3356 "Host serial number to advertise in guest device tree", &error_abort
);
3359 static void spapr_machine_finalizefn(Object
*obj
)
3361 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3363 g_free(spapr
->kvm_type
);
3366 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3368 cpu_synchronize_state(cs
);
3369 ppc_cpu_do_system_reset(cs
);
3372 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3377 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3381 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3382 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3387 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3388 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3390 *fdt_start_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3391 SPAPR_MEMORY_BLOCK_SIZE
);
3395 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3396 bool dedicated_hp_event_source
, Error
**errp
)
3399 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3401 uint64_t addr
= addr_start
;
3402 bool hotplugged
= spapr_drc_hotplugged(dev
);
3403 Error
*local_err
= NULL
;
3405 for (i
= 0; i
< nr_lmbs
; i
++) {
3406 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3407 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3410 spapr_drc_attach(drc
, dev
, &local_err
);
3412 while (addr
> addr_start
) {
3413 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3414 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3415 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3416 spapr_drc_detach(drc
);
3418 error_propagate(errp
, local_err
);
3422 spapr_drc_reset(drc
);
3424 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3426 /* send hotplug notification to the
3427 * guest only in case of hotplugged memory
3430 if (dedicated_hp_event_source
) {
3431 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3432 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3433 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3435 spapr_drc_index(drc
));
3437 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3443 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3446 Error
*local_err
= NULL
;
3447 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3448 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3449 uint64_t size
, addr
;
3451 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3453 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3458 addr
= object_property_get_uint(OBJECT(dimm
),
3459 PC_DIMM_ADDR_PROP
, &local_err
);
3464 spapr_add_lmbs(dev
, addr
, size
, spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3473 pc_dimm_unplug(dimm
, MACHINE(ms
));
3475 error_propagate(errp
, local_err
);
3478 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3481 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3482 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3483 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3484 Error
*local_err
= NULL
;
3489 if (!smc
->dr_lmb_enabled
) {
3490 error_setg(errp
, "Memory hotplug not supported for this machine");
3494 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3496 error_propagate(errp
, local_err
);
3500 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3501 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3502 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3506 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3508 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3509 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3511 error_propagate(errp
, local_err
);
3515 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3518 struct SpaprDimmState
{
3521 QTAILQ_ENTRY(SpaprDimmState
) next
;
3524 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3527 SpaprDimmState
*dimm_state
= NULL
;
3529 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3530 if (dimm_state
->dimm
== dimm
) {
3537 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3541 SpaprDimmState
*ds
= NULL
;
3544 * If this request is for a DIMM whose removal had failed earlier
3545 * (due to guest's refusal to remove the LMBs), we would have this
3546 * dimm already in the pending_dimm_unplugs list. In that
3547 * case don't add again.
3549 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3551 ds
= g_malloc0(sizeof(SpaprDimmState
));
3552 ds
->nr_lmbs
= nr_lmbs
;
3554 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3559 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3560 SpaprDimmState
*dimm_state
)
3562 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3566 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3570 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3572 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3573 uint32_t avail_lmbs
= 0;
3574 uint64_t addr_start
, addr
;
3577 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3581 for (i
= 0; i
< nr_lmbs
; i
++) {
3582 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3583 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3588 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3591 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3594 /* Callback to be called during DRC release. */
3595 void spapr_lmb_release(DeviceState
*dev
)
3597 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3598 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3599 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3601 /* This information will get lost if a migration occurs
3602 * during the unplug process. In this case recover it. */
3604 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3606 /* The DRC being examined by the caller at least must be counted */
3607 g_assert(ds
->nr_lmbs
);
3610 if (--ds
->nr_lmbs
) {
3615 * Now that all the LMBs have been removed by the guest, call the
3616 * unplug handler chain. This can never fail.
3618 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3619 object_unparent(OBJECT(dev
));
3622 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3624 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3625 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3627 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3628 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3629 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3632 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3633 DeviceState
*dev
, Error
**errp
)
3635 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3636 Error
*local_err
= NULL
;
3637 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3639 uint64_t size
, addr_start
, addr
;
3643 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3644 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3646 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3653 * An existing pending dimm state for this DIMM means that there is an
3654 * unplug operation in progress, waiting for the spapr_lmb_release
3655 * callback to complete the job (BQL can't cover that far). In this case,
3656 * bail out to avoid detaching DRCs that were already released.
3658 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3659 error_setg(&local_err
,
3660 "Memory unplug already in progress for device %s",
3665 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3668 for (i
= 0; i
< nr_lmbs
; i
++) {
3669 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3670 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3673 spapr_drc_detach(drc
);
3674 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3677 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3678 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3679 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3680 nr_lmbs
, spapr_drc_index(drc
));
3682 error_propagate(errp
, local_err
);
3685 /* Callback to be called during DRC release. */
3686 void spapr_core_release(DeviceState
*dev
)
3688 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3690 /* Call the unplug handler chain. This can never fail. */
3691 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3692 object_unparent(OBJECT(dev
));
3695 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3697 MachineState
*ms
= MACHINE(hotplug_dev
);
3698 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3699 CPUCore
*cc
= CPU_CORE(dev
);
3700 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3702 if (smc
->pre_2_10_has_unused_icps
) {
3703 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3706 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3707 CPUState
*cs
= CPU(sc
->threads
[i
]);
3709 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3714 core_slot
->cpu
= NULL
;
3715 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3719 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3722 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3725 CPUCore
*cc
= CPU_CORE(dev
);
3727 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3728 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3733 error_setg(errp
, "Boot CPU core may not be unplugged");
3737 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3738 spapr_vcpu_id(spapr
, cc
->core_id
));
3741 spapr_drc_detach(drc
);
3743 spapr_hotplug_req_remove_by_index(drc
);
3746 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3747 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3749 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3750 CPUState
*cs
= CPU(core
->threads
[0]);
3751 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3752 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3753 int id
= spapr_get_vcpu_id(cpu
);
3757 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3758 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3761 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3763 *fdt_start_offset
= offset
;
3767 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3770 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3771 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3772 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3773 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3774 CPUCore
*cc
= CPU_CORE(dev
);
3777 Error
*local_err
= NULL
;
3778 CPUArchId
*core_slot
;
3780 bool hotplugged
= spapr_drc_hotplugged(dev
);
3783 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3785 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3789 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3790 spapr_vcpu_id(spapr
, cc
->core_id
));
3792 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3795 spapr_drc_attach(drc
, dev
, &local_err
);
3797 error_propagate(errp
, local_err
);
3803 * Send hotplug notification interrupt to the guest only
3804 * in case of hotplugged CPUs.
3806 spapr_hotplug_req_add_by_index(drc
);
3808 spapr_drc_reset(drc
);
3812 core_slot
->cpu
= OBJECT(dev
);
3814 if (smc
->pre_2_10_has_unused_icps
) {
3815 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3816 cs
= CPU(core
->threads
[i
]);
3817 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3822 * Set compatibility mode to match the boot CPU, which was either set
3823 * by the machine reset code or by CAS.
3826 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3827 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3830 error_propagate(errp
, local_err
);
3837 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3840 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3841 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3842 Error
*local_err
= NULL
;
3843 CPUCore
*cc
= CPU_CORE(dev
);
3844 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3845 const char *type
= object_get_typename(OBJECT(dev
));
3846 CPUArchId
*core_slot
;
3848 unsigned int smp_threads
= machine
->smp
.threads
;
3850 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3851 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3855 if (strcmp(base_core_type
, type
)) {
3856 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3860 if (cc
->core_id
% smp_threads
) {
3861 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3866 * In general we should have homogeneous threads-per-core, but old
3867 * (pre hotplug support) machine types allow the last core to have
3868 * reduced threads as a compatibility hack for when we allowed
3869 * total vcpus not a multiple of threads-per-core.
3871 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3872 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3873 cc
->nr_threads
, smp_threads
);
3877 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3879 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3883 if (core_slot
->cpu
) {
3884 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3888 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3891 error_propagate(errp
, local_err
);
3894 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3895 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3897 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3900 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3901 if (intc_phandle
<= 0) {
3905 if (spapr_dt_phb(sphb
, intc_phandle
, fdt
, spapr
->irq
->nr_msis
,
3906 fdt_start_offset
)) {
3907 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3911 /* generally SLOF creates these, for hotplug it's up to QEMU */
3912 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3917 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3920 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3921 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3922 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3923 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3925 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3926 error_setg(errp
, "PHB hotplug not supported for this machine");
3930 if (sphb
->index
== (uint32_t)-1) {
3931 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3936 * This will check that sphb->index doesn't exceed the maximum number of
3937 * PHBs for the current machine type.
3939 smc
->phb_placement(spapr
, sphb
->index
,
3940 &sphb
->buid
, &sphb
->io_win_addr
,
3941 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3942 windows_supported
, sphb
->dma_liobn
,
3943 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3947 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3950 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3951 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3952 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3954 bool hotplugged
= spapr_drc_hotplugged(dev
);
3955 Error
*local_err
= NULL
;
3957 if (!smc
->dr_phb_enabled
) {
3961 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3962 /* hotplug hooks should check it's enabled before getting this far */
3965 spapr_drc_attach(drc
, DEVICE(dev
), &local_err
);
3967 error_propagate(errp
, local_err
);
3972 spapr_hotplug_req_add_by_index(drc
);
3974 spapr_drc_reset(drc
);
3978 void spapr_phb_release(DeviceState
*dev
)
3980 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3982 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3983 object_unparent(OBJECT(dev
));
3986 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3988 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3991 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
3992 DeviceState
*dev
, Error
**errp
)
3994 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3997 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4000 if (!spapr_drc_unplug_requested(drc
)) {
4001 spapr_drc_detach(drc
);
4002 spapr_hotplug_req_remove_by_index(drc
);
4006 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4009 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4010 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4012 if (spapr
->tpm_proxy
!= NULL
) {
4013 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4017 spapr
->tpm_proxy
= tpm_proxy
;
4020 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4022 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4024 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4025 object_unparent(OBJECT(dev
));
4026 spapr
->tpm_proxy
= NULL
;
4029 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4030 DeviceState
*dev
, Error
**errp
)
4032 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4033 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4034 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4035 spapr_core_plug(hotplug_dev
, dev
, errp
);
4036 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4037 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4038 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4039 spapr_tpm_proxy_plug(hotplug_dev
, dev
, errp
);
4043 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4044 DeviceState
*dev
, Error
**errp
)
4046 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4047 spapr_memory_unplug(hotplug_dev
, dev
);
4048 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4049 spapr_core_unplug(hotplug_dev
, dev
);
4050 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4051 spapr_phb_unplug(hotplug_dev
, dev
);
4052 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4053 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4057 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4058 DeviceState
*dev
, Error
**errp
)
4060 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4061 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4062 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4064 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4065 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4066 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4068 /* NOTE: this means there is a window after guest reset, prior to
4069 * CAS negotiation, where unplug requests will fail due to the
4070 * capability not being detected yet. This is a bit different than
4071 * the case with PCI unplug, where the events will be queued and
4072 * eventually handled by the guest after boot
4074 error_setg(errp
, "Memory hot unplug not supported for this guest");
4076 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4077 if (!mc
->has_hotpluggable_cpus
) {
4078 error_setg(errp
, "CPU hot unplug not supported on this machine");
4081 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4082 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4083 if (!smc
->dr_phb_enabled
) {
4084 error_setg(errp
, "PHB hot unplug not supported on this machine");
4087 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4088 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4089 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4093 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4094 DeviceState
*dev
, Error
**errp
)
4096 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4097 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4098 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4099 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4100 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4101 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4105 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4108 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4109 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4110 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4111 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4112 return HOTPLUG_HANDLER(machine
);
4114 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4115 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4116 PCIBus
*root
= pci_device_root_bus(pcidev
);
4117 SpaprPhbState
*phb
=
4118 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4119 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4122 return HOTPLUG_HANDLER(phb
);
4128 static CpuInstanceProperties
4129 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4131 CPUArchId
*core_slot
;
4132 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4134 /* make sure possible_cpu are intialized */
4135 mc
->possible_cpu_arch_ids(machine
);
4136 /* get CPU core slot containing thread that matches cpu_index */
4137 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4139 return core_slot
->props
;
4142 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4144 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4147 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4150 unsigned int smp_threads
= machine
->smp
.threads
;
4151 unsigned int smp_cpus
= machine
->smp
.cpus
;
4152 const char *core_type
;
4153 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4154 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4156 if (!mc
->has_hotpluggable_cpus
) {
4157 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4159 if (machine
->possible_cpus
) {
4160 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4161 return machine
->possible_cpus
;
4164 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4166 error_report("Unable to find sPAPR CPU Core definition");
4170 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4171 sizeof(CPUArchId
) * spapr_max_cores
);
4172 machine
->possible_cpus
->len
= spapr_max_cores
;
4173 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4174 int core_id
= i
* smp_threads
;
4176 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4177 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4178 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4179 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4180 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4182 return machine
->possible_cpus
;
4185 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4186 uint64_t *buid
, hwaddr
*pio
,
4187 hwaddr
*mmio32
, hwaddr
*mmio64
,
4188 unsigned n_dma
, uint32_t *liobns
,
4189 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4192 * New-style PHB window placement.
4194 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4195 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4198 * Some guest kernels can't work with MMIO windows above 1<<46
4199 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4201 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4202 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4203 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4204 * 1TiB 64-bit MMIO windows for each PHB.
4206 const uint64_t base_buid
= 0x800000020000000ULL
;
4209 /* Sanity check natural alignments */
4210 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4211 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4212 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4213 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4214 /* Sanity check bounds */
4215 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4216 SPAPR_PCI_MEM32_WIN_SIZE
);
4217 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4218 SPAPR_PCI_MEM64_WIN_SIZE
);
4220 if (index
>= SPAPR_MAX_PHBS
) {
4221 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4222 SPAPR_MAX_PHBS
- 1);
4226 *buid
= base_buid
+ index
;
4227 for (i
= 0; i
< n_dma
; ++i
) {
4228 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4231 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4232 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4233 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4235 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4236 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4239 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4241 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4243 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4246 static void spapr_ics_resend(XICSFabric
*dev
)
4248 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4250 ics_resend(spapr
->ics
);
4253 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4255 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4257 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4260 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4263 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4265 spapr
->irq
->print_info(spapr
, mon
);
4266 monitor_printf(mon
, "irqchip: %s\n",
4267 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4270 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4272 return cpu
->vcpu_id
;
4275 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4277 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4278 MachineState
*ms
= MACHINE(spapr
);
4281 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4283 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4284 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4285 error_append_hint(errp
, "Adjust the number of cpus to %d "
4286 "or try to raise the number of threads per core\n",
4287 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4291 cpu
->vcpu_id
= vcpu_id
;
4294 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4299 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4301 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4309 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4311 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4313 /* These are only called by TCG, KVM maintains dispatch state */
4315 spapr_cpu
->prod
= false;
4316 if (spapr_cpu
->vpa_addr
) {
4317 CPUState
*cs
= CPU(cpu
);
4320 dispatch
= ldl_be_phys(cs
->as
,
4321 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4323 if ((dispatch
& 1) != 0) {
4324 qemu_log_mask(LOG_GUEST_ERROR
,
4325 "VPA: incorrect dispatch counter value for "
4326 "dispatched partition %u, correcting.\n", dispatch
);
4330 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4334 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4336 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4338 if (spapr_cpu
->vpa_addr
) {
4339 CPUState
*cs
= CPU(cpu
);
4342 dispatch
= ldl_be_phys(cs
->as
,
4343 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4345 if ((dispatch
& 1) != 1) {
4346 qemu_log_mask(LOG_GUEST_ERROR
,
4347 "VPA: incorrect dispatch counter value for "
4348 "preempted partition %u, correcting.\n", dispatch
);
4352 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4356 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4358 MachineClass
*mc
= MACHINE_CLASS(oc
);
4359 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4360 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4361 NMIClass
*nc
= NMI_CLASS(oc
);
4362 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4363 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4364 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4365 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4367 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4368 mc
->ignore_boot_device_suffixes
= true;
4371 * We set up the default / latest behaviour here. The class_init
4372 * functions for the specific versioned machine types can override
4373 * these details for backwards compatibility
4375 mc
->init
= spapr_machine_init
;
4376 mc
->reset
= spapr_machine_reset
;
4377 mc
->block_default_type
= IF_SCSI
;
4378 mc
->max_cpus
= 1024;
4379 mc
->no_parallel
= 1;
4380 mc
->default_boot_order
= "";
4381 mc
->default_ram_size
= 512 * MiB
;
4382 mc
->default_display
= "std";
4383 mc
->kvm_type
= spapr_kvm_type
;
4384 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4385 mc
->pci_allow_0_address
= true;
4386 assert(!mc
->get_hotplug_handler
);
4387 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4388 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4389 hc
->plug
= spapr_machine_device_plug
;
4390 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4391 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4392 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4393 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4394 hc
->unplug
= spapr_machine_device_unplug
;
4396 smc
->dr_lmb_enabled
= true;
4397 smc
->update_dt_enabled
= true;
4398 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4399 mc
->has_hotpluggable_cpus
= true;
4400 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4401 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4402 nc
->nmi_monitor_handler
= spapr_nmi
;
4403 smc
->phb_placement
= spapr_phb_placement
;
4404 vhc
->hypercall
= emulate_spapr_hypercall
;
4405 vhc
->hpt_mask
= spapr_hpt_mask
;
4406 vhc
->map_hptes
= spapr_map_hptes
;
4407 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4408 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4409 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4410 vhc
->get_pate
= spapr_get_pate
;
4411 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4412 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4413 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4414 xic
->ics_get
= spapr_ics_get
;
4415 xic
->ics_resend
= spapr_ics_resend
;
4416 xic
->icp_get
= spapr_icp_get
;
4417 ispc
->print_info
= spapr_pic_print_info
;
4418 /* Force NUMA node memory size to be a multiple of
4419 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4420 * in which LMBs are represented and hot-added
4422 mc
->numa_mem_align_shift
= 28;
4423 mc
->numa_mem_supported
= true;
4425 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4426 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4427 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4428 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4429 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4430 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4431 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4432 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4433 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4434 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4435 spapr_caps_add_properties(smc
, &error_abort
);
4436 smc
->irq
= &spapr_irq_dual
;
4437 smc
->dr_phb_enabled
= true;
4438 smc
->linux_pci_probe
= true;
4441 static const TypeInfo spapr_machine_info
= {
4442 .name
= TYPE_SPAPR_MACHINE
,
4443 .parent
= TYPE_MACHINE
,
4445 .instance_size
= sizeof(SpaprMachineState
),
4446 .instance_init
= spapr_instance_init
,
4447 .instance_finalize
= spapr_machine_finalizefn
,
4448 .class_size
= sizeof(SpaprMachineClass
),
4449 .class_init
= spapr_machine_class_init
,
4450 .interfaces
= (InterfaceInfo
[]) {
4451 { TYPE_FW_PATH_PROVIDER
},
4453 { TYPE_HOTPLUG_HANDLER
},
4454 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4455 { TYPE_XICS_FABRIC
},
4456 { TYPE_INTERRUPT_STATS_PROVIDER
},
4461 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4462 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4465 MachineClass *mc = MACHINE_CLASS(oc); \
4466 spapr_machine_##suffix##_class_options(mc); \
4468 mc->alias = "pseries"; \
4469 mc->is_default = 1; \
4472 static const TypeInfo spapr_machine_##suffix##_info = { \
4473 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4474 .parent = TYPE_SPAPR_MACHINE, \
4475 .class_init = spapr_machine_##suffix##_class_init, \
4477 static void spapr_machine_register_##suffix(void) \
4479 type_register(&spapr_machine_##suffix##_info); \
4481 type_init(spapr_machine_register_##suffix)
4486 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4488 /* Defaults for the latest behaviour inherited from the base class */
4491 DEFINE_SPAPR_MACHINE(4_2
, "4.2", true);
4496 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4498 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4499 static GlobalProperty compat
[] = {
4500 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4501 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4504 spapr_machine_4_2_class_options(mc
);
4505 smc
->linux_pci_probe
= false;
4506 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4507 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4510 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4515 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4516 uint64_t *buid
, hwaddr
*pio
,
4517 hwaddr
*mmio32
, hwaddr
*mmio64
,
4518 unsigned n_dma
, uint32_t *liobns
,
4519 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4521 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4522 nv2gpa
, nv2atsd
, errp
);
4527 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4529 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4531 spapr_machine_4_1_class_options(mc
);
4532 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4533 smc
->phb_placement
= phb_placement_4_0
;
4534 smc
->irq
= &spapr_irq_xics
;
4535 smc
->pre_4_1_migration
= true;
4538 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4543 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4545 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4547 spapr_machine_4_0_class_options(mc
);
4548 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4550 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4551 smc
->update_dt_enabled
= false;
4552 smc
->dr_phb_enabled
= false;
4553 smc
->broken_host_serial_model
= true;
4554 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4555 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4556 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4557 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4560 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4566 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4568 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4570 spapr_machine_3_1_class_options(mc
);
4571 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4573 smc
->legacy_irq_allocation
= true;
4574 smc
->irq
= &spapr_irq_xics_legacy
;
4577 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4582 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4584 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4585 static GlobalProperty compat
[] = {
4586 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4587 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4590 spapr_machine_3_0_class_options(mc
);
4591 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4592 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4594 /* We depend on kvm_enabled() to choose a default value for the
4595 * hpt-max-page-size capability. Of course we can't do it here
4596 * because this is too early and the HW accelerator isn't initialzed
4597 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4599 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4602 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4604 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4606 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4608 spapr_machine_2_12_class_options(mc
);
4609 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4610 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4611 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4614 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4620 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4622 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4624 spapr_machine_2_12_class_options(mc
);
4625 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4626 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4629 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4635 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4637 spapr_machine_2_11_class_options(mc
);
4638 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4641 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4647 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4649 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4650 static GlobalProperty compat
[] = {
4651 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4654 spapr_machine_2_10_class_options(mc
);
4655 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4656 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4657 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4658 smc
->pre_2_10_has_unused_icps
= true;
4659 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4662 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4668 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4670 static GlobalProperty compat
[] = {
4671 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4674 spapr_machine_2_9_class_options(mc
);
4675 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4676 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4677 mc
->numa_mem_align_shift
= 23;
4680 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4686 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4687 uint64_t *buid
, hwaddr
*pio
,
4688 hwaddr
*mmio32
, hwaddr
*mmio64
,
4689 unsigned n_dma
, uint32_t *liobns
,
4690 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4692 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4693 const uint64_t base_buid
= 0x800000020000000ULL
;
4694 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4695 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4696 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4697 const uint32_t max_index
= 255;
4698 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4700 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4701 hwaddr phb0_base
, phb_base
;
4704 /* Do we have device memory? */
4705 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4706 /* Can't just use maxram_size, because there may be an
4707 * alignment gap between normal and device memory regions
4709 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4710 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4713 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4715 if (index
> max_index
) {
4716 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4721 *buid
= base_buid
+ index
;
4722 for (i
= 0; i
< n_dma
; ++i
) {
4723 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4726 phb_base
= phb0_base
+ index
* phb_spacing
;
4727 *pio
= phb_base
+ pio_offset
;
4728 *mmio32
= phb_base
+ mmio_offset
;
4730 * We don't set the 64-bit MMIO window, relying on the PHB's
4731 * fallback behaviour of automatically splitting a large "32-bit"
4732 * window into contiguous 32-bit and 64-bit windows
4739 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4741 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4742 static GlobalProperty compat
[] = {
4743 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4744 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4745 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4746 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4749 spapr_machine_2_8_class_options(mc
);
4750 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4751 mc
->default_machine_opts
= "modern-hotplug-events=off";
4752 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4753 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4754 smc
->phb_placement
= phb_placement_2_7
;
4757 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4763 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4765 static GlobalProperty compat
[] = {
4766 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4769 spapr_machine_2_7_class_options(mc
);
4770 mc
->has_hotpluggable_cpus
= false;
4771 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4772 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4775 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4781 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4783 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4784 static GlobalProperty compat
[] = {
4785 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4788 spapr_machine_2_6_class_options(mc
);
4789 smc
->use_ohci_by_default
= true;
4790 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4791 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4794 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4800 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4802 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4804 spapr_machine_2_5_class_options(mc
);
4805 smc
->dr_lmb_enabled
= false;
4806 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4809 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4815 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4817 static GlobalProperty compat
[] = {
4818 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4820 spapr_machine_2_4_class_options(mc
);
4821 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4822 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4824 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4830 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4832 static GlobalProperty compat
[] = {
4833 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4836 spapr_machine_2_3_class_options(mc
);
4837 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4838 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4839 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4841 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4847 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4849 spapr_machine_2_2_class_options(mc
);
4850 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4852 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4854 static void spapr_machine_register_types(void)
4856 type_register_static(&spapr_machine_info
);
4859 type_init(spapr_machine_register_types
)