2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/acpi/cpu_hotplug.h"
57 #include "hw/cpu/icc_bus.h"
58 #include "hw/boards.h"
59 #include "hw/pci/pci_host.h"
60 #include "acpi-build.h"
62 /* debug PC/ISA interrupts */
66 #define DPRINTF(fmt, ...) \
67 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
69 #define DPRINTF(fmt, ...)
72 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
73 #define ACPI_DATA_SIZE 0x10000
74 #define BIOS_CFG_IOPORT 0x510
75 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
76 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
77 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
78 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
79 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
81 #define E820_NR_ENTRIES 16
87 } QEMU_PACKED
__attribute((__aligned__(4)));
91 struct e820_entry entry
[E820_NR_ENTRIES
];
92 } QEMU_PACKED
__attribute((__aligned__(4)));
94 static struct e820_table e820_reserve
;
95 static struct e820_entry
*e820_table
;
96 static unsigned e820_entries
;
97 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
99 void gsi_handler(void *opaque
, int n
, int level
)
101 GSIState
*s
= opaque
;
103 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
104 if (n
< ISA_NUM_IRQS
) {
105 qemu_set_irq(s
->i8259_irq
[n
], level
);
107 qemu_set_irq(s
->ioapic_irq
[n
], level
);
110 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
115 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
117 return 0xffffffffffffffffULL
;
120 /* MSDOS compatibility mode FPU exception support */
121 static qemu_irq ferr_irq
;
123 void pc_register_ferr_irq(qemu_irq irq
)
128 /* XXX: add IGNNE support */
129 void cpu_set_ferr(CPUX86State
*s
)
131 qemu_irq_raise(ferr_irq
);
134 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
137 qemu_irq_lower(ferr_irq
);
140 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
142 return 0xffffffffffffffffULL
;
146 uint64_t cpu_get_tsc(CPUX86State
*env
)
148 return cpu_get_ticks();
153 static cpu_set_smm_t smm_set
;
154 static void *smm_arg
;
156 void cpu_smm_register(cpu_set_smm_t callback
, void *arg
)
158 assert(smm_set
== NULL
);
159 assert(smm_arg
== NULL
);
164 void cpu_smm_update(CPUX86State
*env
)
166 if (smm_set
&& smm_arg
&& CPU(x86_env_get_cpu(env
)) == first_cpu
) {
167 smm_set(!!(env
->hflags
& HF_SMM_MASK
), smm_arg
);
173 int cpu_get_pic_interrupt(CPUX86State
*env
)
175 X86CPU
*cpu
= x86_env_get_cpu(env
);
178 intno
= apic_get_interrupt(cpu
->apic_state
);
182 /* read the irq from the PIC */
183 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
187 intno
= pic_read_irq(isa_pic
);
191 static void pic_irq_request(void *opaque
, int irq
, int level
)
193 CPUState
*cs
= first_cpu
;
194 X86CPU
*cpu
= X86_CPU(cs
);
196 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
197 if (cpu
->apic_state
) {
200 if (apic_accept_pic_intr(cpu
->apic_state
)) {
201 apic_deliver_pic_intr(cpu
->apic_state
, level
);
206 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
208 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
213 /* PC cmos mappings */
215 #define REG_EQUIPMENT_BYTE 0x14
217 static int cmos_get_fd_drive_type(FDriveType fd0
)
223 /* 1.44 Mb 3"5 drive */
227 /* 2.88 Mb 3"5 drive */
231 /* 1.2 Mb 5"5 drive */
234 case FDRIVE_DRV_NONE
:
242 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
243 int16_t cylinders
, int8_t heads
, int8_t sectors
)
245 rtc_set_memory(s
, type_ofs
, 47);
246 rtc_set_memory(s
, info_ofs
, cylinders
);
247 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
248 rtc_set_memory(s
, info_ofs
+ 2, heads
);
249 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
250 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
251 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
252 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
253 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
254 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
257 /* convert boot_device letter to something recognizable by the bios */
258 static int boot_device2nibble(char boot_device
)
260 switch(boot_device
) {
263 return 0x01; /* floppy boot */
265 return 0x02; /* hard drive boot */
267 return 0x03; /* CD-ROM boot */
269 return 0x04; /* Network boot */
274 static int set_boot_dev(ISADevice
*s
, const char *boot_device
)
276 #define PC_MAX_BOOT_DEVICES 3
277 int nbds
, bds
[3] = { 0, };
280 nbds
= strlen(boot_device
);
281 if (nbds
> PC_MAX_BOOT_DEVICES
) {
282 error_report("Too many boot devices for PC");
285 for (i
= 0; i
< nbds
; i
++) {
286 bds
[i
] = boot_device2nibble(boot_device
[i
]);
288 error_report("Invalid boot device for PC: '%c'",
293 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
294 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
298 static int pc_boot_set(void *opaque
, const char *boot_device
)
300 return set_boot_dev(opaque
, boot_device
);
303 typedef struct pc_cmos_init_late_arg
{
304 ISADevice
*rtc_state
;
306 } pc_cmos_init_late_arg
;
308 static void pc_cmos_init_late(void *opaque
)
310 pc_cmos_init_late_arg
*arg
= opaque
;
311 ISADevice
*s
= arg
->rtc_state
;
313 int8_t heads
, sectors
;
318 if (ide_get_geometry(arg
->idebus
[0], 0,
319 &cylinders
, &heads
, §ors
) >= 0) {
320 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
323 if (ide_get_geometry(arg
->idebus
[0], 1,
324 &cylinders
, &heads
, §ors
) >= 0) {
325 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
328 rtc_set_memory(s
, 0x12, val
);
331 for (i
= 0; i
< 4; i
++) {
332 /* NOTE: ide_get_geometry() returns the physical
333 geometry. It is always such that: 1 <= sects <= 63, 1
334 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
335 geometry can be different if a translation is done. */
336 if (ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
337 &cylinders
, &heads
, §ors
) >= 0) {
338 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
339 assert((trans
& ~3) == 0);
340 val
|= trans
<< (i
* 2);
343 rtc_set_memory(s
, 0x39, val
);
345 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
348 typedef struct RTCCPUHotplugArg
{
349 Notifier cpu_added_notifier
;
350 ISADevice
*rtc_state
;
353 static void rtc_notify_cpu_added(Notifier
*notifier
, void *data
)
355 RTCCPUHotplugArg
*arg
= container_of(notifier
, RTCCPUHotplugArg
,
357 ISADevice
*s
= arg
->rtc_state
;
359 /* increment the number of CPUs */
360 rtc_set_memory(s
, 0x5f, rtc_get_memory(s
, 0x5f) + 1);
363 void pc_cmos_init(ram_addr_t ram_size
, ram_addr_t above_4g_mem_size
,
364 const char *boot_device
,
365 ISADevice
*floppy
, BusState
*idebus0
, BusState
*idebus1
,
369 FDriveType fd_type
[2] = { FDRIVE_DRV_NONE
, FDRIVE_DRV_NONE
};
370 static pc_cmos_init_late_arg arg
;
371 static RTCCPUHotplugArg cpu_hotplug_cb
;
373 /* various important CMOS locations needed by PC/Bochs bios */
376 /* base memory (first MiB) */
377 val
= MIN(ram_size
/ 1024, 640);
378 rtc_set_memory(s
, 0x15, val
);
379 rtc_set_memory(s
, 0x16, val
>> 8);
380 /* extended memory (next 64MiB) */
381 if (ram_size
> 1024 * 1024) {
382 val
= (ram_size
- 1024 * 1024) / 1024;
388 rtc_set_memory(s
, 0x17, val
);
389 rtc_set_memory(s
, 0x18, val
>> 8);
390 rtc_set_memory(s
, 0x30, val
);
391 rtc_set_memory(s
, 0x31, val
>> 8);
392 /* memory between 16MiB and 4GiB */
393 if (ram_size
> 16 * 1024 * 1024) {
394 val
= (ram_size
- 16 * 1024 * 1024) / 65536;
400 rtc_set_memory(s
, 0x34, val
);
401 rtc_set_memory(s
, 0x35, val
>> 8);
402 /* memory above 4GiB */
403 val
= above_4g_mem_size
/ 65536;
404 rtc_set_memory(s
, 0x5b, val
);
405 rtc_set_memory(s
, 0x5c, val
>> 8);
406 rtc_set_memory(s
, 0x5d, val
>> 16);
408 /* set the number of CPU */
409 rtc_set_memory(s
, 0x5f, smp_cpus
- 1);
410 /* init CPU hotplug notifier */
411 cpu_hotplug_cb
.rtc_state
= s
;
412 cpu_hotplug_cb
.cpu_added_notifier
.notify
= rtc_notify_cpu_added
;
413 qemu_register_cpu_added_notifier(&cpu_hotplug_cb
.cpu_added_notifier
);
415 if (set_boot_dev(s
, boot_device
)) {
421 for (i
= 0; i
< 2; i
++) {
422 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
425 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
426 cmos_get_fd_drive_type(fd_type
[1]);
427 rtc_set_memory(s
, 0x10, val
);
431 if (fd_type
[0] < FDRIVE_DRV_NONE
) {
434 if (fd_type
[1] < FDRIVE_DRV_NONE
) {
441 val
|= 0x01; /* 1 drive, ready for boot */
444 val
|= 0x41; /* 2 drives, ready for boot */
447 val
|= 0x02; /* FPU is there */
448 val
|= 0x04; /* PS/2 mouse installed */
449 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
453 arg
.idebus
[0] = idebus0
;
454 arg
.idebus
[1] = idebus1
;
455 qemu_register_reset(pc_cmos_init_late
, &arg
);
458 #define TYPE_PORT92 "port92"
459 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
461 /* port 92 stuff: could be split off */
462 typedef struct Port92State
{
463 ISADevice parent_obj
;
470 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
473 Port92State
*s
= opaque
;
475 DPRINTF("port92: write 0x%02x\n", val
);
477 qemu_set_irq(*s
->a20_out
, (val
>> 1) & 1);
479 qemu_system_reset_request();
483 static uint64_t port92_read(void *opaque
, hwaddr addr
,
486 Port92State
*s
= opaque
;
490 DPRINTF("port92: read 0x%02x\n", ret
);
494 static void port92_init(ISADevice
*dev
, qemu_irq
*a20_out
)
496 Port92State
*s
= PORT92(dev
);
498 s
->a20_out
= a20_out
;
501 static const VMStateDescription vmstate_port92_isa
= {
504 .minimum_version_id
= 1,
505 .minimum_version_id_old
= 1,
506 .fields
= (VMStateField
[]) {
507 VMSTATE_UINT8(outport
, Port92State
),
508 VMSTATE_END_OF_LIST()
512 static void port92_reset(DeviceState
*d
)
514 Port92State
*s
= PORT92(d
);
519 static const MemoryRegionOps port92_ops
= {
521 .write
= port92_write
,
523 .min_access_size
= 1,
524 .max_access_size
= 1,
526 .endianness
= DEVICE_LITTLE_ENDIAN
,
529 static void port92_initfn(Object
*obj
)
531 Port92State
*s
= PORT92(obj
);
533 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
538 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
540 ISADevice
*isadev
= ISA_DEVICE(dev
);
541 Port92State
*s
= PORT92(dev
);
543 isa_register_ioport(isadev
, &s
->io
, 0x92);
546 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
548 DeviceClass
*dc
= DEVICE_CLASS(klass
);
550 dc
->realize
= port92_realizefn
;
551 dc
->reset
= port92_reset
;
552 dc
->vmsd
= &vmstate_port92_isa
;
554 * Reason: unlike ordinary ISA devices, this one needs additional
555 * wiring: its A20 output line needs to be wired up by
558 dc
->cannot_instantiate_with_device_add_yet
= true;
561 static const TypeInfo port92_info
= {
563 .parent
= TYPE_ISA_DEVICE
,
564 .instance_size
= sizeof(Port92State
),
565 .instance_init
= port92_initfn
,
566 .class_init
= port92_class_initfn
,
569 static void port92_register_types(void)
571 type_register_static(&port92_info
);
574 type_init(port92_register_types
)
576 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
578 X86CPU
*cpu
= opaque
;
580 /* XXX: send to all CPUs ? */
581 /* XXX: add logic to handle multiple A20 line sources */
582 x86_cpu_set_a20(cpu
, level
);
585 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
587 int index
= le32_to_cpu(e820_reserve
.count
);
588 struct e820_entry
*entry
;
590 if (type
!= E820_RAM
) {
591 /* old FW_CFG_E820_TABLE entry -- reservations only */
592 if (index
>= E820_NR_ENTRIES
) {
595 entry
= &e820_reserve
.entry
[index
++];
597 entry
->address
= cpu_to_le64(address
);
598 entry
->length
= cpu_to_le64(length
);
599 entry
->type
= cpu_to_le32(type
);
601 e820_reserve
.count
= cpu_to_le32(index
);
604 /* new "etc/e820" file -- include ram too */
605 e820_table
= g_realloc(e820_table
,
606 sizeof(struct e820_entry
) * (e820_entries
+1));
607 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
608 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
609 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
615 int e820_get_num_entries(void)
620 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
622 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
623 *address
= le64_to_cpu(e820_table
[idx
].address
);
624 *length
= le64_to_cpu(e820_table
[idx
].length
);
630 /* Calculates the limit to CPU APIC ID values
632 * This function returns the limit for the APIC ID value, so that all
633 * CPU APIC IDs are < pc_apic_id_limit().
635 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
637 static unsigned int pc_apic_id_limit(unsigned int max_cpus
)
639 return x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
642 static FWCfgState
*bochs_bios_init(void)
645 uint8_t *smbios_table
;
647 uint64_t *numa_fw_cfg
;
649 unsigned int apic_id_limit
= pc_apic_id_limit(max_cpus
);
651 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
652 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
654 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
655 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
656 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
657 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
660 * So, this means we must not use max_cpus, here, but the maximum possible
661 * APIC ID value, plus one.
663 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
664 * the APIC ID, not the "CPU index"
666 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)apic_id_limit
);
667 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
668 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
669 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
670 acpi_tables
, acpi_tables_len
);
671 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
673 smbios_table
= smbios_get_table_legacy(&smbios_len
);
675 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
676 smbios_table
, smbios_len
);
677 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
678 &e820_reserve
, sizeof(e820_reserve
));
679 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
680 sizeof(struct e820_entry
) * e820_entries
);
682 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
683 /* allocate memory for the NUMA channel: one (64bit) word for the number
684 * of nodes, one word for each VCPU->node and one word for each node to
685 * hold the amount of memory.
687 numa_fw_cfg
= g_new0(uint64_t, 1 + apic_id_limit
+ nb_numa_nodes
);
688 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
689 for (i
= 0; i
< max_cpus
; i
++) {
690 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
691 assert(apic_id
< apic_id_limit
);
692 for (j
= 0; j
< nb_numa_nodes
; j
++) {
693 if (test_bit(i
, node_cpumask
[j
])) {
694 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(j
);
699 for (i
= 0; i
< nb_numa_nodes
; i
++) {
700 numa_fw_cfg
[apic_id_limit
+ 1 + i
] = cpu_to_le64(node_mem
[i
]);
702 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
703 (1 + apic_id_limit
+ nb_numa_nodes
) *
704 sizeof(*numa_fw_cfg
));
709 static long get_file_size(FILE *f
)
713 /* XXX: on Unix systems, using fstat() probably makes more sense */
716 fseek(f
, 0, SEEK_END
);
718 fseek(f
, where
, SEEK_SET
);
723 static void load_linux(FWCfgState
*fw_cfg
,
724 const char *kernel_filename
,
725 const char *initrd_filename
,
726 const char *kernel_cmdline
,
730 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
732 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
733 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
737 /* Align to 16 bytes as a paranoia measure */
738 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
740 /* load the kernel header */
741 f
= fopen(kernel_filename
, "rb");
742 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
743 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
744 MIN(ARRAY_SIZE(header
), kernel_size
)) {
745 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
746 kernel_filename
, strerror(errno
));
750 /* kernel protocol version */
752 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
754 if (ldl_p(header
+0x202) == 0x53726448) {
755 protocol
= lduw_p(header
+0x206);
757 /* This looks like a multiboot kernel. If it is, let's stop
758 treating it like a Linux kernel. */
759 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
760 kernel_cmdline
, kernel_size
, header
)) {
766 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
769 cmdline_addr
= 0x9a000 - cmdline_size
;
771 } else if (protocol
< 0x202) {
772 /* High but ancient kernel */
774 cmdline_addr
= 0x9a000 - cmdline_size
;
775 prot_addr
= 0x100000;
777 /* High and recent kernel */
779 cmdline_addr
= 0x20000;
780 prot_addr
= 0x100000;
785 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
786 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
787 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
793 /* highest address for loading the initrd */
794 if (protocol
>= 0x203) {
795 initrd_max
= ldl_p(header
+0x22c);
797 initrd_max
= 0x37ffffff;
800 if (initrd_max
>= max_ram_size
-ACPI_DATA_SIZE
)
801 initrd_max
= max_ram_size
-ACPI_DATA_SIZE
-1;
803 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
804 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
805 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
807 if (protocol
>= 0x202) {
808 stl_p(header
+0x228, cmdline_addr
);
810 stw_p(header
+0x20, 0xA33F);
811 stw_p(header
+0x22, cmdline_addr
-real_addr
);
814 /* handle vga= parameter */
815 vmode
= strstr(kernel_cmdline
, "vga=");
817 unsigned int video_mode
;
820 if (!strncmp(vmode
, "normal", 6)) {
822 } else if (!strncmp(vmode
, "ext", 3)) {
824 } else if (!strncmp(vmode
, "ask", 3)) {
827 video_mode
= strtol(vmode
, NULL
, 0);
829 stw_p(header
+0x1fa, video_mode
);
833 /* High nybble = B reserved for QEMU; low nybble is revision number.
834 If this code is substantially changed, you may want to consider
835 incrementing the revision. */
836 if (protocol
>= 0x200) {
837 header
[0x210] = 0xB0;
840 if (protocol
>= 0x201) {
841 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
842 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
846 if (initrd_filename
) {
847 if (protocol
< 0x200) {
848 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
852 initrd_size
= get_image_size(initrd_filename
);
853 if (initrd_size
< 0) {
854 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
855 initrd_filename
, strerror(errno
));
859 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
861 initrd_data
= g_malloc(initrd_size
);
862 load_image(initrd_filename
, initrd_data
);
864 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
865 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
866 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
868 stl_p(header
+0x218, initrd_addr
);
869 stl_p(header
+0x21c, initrd_size
);
872 /* load kernel and setup */
873 setup_size
= header
[0x1f1];
874 if (setup_size
== 0) {
877 setup_size
= (setup_size
+1)*512;
878 kernel_size
-= setup_size
;
880 setup
= g_malloc(setup_size
);
881 kernel
= g_malloc(kernel_size
);
882 fseek(f
, 0, SEEK_SET
);
883 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
884 fprintf(stderr
, "fread() failed\n");
887 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
888 fprintf(stderr
, "fread() failed\n");
892 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
894 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
895 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
896 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
898 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
899 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
900 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
902 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
903 option_rom
[nb_option_roms
].bootindex
= 0;
907 #define NE2000_NB_MAX 6
909 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
911 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
913 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
914 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
916 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
918 static int nb_ne2k
= 0;
920 if (nb_ne2k
== NE2000_NB_MAX
)
922 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
923 ne2000_irq
[nb_ne2k
], nd
);
927 DeviceState
*cpu_get_current_apic(void)
930 X86CPU
*cpu
= X86_CPU(current_cpu
);
931 return cpu
->apic_state
;
937 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
939 X86CPU
*cpu
= opaque
;
942 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
946 static X86CPU
*pc_new_cpu(const char *cpu_model
, int64_t apic_id
,
947 DeviceState
*icc_bridge
, Error
**errp
)
950 Error
*local_err
= NULL
;
952 cpu
= cpu_x86_create(cpu_model
, icc_bridge
, &local_err
);
953 if (local_err
!= NULL
) {
954 error_propagate(errp
, local_err
);
958 object_property_set_int(OBJECT(cpu
), apic_id
, "apic-id", &local_err
);
959 object_property_set_bool(OBJECT(cpu
), true, "realized", &local_err
);
962 error_propagate(errp
, local_err
);
963 object_unref(OBJECT(cpu
));
969 static const char *current_cpu_model
;
971 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
973 DeviceState
*icc_bridge
;
974 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
977 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
981 if (cpu_exists(apic_id
)) {
982 error_setg(errp
, "Unable to add CPU: %" PRIi64
983 ", it already exists", id
);
987 if (id
>= max_cpus
) {
988 error_setg(errp
, "Unable to add CPU: %" PRIi64
989 ", max allowed: %d", id
, max_cpus
- 1);
993 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
994 error_setg(errp
, "Unable to add CPU: %" PRIi64
995 ", resulting APIC ID (%" PRIi64
") is too large",
1000 icc_bridge
= DEVICE(object_resolve_path_type("icc-bridge",
1001 TYPE_ICC_BRIDGE
, NULL
));
1002 pc_new_cpu(current_cpu_model
, apic_id
, icc_bridge
, errp
);
1005 void pc_cpus_init(const char *cpu_model
, DeviceState
*icc_bridge
)
1009 Error
*error
= NULL
;
1010 unsigned long apic_id_limit
;
1013 if (cpu_model
== NULL
) {
1014 #ifdef TARGET_X86_64
1015 cpu_model
= "qemu64";
1017 cpu_model
= "qemu32";
1020 current_cpu_model
= cpu_model
;
1022 apic_id_limit
= pc_apic_id_limit(max_cpus
);
1023 if (apic_id_limit
> ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1024 error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1029 for (i
= 0; i
< smp_cpus
; i
++) {
1030 cpu
= pc_new_cpu(cpu_model
, x86_cpu_apic_id_from_index(i
),
1031 icc_bridge
, &error
);
1033 error_report("%s", error_get_pretty(error
));
1039 /* map APIC MMIO area if CPU has APIC */
1040 if (cpu
&& cpu
->apic_state
) {
1041 /* XXX: what if the base changes? */
1042 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge
), 0,
1043 APIC_DEFAULT_ADDRESS
, 0x1000);
1047 /* pci-info ROM file. Little endian format */
1048 typedef struct PcRomPciInfo
{
1055 static void pc_fw_cfg_guest_info(PcGuestInfo
*guest_info
)
1059 bool ambiguous
= false;
1061 if (!guest_info
->has_pci_info
|| !guest_info
->fw_cfg
) {
1064 pci_info
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
1065 g_assert(!ambiguous
);
1070 info
= g_malloc(sizeof *info
);
1071 info
->w32_min
= cpu_to_le64(object_property_get_int(pci_info
,
1072 PCI_HOST_PROP_PCI_HOLE_START
, NULL
));
1073 info
->w32_max
= cpu_to_le64(object_property_get_int(pci_info
,
1074 PCI_HOST_PROP_PCI_HOLE_END
, NULL
));
1075 info
->w64_min
= cpu_to_le64(object_property_get_int(pci_info
,
1076 PCI_HOST_PROP_PCI_HOLE64_START
, NULL
));
1077 info
->w64_max
= cpu_to_le64(object_property_get_int(pci_info
,
1078 PCI_HOST_PROP_PCI_HOLE64_END
, NULL
));
1079 /* Pass PCI hole info to guest via a side channel.
1080 * Required so guest PCI enumeration does the right thing. */
1081 fw_cfg_add_file(guest_info
->fw_cfg
, "etc/pci-info", info
, sizeof *info
);
1084 typedef struct PcGuestInfoState
{
1086 Notifier machine_done
;
1090 void pc_guest_info_machine_done(Notifier
*notifier
, void *data
)
1092 PcGuestInfoState
*guest_info_state
= container_of(notifier
,
1095 pc_fw_cfg_guest_info(&guest_info_state
->info
);
1096 acpi_setup(&guest_info_state
->info
);
1099 PcGuestInfo
*pc_guest_info_init(ram_addr_t below_4g_mem_size
,
1100 ram_addr_t above_4g_mem_size
)
1102 PcGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1103 PcGuestInfo
*guest_info
= &guest_info_state
->info
;
1106 guest_info
->ram_size_below_4g
= below_4g_mem_size
;
1107 guest_info
->ram_size
= below_4g_mem_size
+ above_4g_mem_size
;
1108 guest_info
->apic_id_limit
= pc_apic_id_limit(max_cpus
);
1109 guest_info
->apic_xrupt_override
= kvm_allows_irq0_override();
1110 guest_info
->numa_nodes
= nb_numa_nodes
;
1111 guest_info
->node_mem
= g_memdup(node_mem
, guest_info
->numa_nodes
*
1112 sizeof *guest_info
->node_mem
);
1113 guest_info
->node_cpu
= g_malloc0(guest_info
->apic_id_limit
*
1114 sizeof *guest_info
->node_cpu
);
1116 for (i
= 0; i
< max_cpus
; i
++) {
1117 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
1118 assert(apic_id
< guest_info
->apic_id_limit
);
1119 for (j
= 0; j
< nb_numa_nodes
; j
++) {
1120 if (test_bit(i
, node_cpumask
[j
])) {
1121 guest_info
->node_cpu
[apic_id
] = j
;
1127 guest_info_state
->machine_done
.notify
= pc_guest_info_machine_done
;
1128 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1132 /* setup pci memory address space mapping into system address space */
1133 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1134 MemoryRegion
*pci_address_space
)
1136 /* Set to lower priority than RAM */
1137 memory_region_add_subregion_overlap(system_memory
, 0x0,
1138 pci_address_space
, -1);
1141 void pc_acpi_init(const char *default_dsdt
)
1145 if (acpi_tables
!= NULL
) {
1146 /* manually set via -acpitable, leave it alone */
1150 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1151 if (filename
== NULL
) {
1152 fprintf(stderr
, "WARNING: failed to find %s\n", default_dsdt
);
1158 arg
= g_strdup_printf("file=%s", filename
);
1160 /* creates a deep copy of "arg" */
1161 opts
= qemu_opts_parse(qemu_find_opts("acpi"), arg
, 0);
1162 g_assert(opts
!= NULL
);
1164 acpi_table_add_builtin(opts
, &err
);
1166 error_report("WARNING: failed to load %s: %s", filename
,
1167 error_get_pretty(err
));
1175 FWCfgState
*pc_memory_init(MemoryRegion
*system_memory
,
1176 const char *kernel_filename
,
1177 const char *kernel_cmdline
,
1178 const char *initrd_filename
,
1179 ram_addr_t below_4g_mem_size
,
1180 ram_addr_t above_4g_mem_size
,
1181 MemoryRegion
*rom_memory
,
1182 MemoryRegion
**ram_memory
,
1183 PcGuestInfo
*guest_info
)
1186 MemoryRegion
*ram
, *option_rom_mr
;
1187 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1190 linux_boot
= (kernel_filename
!= NULL
);
1192 /* Allocate RAM. We allocate it as a single memory region and use
1193 * aliases to address portions of it, mostly for backwards compatibility
1194 * with older qemus that used qemu_ram_alloc().
1196 ram
= g_malloc(sizeof(*ram
));
1197 memory_region_init_ram(ram
, NULL
, "pc.ram",
1198 below_4g_mem_size
+ above_4g_mem_size
);
1199 vmstate_register_ram_global(ram
);
1201 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1202 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1203 0, below_4g_mem_size
);
1204 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1205 e820_add_entry(0, below_4g_mem_size
, E820_RAM
);
1206 if (above_4g_mem_size
> 0) {
1207 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1208 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1209 below_4g_mem_size
, above_4g_mem_size
);
1210 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1212 e820_add_entry(0x100000000ULL
, above_4g_mem_size
, E820_RAM
);
1216 /* Initialize PC system firmware */
1217 pc_system_firmware_init(rom_memory
, guest_info
->isapc_ram_fw
);
1219 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1220 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
);
1221 vmstate_register_ram_global(option_rom_mr
);
1222 memory_region_add_subregion_overlap(rom_memory
,
1227 fw_cfg
= bochs_bios_init();
1231 load_linux(fw_cfg
, kernel_filename
, initrd_filename
, kernel_cmdline
, below_4g_mem_size
);
1234 for (i
= 0; i
< nb_option_roms
; i
++) {
1235 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1237 guest_info
->fw_cfg
= fw_cfg
;
1241 qemu_irq
*pc_allocate_cpu_irq(void)
1243 return qemu_allocate_irqs(pic_irq_request
, NULL
, 1);
1246 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1248 DeviceState
*dev
= NULL
;
1251 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1252 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1253 } else if (isa_bus
) {
1254 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1255 dev
= isadev
? DEVICE(isadev
) : NULL
;
1260 static void cpu_request_exit(void *opaque
, int irq
, int level
)
1262 CPUState
*cpu
= current_cpu
;
1269 static const MemoryRegionOps ioport80_io_ops
= {
1270 .write
= ioport80_write
,
1271 .read
= ioport80_read
,
1272 .endianness
= DEVICE_NATIVE_ENDIAN
,
1274 .min_access_size
= 1,
1275 .max_access_size
= 1,
1279 static const MemoryRegionOps ioportF0_io_ops
= {
1280 .write
= ioportF0_write
,
1281 .read
= ioportF0_read
,
1282 .endianness
= DEVICE_NATIVE_ENDIAN
,
1284 .min_access_size
= 1,
1285 .max_access_size
= 1,
1289 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1290 ISADevice
**rtc_state
,
1296 DriveInfo
*fd
[MAX_FD
];
1297 DeviceState
*hpet
= NULL
;
1298 int pit_isa_irq
= 0;
1299 qemu_irq pit_alt_irq
= NULL
;
1300 qemu_irq rtc_irq
= NULL
;
1302 ISADevice
*i8042
, *port92
, *vmmouse
, *pit
= NULL
;
1303 qemu_irq
*cpu_exit_irq
;
1304 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1305 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1307 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1308 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1310 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1311 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1314 * Check if an HPET shall be created.
1316 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1317 * when the HPET wants to take over. Thus we have to disable the latter.
1319 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1320 /* In order to set property, here not using sysbus_try_create_simple */
1321 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1323 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1324 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1327 uint8_t compat
= object_property_get_int(OBJECT(hpet
),
1330 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1332 qdev_init_nofail(hpet
);
1333 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1335 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1336 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1339 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1340 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1343 *rtc_state
= rtc_init(isa_bus
, 2000, rtc_irq
);
1345 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1347 if (!xen_enabled()) {
1348 if (kvm_irqchip_in_kernel()) {
1349 pit
= kvm_pit_init(isa_bus
, 0x40);
1351 pit
= pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1354 /* connect PIT to output control line of the HPET */
1355 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1357 pcspk_init(isa_bus
, pit
);
1360 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1361 if (serial_hds
[i
]) {
1362 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
1366 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
1367 if (parallel_hds
[i
]) {
1368 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
1372 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1373 i8042
= isa_create_simple(isa_bus
, "i8042");
1374 i8042_setup_a20_line(i8042
, &a20_line
[0]);
1376 vmport_init(isa_bus
);
1377 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1382 DeviceState
*dev
= DEVICE(vmmouse
);
1383 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1384 qdev_init_nofail(dev
);
1386 port92
= isa_create_simple(isa_bus
, "port92");
1387 port92_init(port92
, &a20_line
[1]);
1389 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
1390 DMA_init(0, cpu_exit_irq
);
1392 for(i
= 0; i
< MAX_FD
; i
++) {
1393 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1395 *floppy
= fdctrl_init_isa(isa_bus
, fd
);
1398 void pc_nic_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1402 for (i
= 0; i
< nb_nics
; i
++) {
1403 NICInfo
*nd
= &nd_table
[i
];
1405 if (!pci_bus
|| (nd
->model
&& strcmp(nd
->model
, "ne2k_isa") == 0)) {
1406 pc_init_ne2k_isa(isa_bus
, nd
);
1408 pci_nic_init_nofail(nd
, pci_bus
, "e1000", NULL
);
1413 void pc_pci_device_init(PCIBus
*pci_bus
)
1418 max_bus
= drive_get_max_bus(IF_SCSI
);
1419 for (bus
= 0; bus
<= max_bus
; bus
++) {
1420 pci_create_simple(pci_bus
, -1, "lsi53c895a");
1424 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1430 if (kvm_irqchip_in_kernel()) {
1431 dev
= qdev_create(NULL
, "kvm-ioapic");
1433 dev
= qdev_create(NULL
, "ioapic");
1436 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1437 "ioapic", OBJECT(dev
), NULL
);
1439 qdev_init_nofail(dev
);
1440 d
= SYS_BUS_DEVICE(dev
);
1441 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1443 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1444 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);