hw/net/xilinx_axienet.c

   1 /*
   2  * QEMU model of Xilinx AXI-Ethernet.
   3  *
   4  * Copyright (c) 2011 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "qemu/log.h"
  28 #include "net/net.h"
  29 #include "net/checksum.h"
  30
  31 #include "hw/stream.h"
  32
  33 #define DPHY(x)
  34
  35 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
  36 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
  37 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
  38
  39 #define XILINX_AXI_ENET(obj) \
  40      OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
  41
  42 #define XILINX_AXI_ENET_DATA_STREAM(obj) \
  43      OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
  44      TYPE_XILINX_AXI_ENET_DATA_STREAM)
  45
  46 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
  47      OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
  48      TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
  49
  50 /* Advertisement control register. */
  51 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
  52 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
  53 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
  54 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
  55
  56 #define CONTROL_PAYLOAD_WORDS 5
  57 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
  58
  59 struct PHY {
  60     uint32_t regs[32];
  61
  62     int link;
  63
  64     unsigned int (*read)(struct PHY *phy, unsigned int req);
  65     void (*write)(struct PHY *phy, unsigned int req,
  66                   unsigned int data);
  67 };
  68
  69 static unsigned int tdk_read(struct PHY *phy, unsigned int req)
  70 {
  71     int regnum;
  72     unsigned r = 0;
  73
  74     regnum = req & 0x1f;
  75
  76     switch (regnum) {
  77         case 1:
  78             if (!phy->link) {
  79                 break;
  80             }
  81             /* MR1.  */
  82             /* Speeds and modes.  */
  83             r |= (1 << 13) | (1 << 14);
  84             r |= (1 << 11) | (1 << 12);
  85             r |= (1 << 5); /* Autoneg complete.  */
  86             r |= (1 << 3); /* Autoneg able.  */
  87             r |= (1 << 2); /* link.  */
  88             r |= (1 << 1); /* link.  */
  89             break;
  90         case 5:
  91             /* Link partner ability.
  92                We are kind; always agree with whatever best mode
  93                the guest advertises.  */
  94             r = 1 << 14; /* Success.  */
  95             /* Copy advertised modes.  */
  96             r |= phy->regs[4] & (15 << 5);
  97             /* Autoneg support.  */
  98             r |= 1;
  99             break;
 100         case 17:
 101             /* Marvell PHY on many xilinx boards.  */
 102             r = 0x8000; /* 1000Mb  */
 103             break;
 104         case 18:
 105             {
 106                 /* Diagnostics reg.  */
 107                 int duplex = 0;
 108                 int speed_100 = 0;
 109
 110                 if (!phy->link) {
 111                     break;
 112                 }
 113
 114                 /* Are we advertising 100 half or 100 duplex ? */
 115                 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
 116                 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
 117
 118                 /* Are we advertising 10 duplex or 100 duplex ? */
 119                 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
 120                 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
 121                 r = (speed_100 << 10) | (duplex << 11);
 122             }
 123             break;
 124
 125         default:
 126             r = phy->regs[regnum];
 127             break;
 128     }
 129     DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
 130     return r;
 131 }
 132
 133 static void
 134 tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
 135 {
 136     int regnum;
 137
 138     regnum = req & 0x1f;
 139     DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
 140     switch (regnum) {
 141         default:
 142             phy->regs[regnum] = data;
 143             break;
 144     }
 145
 146     /* Unconditionally clear regs[BMCR][BMCR_RESET] */
 147     phy->regs[0] &= ~0x8000;
 148 }
 149
 150 static void
 151 tdk_init(struct PHY *phy)
 152 {
 153     phy->regs[0] = 0x3100;
 154     /* PHY Id.  */
 155     phy->regs[2] = 0x0300;
 156     phy->regs[3] = 0xe400;
 157     /* Autonegotiation advertisement reg.  */
 158     phy->regs[4] = 0x01E1;
 159     phy->link = 1;
 160
 161     phy->read = tdk_read;
 162     phy->write = tdk_write;
 163 }
 164
 165 struct MDIOBus {
 166     /* bus.  */
 167     int mdc;
 168     int mdio;
 169
 170     /* decoder.  */
 171     enum {
 172         PREAMBLE,
 173         SOF,
 174         OPC,
 175         ADDR,
 176         REQ,
 177         TURNAROUND,
 178         DATA
 179     } state;
 180     unsigned int drive;
 181
 182     unsigned int cnt;
 183     unsigned int addr;
 184     unsigned int opc;
 185     unsigned int req;
 186     unsigned int data;
 187
 188     struct PHY *devs[32];
 189 };
 190
 191 static void
 192 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 193 {
 194     bus->devs[addr & 0x1f] = phy;
 195 }
 196
 197 #ifdef USE_THIS_DEAD_CODE
 198 static void
 199 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 200 {
 201     bus->devs[addr & 0x1f] = NULL;
 202 }
 203 #endif
 204
 205 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
 206                   unsigned int reg)
 207 {
 208     struct PHY *phy;
 209     uint16_t data;
 210
 211     phy = bus->devs[addr];
 212     if (phy && phy->read) {
 213         data = phy->read(phy, reg);
 214     } else {
 215         data = 0xffff;
 216     }
 217     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 218     return data;
 219 }
 220
 221 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
 222                unsigned int reg, uint16_t data)
 223 {
 224     struct PHY *phy;
 225
 226     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 227     phy = bus->devs[addr];
 228     if (phy && phy->write) {
 229         phy->write(phy, reg, data);
 230     }
 231 }
 232
 233 #define DENET(x)
 234
 235 #define R_RAF      (0x000 / 4)
 236 enum {
 237     RAF_MCAST_REJ = (1 << 1),
 238     RAF_BCAST_REJ = (1 << 2),
 239     RAF_EMCF_EN = (1 << 12),
 240     RAF_NEWFUNC_EN = (1 << 11)
 241 };
 242
 243 #define R_IS       (0x00C / 4)
 244 enum {
 245     IS_HARD_ACCESS_COMPLETE = 1,
 246     IS_AUTONEG = (1 << 1),
 247     IS_RX_COMPLETE = (1 << 2),
 248     IS_RX_REJECT = (1 << 3),
 249     IS_TX_COMPLETE = (1 << 5),
 250     IS_RX_DCM_LOCK = (1 << 6),
 251     IS_MGM_RDY = (1 << 7),
 252     IS_PHY_RST_DONE = (1 << 8),
 253 };
 254
 255 #define R_IP       (0x010 / 4)
 256 #define R_IE       (0x014 / 4)
 257 #define R_UAWL     (0x020 / 4)
 258 #define R_UAWU     (0x024 / 4)
 259 #define R_PPST     (0x030 / 4)
 260 enum {
 261     PPST_LINKSTATUS = (1 << 0),
 262     PPST_PHY_LINKSTATUS = (1 << 7),
 263 };
 264
 265 #define R_STATS_RX_BYTESL (0x200 / 4)
 266 #define R_STATS_RX_BYTESH (0x204 / 4)
 267 #define R_STATS_TX_BYTESL (0x208 / 4)
 268 #define R_STATS_TX_BYTESH (0x20C / 4)
 269 #define R_STATS_RXL       (0x290 / 4)
 270 #define R_STATS_RXH       (0x294 / 4)
 271 #define R_STATS_RX_BCASTL (0x2a0 / 4)
 272 #define R_STATS_RX_BCASTH (0x2a4 / 4)
 273 #define R_STATS_RX_MCASTL (0x2a8 / 4)
 274 #define R_STATS_RX_MCASTH (0x2ac / 4)
 275
 276 #define R_RCW0     (0x400 / 4)
 277 #define R_RCW1     (0x404 / 4)
 278 enum {
 279     RCW1_VLAN = (1 << 27),
 280     RCW1_RX   = (1 << 28),
 281     RCW1_FCS  = (1 << 29),
 282     RCW1_JUM  = (1 << 30),
 283     RCW1_RST  = (1 << 31),
 284 };
 285
 286 #define R_TC       (0x408 / 4)
 287 enum {
 288     TC_VLAN = (1 << 27),
 289     TC_TX   = (1 << 28),
 290     TC_FCS  = (1 << 29),
 291     TC_JUM  = (1 << 30),
 292     TC_RST  = (1 << 31),
 293 };
 294
 295 #define R_EMMC     (0x410 / 4)
 296 enum {
 297     EMMC_LINKSPEED_10MB = (0 << 30),
 298     EMMC_LINKSPEED_100MB = (1 << 30),
 299     EMMC_LINKSPEED_1000MB = (2 << 30),
 300 };
 301
 302 #define R_PHYC     (0x414 / 4)
 303
 304 #define R_MC       (0x500 / 4)
 305 #define MC_EN      (1 << 6)
 306
 307 #define R_MCR      (0x504 / 4)
 308 #define R_MWD      (0x508 / 4)
 309 #define R_MRD      (0x50c / 4)
 310 #define R_MIS      (0x600 / 4)
 311 #define R_MIP      (0x620 / 4)
 312 #define R_MIE      (0x640 / 4)
 313 #define R_MIC      (0x640 / 4)
 314
 315 #define R_UAW0     (0x700 / 4)
 316 #define R_UAW1     (0x704 / 4)
 317 #define R_FMI      (0x708 / 4)
 318 #define R_AF0      (0x710 / 4)
 319 #define R_AF1      (0x714 / 4)
 320 #define R_MAX      (0x34 / 4)
 321
 322 /* Indirect registers.  */
 323 struct TEMAC  {
 324     struct MDIOBus mdio_bus;
 325     struct PHY phy;
 326
 327     void *parent;
 328 };
 329
 330 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
 331 typedef struct XilinxAXIEnet XilinxAXIEnet;
 332
 333 struct XilinxAXIEnetStreamSlave {
 334     Object parent;
 335
 336     struct XilinxAXIEnet *enet;
 337 } ;
 338
 339 struct XilinxAXIEnet {
 340     SysBusDevice busdev;
 341     MemoryRegion iomem;
 342     qemu_irq irq;
 343     StreamSlave *tx_data_dev;
 344     StreamSlave *tx_control_dev;
 345     XilinxAXIEnetStreamSlave rx_data_dev;
 346     XilinxAXIEnetStreamSlave rx_control_dev;
 347     NICState *nic;
 348     NICConf conf;
 349
 350
 351     uint32_t c_rxmem;
 352     uint32_t c_txmem;
 353     uint32_t c_phyaddr;
 354
 355     struct TEMAC TEMAC;
 356
 357     /* MII regs.  */
 358     union {
 359         uint32_t regs[4];
 360         struct {
 361             uint32_t mc;
 362             uint32_t mcr;
 363             uint32_t mwd;
 364             uint32_t mrd;
 365         };
 366     } mii;
 367
 368     struct {
 369         uint64_t rx_bytes;
 370         uint64_t tx_bytes;
 371
 372         uint64_t rx;
 373         uint64_t rx_bcast;
 374         uint64_t rx_mcast;
 375     } stats;
 376
 377     /* Receive configuration words.  */
 378     uint32_t rcw[2];
 379     /* Transmit config.  */
 380     uint32_t tc;
 381     uint32_t emmc;
 382     uint32_t phyc;
 383
 384     /* Unicast Address Word.  */
 385     uint32_t uaw[2];
 386     /* Unicast address filter used with extended mcast.  */
 387     uint32_t ext_uaw[2];
 388     uint32_t fmi;
 389
 390     uint32_t regs[R_MAX];
 391
 392     /* Multicast filter addrs.  */
 393     uint32_t maddr[4][2];
 394     /* 32K x 1 lookup filter.  */
 395     uint32_t ext_mtable[1024];
 396
 397     uint32_t hdr[CONTROL_PAYLOAD_WORDS];
 398
 399     uint8_t *rxmem;
 400     uint32_t rxsize;
 401     uint32_t rxpos;
 402
 403     uint8_t rxapp[CONTROL_PAYLOAD_SIZE];
 404     uint32_t rxappsize;
 405
 406     /* Whether axienet_eth_rx_notify should flush incoming queue. */
 407     bool need_flush;
 408 };
 409
 410 static void axienet_rx_reset(XilinxAXIEnet *s)
 411 {
 412     s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
 413 }
 414
 415 static void axienet_tx_reset(XilinxAXIEnet *s)
 416 {
 417     s->tc = TC_JUM | TC_TX | TC_VLAN;
 418 }
 419
 420 static inline int axienet_rx_resetting(XilinxAXIEnet *s)
 421 {
 422     return s->rcw[1] & RCW1_RST;
 423 }
 424
 425 static inline int axienet_rx_enabled(XilinxAXIEnet *s)
 426 {
 427     return s->rcw[1] & RCW1_RX;
 428 }
 429
 430 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s)
 431 {
 432     return !!(s->regs[R_RAF] & RAF_EMCF_EN);
 433 }
 434
 435 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s)
 436 {
 437     return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
 438 }
 439
 440 static void xilinx_axienet_reset(DeviceState *d)
 441 {
 442     XilinxAXIEnet *s = XILINX_AXI_ENET(d);
 443
 444     axienet_rx_reset(s);
 445     axienet_tx_reset(s);
 446
 447     s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
 448     s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
 449
 450     s->emmc = EMMC_LINKSPEED_100MB;
 451 }
 452
 453 static void enet_update_irq(XilinxAXIEnet *s)
 454 {
 455     s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
 456     qemu_set_irq(s->irq, !!s->regs[R_IP]);
 457 }
 458
 459 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
 460 {
 461     XilinxAXIEnet *s = opaque;
 462     uint32_t r = 0;
 463     addr >>= 2;
 464
 465     switch (addr) {
 466         case R_RCW0:
 467         case R_RCW1:
 468             r = s->rcw[addr & 1];
 469             break;
 470
 471         case R_TC:
 472             r = s->tc;
 473             break;
 474
 475         case R_EMMC:
 476             r = s->emmc;
 477             break;
 478
 479         case R_PHYC:
 480             r = s->phyc;
 481             break;
 482
 483         case R_MCR:
 484             r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready.  */
 485             break;
 486
 487         case R_STATS_RX_BYTESL:
 488         case R_STATS_RX_BYTESH:
 489             r = s->stats.rx_bytes >> (32 * (addr & 1));
 490             break;
 491
 492         case R_STATS_TX_BYTESL:
 493         case R_STATS_TX_BYTESH:
 494             r = s->stats.tx_bytes >> (32 * (addr & 1));
 495             break;
 496
 497         case R_STATS_RXL:
 498         case R_STATS_RXH:
 499             r = s->stats.rx >> (32 * (addr & 1));
 500             break;
 501         case R_STATS_RX_BCASTL:
 502         case R_STATS_RX_BCASTH:
 503             r = s->stats.rx_bcast >> (32 * (addr & 1));
 504             break;
 505         case R_STATS_RX_MCASTL:
 506         case R_STATS_RX_MCASTH:
 507             r = s->stats.rx_mcast >> (32 * (addr & 1));
 508             break;
 509
 510         case R_MC:
 511         case R_MWD:
 512         case R_MRD:
 513             r = s->mii.regs[addr & 3];
 514             break;
 515
 516         case R_UAW0:
 517         case R_UAW1:
 518             r = s->uaw[addr & 1];
 519             break;
 520
 521         case R_UAWU:
 522         case R_UAWL:
 523             r = s->ext_uaw[addr & 1];
 524             break;
 525
 526         case R_FMI:
 527             r = s->fmi;
 528             break;
 529
 530         case R_AF0:
 531         case R_AF1:
 532             r = s->maddr[s->fmi & 3][addr & 1];
 533             break;
 534
 535         case 0x8000 ... 0x83ff:
 536             r = s->ext_mtable[addr - 0x8000];
 537             break;
 538
 539         default:
 540             if (addr < ARRAY_SIZE(s->regs)) {
 541                 r = s->regs[addr];
 542             }
 543             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 544                             __func__, addr * 4, r));
 545             break;
 546     }
 547     return r;
 548 }
 549
 550 static void enet_write(void *opaque, hwaddr addr,
 551                        uint64_t value, unsigned size)
 552 {
 553     XilinxAXIEnet *s = opaque;
 554     struct TEMAC *t = &s->TEMAC;
 555
 556     addr >>= 2;
 557     switch (addr) {
 558         case R_RCW0:
 559         case R_RCW1:
 560             s->rcw[addr & 1] = value;
 561             if ((addr & 1) && value & RCW1_RST) {
 562                 axienet_rx_reset(s);
 563             } else {
 564                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 565             }
 566             break;
 567
 568         case R_TC:
 569             s->tc = value;
 570             if (value & TC_RST) {
 571                 axienet_tx_reset(s);
 572             }
 573             break;
 574
 575         case R_EMMC:
 576             s->emmc = value;
 577             break;
 578
 579         case R_PHYC:
 580             s->phyc = value;
 581             break;
 582
 583         case R_MC:
 584              value &= ((1 << 7) - 1);
 585
 586              /* Enable the MII.  */
 587              if (value & MC_EN) {
 588                  unsigned int miiclkdiv = value & ((1 << 6) - 1);
 589                  if (!miiclkdiv) {
 590                      qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
 591                  }
 592              }
 593              s->mii.mc = value;
 594              break;
 595
 596         case R_MCR: {
 597              unsigned int phyaddr = (value >> 24) & 0x1f;
 598              unsigned int regaddr = (value >> 16) & 0x1f;
 599              unsigned int op = (value >> 14) & 3;
 600              unsigned int initiate = (value >> 11) & 1;
 601
 602              if (initiate) {
 603                  if (op == 1) {
 604                      mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
 605                  } else if (op == 2) {
 606                      s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
 607                  } else {
 608                      qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
 609                  }
 610              }
 611              s->mii.mcr = value;
 612              break;
 613         }
 614
 615         case R_MWD:
 616         case R_MRD:
 617              s->mii.regs[addr & 3] = value;
 618              break;
 619
 620
 621         case R_UAW0:
 622         case R_UAW1:
 623             s->uaw[addr & 1] = value;
 624             break;
 625
 626         case R_UAWL:
 627         case R_UAWU:
 628             s->ext_uaw[addr & 1] = value;
 629             break;
 630
 631         case R_FMI:
 632             s->fmi = value;
 633             break;
 634
 635         case R_AF0:
 636         case R_AF1:
 637             s->maddr[s->fmi & 3][addr & 1] = value;
 638             break;
 639
 640         case R_IS:
 641             s->regs[addr] &= ~value;
 642             break;
 643
 644         case 0x8000 ... 0x83ff:
 645             s->ext_mtable[addr - 0x8000] = value;
 646             break;
 647
 648         default:
 649             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 650                            __func__, addr * 4, (unsigned)value));
 651             if (addr < ARRAY_SIZE(s->regs)) {
 652                 s->regs[addr] = value;
 653             }
 654             break;
 655     }
 656     enet_update_irq(s);
 657 }
 658
 659 static const MemoryRegionOps enet_ops = {
 660     .read = enet_read,
 661     .write = enet_write,
 662     .endianness = DEVICE_LITTLE_ENDIAN,
 663 };
 664
 665 static int eth_can_rx(XilinxAXIEnet *s)
 666 {
 667     /* RX enabled?  */
 668     return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s);
 669 }
 670
 671 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
 672 {
 673     int match = 1;
 674
 675     if (memcmp(buf, &f0, 4)) {
 676         match = 0;
 677     }
 678
 679     if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
 680         match = 0;
 681     }
 682
 683     return match;
 684 }
 685
 686 static void axienet_eth_rx_notify(void *opaque)
 687 {
 688     XilinxAXIEnet *s = XILINX_AXI_ENET(opaque);
 689
 690     while (s->rxappsize && stream_can_push(s->tx_control_dev,
 691                                            axienet_eth_rx_notify, s)) {
 692         size_t ret = stream_push(s->tx_control_dev,
 693                                  (void *)s->rxapp + CONTROL_PAYLOAD_SIZE
 694                                  - s->rxappsize, s->rxappsize);
 695         s->rxappsize -= ret;
 696     }
 697
 698     while (s->rxsize && stream_can_push(s->tx_data_dev,
 699                                         axienet_eth_rx_notify, s)) {
 700         size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos,
 701                                  s->rxsize);
 702         s->rxsize -= ret;
 703         s->rxpos += ret;
 704         if (!s->rxsize) {
 705             s->regs[R_IS] |= IS_RX_COMPLETE;
 706             if (s->need_flush) {
 707                 s->need_flush = false;
 708                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 709             }
 710         }
 711     }
 712     enet_update_irq(s);
 713 }
 714
 715 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 716 {
 717     XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
 718     static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
 719                                               0xff, 0xff, 0xff};
 720     static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
 721     uint32_t app[CONTROL_PAYLOAD_WORDS] = {0};
 722     int promisc = s->fmi & (1 << 31);
 723     int unicast, broadcast, multicast, ip_multicast = 0;
 724     uint32_t csum32;
 725     uint16_t csum16;
 726     int i;
 727
 728     DENET(qemu_log("%s: %zd bytes\n", __func__, size));
 729
 730     if (!eth_can_rx(s)) {
 731         s->need_flush = true;
 732         return 0;
 733     }
 734
 735     unicast = ~buf[0] & 0x1;
 736     broadcast = memcmp(buf, sa_bcast, 6) == 0;
 737     multicast = !unicast && !broadcast;
 738     if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
 739         ip_multicast = 1;
 740     }
 741
 742     /* Jumbo or vlan sizes ?  */
 743     if (!(s->rcw[1] & RCW1_JUM)) {
 744         if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
 745             return size;
 746         }
 747     }
 748
 749     /* Basic Address filters.  If you want to use the extended filters
 750        you'll generally have to place the ethernet mac into promiscuous mode
 751        to avoid the basic filtering from dropping most frames.  */
 752     if (!promisc) {
 753         if (unicast) {
 754             if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
 755                 return size;
 756             }
 757         } else {
 758             if (broadcast) {
 759                 /* Broadcast.  */
 760                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 761                     return size;
 762                 }
 763             } else {
 764                 int drop = 1;
 765
 766                 /* Multicast.  */
 767                 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
 768                     return size;
 769                 }
 770
 771                 for (i = 0; i < 4; i++) {
 772                     if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
 773                         drop = 0;
 774                         break;
 775                     }
 776                 }
 777
 778                 if (drop) {
 779                     return size;
 780                 }
 781             }
 782         }
 783     }
 784
 785     /* Extended mcast filtering enabled?  */
 786     if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
 787         if (unicast) {
 788             if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
 789                 return size;
 790             }
 791         } else {
 792             if (broadcast) {
 793                 /* Broadcast. ???  */
 794                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 795                     return size;
 796                 }
 797             } else {
 798                 int idx, bit;
 799
 800                 /* Multicast.  */
 801                 if (!memcmp(buf, sa_ipmcast, 3)) {
 802                     return size;
 803                 }
 804
 805                 idx  = (buf[4] & 0x7f) << 8;
 806                 idx |= buf[5];
 807
 808                 bit = 1 << (idx & 0x1f);
 809                 idx >>= 5;
 810
 811                 if (!(s->ext_mtable[idx] & bit)) {
 812                     return size;
 813                 }
 814             }
 815         }
 816     }
 817
 818     if (size < 12) {
 819         s->regs[R_IS] |= IS_RX_REJECT;
 820         enet_update_irq(s);
 821         return -1;
 822     }
 823
 824     if (size > (s->c_rxmem - 4)) {
 825         size = s->c_rxmem - 4;
 826     }
 827
 828     memcpy(s->rxmem, buf, size);
 829     memset(s->rxmem + size, 0, 4); /* Clear the FCS.  */
 830
 831     if (s->rcw[1] & RCW1_FCS) {
 832         size += 4; /* fcs is inband.  */
 833     }
 834
 835     app[0] = 5 << 28;
 836     csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
 837     /* Fold it once.  */
 838     csum32 = (csum32 & 0xffff) + (csum32 >> 16);
 839     /* And twice to get rid of possible carries.  */
 840     csum16 = (csum32 & 0xffff) + (csum32 >> 16);
 841     app[3] = csum16;
 842     app[4] = size & 0xffff;
 843
 844     s->stats.rx_bytes += size;
 845     s->stats.rx++;
 846     if (multicast) {
 847         s->stats.rx_mcast++;
 848         app[2] |= 1 | (ip_multicast << 1);
 849     } else if (broadcast) {
 850         s->stats.rx_bcast++;
 851         app[2] |= 1 << 3;
 852     }
 853
 854     /* Good frame.  */
 855     app[2] |= 1 << 6;
 856
 857     s->rxsize = size;
 858     s->rxpos = 0;
 859     for (i = 0; i < ARRAY_SIZE(app); ++i) {
 860         app[i] = cpu_to_le32(app[i]);
 861     }
 862     s->rxappsize = CONTROL_PAYLOAD_SIZE;
 863     memcpy(s->rxapp, app, s->rxappsize);
 864     axienet_eth_rx_notify(s);
 865
 866     enet_update_irq(s);
 867     return size;
 868 }
 869
 870 static size_t
 871 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len)
 872 {
 873     int i;
 874     XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
 875     XilinxAXIEnet *s = cs->enet;
 876
 877     if (len != CONTROL_PAYLOAD_SIZE) {
 878         hw_error("AXI Enet requires %d byte control stream payload\n",
 879                  (int)CONTROL_PAYLOAD_SIZE);
 880     }
 881
 882     memcpy(s->hdr, buf, len);
 883
 884     for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) {
 885         s->hdr[i] = le32_to_cpu(s->hdr[i]);
 886     }
 887     return len;
 888 }
 889
 890 static size_t
 891 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size)
 892 {
 893     XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
 894     XilinxAXIEnet *s = ds->enet;
 895
 896     /* TX enable ?  */
 897     if (!(s->tc & TC_TX)) {
 898         return size;
 899     }
 900
 901     /* Jumbo or vlan sizes ?  */
 902     if (!(s->tc & TC_JUM)) {
 903         if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
 904             return size;
 905         }
 906     }
 907
 908     if (s->hdr[0] & 1) {
 909         unsigned int start_off = s->hdr[1] >> 16;
 910         unsigned int write_off = s->hdr[1] & 0xffff;
 911         uint32_t tmp_csum;
 912         uint16_t csum;
 913
 914         tmp_csum = net_checksum_add(size - start_off,
 915                                     (uint8_t *)buf + start_off);
 916         /* Accumulate the seed.  */
 917         tmp_csum += s->hdr[2] & 0xffff;
 918
 919         /* Fold the 32bit partial checksum.  */
 920         csum = net_checksum_finish(tmp_csum);
 921
 922         /* Writeback.  */
 923         buf[write_off] = csum >> 8;
 924         buf[write_off + 1] = csum & 0xff;
 925     }
 926
 927     qemu_send_packet(qemu_get_queue(s->nic), buf, size);
 928
 929     s->stats.tx_bytes += size;
 930     s->regs[R_IS] |= IS_TX_COMPLETE;
 931     enet_update_irq(s);
 932
 933     return size;
 934 }
 935
 936 static NetClientInfo net_xilinx_enet_info = {
 937     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 938     .size = sizeof(NICState),
 939     .receive = eth_rx,
 940 };
 941
 942 static void xilinx_enet_realize(DeviceState *dev, Error **errp)
 943 {
 944     XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
 945     XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
 946     XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
 947                                                             &s->rx_control_dev);
 948     Error *local_err = NULL;
 949
 950     object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
 951                              (Object **) &ds->enet,
 952                              object_property_allow_set_link,
 953                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
 954                              &local_err);
 955     object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet",
 956                              (Object **) &cs->enet,
 957                              object_property_allow_set_link,
 958                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
 959                              &local_err);
 960     if (local_err) {
 961         goto xilinx_enet_realize_fail;
 962     }
 963     object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err);
 964     object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err);
 965     if (local_err) {
 966         goto xilinx_enet_realize_fail;
 967     }
 968
 969     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 970     s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
 971                           object_get_typename(OBJECT(dev)), dev->id, s);
 972     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 973
 974     tdk_init(&s->TEMAC.phy);
 975     mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
 976
 977     s->TEMAC.parent = s;
 978
 979     s->rxmem = g_malloc(s->c_rxmem);
 980     return;
 981
 982 xilinx_enet_realize_fail:
 983     if (!*errp) {
 984         *errp = local_err;
 985     }
 986 }
 987
 988 static void xilinx_enet_init(Object *obj)
 989 {
 990     XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
 991     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 992
 993     object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
 994                              (Object **) &s->tx_data_dev,
 995                              qdev_prop_allow_set_link_before_realize,
 996                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
 997                              &error_abort);
 998     object_property_add_link(obj, "axistream-control-connected",
 999                              TYPE_STREAM_SLAVE,
1000                              (Object **) &s->tx_control_dev,
1001                              qdev_prop_allow_set_link_before_realize,
1002                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
1003                              &error_abort);
1004
1005     object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
1006                       TYPE_XILINX_AXI_ENET_DATA_STREAM);
1007     object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
1008                       TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
1009     object_property_add_child(OBJECT(s), "axistream-connected-target",
1010                               (Object *)&s->rx_data_dev, &error_abort);
1011     object_property_add_child(OBJECT(s), "axistream-control-connected-target",
1012                               (Object *)&s->rx_control_dev, &error_abort);
1013
1014     sysbus_init_irq(sbd, &s->irq);
1015
1016     memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000);
1017     sysbus_init_mmio(sbd, &s->iomem);
1018 }
1019
1020 static Property xilinx_enet_properties[] = {
1021     DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7),
1022     DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
1023     DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
1024     DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
1025     DEFINE_PROP_END_OF_LIST(),
1026 };
1027
1028 static void xilinx_enet_class_init(ObjectClass *klass, void *data)
1029 {
1030     DeviceClass *dc = DEVICE_CLASS(klass);
1031
1032     dc->realize = xilinx_enet_realize;
1033     dc->props = xilinx_enet_properties;
1034     dc->reset = xilinx_axienet_reset;
1035 }
1036
1037 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data)
1038 {
1039     StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
1040
1041     ssc->push = data;
1042 }
1043
1044 static const TypeInfo xilinx_enet_info = {
1045     .name          = TYPE_XILINX_AXI_ENET,
1046     .parent        = TYPE_SYS_BUS_DEVICE,
1047     .instance_size = sizeof(XilinxAXIEnet),
1048     .class_init    = xilinx_enet_class_init,
1049     .instance_init = xilinx_enet_init,
1050 };
1051
1052 static const TypeInfo xilinx_enet_data_stream_info = {
1053     .name          = TYPE_XILINX_AXI_ENET_DATA_STREAM,
1054     .parent        = TYPE_OBJECT,
1055     .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1056     .class_init    = xilinx_enet_stream_class_init,
1057     .class_data    = xilinx_axienet_data_stream_push,
1058     .interfaces = (InterfaceInfo[]) {
1059             { TYPE_STREAM_SLAVE },
1060             { }
1061     }
1062 };
1063
1064 static const TypeInfo xilinx_enet_control_stream_info = {
1065     .name          = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
1066     .parent        = TYPE_OBJECT,
1067     .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1068     .class_init    = xilinx_enet_stream_class_init,
1069     .class_data    = xilinx_axienet_control_stream_push,
1070     .interfaces = (InterfaceInfo[]) {
1071             { TYPE_STREAM_SLAVE },
1072             { }
1073     }
1074 };
1075
1076 static void xilinx_enet_register_types(void)
1077 {
1078     type_register_static(&xilinx_enet_info);
1079     type_register_static(&xilinx_enet_data_stream_info);
1080     type_register_static(&xilinx_enet_control_stream_info);
1081 }
1082
1083 type_init(xilinx_enet_register_types)