hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "cpu.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/xics.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qapi/visitor.h"
  38 #include "migration/vmstate.h"
  39 #include "monitor/monitor.h"
  40 #include "hw/intc/intc.h"
  41 #include "hw/irq.h"
  42 #include "sysemu/kvm.h"
  43 #include "sysemu/reset.h"
  44
  45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  46 {
  47     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  48
  49     if (!icp->output) {
  50         return;
  51     }
  52
  53     if (kvm_irqchip_in_kernel()) {
  54         icp_synchronize_state(icp);
  55     }
  56
  57     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  58                    cpu_index, icp->xirr, icp->xirr_owner,
  59                    icp->pending_priority, icp->mfrr);
  60 }
  61
  62 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  63 {
  64     uint32_t i;
  65
  66     monitor_printf(mon, "ICS %4x..%4x %p\n",
  67                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  68
  69     if (!ics->irqs) {
  70         return;
  71     }
  72
  73     if (kvm_irqchip_in_kernel()) {
  74         ics_synchronize_state(ics);
  75     }
  76
  77     for (i = 0; i < ics->nr_irqs; i++) {
  78         ICSIRQState *irq = ics->irqs + i;
  79
  80         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  81             continue;
  82         }
  83         monitor_printf(mon, "  %4x %s %02x %02x\n",
  84                        ics->offset + i,
  85                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  86                        "LSI" : "MSI",
  87                        irq->priority, irq->status);
  88     }
  89 }
  90
  91 /*
  92  * ICP: Presentation layer
  93  */
  94
  95 #define XISR_MASK  0x00ffffff
  96 #define CPPR_MASK  0xff000000
  97
  98 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
  99 #define CPPR(icp)   (((icp)->xirr) >> 24)
 100
 101 static void ics_reject(ICSState *ics, uint32_t nr);
 102 static void ics_eoi(ICSState *ics, uint32_t nr);
 103
 104 static void icp_check_ipi(ICPState *icp)
 105 {
 106     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 107         return;
 108     }
 109
 110     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 111
 112     if (XISR(icp) && icp->xirr_owner) {
 113         ics_reject(icp->xirr_owner, XISR(icp));
 114     }
 115
 116     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 117     icp->pending_priority = icp->mfrr;
 118     icp->xirr_owner = NULL;
 119     qemu_irq_raise(icp->output);
 120 }
 121
 122 void icp_resend(ICPState *icp)
 123 {
 124     XICSFabric *xi = icp->xics;
 125     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 126
 127     if (icp->mfrr < CPPR(icp)) {
 128         icp_check_ipi(icp);
 129     }
 130
 131     xic->ics_resend(xi);
 132 }
 133
 134 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 135 {
 136     uint8_t old_cppr;
 137     uint32_t old_xisr;
 138
 139     old_cppr = CPPR(icp);
 140     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 141
 142     if (cppr < old_cppr) {
 143         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 144             old_xisr = XISR(icp);
 145             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 146             icp->pending_priority = 0xff;
 147             qemu_irq_lower(icp->output);
 148             if (icp->xirr_owner) {
 149                 ics_reject(icp->xirr_owner, old_xisr);
 150                 icp->xirr_owner = NULL;
 151             }
 152         }
 153     } else {
 154         if (!XISR(icp)) {
 155             icp_resend(icp);
 156         }
 157     }
 158 }
 159
 160 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 161 {
 162     icp->mfrr = mfrr;
 163     if (mfrr < CPPR(icp)) {
 164         icp_check_ipi(icp);
 165     }
 166 }
 167
 168 uint32_t icp_accept(ICPState *icp)
 169 {
 170     uint32_t xirr = icp->xirr;
 171
 172     qemu_irq_lower(icp->output);
 173     icp->xirr = icp->pending_priority << 24;
 174     icp->pending_priority = 0xff;
 175     icp->xirr_owner = NULL;
 176
 177     trace_xics_icp_accept(xirr, icp->xirr);
 178
 179     return xirr;
 180 }
 181
 182 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 183 {
 184     if (mfrr) {
 185         *mfrr = icp->mfrr;
 186     }
 187     return icp->xirr;
 188 }
 189
 190 void icp_eoi(ICPState *icp, uint32_t xirr)
 191 {
 192     XICSFabric *xi = icp->xics;
 193     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 194     ICSState *ics;
 195     uint32_t irq;
 196
 197     /* Send EOI -> ICS */
 198     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 199     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 200     irq = xirr & XISR_MASK;
 201
 202     ics = xic->ics_get(xi, irq);
 203     if (ics) {
 204         ics_eoi(ics, irq);
 205     }
 206     if (!XISR(icp)) {
 207         icp_resend(icp);
 208     }
 209 }
 210
 211 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 212 {
 213     ICPState *icp = xics_icp_get(ics->xics, server);
 214
 215     trace_xics_icp_irq(server, nr, priority);
 216
 217     if ((priority >= CPPR(icp))
 218         || (XISR(icp) && (icp->pending_priority <= priority))) {
 219         ics_reject(ics, nr);
 220     } else {
 221         if (XISR(icp) && icp->xirr_owner) {
 222             ics_reject(icp->xirr_owner, XISR(icp));
 223             icp->xirr_owner = NULL;
 224         }
 225         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 226         icp->xirr_owner = ics;
 227         icp->pending_priority = priority;
 228         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 229         qemu_irq_raise(icp->output);
 230     }
 231 }
 232
 233 static int icp_pre_save(void *opaque)
 234 {
 235     ICPState *icp = opaque;
 236
 237     if (kvm_irqchip_in_kernel()) {
 238         icp_get_kvm_state(icp);
 239     }
 240
 241     return 0;
 242 }
 243
 244 static int icp_post_load(void *opaque, int version_id)
 245 {
 246     ICPState *icp = opaque;
 247
 248     if (kvm_irqchip_in_kernel()) {
 249         Error *local_err = NULL;
 250         int ret;
 251
 252         ret = icp_set_kvm_state(icp, &local_err);
 253         if (ret < 0) {
 254             error_report_err(local_err);
 255             return ret;
 256         }
 257     }
 258
 259     return 0;
 260 }
 261
 262 static const VMStateDescription vmstate_icp_server = {
 263     .name = "icp/server",
 264     .version_id = 1,
 265     .minimum_version_id = 1,
 266     .pre_save = icp_pre_save,
 267     .post_load = icp_post_load,
 268     .fields = (VMStateField[]) {
 269         /* Sanity check */
 270         VMSTATE_UINT32(xirr, ICPState),
 271         VMSTATE_UINT8(pending_priority, ICPState),
 272         VMSTATE_UINT8(mfrr, ICPState),
 273         VMSTATE_END_OF_LIST()
 274     },
 275 };
 276
 277 static void icp_reset_handler(void *dev)
 278 {
 279     ICPState *icp = ICP(dev);
 280
 281     icp->xirr = 0;
 282     icp->pending_priority = 0xff;
 283     icp->mfrr = 0xff;
 284
 285     /* Make all outputs are deasserted */
 286     qemu_set_irq(icp->output, 0);
 287
 288     if (kvm_irqchip_in_kernel()) {
 289         Error *local_err = NULL;
 290
 291         icp_set_kvm_state(ICP(dev), &local_err);
 292         if (local_err) {
 293             error_report_err(local_err);
 294         }
 295     }
 296 }
 297
 298 static void icp_realize(DeviceState *dev, Error **errp)
 299 {
 300     ICPState *icp = ICP(dev);
 301     PowerPCCPU *cpu;
 302     CPUPPCState *env;
 303     Object *obj;
 304     Error *err = NULL;
 305
 306     obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
 307     if (!obj) {
 308         error_propagate_prepend(errp, err,
 309                                 "required link '" ICP_PROP_XICS
 310                                 "' not found: ");
 311         return;
 312     }
 313
 314     icp->xics = XICS_FABRIC(obj);
 315
 316     obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
 317     if (!obj) {
 318         error_propagate_prepend(errp, err,
 319                                 "required link '" ICP_PROP_CPU
 320                                 "' not found: ");
 321         return;
 322     }
 323
 324     cpu = POWERPC_CPU(obj);
 325     icp->cs = CPU(obj);
 326
 327     env = &cpu->env;
 328     switch (PPC_INPUT(env)) {
 329     case PPC_FLAGS_INPUT_POWER7:
 330         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 331         break;
 332     case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
 333         icp->output = env->irq_inputs[POWER9_INPUT_INT];
 334         break;
 335
 336     case PPC_FLAGS_INPUT_970:
 337         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 338         break;
 339
 340     default:
 341         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 342         return;
 343     }
 344
 345     /* Connect the presenter to the VCPU (required for CPU hotplug) */
 346     if (kvm_irqchip_in_kernel()) {
 347         icp_kvm_realize(dev, &err);
 348         if (err) {
 349             error_propagate(errp, err);
 350             return;
 351         }
 352     }
 353
 354     qemu_register_reset(icp_reset_handler, dev);
 355     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 356 }
 357
 358 static void icp_unrealize(DeviceState *dev, Error **errp)
 359 {
 360     ICPState *icp = ICP(dev);
 361
 362     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 363     qemu_unregister_reset(icp_reset_handler, dev);
 364 }
 365
 366 static void icp_class_init(ObjectClass *klass, void *data)
 367 {
 368     DeviceClass *dc = DEVICE_CLASS(klass);
 369
 370     dc->realize = icp_realize;
 371     dc->unrealize = icp_unrealize;
 372     /*
 373      * Reason: part of XICS interrupt controller, needs to be wired up
 374      * by icp_create().
 375      */
 376     dc->user_creatable = false;
 377 }
 378
 379 static const TypeInfo icp_info = {
 380     .name = TYPE_ICP,
 381     .parent = TYPE_DEVICE,
 382     .instance_size = sizeof(ICPState),
 383     .class_init = icp_class_init,
 384     .class_size = sizeof(ICPStateClass),
 385 };
 386
 387 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 388 {
 389     Error *local_err = NULL;
 390     Object *obj;
 391
 392     obj = object_new(type);
 393     object_property_add_child(cpu, type, obj, &error_abort);
 394     object_unref(obj);
 395     object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
 396                                    &error_abort);
 397     object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
 398     object_property_set_bool(obj, true, "realized", &local_err);
 399     if (local_err) {
 400         object_unparent(obj);
 401         error_propagate(errp, local_err);
 402         obj = NULL;
 403     }
 404
 405     return obj;
 406 }
 407
 408 /*
 409  * ICS: Source layer
 410  */
 411 static void ics_resend_msi(ICSState *ics, int srcno)
 412 {
 413     ICSIRQState *irq = ics->irqs + srcno;
 414
 415     /* FIXME: filter by server#? */
 416     if (irq->status & XICS_STATUS_REJECTED) {
 417         irq->status &= ~XICS_STATUS_REJECTED;
 418         if (irq->priority != 0xff) {
 419             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 420         }
 421     }
 422 }
 423
 424 static void ics_resend_lsi(ICSState *ics, int srcno)
 425 {
 426     ICSIRQState *irq = ics->irqs + srcno;
 427
 428     if ((irq->priority != 0xff)
 429         && (irq->status & XICS_STATUS_ASSERTED)
 430         && !(irq->status & XICS_STATUS_SENT)) {
 431         irq->status |= XICS_STATUS_SENT;
 432         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 433     }
 434 }
 435
 436 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
 437 {
 438     ICSIRQState *irq = ics->irqs + srcno;
 439
 440     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
 441
 442     if (val) {
 443         if (irq->priority == 0xff) {
 444             irq->status |= XICS_STATUS_MASKED_PENDING;
 445             trace_xics_masked_pending();
 446         } else  {
 447             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 448         }
 449     }
 450 }
 451
 452 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
 453 {
 454     ICSIRQState *irq = ics->irqs + srcno;
 455
 456     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
 457     if (val) {
 458         irq->status |= XICS_STATUS_ASSERTED;
 459     } else {
 460         irq->status &= ~XICS_STATUS_ASSERTED;
 461     }
 462     ics_resend_lsi(ics, srcno);
 463 }
 464
 465 void ics_set_irq(void *opaque, int srcno, int val)
 466 {
 467     ICSState *ics = (ICSState *)opaque;
 468
 469     if (kvm_irqchip_in_kernel()) {
 470         ics_kvm_set_irq(ics, srcno, val);
 471         return;
 472     }
 473
 474     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 475         ics_set_irq_lsi(ics, srcno, val);
 476     } else {
 477         ics_set_irq_msi(ics, srcno, val);
 478     }
 479 }
 480
 481 static void ics_write_xive_msi(ICSState *ics, int srcno)
 482 {
 483     ICSIRQState *irq = ics->irqs + srcno;
 484
 485     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 486         || (irq->priority == 0xff)) {
 487         return;
 488     }
 489
 490     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 491     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 492 }
 493
 494 static void ics_write_xive_lsi(ICSState *ics, int srcno)
 495 {
 496     ics_resend_lsi(ics, srcno);
 497 }
 498
 499 void ics_write_xive(ICSState *ics, int srcno, int server,
 500                     uint8_t priority, uint8_t saved_priority)
 501 {
 502     ICSIRQState *irq = ics->irqs + srcno;
 503
 504     irq->server = server;
 505     irq->priority = priority;
 506     irq->saved_priority = saved_priority;
 507
 508     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
 509
 510     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 511         ics_write_xive_lsi(ics, srcno);
 512     } else {
 513         ics_write_xive_msi(ics, srcno);
 514     }
 515 }
 516
 517 static void ics_reject(ICSState *ics, uint32_t nr)
 518 {
 519     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 520
 521     trace_xics_ics_reject(nr, nr - ics->offset);
 522     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 523         irq->status |= XICS_STATUS_REJECTED;
 524     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 525         irq->status &= ~XICS_STATUS_SENT;
 526     }
 527 }
 528
 529 void ics_resend(ICSState *ics)
 530 {
 531     int i;
 532
 533     for (i = 0; i < ics->nr_irqs; i++) {
 534         /* FIXME: filter by server#? */
 535         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 536             ics_resend_lsi(ics, i);
 537         } else {
 538             ics_resend_msi(ics, i);
 539         }
 540     }
 541 }
 542
 543 static void ics_eoi(ICSState *ics, uint32_t nr)
 544 {
 545     int srcno = nr - ics->offset;
 546     ICSIRQState *irq = ics->irqs + srcno;
 547
 548     trace_xics_ics_eoi(nr);
 549
 550     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 551         irq->status &= ~XICS_STATUS_SENT;
 552     }
 553 }
 554
 555 static void ics_reset_irq(ICSIRQState *irq)
 556 {
 557     irq->priority = 0xff;
 558     irq->saved_priority = 0xff;
 559 }
 560
 561 static void ics_reset(DeviceState *dev)
 562 {
 563     ICSState *ics = ICS(dev);
 564     int i;
 565     uint8_t flags[ics->nr_irqs];
 566
 567     for (i = 0; i < ics->nr_irqs; i++) {
 568         flags[i] = ics->irqs[i].flags;
 569     }
 570
 571     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 572
 573     for (i = 0; i < ics->nr_irqs; i++) {
 574         ics_reset_irq(ics->irqs + i);
 575         ics->irqs[i].flags = flags[i];
 576     }
 577
 578     if (kvm_irqchip_in_kernel()) {
 579         Error *local_err = NULL;
 580
 581         ics_set_kvm_state(ICS(dev), &local_err);
 582         if (local_err) {
 583             error_report_err(local_err);
 584         }
 585     }
 586 }
 587
 588 static void ics_reset_handler(void *dev)
 589 {
 590     ics_reset(dev);
 591 }
 592
 593 static void ics_realize(DeviceState *dev, Error **errp)
 594 {
 595     ICSState *ics = ICS(dev);
 596     Error *local_err = NULL;
 597     Object *obj;
 598
 599     obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err);
 600     if (!obj) {
 601         error_propagate_prepend(errp, local_err,
 602                                 "required link '" ICS_PROP_XICS
 603                                 "' not found: ");
 604         return;
 605     }
 606     ics->xics = XICS_FABRIC(obj);
 607
 608     if (!ics->nr_irqs) {
 609         error_setg(errp, "Number of interrupts needs to be greater 0");
 610         return;
 611     }
 612     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 613
 614     qemu_register_reset(ics_reset_handler, ics);
 615 }
 616
 617 static void ics_instance_init(Object *obj)
 618 {
 619     ICSState *ics = ICS(obj);
 620
 621     ics->offset = XICS_IRQ_BASE;
 622 }
 623
 624 static int ics_pre_save(void *opaque)
 625 {
 626     ICSState *ics = opaque;
 627
 628     if (kvm_irqchip_in_kernel()) {
 629         ics_get_kvm_state(ics);
 630     }
 631
 632     return 0;
 633 }
 634
 635 static int ics_post_load(void *opaque, int version_id)
 636 {
 637     ICSState *ics = opaque;
 638
 639     if (kvm_irqchip_in_kernel()) {
 640         Error *local_err = NULL;
 641         int ret;
 642
 643         ret = ics_set_kvm_state(ics, &local_err);
 644         if (ret < 0) {
 645             error_report_err(local_err);
 646             return ret;
 647         }
 648     }
 649
 650     return 0;
 651 }
 652
 653 static const VMStateDescription vmstate_ics_irq = {
 654     .name = "ics/irq",
 655     .version_id = 2,
 656     .minimum_version_id = 1,
 657     .fields = (VMStateField[]) {
 658         VMSTATE_UINT32(server, ICSIRQState),
 659         VMSTATE_UINT8(priority, ICSIRQState),
 660         VMSTATE_UINT8(saved_priority, ICSIRQState),
 661         VMSTATE_UINT8(status, ICSIRQState),
 662         VMSTATE_UINT8(flags, ICSIRQState),
 663         VMSTATE_END_OF_LIST()
 664     },
 665 };
 666
 667 static const VMStateDescription vmstate_ics = {
 668     .name = "ics",
 669     .version_id = 1,
 670     .minimum_version_id = 1,
 671     .pre_save = ics_pre_save,
 672     .post_load = ics_post_load,
 673     .fields = (VMStateField[]) {
 674         /* Sanity check */
 675         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 676
 677         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 678                                              vmstate_ics_irq,
 679                                              ICSIRQState),
 680         VMSTATE_END_OF_LIST()
 681     },
 682 };
 683
 684 static Property ics_properties[] = {
 685     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 686     DEFINE_PROP_END_OF_LIST(),
 687 };
 688
 689 static void ics_class_init(ObjectClass *klass, void *data)
 690 {
 691     DeviceClass *dc = DEVICE_CLASS(klass);
 692
 693     dc->realize = ics_realize;
 694     dc->props = ics_properties;
 695     dc->reset = ics_reset;
 696     dc->vmsd = &vmstate_ics;
 697     /*
 698      * Reason: part of XICS interrupt controller, needs to be wired up,
 699      * e.g. by spapr_irq_init().
 700      */
 701     dc->user_creatable = false;
 702 }
 703
 704 static const TypeInfo ics_info = {
 705     .name = TYPE_ICS,
 706     .parent = TYPE_DEVICE,
 707     .instance_size = sizeof(ICSState),
 708     .instance_init = ics_instance_init,
 709     .class_init = ics_class_init,
 710     .class_size = sizeof(ICSStateClass),
 711 };
 712
 713 static const TypeInfo xics_fabric_info = {
 714     .name = TYPE_XICS_FABRIC,
 715     .parent = TYPE_INTERFACE,
 716     .class_size = sizeof(XICSFabricClass),
 717 };
 718
 719 /*
 720  * Exported functions
 721  */
 722 ICPState *xics_icp_get(XICSFabric *xi, int server)
 723 {
 724     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 725
 726     return xic->icp_get(xi, server);
 727 }
 728
 729 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 730 {
 731     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 732
 733     ics->irqs[srcno].flags |=
 734         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 735
 736     if (kvm_irqchip_in_kernel()) {
 737         Error *local_err = NULL;
 738
 739         ics_reset_irq(ics->irqs + srcno);
 740         ics_set_kvm_state_one(ics, srcno, &local_err);
 741         if (local_err) {
 742             error_report_err(local_err);
 743         }
 744     }
 745 }
 746
 747 static void xics_register_types(void)
 748 {
 749     type_register_static(&ics_info);
 750     type_register_static(&icp_info);
 751     type_register_static(&xics_fabric_info);
 752 }
 753
 754 type_init(xics_register_types)