tmp105: update the register in post_load where it needs updating.
[qemu/ar7.git] / hw / ppce500_mpc8544ds.c
blob0901fa6ffe7511fe35d4b8d8e8b4fe17257e7172
1 /*
2 * Qemu PowerPC MPC8544DS board emualtion
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <dirent.h>
19 #include "config.h"
20 #include "qemu-common.h"
21 #include "net.h"
22 #include "hw.h"
23 #include "pc.h"
24 #include "pci.h"
25 #include "boards.h"
26 #include "sysemu.h"
27 #include "kvm.h"
28 #include "kvm_ppc.h"
29 #include "device_tree.h"
30 #include "openpic.h"
31 #include "ppce500.h"
32 #include "loader.h"
33 #include "elf.h"
35 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
36 #define UIMAGE_LOAD_BASE 0
37 #define DTC_LOAD_PAD 0x500000
38 #define DTC_PAD_MASK 0xFFFFF
39 #define INITRD_LOAD_PAD 0x2000000
40 #define INITRD_PAD_MASK 0xFFFFFF
42 #define RAM_SIZES_ALIGN (64UL << 20)
44 #define MPC8544_CCSRBAR_BASE 0xE0000000
45 #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000)
46 #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500)
47 #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600)
48 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000)
49 #define MPC8544_PCI_REGS_SIZE 0x1000
50 #define MPC8544_PCI_IO 0xE1000000
51 #define MPC8544_PCI_IOLEN 0x10000
53 #ifdef CONFIG_FDT
54 static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop)
56 uint32_t cell;
57 int ret;
59 ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
60 if (ret < 0) {
61 fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
62 goto out;
65 ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
66 prop, cell);
67 if (ret < 0) {
68 fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
69 goto out;
72 out:
73 return ret;
75 #endif
77 static int mpc8544_load_device_tree(target_phys_addr_t addr,
78 uint32_t ramsize,
79 target_phys_addr_t initrd_base,
80 target_phys_addr_t initrd_size,
81 const char *kernel_cmdline)
83 int ret = -1;
84 #ifdef CONFIG_FDT
85 uint32_t mem_reg_property[] = {0, ramsize};
86 char *filename;
87 int fdt_size;
88 void *fdt;
90 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
91 if (!filename) {
92 goto out;
94 fdt = load_device_tree(filename, &fdt_size);
95 qemu_free(filename);
96 if (fdt == NULL) {
97 goto out;
100 /* Manipulate device tree in memory. */
101 ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
102 sizeof(mem_reg_property));
103 if (ret < 0)
104 fprintf(stderr, "couldn't set /memory/reg\n");
106 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
107 initrd_base);
108 if (ret < 0)
109 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
111 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
112 (initrd_base + initrd_size));
113 if (ret < 0)
114 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
116 ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
117 kernel_cmdline);
118 if (ret < 0)
119 fprintf(stderr, "couldn't set /chosen/bootargs\n");
121 if (kvm_enabled()) {
122 struct dirent *dirp;
123 DIR *dp;
124 char buf[128];
126 if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) {
127 printf("Can't open directory /proc/device-tree/cpus/\n");
128 ret = -1;
129 goto out;
132 buf[0] = '\0';
133 while ((dirp = readdir(dp)) != NULL) {
134 if (strncmp(dirp->d_name, "PowerPC", 7) == 0) {
135 snprintf(buf, 128, "/cpus/%s", dirp->d_name);
136 break;
139 closedir(dp);
140 if (buf[0] == '\0') {
141 printf("Unknow host!\n");
142 ret = -1;
143 goto out;
146 mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
147 mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
150 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
151 qemu_free(fdt);
153 out:
154 #endif
156 return ret;
159 static void mpc8544ds_init(ram_addr_t ram_size,
160 const char *boot_device,
161 const char *kernel_filename,
162 const char *kernel_cmdline,
163 const char *initrd_filename,
164 const char *cpu_model)
166 PCIBus *pci_bus;
167 CPUState *env;
168 uint64_t elf_entry;
169 uint64_t elf_lowaddr;
170 target_phys_addr_t entry=0;
171 target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
172 target_long kernel_size=0;
173 target_ulong dt_base = 0;
174 target_ulong initrd_base = 0;
175 target_long initrd_size=0;
176 int i=0;
177 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
178 qemu_irq *irqs, *mpic, *pci_irqs;
179 SerialState * serial[2];
181 /* Setup CPU */
182 env = cpu_ppc_init("e500v2_v30");
183 if (!env) {
184 fprintf(stderr, "Unable to initialize CPU!\n");
185 exit(1);
188 /* Fixup Memory size on a alignment boundary */
189 ram_size &= ~(RAM_SIZES_ALIGN - 1);
191 /* Register Memory */
192 cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(ram_size));
194 /* MPIC */
195 irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
196 irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
197 irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
198 mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
200 /* Serial */
201 if (serial_hds[0]) {
202 serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
203 0, mpic[12+26], 399193,
204 serial_hds[0], 1, 1);
207 if (serial_hds[1]) {
208 serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
209 0, mpic[12+26], 399193,
210 serial_hds[0], 1, 1);
213 /* PCI */
214 pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
215 pci_irqs[0] = mpic[pci_irq_nrs[0]];
216 pci_irqs[1] = mpic[pci_irq_nrs[1]];
217 pci_irqs[2] = mpic[pci_irq_nrs[2]];
218 pci_irqs[3] = mpic[pci_irq_nrs[3]];
219 pci_bus = ppce500_pci_init(pci_irqs, MPC8544_PCI_REGS_BASE);
220 if (!pci_bus)
221 printf("couldn't create PCI controller!\n");
223 isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN, 1);
225 if (pci_bus) {
226 /* Register network interfaces. */
227 for (i = 0; i < nb_nics; i++) {
228 pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
232 /* Load kernel. */
233 if (kernel_filename) {
234 kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
235 if (kernel_size < 0) {
236 kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
237 &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
238 entry = elf_entry;
239 loadaddr = elf_lowaddr;
241 /* XXX try again as binary */
242 if (kernel_size < 0) {
243 fprintf(stderr, "qemu: could not load kernel '%s'\n",
244 kernel_filename);
245 exit(1);
249 /* Load initrd. */
250 if (initrd_filename) {
251 initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
252 initrd_size = load_image_targphys(initrd_filename, initrd_base,
253 ram_size - initrd_base);
255 if (initrd_size < 0) {
256 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
257 initrd_filename);
258 exit(1);
262 /* If we're loading a kernel directly, we must load the device tree too. */
263 if (kernel_filename) {
264 dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
265 if (mpc8544_load_device_tree(dt_base, ram_size,
266 initrd_base, initrd_size, kernel_cmdline) < 0) {
267 fprintf(stderr, "couldn't load device tree\n");
268 exit(1);
271 cpu_synchronize_state(env);
273 /* Set initial guest state. */
274 env->gpr[1] = (16<<20) - 8;
275 env->gpr[3] = dt_base;
276 env->nip = entry;
277 /* XXX we currently depend on KVM to create some initial TLB entries. */
280 if (kvm_enabled())
281 kvmppc_init();
283 return;
286 static QEMUMachine mpc8544ds_machine = {
287 .name = "mpc8544ds",
288 .desc = "mpc8544ds",
289 .init = mpc8544ds_init,
292 static void mpc8544ds_machine_init(void)
294 qemu_register_machine(&mpc8544ds_machine);
297 machine_init(mpc8544ds_machine_init);