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target/arm/kvm: Implement virtual time adjustment
[qemu/ar7.git] / hw / arm / aspeed_soc.c
blobb5e809a1d3fef81183033e239c9c694ef0c79afa
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_IOMEM] = 0x1E600000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_VIC] = 0x1E6C0000,
34 [ASPEED_SDMC] = 0x1E6E0000,
35 [ASPEED_SCU] = 0x1E6E2000,
36 [ASPEED_XDMA] = 0x1E6E7000,
37 [ASPEED_VIDEO] = 0x1E700000,
38 [ASPEED_ADC] = 0x1E6E9000,
39 [ASPEED_SRAM] = 0x1E720000,
40 [ASPEED_SDHCI] = 0x1E740000,
41 [ASPEED_GPIO] = 0x1E780000,
42 [ASPEED_RTC] = 0x1E781000,
43 [ASPEED_TIMER1] = 0x1E782000,
44 [ASPEED_WDT] = 0x1E785000,
45 [ASPEED_PWM] = 0x1E786000,
46 [ASPEED_LPC] = 0x1E789000,
47 [ASPEED_IBT] = 0x1E789140,
48 [ASPEED_I2C] = 0x1E78A000,
49 [ASPEED_ETH1] = 0x1E660000,
50 [ASPEED_ETH2] = 0x1E680000,
51 [ASPEED_UART1] = 0x1E783000,
52 [ASPEED_UART5] = 0x1E784000,
53 [ASPEED_VUART] = 0x1E787000,
54 [ASPEED_SDRAM] = 0x40000000,
55 };
56
57 static const hwaddr aspeed_soc_ast2500_memmap[] = {
58 [ASPEED_IOMEM] = 0x1E600000,
59 [ASPEED_FMC] = 0x1E620000,
60 [ASPEED_SPI1] = 0x1E630000,
61 [ASPEED_SPI2] = 0x1E631000,
62 [ASPEED_VIC] = 0x1E6C0000,
63 [ASPEED_SDMC] = 0x1E6E0000,
64 [ASPEED_SCU] = 0x1E6E2000,
65 [ASPEED_XDMA] = 0x1E6E7000,
66 [ASPEED_ADC] = 0x1E6E9000,
67 [ASPEED_VIDEO] = 0x1E700000,
68 [ASPEED_SRAM] = 0x1E720000,
69 [ASPEED_SDHCI] = 0x1E740000,
70 [ASPEED_GPIO] = 0x1E780000,
71 [ASPEED_RTC] = 0x1E781000,
72 [ASPEED_TIMER1] = 0x1E782000,
73 [ASPEED_WDT] = 0x1E785000,
74 [ASPEED_PWM] = 0x1E786000,
75 [ASPEED_LPC] = 0x1E789000,
76 [ASPEED_IBT] = 0x1E789140,
77 [ASPEED_I2C] = 0x1E78A000,
78 [ASPEED_ETH1] = 0x1E660000,
79 [ASPEED_ETH2] = 0x1E680000,
80 [ASPEED_UART1] = 0x1E783000,
81 [ASPEED_UART5] = 0x1E784000,
82 [ASPEED_VUART] = 0x1E787000,
83 [ASPEED_SDRAM] = 0x80000000,
84 };
85
86 static const int aspeed_soc_ast2400_irqmap[] = {
87 [ASPEED_UART1] = 9,
88 [ASPEED_UART2] = 32,
89 [ASPEED_UART3] = 33,
90 [ASPEED_UART4] = 34,
91 [ASPEED_UART5] = 10,
92 [ASPEED_VUART] = 8,
93 [ASPEED_FMC] = 19,
94 [ASPEED_SDMC] = 0,
95 [ASPEED_SCU] = 21,
96 [ASPEED_ADC] = 31,
97 [ASPEED_GPIO] = 20,
98 [ASPEED_RTC] = 22,
99 [ASPEED_TIMER1] = 16,
100 [ASPEED_TIMER2] = 17,
101 [ASPEED_TIMER3] = 18,
102 [ASPEED_TIMER4] = 35,
103 [ASPEED_TIMER5] = 36,
104 [ASPEED_TIMER6] = 37,
105 [ASPEED_TIMER7] = 38,
106 [ASPEED_TIMER8] = 39,
107 [ASPEED_WDT] = 27,
108 [ASPEED_PWM] = 28,
109 [ASPEED_LPC] = 8,
110 [ASPEED_IBT] = 8, /* LPC */
111 [ASPEED_I2C] = 12,
112 [ASPEED_ETH1] = 2,
113 [ASPEED_ETH2] = 3,
114 [ASPEED_XDMA] = 6,
115 [ASPEED_SDHCI] = 26,
116 };
117
118 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
119
120 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
121 {
122 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
123
124 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
125 }
126
127 static void aspeed_soc_init(Object *obj)
128 {
129 AspeedSoCState *s = ASPEED_SOC(obj);
130 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
131 int i;
132 char socname[8];
133 char typename[64];
134
135 if (sscanf(sc->name, "%7s", socname) != 1) {
136 g_assert_not_reached();
137 }
138
139 for (i = 0; i < sc->num_cpus; i++) {
140 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
141 sizeof(s->cpu[i]), sc->cpu_type,
142 &error_abort, NULL);
143 }
144
145 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
146 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
147 typename);
148 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
149 sc->silicon_rev);
150 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
151 "hw-strap1", &error_abort);
152 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
153 "hw-strap2", &error_abort);
154 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
155 "hw-prot-key", &error_abort);
156
157 sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
158 TYPE_ASPEED_VIC);
159
160 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
161 TYPE_ASPEED_RTC);
162
163 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
164 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
165 sizeof(s->timerctrl), typename);
166
167 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
168 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
169 typename);
170
171 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
172 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
173 typename);
174 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
175 &error_abort);
176
177 for (i = 0; i < sc->spis_num; i++) {
178 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
179 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
180 sizeof(s->spi[i]), typename);
181 }
182
183 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
184 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
185 typename);
186 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
187 "ram-size", &error_abort);
188 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
189 "max-ram-size", &error_abort);
190
191 for (i = 0; i < sc->wdts_num; i++) {
192 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
193 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
194 sizeof(s->wdt[i]), typename);
195 }
196
197 for (i = 0; i < sc->macs_num; i++) {
198 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
199 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
200 }
201
202 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
203 TYPE_ASPEED_XDMA);
204
205 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
206 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
207 typename);
208
209 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
210 TYPE_ASPEED_SDHCI);
211
212 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
213
214 /* Init sd card slot class here so that they're under the correct parent */
215 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
216 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
217 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
218 }
219 }
220
221 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
222 {
223 int i;
224 AspeedSoCState *s = ASPEED_SOC(dev);
225 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
226 Error *err = NULL, *local_err = NULL;
227
228 /* IO space */
229 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
230 ASPEED_SOC_IOMEM_SIZE);
231
232 /* Video engine stub */
233 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
234 0x1000);
235
236 if (s->num_cpus > sc->num_cpus) {
237 warn_report("%s: invalid number of CPUs %d, using default %d",
238 sc->name, s->num_cpus, sc->num_cpus);
239 s->num_cpus = sc->num_cpus;
240 }
241
242 /* CPU */
243 for (i = 0; i < s->num_cpus; i++) {
244 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
245 if (err) {
246 error_propagate(errp, err);
247 return;
248 }
249 }
250
251 /* SRAM */
252 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
253 sc->sram_size, &err);
254 if (err) {
255 error_propagate(errp, err);
256 return;
257 }
258 memory_region_add_subregion(get_system_memory(),
259 sc->memmap[ASPEED_SRAM], &s->sram);
260
261 /* SCU */
262 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
263 if (err) {
264 error_propagate(errp, err);
265 return;
266 }
267 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
268
269 /* VIC */
270 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
271 if (err) {
272 error_propagate(errp, err);
273 return;
274 }
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
276 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
277 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
278 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
279 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
280
281 /* RTC */
282 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
283 if (err) {
284 error_propagate(errp, err);
285 return;
286 }
287 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
288 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
289 aspeed_soc_get_irq(s, ASPEED_RTC));
290
291 /* Timer */
292 object_property_set_link(OBJECT(&s->timerctrl),
293 OBJECT(&s->scu), "scu", &error_abort);
294 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
295 if (err) {
296 error_propagate(errp, err);
297 return;
298 }
299 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
300 sc->memmap[ASPEED_TIMER1]);
301 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
302 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
304 }
305
306 /* UART - attach an 8250 to the IO space as our UART5 */
307 if (serial_hd(0)) {
308 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
309 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
310 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
311 }
312
313 /* I2C */
314 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
315 if (err) {
316 error_propagate(errp, err);
317 return;
318 }
319 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
320 if (err) {
321 error_propagate(errp, err);
322 return;
323 }
324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
325 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
326 aspeed_soc_get_irq(s, ASPEED_I2C));
327
328 /* FMC, The number of CS is set at the board level */
329 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
330 if (err) {
331 error_propagate(errp, err);
332 return;
333 }
334 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
335 "sdram-base", &err);
336 if (err) {
337 error_propagate(errp, err);
338 return;
339 }
340 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
341 if (err) {
342 error_propagate(errp, err);
343 return;
344 }
345 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
346 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
347 s->fmc.ctrl->flash_window_base);
348 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
349 aspeed_soc_get_irq(s, ASPEED_FMC));
350
351 /* SPI */
352 for (i = 0; i < sc->spis_num; i++) {
353 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
354 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
355 &local_err);
356 error_propagate(&err, local_err);
357 if (err) {
358 error_propagate(errp, err);
359 return;
360 }
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
362 sc->memmap[ASPEED_SPI1 + i]);
363 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
364 s->spi[i].ctrl->flash_window_base);
365 }
366
367 /* SDMC - SDRAM Memory Controller */
368 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
369 if (err) {
370 error_propagate(errp, err);
371 return;
372 }
373 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
374
375 /* Watch dog */
376 for (i = 0; i < sc->wdts_num; i++) {
377 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
378
379 object_property_set_link(OBJECT(&s->wdt[i]),
380 OBJECT(&s->scu), "scu", &error_abort);
381 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
382 if (err) {
383 error_propagate(errp, err);
384 return;
385 }
386 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
387 sc->memmap[ASPEED_WDT] + i * awc->offset);
388 }
389
390 /* Net */
391 for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
392 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
393 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
394 &err);
395 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
396 &local_err);
397 error_propagate(&err, local_err);
398 if (err) {
399 error_propagate(errp, err);
400 return;
401 }
402 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
403 sc->memmap[ASPEED_ETH1 + i]);
404 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
405 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
406 }
407
408 /* XDMA */
409 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
410 if (err) {
411 error_propagate(errp, err);
412 return;
413 }
414 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
415 sc->memmap[ASPEED_XDMA]);
416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
417 aspeed_soc_get_irq(s, ASPEED_XDMA));
418
419 /* GPIO */
420 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
421 if (err) {
422 error_propagate(errp, err);
423 return;
424 }
425 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
427 aspeed_soc_get_irq(s, ASPEED_GPIO));
428
429 /* SDHCI */
430 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
431 if (err) {
432 error_propagate(errp, err);
433 return;
434 }
435 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
436 sc->memmap[ASPEED_SDHCI]);
437 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
438 aspeed_soc_get_irq(s, ASPEED_SDHCI));
439 }
440 static Property aspeed_soc_properties[] = {
441 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
442 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
443 MemoryRegion *),
444 DEFINE_PROP_END_OF_LIST(),
445 };
446
447 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
448 {
449 DeviceClass *dc = DEVICE_CLASS(oc);
450
451 dc->realize = aspeed_soc_realize;
452 /* Reason: Uses serial_hds and nd_table in realize() directly */
453 dc->user_creatable = false;
454 device_class_set_props(dc, aspeed_soc_properties);
455 }
456
457 static const TypeInfo aspeed_soc_type_info = {
458 .name = TYPE_ASPEED_SOC,
459 .parent = TYPE_DEVICE,
460 .instance_size = sizeof(AspeedSoCState),
461 .class_size = sizeof(AspeedSoCClass),
462 .class_init = aspeed_soc_class_init,
463 .abstract = true,
464 };
465
466 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
467 {
468 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
469
470 sc->name = "ast2400-a1";
471 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
472 sc->silicon_rev = AST2400_A1_SILICON_REV;
473 sc->sram_size = 0x8000;
474 sc->spis_num = 1;
475 sc->wdts_num = 2;
476 sc->macs_num = 2;
477 sc->irqmap = aspeed_soc_ast2400_irqmap;
478 sc->memmap = aspeed_soc_ast2400_memmap;
479 sc->num_cpus = 1;
480 }
481
482 static const TypeInfo aspeed_soc_ast2400_type_info = {
483 .name = "ast2400-a1",
484 .parent = TYPE_ASPEED_SOC,
485 .instance_init = aspeed_soc_init,
486 .instance_size = sizeof(AspeedSoCState),
487 .class_init = aspeed_soc_ast2400_class_init,
488 };
489
490 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
491 {
492 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
493
494 sc->name = "ast2500-a1";
495 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
496 sc->silicon_rev = AST2500_A1_SILICON_REV;
497 sc->sram_size = 0x9000;
498 sc->spis_num = 2;
499 sc->wdts_num = 3;
500 sc->macs_num = 2;
501 sc->irqmap = aspeed_soc_ast2500_irqmap;
502 sc->memmap = aspeed_soc_ast2500_memmap;
503 sc->num_cpus = 1;
504 }
505
506 static const TypeInfo aspeed_soc_ast2500_type_info = {
507 .name = "ast2500-a1",
508 .parent = TYPE_ASPEED_SOC,
509 .instance_init = aspeed_soc_init,
510 .instance_size = sizeof(AspeedSoCState),
511 .class_init = aspeed_soc_ast2500_class_init,
512 };
513 static void aspeed_soc_register_types(void)
514 {
515 type_register_static(&aspeed_soc_type_info);
516 type_register_static(&aspeed_soc_ast2400_type_info);
517 type_register_static(&aspeed_soc_ast2500_type_info);
518 };
519
520 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU