hw/net/can/can_sja1000.h

   1 /*
   2  * CAN device - SJA1000 chip emulation for QEMU
   3  *
   4  * Copyright (c) 2013-2014 Jin Yang
   5  * Copyright (c) 2014-2018 Pavel Pisa
   6  *
   7  * Initial development supported by Google GSoC 2013 from RTEMS project slot
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27 #ifndef HW_CAN_SJA1000_H
  28 #define HW_CAN_SJA1000_H
  29
  30 #include "net/can_emu.h"
  31
  32 #define CAN_SJA_MEM_SIZE      128
  33
  34 /* The max size for a message buffer, EFF and DLC=8, DS-p39 */
  35 #define SJA_MSG_MAX_LEN       13
  36 /* The receive buffer size. */
  37 #define SJA_RCV_BUF_LEN       64
  38
  39 typedef struct CanSJA1000State {
  40     /* PeliCAN state and registers sorted by address */
  41     uint8_t         mode;          /* 0  .. Mode register, DS-p26 */
  42                                    /* 1  .. Command register */
  43     uint8_t         status_pel;    /* 2  .. Status register, p15 */
  44     uint8_t         interrupt_pel; /* 3  .. Interrupt register */
  45     uint8_t         interrupt_en;  /* 4  .. Interrupt Enable register */
  46     uint8_t         rxmsg_cnt;     /* 29 .. RX message counter. DS-p49 */
  47     uint8_t         rxbuf_start;   /* 30 .. RX buffer start address, DS-p49 */
  48     uint8_t         clock;         /* 31 .. Clock Divider register, DS-p55 */
  49
  50     uint8_t         code_mask[8];  /* 16~23 */
  51     uint8_t         tx_buff[13];   /* 96~108 .. transmit buffer */
  52                                    /* 10~19  .. transmit buffer for BasicCAN */
  53
  54     uint8_t         rx_buff[SJA_RCV_BUF_LEN];  /* 32~95 .. 64bytes Rx FIFO */
  55     uint32_t        rx_ptr;        /* Count by bytes. */
  56     uint32_t        rx_cnt;        /* Count by bytes. */
  57
  58     /* PeliCAN state and registers sorted by address */
  59     uint8_t         control;       /* 0 .. Control register */
  60                                    /* 1 .. Command register */
  61     uint8_t         status_bas;    /* 2 .. Status register */
  62     uint8_t         interrupt_bas; /* 3 .. Interrupt register */
  63     uint8_t         code;          /* 4 .. Acceptance code register */
  64     uint8_t         mask;          /* 5 .. Acceptance mask register */
  65
  66     qemu_can_filter filter[4];
  67
  68     qemu_irq          irq;
  69     CanBusClientState bus_client;
  70 } CanSJA1000State;
  71
  72 /* PeliCAN mode */
  73 enum SJA1000_PeliCAN_regs {
  74         SJA_MOD      = 0x00,    /* Mode control register */
  75         SJA_CMR      = 0x01,    /* Command register */
  76         SJA_SR       = 0x02,    /* Status register */
  77         SJA_IR       = 0x03,    /* Interrupt register */
  78         SJA_IER      = 0x04,    /* Interrupt Enable */
  79         SJA_BTR0     = 0x06,    /* Bus Timing register 0 */
  80         SJA_BTR1     = 0x07,    /* Bus Timing register 1 */
  81         SJA_OCR      = 0x08,    /* Output Control register */
  82         SJA_ALC      = 0x0b,    /* Arbitration Lost Capture */
  83         SJA_ECC      = 0x0c,    /* Error Code Capture */
  84         SJA_EWLR     = 0x0d,    /* Error Warning Limit */
  85         SJA_RXERR    = 0x0e,    /* RX Error Counter */
  86         SJA_TXERR0   = 0x0e,    /* TX Error Counter */
  87         SJA_TXERR1   = 0x0f,
  88         SJA_RMC      = 0x1d,    /* Rx Message Counter
  89                                  * number of messages in RX FIFO
  90                                  */
  91         SJA_RBSA     = 0x1e,    /* Rx Buffer Start Addr
  92                                  * address of current message
  93                                  */
  94         SJA_FRM      = 0x10,    /* Transmit Buffer
  95                                  * write: Receive Buffer
  96                                  * read: Frame Information
  97                                  */
  98 /*
  99  * ID bytes (11 bits in 0 and 1 for standard message or
 100  *          16 bits in 0,1 and 13 bits in 2,3 for extended message)
 101  *          The most significant bit of ID is placed in MSB
 102  *          position of ID0 register.
 103  */
 104         SJA_ID0      = 0x11,    /* ID for standard and extended frames */
 105         SJA_ID1      = 0x12,
 106         SJA_ID2      = 0x13,    /* ID cont. for extended frames */
 107         SJA_ID3      = 0x14,
 108
 109         SJA_DATS     = 0x13,    /* Data start standard frame */
 110         SJA_DATE     = 0x15,    /* Data start extended frame */
 111         SJA_ACR0     = 0x10,    /* Acceptance Code (4 bytes) in RESET mode */
 112         SJA_AMR0     = 0x14,    /* Acceptance Mask (4 bytes) in RESET mode */
 113         SJA_PeliCAN_AC_LEN = 4, /* 4 bytes */
 114         SJA_CDR      = 0x1f     /* Clock Divider */
 115 };
 116
 117
 118 /* BasicCAN  mode */
 119 enum SJA1000_BasicCAN_regs {
 120         SJA_BCAN_CTR = 0x00,    /* Control register */
 121         SJA_BCAN_CMR = 0x01,    /* Command register */
 122         SJA_BCAN_SR  = 0x02,    /* Status register */
 123         SJA_BCAN_IR  = 0x03     /* Interrupt register */
 124 };
 125
 126 void can_sja_hardware_reset(CanSJA1000State *s);
 127
 128 void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
 129                        unsigned size);
 130
 131 uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size);
 132
 133 int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus);
 134
 135 void can_sja_disconnect(CanSJA1000State *s);
 136
 137 int can_sja_init(CanSJA1000State *s, qemu_irq irq);
 138
 139 int can_sja_can_receive(CanBusClientState *client);
 140
 141 ssize_t can_sja_receive(CanBusClientState *client,
 142                         const qemu_can_frame *frames, size_t frames_cnt);
 143
 144 extern const VMStateDescription vmstate_can_sja;
 145
 146 #endif