2 * libqos virtio PCI driver
4 * Copyright (c) 2014 Marc MarĂ
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "libqos/virtio.h"
13 #include "libqos/virtio-pci.h"
14 #include "libqos/pci.h"
15 #include "libqos/pci-pc.h"
16 #include "libqos/malloc.h"
17 #include "libqos/malloc-pc.h"
18 #include "libqos/qgraph.h"
19 #include "standard-headers/linux/virtio_ring.h"
20 #include "standard-headers/linux/virtio_pci.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/pci_regs.h"
25 /* virtio-pci is a superclass of all virtio-xxx-pci devices;
26 * the relation between virtio-pci and virtio-xxx-pci is implicit,
27 * and therefore virtio-pci does not produce virtio and is not
28 * reached by any edge, not even as a "contains" edge.
29 * In facts, every device is a QVirtioPCIDevice with
30 * additional fields, since every one has its own
31 * number of queues and various attributes.
32 * Virtio-pci provides default functions to start the
33 * hw and destroy the object, and nodes that want to
34 * override them should always remember to call the
35 * original qvirtio_pci_destructor and qvirtio_pci_start_hw.
38 static inline bool qvirtio_pci_is_big_endian(QVirtioPCIDevice
*dev
)
40 QPCIBus
*bus
= dev
->pdev
->bus
;
42 /* FIXME: virtio 1.0 is always little-endian */
43 return qtest_big_endian(bus
->qts
);
46 #define CONFIG_BASE(dev) (VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))
48 static uint8_t qvirtio_pci_config_readb(QVirtioDevice
*d
, uint64_t off
)
50 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
51 return qpci_io_readb(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
54 /* PCI is always read in little-endian order
55 * but virtio ( < 1.0) is in guest order
56 * so with a big-endian guest the order has been reversed,
58 * virtio-1.0 is always little-endian, like PCI, but this
59 * case will be managed inside qvirtio_pci_is_big_endian()
62 static uint16_t qvirtio_pci_config_readw(QVirtioDevice
*d
, uint64_t off
)
64 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
67 value
= qpci_io_readw(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
68 if (qvirtio_is_big_endian(d
)) {
69 value
= bswap16(value
);
74 static uint32_t qvirtio_pci_config_readl(QVirtioDevice
*d
, uint64_t off
)
76 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
79 value
= qpci_io_readl(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
80 if (qvirtio_is_big_endian(d
)) {
81 value
= bswap32(value
);
86 static uint64_t qvirtio_pci_config_readq(QVirtioDevice
*d
, uint64_t off
)
88 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
91 val
= qpci_io_readq(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
92 if (qvirtio_is_big_endian(d
)) {
99 static uint64_t qvirtio_pci_get_features(QVirtioDevice
*d
)
101 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
102 return qpci_io_readl(dev
->pdev
, dev
->bar
, VIRTIO_PCI_HOST_FEATURES
);
105 static void qvirtio_pci_set_features(QVirtioDevice
*d
, uint64_t features
)
107 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
108 qpci_io_writel(dev
->pdev
, dev
->bar
, VIRTIO_PCI_GUEST_FEATURES
, features
);
111 static uint64_t qvirtio_pci_get_guest_features(QVirtioDevice
*d
)
113 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
114 return qpci_io_readl(dev
->pdev
, dev
->bar
, VIRTIO_PCI_GUEST_FEATURES
);
117 static uint8_t qvirtio_pci_get_status(QVirtioDevice
*d
)
119 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
120 return qpci_io_readb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_STATUS
);
123 static void qvirtio_pci_set_status(QVirtioDevice
*d
, uint8_t status
)
125 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
126 qpci_io_writeb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_STATUS
, status
);
129 static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice
*d
, QVirtQueue
*vq
)
131 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
132 QVirtQueuePCI
*vqpci
= (QVirtQueuePCI
*)vq
;
135 if (dev
->pdev
->msix_enabled
) {
136 g_assert_cmpint(vqpci
->msix_entry
, !=, -1);
137 if (qpci_msix_masked(dev
->pdev
, vqpci
->msix_entry
)) {
138 /* No ISR checking should be done if masked, but read anyway */
139 return qpci_msix_pending(dev
->pdev
, vqpci
->msix_entry
);
141 data
= qtest_readl(dev
->pdev
->bus
->qts
, vqpci
->msix_addr
);
142 if (data
== vqpci
->msix_data
) {
143 qtest_writel(dev
->pdev
->bus
->qts
, vqpci
->msix_addr
, 0);
150 return qpci_io_readb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_ISR
) & 1;
154 static bool qvirtio_pci_get_config_isr_status(QVirtioDevice
*d
)
156 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
159 if (dev
->pdev
->msix_enabled
) {
160 g_assert_cmpint(dev
->config_msix_entry
, !=, -1);
161 if (qpci_msix_masked(dev
->pdev
, dev
->config_msix_entry
)) {
162 /* No ISR checking should be done if masked, but read anyway */
163 return qpci_msix_pending(dev
->pdev
, dev
->config_msix_entry
);
165 data
= qtest_readl(dev
->pdev
->bus
->qts
, dev
->config_msix_addr
);
166 if (data
== dev
->config_msix_data
) {
167 qtest_writel(dev
->pdev
->bus
->qts
, dev
->config_msix_addr
, 0);
174 return qpci_io_readb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_ISR
) & 2;
178 static void qvirtio_pci_wait_config_isr_status(QVirtioDevice
*d
,
181 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
182 gint64 start_time
= g_get_monotonic_time();
185 g_assert(g_get_monotonic_time() - start_time
<= timeout_us
);
186 qtest_clock_step(dev
->pdev
->bus
->qts
, 100);
187 } while (!qvirtio_pci_get_config_isr_status(d
));
190 static void qvirtio_pci_queue_select(QVirtioDevice
*d
, uint16_t index
)
192 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
193 qpci_io_writeb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_SEL
, index
);
196 static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice
*d
)
198 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
199 return qpci_io_readw(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_NUM
);
202 static void qvirtio_pci_set_queue_address(QVirtioDevice
*d
, QVirtQueue
*vq
)
204 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
205 uint64_t pfn
= vq
->desc
/ VIRTIO_PCI_VRING_ALIGN
;
207 qpci_io_writel(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_PFN
, pfn
);
210 QVirtQueue
*qvirtio_pci_virtqueue_setup_common(QVirtioDevice
*d
,
211 QGuestAllocator
*alloc
,
216 QVirtQueuePCI
*vqpci
;
217 QVirtioPCIDevice
*qvpcidev
= container_of(d
, QVirtioPCIDevice
, vdev
);
219 vqpci
= g_malloc0(sizeof(*vqpci
));
220 feat
= d
->bus
->get_guest_features(d
);
222 d
->bus
->queue_select(d
, index
);
224 vqpci
->vq
.index
= index
;
225 vqpci
->vq
.size
= d
->bus
->get_queue_size(d
);
226 vqpci
->vq
.free_head
= 0;
227 vqpci
->vq
.num_free
= vqpci
->vq
.size
;
228 vqpci
->vq
.align
= VIRTIO_PCI_VRING_ALIGN
;
229 vqpci
->vq
.indirect
= feat
& (1ull << VIRTIO_RING_F_INDIRECT_DESC
);
230 vqpci
->vq
.event
= feat
& (1ull << VIRTIO_RING_F_EVENT_IDX
);
232 vqpci
->msix_entry
= -1;
233 vqpci
->msix_addr
= 0;
234 vqpci
->msix_data
= 0x12345678;
236 /* Check different than 0 */
237 g_assert_cmpint(vqpci
->vq
.size
, !=, 0);
239 /* Check power of 2 */
240 g_assert_cmpint(vqpci
->vq
.size
& (vqpci
->vq
.size
- 1), ==, 0);
242 addr
= guest_alloc(alloc
, qvring_size(vqpci
->vq
.size
,
243 VIRTIO_PCI_VRING_ALIGN
));
244 qvring_init(qvpcidev
->pdev
->bus
->qts
, alloc
, &vqpci
->vq
, addr
);
245 d
->bus
->set_queue_address(d
, &vqpci
->vq
);
250 void qvirtio_pci_virtqueue_cleanup_common(QVirtQueue
*vq
,
251 QGuestAllocator
*alloc
)
253 QVirtQueuePCI
*vqpci
= container_of(vq
, QVirtQueuePCI
, vq
);
255 guest_free(alloc
, vq
->desc
);
259 static void qvirtio_pci_virtqueue_kick(QVirtioDevice
*d
, QVirtQueue
*vq
)
261 QVirtioPCIDevice
*dev
= container_of(d
, QVirtioPCIDevice
, vdev
);
262 qpci_io_writew(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_NOTIFY
, vq
->index
);
265 const QVirtioBus qvirtio_pci
= {
266 .config_readb
= qvirtio_pci_config_readb
,
267 .config_readw
= qvirtio_pci_config_readw
,
268 .config_readl
= qvirtio_pci_config_readl
,
269 .config_readq
= qvirtio_pci_config_readq
,
270 .get_features
= qvirtio_pci_get_features
,
271 .set_features
= qvirtio_pci_set_features
,
272 .get_guest_features
= qvirtio_pci_get_guest_features
,
273 .get_status
= qvirtio_pci_get_status
,
274 .set_status
= qvirtio_pci_set_status
,
275 .get_queue_isr_status
= qvirtio_pci_get_queue_isr_status
,
276 .wait_config_isr_status
= qvirtio_pci_wait_config_isr_status
,
277 .queue_select
= qvirtio_pci_queue_select
,
278 .get_queue_size
= qvirtio_pci_get_queue_size
,
279 .set_queue_address
= qvirtio_pci_set_queue_address
,
280 .virtqueue_setup
= qvirtio_pci_virtqueue_setup_common
,
281 .virtqueue_cleanup
= qvirtio_pci_virtqueue_cleanup_common
,
282 .virtqueue_kick
= qvirtio_pci_virtqueue_kick
,
285 static void qvirtio_pci_set_config_vector(QVirtioPCIDevice
*d
, uint16_t entry
)
289 qpci_io_writew(d
->pdev
, d
->bar
, VIRTIO_MSI_CONFIG_VECTOR
, entry
);
290 vector
= qpci_io_readw(d
->pdev
, d
->bar
, VIRTIO_MSI_CONFIG_VECTOR
);
291 g_assert_cmphex(vector
, !=, VIRTIO_MSI_NO_VECTOR
);
294 static void qvirtio_pci_set_queue_vector(QVirtioPCIDevice
*d
, uint16_t vq_idx
,
299 qvirtio_pci_queue_select(&d
->vdev
, vq_idx
);
300 qpci_io_writew(d
->pdev
, d
->bar
, VIRTIO_MSI_QUEUE_VECTOR
, entry
);
301 vector
= qpci_io_readw(d
->pdev
, d
->bar
, VIRTIO_MSI_QUEUE_VECTOR
);
302 g_assert_cmphex(vector
, !=, VIRTIO_MSI_NO_VECTOR
);
305 static const QVirtioPCIMSIXOps qvirtio_pci_msix_ops_legacy
= {
306 .set_config_vector
= qvirtio_pci_set_config_vector
,
307 .set_queue_vector
= qvirtio_pci_set_queue_vector
,
310 void qvirtio_pci_device_enable(QVirtioPCIDevice
*d
)
312 qpci_device_enable(d
->pdev
);
313 d
->bar
= qpci_iomap(d
->pdev
, 0, NULL
);
316 void qvirtio_pci_device_disable(QVirtioPCIDevice
*d
)
318 qpci_iounmap(d
->pdev
, d
->bar
);
321 void qvirtqueue_pci_msix_setup(QVirtioPCIDevice
*d
, QVirtQueuePCI
*vqpci
,
322 QGuestAllocator
*alloc
, uint16_t entry
)
327 g_assert(d
->pdev
->msix_enabled
);
328 off
= d
->pdev
->msix_table_off
+ (entry
* 16);
330 g_assert_cmpint(entry
, >=, 0);
331 g_assert_cmpint(entry
, <, qpci_msix_table_size(d
->pdev
));
332 vqpci
->msix_entry
= entry
;
334 vqpci
->msix_addr
= guest_alloc(alloc
, 4);
335 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
336 off
+ PCI_MSIX_ENTRY_LOWER_ADDR
, vqpci
->msix_addr
& ~0UL);
337 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
338 off
+ PCI_MSIX_ENTRY_UPPER_ADDR
,
339 (vqpci
->msix_addr
>> 32) & ~0UL);
340 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
341 off
+ PCI_MSIX_ENTRY_DATA
, vqpci
->msix_data
);
343 control
= qpci_io_readl(d
->pdev
, d
->pdev
->msix_table_bar
,
344 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
345 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
346 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
,
347 control
& ~PCI_MSIX_ENTRY_CTRL_MASKBIT
);
349 d
->msix_ops
->set_queue_vector(d
, vqpci
->vq
.index
, entry
);
352 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice
*d
,
353 QGuestAllocator
*alloc
, uint16_t entry
)
358 g_assert(d
->pdev
->msix_enabled
);
359 off
= d
->pdev
->msix_table_off
+ (entry
* 16);
361 g_assert_cmpint(entry
, >=, 0);
362 g_assert_cmpint(entry
, <, qpci_msix_table_size(d
->pdev
));
363 d
->config_msix_entry
= entry
;
365 d
->config_msix_data
= 0x12345678;
366 d
->config_msix_addr
= guest_alloc(alloc
, 4);
368 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
369 off
+ PCI_MSIX_ENTRY_LOWER_ADDR
, d
->config_msix_addr
& ~0UL);
370 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
371 off
+ PCI_MSIX_ENTRY_UPPER_ADDR
,
372 (d
->config_msix_addr
>> 32) & ~0UL);
373 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
374 off
+ PCI_MSIX_ENTRY_DATA
, d
->config_msix_data
);
376 control
= qpci_io_readl(d
->pdev
, d
->pdev
->msix_table_bar
,
377 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
378 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
379 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
,
380 control
& ~PCI_MSIX_ENTRY_CTRL_MASKBIT
);
382 d
->msix_ops
->set_config_vector(d
, entry
);
385 void qvirtio_pci_destructor(QOSGraphObject
*obj
)
387 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)obj
;
388 qvirtio_pci_device_disable(dev
);
392 void qvirtio_pci_start_hw(QOSGraphObject
*obj
)
394 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)obj
;
395 qvirtio_pci_device_enable(dev
);
396 qvirtio_start_device(&dev
->vdev
);
399 static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevice
*dev
, QPCIDevice
*pci_dev
)
402 dev
->vdev
.device_type
= qpci_config_readw(pci_dev
, PCI_SUBSYSTEM_ID
);
404 dev
->config_msix_entry
= -1;
405 dev
->msix_ops
= &qvirtio_pci_msix_ops_legacy
;
407 dev
->vdev
.bus
= &qvirtio_pci
;
408 dev
->vdev
.big_endian
= qvirtio_pci_is_big_endian(dev
);
410 /* each virtio-xxx-pci device should override at least this function */
411 dev
->obj
.get_driver
= NULL
;
412 dev
->obj
.start_hw
= qvirtio_pci_start_hw
;
413 dev
->obj
.destructor
= qvirtio_pci_destructor
;
416 void virtio_pci_init(QVirtioPCIDevice
*dev
, QPCIBus
*bus
, QPCIAddress
* addr
)
418 QPCIDevice
*pci_dev
= qpci_device_find(bus
, addr
->devfn
);
419 g_assert_nonnull(pci_dev
);
420 qvirtio_pci_init_from_pcidev(dev
, pci_dev
);
423 QVirtioPCIDevice
*virtio_pci_new(QPCIBus
*bus
, QPCIAddress
* addr
)
425 QVirtioPCIDevice
*dev
;
426 QPCIDevice
*pci_dev
= qpci_device_find(bus
, addr
->devfn
);
431 dev
= g_new0(QVirtioPCIDevice
, 1);
432 qvirtio_pci_init_from_pcidev(dev
, pci_dev
);
433 dev
->obj
.free
= g_free
;