target-arm: Widen thread-local register state fields to 64 bits
[qemu/ar7.git] / target-arm / translate.h
blob67da6996c969d9a146c12ef00e3a0e8ce82ebfe8
1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
4 /* internal defines */
5 typedef struct DisasContext {
6 target_ulong pc;
7 uint32_t insn;
8 int is_jmp;
9 /* Nonzero if this instruction has been conditionally skipped. */
10 int condjmp;
11 /* The label that will be jumped to when the instruction is skipped. */
12 int condlabel;
13 /* Thumb-2 conditional execution bits. */
14 int condexec_mask;
15 int condexec_cond;
16 struct TranslationBlock *tb;
17 int singlestep_enabled;
18 int thumb;
19 int bswap_code;
20 #if !defined(CONFIG_USER_ONLY)
21 int user;
22 #endif
23 int vfp_enabled;
24 int vec_len;
25 int vec_stride;
26 int aarch64;
27 int current_pl;
28 GHashTable *cp_regs;
29 #define TMP_A64_MAX 16
30 int tmp_a64_count;
31 TCGv_i64 tmp_a64[TMP_A64_MAX];
32 } DisasContext;
34 extern TCGv_ptr cpu_env;
36 /* target-specific extra values for is_jmp */
37 /* These instructions trap after executing, so the A32/T32 decoder must
38 * defer them until after the conditional execution state has been updated.
39 * WFI also needs special handling when single-stepping.
41 #define DISAS_WFI 4
42 #define DISAS_SWI 5
43 /* For instructions which unconditionally cause an exception we can skip
44 * emitting unreachable code at the end of the TB in the A64 decoder
46 #define DISAS_EXC 6
48 #ifdef TARGET_AARCH64
49 void a64_translate_init(void);
50 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
51 TranslationBlock *tb,
52 bool search_pc);
53 void gen_a64_set_pc_im(uint64_t val);
54 #else
55 static inline void a64_translate_init(void)
59 static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
60 TranslationBlock *tb,
61 bool search_pc)
65 static inline void gen_a64_set_pc_im(uint64_t val)
68 #endif
70 void arm_gen_test_cc(int cc, int label);
72 #endif /* TARGET_ARM_TRANSLATE_H */