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hw/core: Add CPUClass.get_pc
[qemu/ar7.git] / target / mips / cpu.c
blobda58eb88928e767754fd0906c7cc23b54d29c0ec
1 /*
2 * QEMU MIPS CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/cutils.h"
23 #include "qemu/qemu-print.h"
24 #include "qapi/error.h"
25 #include "cpu.h"
26 #include "internal.h"
27 #include "kvm_mips.h"
28 #include "qemu/module.h"
29 #include "sysemu/kvm.h"
30 #include "sysemu/qtest.h"
31 #include "exec/exec-all.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-clock.h"
34 #include "semihosting/semihost.h"
35 #include "qapi/qapi-commands-machine-target.h"
36 #include "fpu_helper.h"
37
38 const char regnames[32][3] = {
39 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
40 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
41 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
42 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
43 };
44
45 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
46 {
47 if (is_fpu64) {
48 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n",
49 fpr->w[FP_ENDIAN_IDX], fpr->d,
50 (double)fpr->fd,
51 (double)fpr->fs[FP_ENDIAN_IDX],
52 (double)fpr->fs[!FP_ENDIAN_IDX]);
53 } else {
54 fpr_t tmp;
55
56 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
57 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
58 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n",
59 tmp.w[FP_ENDIAN_IDX], tmp.d,
60 (double)tmp.fd,
61 (double)tmp.fs[FP_ENDIAN_IDX],
62 (double)tmp.fs[!FP_ENDIAN_IDX]);
63 }
64 }
65
66 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
67 {
68 int i;
69 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
70
71 qemu_fprintf(f,
72 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
73 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
74 get_float_exception_flags(&env->active_fpu.fp_status));
75 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
76 qemu_fprintf(f, "%3s: ", fregnames[i]);
77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64);
78 }
79 }
80
81 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
82 {
83 MIPSCPU *cpu = MIPS_CPU(cs);
84 CPUMIPSState *env = &cpu->env;
85 int i;
86
87 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
88 " LO=0x" TARGET_FMT_lx " ds %04x "
89 TARGET_FMT_lx " " TARGET_FMT_ld "\n",
90 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
91 env->hflags, env->btarget, env->bcond);
92 for (i = 0; i < 32; i++) {
93 if ((i & 3) == 0) {
94 qemu_fprintf(f, "GPR%02d:", i);
95 }
96 qemu_fprintf(f, " %s " TARGET_FMT_lx,
97 regnames[i], env->active_tc.gpr[i]);
98 if ((i & 3) == 3) {
99 qemu_fprintf(f, "\n");
100 }
101 }
102
103 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
104 TARGET_FMT_lx "\n",
105 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
106 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
107 PRIx64 "\n",
108 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
109 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
110 env->CP0_Config2, env->CP0_Config3);
111 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
112 env->CP0_Config4, env->CP0_Config5);
113 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
114 fpu_dump_state(env, f, flags);
115 }
116 }
117
118 void cpu_set_exception_base(int vp_index, target_ulong address)
119 {
120 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
121 vp->env.exception_base = address;
122 }
123
124 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
125 {
126 MIPSCPU *cpu = MIPS_CPU(cs);
127
128 mips_env_set_pc(&cpu->env, value);
129 }
130
131 static vaddr mips_cpu_get_pc(CPUState *cs)
132 {
133 MIPSCPU *cpu = MIPS_CPU(cs);
134
135 return cpu->env.active_tc.PC;
136 }
137
138 static bool mips_cpu_has_work(CPUState *cs)
139 {
140 MIPSCPU *cpu = MIPS_CPU(cs);
141 CPUMIPSState *env = &cpu->env;
142 bool has_work = false;
143
144 /*
145 * Prior to MIPS Release 6 it is implementation dependent if non-enabled
146 * interrupts wake-up the CPU, however most of the implementations only
147 * check for interrupts that can be taken.
148 */
149 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
150 cpu_mips_hw_interrupts_pending(env)) {
151 if (cpu_mips_hw_interrupts_enabled(env) ||
152 (env->insn_flags & ISA_MIPS_R6)) {
153 has_work = true;
154 }
155 }
156
157 /* MIPS-MT has the ability to halt the CPU. */
158 if (ase_mt_available(env)) {
159 /*
160 * The QEMU model will issue an _WAKE request whenever the CPUs
161 * should be woken up.
162 */
163 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
164 has_work = true;
165 }
166
167 if (!mips_vpe_active(env)) {
168 has_work = false;
169 }
170 }
171 /* MIPS Release 6 has the ability to halt the CPU. */
172 if (env->CP0_Config5 & (1 << CP0C5_VP)) {
173 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
174 has_work = true;
175 }
176 if (!mips_vp_active(env)) {
177 has_work = false;
178 }
179 }
180 return has_work;
181 }
182
183 #include "cpu-defs.c.inc"
184
185 static void mips_cpu_reset(DeviceState *dev)
186 {
187 CPUState *cs = CPU(dev);
188 MIPSCPU *cpu = MIPS_CPU(cs);
189 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
190 CPUMIPSState *env = &cpu->env;
191
192 mcc->parent_reset(dev);
193
194 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
195
196 /* Reset registers to their default values */
197 env->CP0_PRid = env->cpu_model->CP0_PRid;
198 env->CP0_Config0 = env->cpu_model->CP0_Config0;
199 #if TARGET_BIG_ENDIAN
200 env->CP0_Config0 |= (1 << CP0C0_BE);
201 #endif
202 env->CP0_Config1 = env->cpu_model->CP0_Config1;
203 env->CP0_Config2 = env->cpu_model->CP0_Config2;
204 env->CP0_Config3 = env->cpu_model->CP0_Config3;
205 env->CP0_Config4 = env->cpu_model->CP0_Config4;
206 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
207 env->CP0_Config5 = env->cpu_model->CP0_Config5;
208 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
209 env->CP0_Config6 = env->cpu_model->CP0_Config6;
210 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
211 env->CP0_Config7 = env->cpu_model->CP0_Config7;
212 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
213 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
214 << env->cpu_model->CP0_LLAddr_shift;
215 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
216 env->SYNCI_Step = env->cpu_model->SYNCI_Step;
217 env->CCRes = env->cpu_model->CCRes;
218 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
219 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
220 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
221 env->current_tc = 0;
222 env->SEGBITS = env->cpu_model->SEGBITS;
223 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
224 #if defined(TARGET_MIPS64)
225 if (env->cpu_model->insn_flags & ISA_MIPS3) {
226 env->SEGMask |= 3ULL << 62;
227 }
228 #endif
229 env->PABITS = env->cpu_model->PABITS;
230 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
231 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
232 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
233 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
234 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
235 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
236 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
237 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
238 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
239 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
240 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
241 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
242 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
243 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
244 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
245 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
246 env->msair = env->cpu_model->MSAIR;
247 env->insn_flags = env->cpu_model->insn_flags;
248
249 #if defined(CONFIG_USER_ONLY)
250 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
251 # ifdef TARGET_MIPS64
252 /* Enable 64-bit register mode. */
253 env->CP0_Status |= (1 << CP0St_PX);
254 # endif
255 # ifdef TARGET_ABI_MIPSN64
256 /* Enable 64-bit address mode. */
257 env->CP0_Status |= (1 << CP0St_UX);
258 # endif
259 /*
260 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
261 * hardware registers.
262 */
263 env->CP0_HWREna |= 0x0000000F;
264 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
265 env->CP0_Status |= (1 << CP0St_CU1);
266 }
267 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
268 env->CP0_Status |= (1 << CP0St_MX);
269 }
270 # if defined(TARGET_MIPS64)
271 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
272 if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
273 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
274 env->CP0_Status |= (1 << CP0St_FR);
275 }
276 # endif
277 #else /* !CONFIG_USER_ONLY */
278 if (env->hflags & MIPS_HFLAG_BMASK) {
279 /*
280 * If the exception was raised from a delay slot,
281 * come back to the jump.
282 */
283 env->CP0_ErrorEPC = (env->active_tc.PC
284 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
285 } else {
286 env->CP0_ErrorEPC = env->active_tc.PC;
287 }
288 env->active_tc.PC = env->exception_base;
289 env->CP0_Random = env->tlb->nb_tlb - 1;
290 env->tlb->tlb_in_use = env->tlb->nb_tlb;
291 env->CP0_Wired = 0;
292 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
293 env->CP0_EBase = (cs->cpu_index & 0x3FF);
294 if (mips_um_ksegs_enabled()) {
295 env->CP0_EBase |= 0x40000000;
296 } else {
297 env->CP0_EBase |= (int32_t)0x80000000;
298 }
299 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
300 env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
301 }
302 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
303 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
304 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
305 /*
306 * Vectored interrupts not implemented, timer on int 7,
307 * no performance counters.
308 */
309 env->CP0_IntCtl = 0xe0000000;
310 {
311 int i;
312
313 for (i = 0; i < 7; i++) {
314 env->CP0_WatchLo[i] = 0;
315 env->CP0_WatchHi[i] = 1 << CP0WH_M;
316 }
317 env->CP0_WatchLo[7] = 0;
318 env->CP0_WatchHi[7] = 0;
319 }
320 /* Count register increments in debug mode, EJTAG version 1 */
321 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
322
323 cpu_mips_store_count(env, 1);
324
325 if (ase_mt_available(env)) {
326 int i;
327
328 /* Only TC0 on VPE 0 starts as active. */
329 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
330 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
331 env->tcs[i].CP0_TCHalt = 1;
332 }
333 env->active_tc.CP0_TCHalt = 1;
334 cs->halted = 1;
335
336 if (cs->cpu_index == 0) {
337 /* VPE0 starts up enabled. */
338 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
339 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
340
341 /* TC0 starts up unhalted. */
342 cs->halted = 0;
343 env->active_tc.CP0_TCHalt = 0;
344 env->tcs[0].CP0_TCHalt = 0;
345 /* With thread 0 active. */
346 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
347 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
348 }
349 }
350
351 /*
352 * Configure default legacy segmentation control. We use this regardless of
353 * whether segmentation control is presented to the guest.
354 */
355 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
356 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM);
357 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
358 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
359 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
360 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
361 (2 << CP0SC_C);
362 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
363 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
364 (3 << CP0SC_C)) << 16;
365 /* USeg (seg4 0x40000000..0x7FFFFFFF) */
366 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
367 (1 << CP0SC_EU) | (2 << CP0SC_C);
368 /* USeg (seg5 0x00000000..0x3FFFFFFF) */
369 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
370 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
371 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
372 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
373 #endif /* !CONFIG_USER_ONLY */
374 if ((env->insn_flags & ISA_MIPS_R6) &&
375 (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
376 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
377 env->CP0_Status |= (1 << CP0St_FR);
378 }
379
380 if (env->insn_flags & ISA_MIPS_R6) {
381 /* PTW = 1 */
382 env->CP0_PWSize = 0x40;
383 /* GDI = 12 */
384 /* UDI = 12 */
385 /* MDI = 12 */
386 /* PRI = 12 */
387 /* PTEI = 2 */
388 env->CP0_PWField = 0x0C30C302;
389 } else {
390 /* GDI = 0 */
391 /* UDI = 0 */
392 /* MDI = 0 */
393 /* PRI = 0 */
394 /* PTEI = 2 */
395 env->CP0_PWField = 0x02;
396 }
397
398 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
399 /* microMIPS on reset when Config3.ISA is 3 */
400 env->hflags |= MIPS_HFLAG_M16;
401 }
402
403 msa_reset(env);
404
405 compute_hflags(env);
406 restore_fp_status(env);
407 restore_pamask(env);
408 cs->exception_index = EXCP_NONE;
409
410 if (semihosting_get_argc()) {
411 /* UHI interface can be used to obtain argc and argv */
412 env->active_tc.gpr[4] = -1;
413 }
414
415 #ifndef CONFIG_USER_ONLY
416 if (kvm_enabled()) {
417 kvm_mips_reset_vcpu(cpu);
418 }
419 #endif
420 }
421
422 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
423 {
424 MIPSCPU *cpu = MIPS_CPU(s);
425 CPUMIPSState *env = &cpu->env;
426
427 if (!(env->insn_flags & ISA_NANOMIPS32)) {
428 #if TARGET_BIG_ENDIAN
429 info->print_insn = print_insn_big_mips;
430 #else
431 info->print_insn = print_insn_little_mips;
432 #endif
433 } else {
434 #if defined(CONFIG_NANOMIPS_DIS)
435 info->print_insn = print_insn_nanomips;
436 #endif
437 }
438 }
439
440 /*
441 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
442 */
443 #define CPU_FREQ_HZ_DEFAULT 200000000
444
445 static void mips_cp0_period_set(MIPSCPU *cpu)
446 {
447 CPUMIPSState *env = &cpu->env;
448
449 env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
450 env->cpu_model->CCRes);
451 assert(env->cp0_count_ns);
452 }
453
454 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
455 {
456 CPUState *cs = CPU(dev);
457 MIPSCPU *cpu = MIPS_CPU(dev);
458 CPUMIPSState *env = &cpu->env;
459 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
460 Error *local_err = NULL;
461
462 if (!clock_get(cpu->clock)) {
463 #ifndef CONFIG_USER_ONLY
464 if (!qtest_enabled()) {
465 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
466
467 warn_report("CPU input clock is not connected to any output clock, "
468 "using default frequency of %s.", cpu_freq_str);
469 }
470 #endif
471 /* Initialize the frequency in case the clock remains unconnected. */
472 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
473 }
474 mips_cp0_period_set(cpu);
475
476 cpu_exec_realizefn(cs, &local_err);
477 if (local_err != NULL) {
478 error_propagate(errp, local_err);
479 return;
480 }
481
482 env->exception_base = (int32_t)0xBFC00000;
483
484 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
485 mmu_init(env, env->cpu_model);
486 #endif
487 fpu_init(env, env->cpu_model);
488 mvp_init(env);
489
490 cpu_reset(cs);
491 qemu_init_vcpu(cs);
492
493 mcc->parent_realize(dev, errp);
494 }
495
496 static void mips_cpu_initfn(Object *obj)
497 {
498 MIPSCPU *cpu = MIPS_CPU(obj);
499 CPUMIPSState *env = &cpu->env;
500 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
501
502 cpu_set_cpustate_pointers(cpu);
503 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
504 env->cpu_model = mcc->cpu_def;
505 }
506
507 static char *mips_cpu_type_name(const char *cpu_model)
508 {
509 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
510 }
511
512 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
513 {
514 ObjectClass *oc;
515 char *typename;
516
517 typename = mips_cpu_type_name(cpu_model);
518 oc = object_class_by_name(typename);
519 g_free(typename);
520 return oc;
521 }
522
523 #ifndef CONFIG_USER_ONLY
524 #include "hw/core/sysemu-cpu-ops.h"
525
526 static const struct SysemuCPUOps mips_sysemu_ops = {
527 .get_phys_page_debug = mips_cpu_get_phys_page_debug,
528 .legacy_vmsd = &vmstate_mips_cpu,
529 };
530 #endif
531
532 #ifdef CONFIG_TCG
533 #include "hw/core/tcg-cpu-ops.h"
534 /*
535 * NB: cannot be const, as some elements are changed for specific
536 * mips hardware (see hw/mips/jazz.c).
537 */
538 static const struct TCGCPUOps mips_tcg_ops = {
539 .initialize = mips_tcg_init,
540 .synchronize_from_tb = mips_cpu_synchronize_from_tb,
541
542 #if !defined(CONFIG_USER_ONLY)
543 .tlb_fill = mips_cpu_tlb_fill,
544 .cpu_exec_interrupt = mips_cpu_exec_interrupt,
545 .do_interrupt = mips_cpu_do_interrupt,
546 .do_transaction_failed = mips_cpu_do_transaction_failed,
547 .do_unaligned_access = mips_cpu_do_unaligned_access,
548 .io_recompile_replay_branch = mips_io_recompile_replay_branch,
549 #endif /* !CONFIG_USER_ONLY */
550 };
551 #endif /* CONFIG_TCG */
552
553 static void mips_cpu_class_init(ObjectClass *c, void *data)
554 {
555 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
556 CPUClass *cc = CPU_CLASS(c);
557 DeviceClass *dc = DEVICE_CLASS(c);
558
559 device_class_set_parent_realize(dc, mips_cpu_realizefn,
560 &mcc->parent_realize);
561 device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
562
563 cc->class_by_name = mips_cpu_class_by_name;
564 cc->has_work = mips_cpu_has_work;
565 cc->dump_state = mips_cpu_dump_state;
566 cc->set_pc = mips_cpu_set_pc;
567 cc->get_pc = mips_cpu_get_pc;
568 cc->gdb_read_register = mips_cpu_gdb_read_register;
569 cc->gdb_write_register = mips_cpu_gdb_write_register;
570 #ifndef CONFIG_USER_ONLY
571 cc->sysemu_ops = &mips_sysemu_ops;
572 #endif
573 cc->disas_set_info = mips_cpu_disas_set_info;
574 cc->gdb_num_core_regs = 73;
575 cc->gdb_stop_before_watchpoint = true;
576 #ifdef CONFIG_TCG
577 cc->tcg_ops = &mips_tcg_ops;
578 #endif /* CONFIG_TCG */
579 }
580
581 static const TypeInfo mips_cpu_type_info = {
582 .name = TYPE_MIPS_CPU,
583 .parent = TYPE_CPU,
584 .instance_size = sizeof(MIPSCPU),
585 .instance_init = mips_cpu_initfn,
586 .abstract = true,
587 .class_size = sizeof(MIPSCPUClass),
588 .class_init = mips_cpu_class_init,
589 };
590
591 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
592 {
593 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
594 mcc->cpu_def = data;
595 }
596
597 static void mips_register_cpudef_type(const struct mips_def_t *def)
598 {
599 char *typename = mips_cpu_type_name(def->name);
600 TypeInfo ti = {
601 .name = typename,
602 .parent = TYPE_MIPS_CPU,
603 .class_init = mips_cpu_cpudef_class_init,
604 .class_data = (void *)def,
605 };
606
607 type_register(&ti);
608 g_free(typename);
609 }
610
611 static void mips_cpu_register_types(void)
612 {
613 int i;
614
615 type_register_static(&mips_cpu_type_info);
616 for (i = 0; i < mips_defs_number; i++) {
617 mips_register_cpudef_type(&mips_defs[i]);
618 }
619 }
620
621 type_init(mips_cpu_register_types)
622
623 static void mips_cpu_add_definition(gpointer data, gpointer user_data)
624 {
625 ObjectClass *oc = data;
626 CpuDefinitionInfoList **cpu_list = user_data;
627 CpuDefinitionInfo *info;
628 const char *typename;
629
630 typename = object_class_get_name(oc);
631 info = g_malloc0(sizeof(*info));
632 info->name = g_strndup(typename,
633 strlen(typename) - strlen("-" TYPE_MIPS_CPU));
634 info->q_typename = g_strdup(typename);
635
636 QAPI_LIST_PREPEND(*cpu_list, info);
637 }
638
639 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
640 {
641 CpuDefinitionInfoList *cpu_list = NULL;
642 GSList *list;
643
644 list = object_class_get_list(TYPE_MIPS_CPU, false);
645 g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
646 g_slist_free(list);
647
648 return cpu_list;
649 }
650
651 /* Could be used by generic CPU object */
652 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
653 {
654 DeviceState *cpu;
655
656 cpu = DEVICE(object_new(cpu_type));
657 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
658 qdev_realize(cpu, NULL, &error_abort);
659
660 return MIPS_CPU(cpu);
661 }
662
663 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
664 {
665 return (env->cpu_model->insn_flags & isa_mask) != 0;
666 }
667
668 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
669 {
670 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
671 return (mcc->cpu_def->insn_flags & isa) != 0;
672 }
673
674 bool cpu_type_supports_cps_smp(const char *cpu_type)
675 {
676 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
677 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
678 }
AR7 emulation for QEMU