hw/input/pckbd.c

   1 /*
   2  * QEMU PC keyboard emulation
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/log.h"
  28 #include "qemu/timer.h"
  29 #include "hw/isa/isa.h"
  30 #include "migration/vmstate.h"
  31 #include "hw/acpi/aml-build.h"
  32 #include "hw/input/ps2.h"
  33 #include "hw/irq.h"
  34 #include "hw/input/i8042.h"
  35 #include "hw/qdev-properties.h"
  36 #include "sysemu/reset.h"
  37 #include "sysemu/runstate.h"
  38
  39 #include "trace.h"
  40
  41 /*      Keyboard Controller Commands */
  42 #define KBD_CCMD_READ_MODE      0x20    /* Read mode bits */
  43 #define KBD_CCMD_WRITE_MODE     0x60    /* Write mode bits */
  44 #define KBD_CCMD_GET_VERSION    0xA1    /* Get controller version */
  45 #define KBD_CCMD_MOUSE_DISABLE  0xA7    /* Disable mouse interface */
  46 #define KBD_CCMD_MOUSE_ENABLE   0xA8    /* Enable mouse interface */
  47 #define KBD_CCMD_TEST_MOUSE     0xA9    /* Mouse interface test */
  48 #define KBD_CCMD_SELF_TEST      0xAA    /* Controller self test */
  49 #define KBD_CCMD_KBD_TEST       0xAB    /* Keyboard interface test */
  50 #define KBD_CCMD_KBD_DISABLE    0xAD    /* Keyboard interface disable */
  51 #define KBD_CCMD_KBD_ENABLE     0xAE    /* Keyboard interface enable */
  52 #define KBD_CCMD_READ_INPORT    0xC0    /* read input port */
  53 #define KBD_CCMD_READ_OUTPORT   0xD0    /* read output port */
  54 #define KBD_CCMD_WRITE_OUTPORT  0xD1    /* write output port */
  55 #define KBD_CCMD_WRITE_OBUF     0xD2
  56 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3    /* Write to output buffer as if
  57                                            initiated by the auxiliary device */
  58 #define KBD_CCMD_WRITE_MOUSE    0xD4    /* Write the following byte to the mouse */
  59 #define KBD_CCMD_DISABLE_A20    0xDD    /* HP vectra only ? */
  60 #define KBD_CCMD_ENABLE_A20     0xDF    /* HP vectra only ? */
  61 #define KBD_CCMD_PULSE_BITS_3_0 0xF0    /* Pulse bits 3-0 of the output port P2. */
  62 #define KBD_CCMD_RESET          0xFE    /* Pulse bit 0 of the output port P2 = CPU reset. */
  63 #define KBD_CCMD_NO_OP          0xFF    /* Pulse no bits of the output port P2. */
  64
  65 /* Keyboard Commands */
  66 #define KBD_CMD_SET_LEDS        0xED    /* Set keyboard leds */
  67 #define KBD_CMD_ECHO            0xEE
  68 #define KBD_CMD_GET_ID          0xF2    /* get keyboard ID */
  69 #define KBD_CMD_SET_RATE        0xF3    /* Set typematic rate */
  70 #define KBD_CMD_ENABLE          0xF4    /* Enable scanning */
  71 #define KBD_CMD_RESET_DISABLE   0xF5    /* reset and disable scanning */
  72 #define KBD_CMD_RESET_ENABLE    0xF6    /* reset and enable scanning */
  73 #define KBD_CMD_RESET           0xFF    /* Reset */
  74
  75 /* Keyboard Replies */
  76 #define KBD_REPLY_POR           0xAA    /* Power on reset */
  77 #define KBD_REPLY_ACK           0xFA    /* Command ACK */
  78 #define KBD_REPLY_RESEND        0xFE    /* Command NACK, send the cmd again */
  79
  80 /* Status Register Bits */
  81 #define KBD_STAT_OBF            0x01    /* Keyboard output buffer full */
  82 #define KBD_STAT_IBF            0x02    /* Keyboard input buffer full */
  83 #define KBD_STAT_SELFTEST       0x04    /* Self test successful */
  84 #define KBD_STAT_CMD            0x08    /* Last write was a command write (0=data) */
  85 #define KBD_STAT_UNLOCKED       0x10    /* Zero if keyboard locked */
  86 #define KBD_STAT_MOUSE_OBF      0x20    /* Mouse output buffer full */
  87 #define KBD_STAT_GTO            0x40    /* General receive/xmit timeout */
  88 #define KBD_STAT_PERR           0x80    /* Parity error */
  89
  90 /* Controller Mode Register Bits */
  91 #define KBD_MODE_KBD_INT        0x01    /* Keyboard data generate IRQ1 */
  92 #define KBD_MODE_MOUSE_INT      0x02    /* Mouse data generate IRQ12 */
  93 #define KBD_MODE_SYS            0x04    /* The system flag (?) */
  94 #define KBD_MODE_NO_KEYLOCK     0x08    /* The keylock doesn't affect the keyboard if set */
  95 #define KBD_MODE_DISABLE_KBD    0x10    /* Disable keyboard interface */
  96 #define KBD_MODE_DISABLE_MOUSE  0x20    /* Disable mouse interface */
  97 #define KBD_MODE_KCC            0x40    /* Scan code conversion to PC format */
  98 #define KBD_MODE_RFU            0x80
  99
 100 /* Output Port Bits */
 101 #define KBD_OUT_RESET           0x01    /* 1=normal mode, 0=reset */
 102 #define KBD_OUT_A20             0x02    /* x86 only */
 103 #define KBD_OUT_OBF             0x10    /* Keyboard output buffer full */
 104 #define KBD_OUT_MOUSE_OBF       0x20    /* Mouse output buffer full */
 105
 106 /* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
 107  * We make the default value of the outport include these four bits,
 108  * so that the subsection is rarely necessary.
 109  */
 110 #define KBD_OUT_ONES            0xcc
 111
 112 /* Mouse Commands */
 113 #define AUX_SET_SCALE11         0xE6    /* Set 1:1 scaling */
 114 #define AUX_SET_SCALE21         0xE7    /* Set 2:1 scaling */
 115 #define AUX_SET_RES             0xE8    /* Set resolution */
 116 #define AUX_GET_SCALE           0xE9    /* Get scaling factor */
 117 #define AUX_SET_STREAM          0xEA    /* Set stream mode */
 118 #define AUX_POLL                0xEB    /* Poll */
 119 #define AUX_RESET_WRAP          0xEC    /* Reset wrap mode */
 120 #define AUX_SET_WRAP            0xEE    /* Set wrap mode */
 121 #define AUX_SET_REMOTE          0xF0    /* Set remote mode */
 122 #define AUX_GET_TYPE            0xF2    /* Get type */
 123 #define AUX_SET_SAMPLE          0xF3    /* Set sample rate */
 124 #define AUX_ENABLE_DEV          0xF4    /* Enable aux device */
 125 #define AUX_DISABLE_DEV         0xF5    /* Disable aux device */
 126 #define AUX_SET_DEFAULT         0xF6
 127 #define AUX_RESET               0xFF    /* Reset aux device */
 128 #define AUX_ACK                 0xFA    /* Command byte ACK. */
 129
 130 #define MOUSE_STATUS_REMOTE     0x40
 131 #define MOUSE_STATUS_ENABLED    0x20
 132 #define MOUSE_STATUS_SCALE21    0x10
 133
 134 #define KBD_PENDING_KBD         1
 135 #define KBD_PENDING_AUX         2
 136 #define KBD_PENDING_CTRL_KBD    0x04
 137 #define KBD_PENDING_CTRL_AUX    0x08
 138
 139 #define KBD_MIGR_TIMER_PENDING  0x1
 140
 141 #define KBD_OBSRC_KBD           0x01
 142 #define KBD_OBSRC_MOUSE         0x02
 143 #define KBD_OBSRC_CTRL          0x04
 144
 145 typedef struct KBDState {
 146     uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
 147     uint8_t status;
 148     uint8_t mode;
 149     uint8_t outport;
 150     uint32_t migration_flags;
 151     uint32_t obsrc;
 152     bool outport_present;
 153     bool extended_state;
 154     bool extended_state_loaded;
 155     /* Bitmask of devices with data available.  */
 156     uint8_t pending;
 157     uint8_t obdata;
 158     uint8_t cbdata;
 159     void *kbd;
 160     void *mouse;
 161     QEMUTimer *throttle_timer;
 162
 163     qemu_irq irq_kbd;
 164     qemu_irq irq_mouse;
 165     qemu_irq a20_out;
 166     hwaddr mask;
 167 } KBDState;
 168
 169 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
 170    incorrect, but it avoids having to simulate exact delays */
 171 static void kbd_update_irq_lines(KBDState *s)
 172 {
 173     int irq_kbd_level, irq_mouse_level;
 174
 175     irq_kbd_level = 0;
 176     irq_mouse_level = 0;
 177
 178     if (s->status & KBD_STAT_OBF) {
 179         if (s->status & KBD_STAT_MOUSE_OBF) {
 180             if (s->mode & KBD_MODE_MOUSE_INT) {
 181                 irq_mouse_level = 1;
 182             }
 183         } else {
 184             if ((s->mode & KBD_MODE_KBD_INT) &&
 185                 !(s->mode & KBD_MODE_DISABLE_KBD)) {
 186                 irq_kbd_level = 1;
 187             }
 188         }
 189     }
 190     qemu_set_irq(s->irq_kbd, irq_kbd_level);
 191     qemu_set_irq(s->irq_mouse, irq_mouse_level);
 192 }
 193
 194 static void kbd_deassert_irq(KBDState *s)
 195 {
 196     s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
 197     s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
 198     kbd_update_irq_lines(s);
 199 }
 200
 201 static uint8_t kbd_pending(KBDState *s)
 202 {
 203     return s->pending;
 204 }
 205
 206 /* update irq and KBD_STAT_[MOUSE_]OBF */
 207 static void kbd_update_irq(KBDState *s)
 208 {
 209     uint8_t pending = kbd_pending(s);
 210
 211     s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
 212     s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
 213     if (pending) {
 214         s->status |= KBD_STAT_OBF;
 215         s->outport |= KBD_OUT_OBF;
 216         if (pending & KBD_PENDING_CTRL_KBD) {
 217             s->obsrc = KBD_OBSRC_CTRL;
 218         } else if (pending & KBD_PENDING_CTRL_AUX) {
 219             s->status |= KBD_STAT_MOUSE_OBF;
 220             s->outport |= KBD_OUT_MOUSE_OBF;
 221             s->obsrc = KBD_OBSRC_CTRL;
 222         } else if (pending & KBD_PENDING_KBD) {
 223             s->obsrc = KBD_OBSRC_KBD;
 224         } else {
 225             s->status |= KBD_STAT_MOUSE_OBF;
 226             s->outport |= KBD_OUT_MOUSE_OBF;
 227             s->obsrc = KBD_OBSRC_MOUSE;
 228         }
 229     }
 230     kbd_update_irq_lines(s);
 231 }
 232
 233 static void kbd_safe_update_irq(KBDState *s)
 234 {
 235     /*
 236      * with KBD_STAT_OBF set, a call to kbd_read_data() will eventually call
 237      * kbd_update_irq()
 238      */
 239     if (s->status & KBD_STAT_OBF) {
 240         return;
 241     }
 242     /* the throttle timer is pending and will call kbd_update_irq() */
 243     if (s->throttle_timer && timer_pending(s->throttle_timer)) {
 244         return;
 245     }
 246     if (kbd_pending(s)) {
 247         kbd_update_irq(s);
 248     }
 249 }
 250
 251 static void kbd_update_kbd_irq(void *opaque, int level)
 252 {
 253     KBDState *s = opaque;
 254
 255     if (level) {
 256         s->pending |= KBD_PENDING_KBD;
 257     } else {
 258         s->pending &= ~KBD_PENDING_KBD;
 259     }
 260     kbd_safe_update_irq(s);
 261 }
 262
 263 static void kbd_update_aux_irq(void *opaque, int level)
 264 {
 265     KBDState *s = opaque;
 266
 267     if (level) {
 268         s->pending |= KBD_PENDING_AUX;
 269     } else {
 270         s->pending &= ~KBD_PENDING_AUX;
 271     }
 272     kbd_safe_update_irq(s);
 273 }
 274
 275 static void kbd_throttle_timeout(void *opaque)
 276 {
 277     KBDState *s = opaque;
 278
 279     if (kbd_pending(s)) {
 280         kbd_update_irq(s);
 281     }
 282 }
 283
 284 static uint64_t kbd_read_status(void *opaque, hwaddr addr,
 285                                 unsigned size)
 286 {
 287     KBDState *s = opaque;
 288     int val;
 289     val = s->status;
 290     trace_pckbd_kbd_read_status(val);
 291     return val;
 292 }
 293
 294 static void kbd_queue(KBDState *s, int b, int aux)
 295 {
 296     if (s->extended_state) {
 297         s->cbdata = b;
 298         s->pending &= ~KBD_PENDING_CTRL_KBD & ~KBD_PENDING_CTRL_AUX;
 299         s->pending |= aux ? KBD_PENDING_CTRL_AUX : KBD_PENDING_CTRL_KBD;
 300         kbd_safe_update_irq(s);
 301     } else {
 302         ps2_queue(aux ? s->mouse : s->kbd, b);
 303     }
 304 }
 305
 306 static uint8_t kbd_dequeue(KBDState *s)
 307 {
 308     uint8_t b = s->cbdata;
 309
 310     s->pending &= ~KBD_PENDING_CTRL_KBD & ~KBD_PENDING_CTRL_AUX;
 311     if (kbd_pending(s)) {
 312         kbd_update_irq(s);
 313     }
 314     return b;
 315 }
 316
 317 static void outport_write(KBDState *s, uint32_t val)
 318 {
 319     trace_pckbd_outport_write(val);
 320     s->outport = val;
 321     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 322     if (!(val & 1)) {
 323         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 324     }
 325 }
 326
 327 static void kbd_write_command(void *opaque, hwaddr addr,
 328                               uint64_t val, unsigned size)
 329 {
 330     KBDState *s = opaque;
 331
 332     trace_pckbd_kbd_write_command(val);
 333
 334     /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
 335      * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
 336      * command specify the output port bits to be pulsed.
 337      * 0: Bit should be pulsed. 1: Bit should not be modified.
 338      * The only useful version of this command is pulsing bit 0,
 339      * which does a CPU reset.
 340      */
 341     if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
 342         if(!(val & 1))
 343             val = KBD_CCMD_RESET;
 344         else
 345             val = KBD_CCMD_NO_OP;
 346     }
 347
 348     switch(val) {
 349     case KBD_CCMD_READ_MODE:
 350         kbd_queue(s, s->mode, 0);
 351         break;
 352     case KBD_CCMD_WRITE_MODE:
 353     case KBD_CCMD_WRITE_OBUF:
 354     case KBD_CCMD_WRITE_AUX_OBUF:
 355     case KBD_CCMD_WRITE_MOUSE:
 356     case KBD_CCMD_WRITE_OUTPORT:
 357         s->write_cmd = val;
 358         break;
 359     case KBD_CCMD_MOUSE_DISABLE:
 360         s->mode |= KBD_MODE_DISABLE_MOUSE;
 361         break;
 362     case KBD_CCMD_MOUSE_ENABLE:
 363         s->mode &= ~KBD_MODE_DISABLE_MOUSE;
 364         break;
 365     case KBD_CCMD_TEST_MOUSE:
 366         kbd_queue(s, 0x00, 0);
 367         break;
 368     case KBD_CCMD_SELF_TEST:
 369         s->status |= KBD_STAT_SELFTEST;
 370         kbd_queue(s, 0x55, 0);
 371         break;
 372     case KBD_CCMD_KBD_TEST:
 373         kbd_queue(s, 0x00, 0);
 374         break;
 375     case KBD_CCMD_KBD_DISABLE:
 376         s->mode |= KBD_MODE_DISABLE_KBD;
 377         break;
 378     case KBD_CCMD_KBD_ENABLE:
 379         s->mode &= ~KBD_MODE_DISABLE_KBD;
 380         kbd_safe_update_irq(s);
 381         break;
 382     case KBD_CCMD_READ_INPORT:
 383         kbd_queue(s, 0x80, 0);
 384         break;
 385     case KBD_CCMD_READ_OUTPORT:
 386         kbd_queue(s, s->outport, 0);
 387         break;
 388     case KBD_CCMD_ENABLE_A20:
 389         qemu_irq_raise(s->a20_out);
 390         s->outport |= KBD_OUT_A20;
 391         break;
 392     case KBD_CCMD_DISABLE_A20:
 393         qemu_irq_lower(s->a20_out);
 394         s->outport &= ~KBD_OUT_A20;
 395         break;
 396     case KBD_CCMD_RESET:
 397         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 398         break;
 399     case KBD_CCMD_NO_OP:
 400         /* ignore that */
 401         break;
 402     default:
 403         qemu_log_mask(LOG_GUEST_ERROR,
 404                       "unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
 405         break;
 406     }
 407 }
 408
 409 static uint64_t kbd_read_data(void *opaque, hwaddr addr,
 410                               unsigned size)
 411 {
 412     KBDState *s = opaque;
 413
 414     if (s->status & KBD_STAT_OBF) {
 415         kbd_deassert_irq(s);
 416         if (s->obsrc & KBD_OBSRC_KBD) {
 417             if (s->throttle_timer) {
 418                 timer_mod(s->throttle_timer,
 419                           qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) + 1000);
 420             }
 421             s->obdata = ps2_read_data(s->kbd);
 422         } else if (s->obsrc & KBD_OBSRC_MOUSE) {
 423             s->obdata = ps2_read_data(s->mouse);
 424         } else if (s->obsrc & KBD_OBSRC_CTRL) {
 425             s->obdata = kbd_dequeue(s);
 426         }
 427     }
 428
 429     trace_pckbd_kbd_read_data(s->obdata);
 430     return s->obdata;
 431 }
 432
 433 static void kbd_write_data(void *opaque, hwaddr addr,
 434                            uint64_t val, unsigned size)
 435 {
 436     KBDState *s = opaque;
 437
 438     trace_pckbd_kbd_write_data(val);
 439
 440     switch(s->write_cmd) {
 441     case 0:
 442         ps2_write_keyboard(s->kbd, val);
 443         break;
 444     case KBD_CCMD_WRITE_MODE:
 445         s->mode = val;
 446         ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
 447         /*
 448          * a write to the mode byte interrupt enable flags directly updates
 449          * the irq lines
 450          */
 451         kbd_update_irq_lines(s);
 452         /*
 453          * a write to the mode byte disable interface flags may raise
 454          * an irq if there is pending data in the PS/2 queues.
 455          */
 456         kbd_safe_update_irq(s);
 457         break;
 458     case KBD_CCMD_WRITE_OBUF:
 459         kbd_queue(s, val, 0);
 460         break;
 461     case KBD_CCMD_WRITE_AUX_OBUF:
 462         kbd_queue(s, val, 1);
 463         break;
 464     case KBD_CCMD_WRITE_OUTPORT:
 465         outport_write(s, val);
 466         break;
 467     case KBD_CCMD_WRITE_MOUSE:
 468         ps2_write_mouse(s->mouse, val);
 469         break;
 470     default:
 471         break;
 472     }
 473     s->write_cmd = 0;
 474 }
 475
 476 static void kbd_reset(void *opaque)
 477 {
 478     KBDState *s = opaque;
 479
 480     s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
 481     s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
 482     s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES;
 483     s->outport_present = false;
 484     s->pending = 0;
 485     kbd_deassert_irq(s);
 486     if (s->throttle_timer) {
 487         timer_del(s->throttle_timer);
 488     }
 489 }
 490
 491 static uint8_t kbd_outport_default(KBDState *s)
 492 {
 493     return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES
 494            | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
 495            | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
 496 }
 497
 498 static int kbd_outport_post_load(void *opaque, int version_id)
 499 {
 500     KBDState *s = opaque;
 501     s->outport_present = true;
 502     return 0;
 503 }
 504
 505 static bool kbd_outport_needed(void *opaque)
 506 {
 507     KBDState *s = opaque;
 508     return s->outport != kbd_outport_default(s);
 509 }
 510
 511 static const VMStateDescription vmstate_kbd_outport = {
 512     .name = "pckbd_outport",
 513     .version_id = 1,
 514     .minimum_version_id = 1,
 515     .post_load = kbd_outport_post_load,
 516     .needed = kbd_outport_needed,
 517     .fields = (VMStateField[]) {
 518         VMSTATE_UINT8(outport, KBDState),
 519         VMSTATE_END_OF_LIST()
 520     }
 521 };
 522
 523 static int kbd_extended_state_pre_save(void *opaque)
 524 {
 525     KBDState *s = opaque;
 526
 527     s->migration_flags = 0;
 528     if (s->throttle_timer && timer_pending(s->throttle_timer)) {
 529         s->migration_flags |= KBD_MIGR_TIMER_PENDING;
 530     }
 531
 532     return 0;
 533 }
 534
 535 static int kbd_extended_state_post_load(void *opaque, int version_id)
 536 {
 537     KBDState *s = opaque;
 538
 539     if (s->migration_flags & KBD_MIGR_TIMER_PENDING) {
 540         kbd_throttle_timeout(s);
 541     }
 542     s->extended_state_loaded = true;
 543
 544     return 0;
 545 }
 546
 547 static bool kbd_extended_state_needed(void *opaque)
 548 {
 549     KBDState *s = opaque;
 550
 551     return s->extended_state;
 552 }
 553
 554 static const VMStateDescription vmstate_kbd_extended_state = {
 555     .name = "pckbd/extended_state",
 556     .post_load = kbd_extended_state_post_load,
 557     .pre_save = kbd_extended_state_pre_save,
 558     .needed = kbd_extended_state_needed,
 559     .fields = (VMStateField[]) {
 560         VMSTATE_UINT32(migration_flags, KBDState),
 561         VMSTATE_UINT32(obsrc, KBDState),
 562         VMSTATE_UINT8(obdata, KBDState),
 563         VMSTATE_UINT8(cbdata, KBDState),
 564         VMSTATE_END_OF_LIST()
 565     }
 566 };
 567
 568 static int kbd_pre_load(void *opaque)
 569 {
 570     KBDState *s = opaque;
 571
 572     s->extended_state_loaded = false;
 573     return 0;
 574 }
 575
 576 static int kbd_post_load(void *opaque, int version_id)
 577 {
 578     KBDState *s = opaque;
 579     if (!s->outport_present) {
 580         s->outport = kbd_outport_default(s);
 581     }
 582     s->outport_present = false;
 583     if (!s->extended_state_loaded) {
 584         s->obsrc = s->status & KBD_STAT_OBF ?
 585             (s->status & KBD_STAT_MOUSE_OBF ? KBD_OBSRC_MOUSE : KBD_OBSRC_KBD) :
 586             0;
 587     }
 588     return 0;
 589 }
 590
 591 static const VMStateDescription vmstate_kbd = {
 592     .name = "pckbd",
 593     .version_id = 3,
 594     .minimum_version_id = 3,
 595     .pre_load = kbd_pre_load,
 596     .post_load = kbd_post_load,
 597     .fields = (VMStateField[]) {
 598         VMSTATE_UINT8(write_cmd, KBDState),
 599         VMSTATE_UINT8(status, KBDState),
 600         VMSTATE_UINT8(mode, KBDState),
 601         VMSTATE_UINT8(pending, KBDState),
 602         VMSTATE_END_OF_LIST()
 603     },
 604     .subsections = (const VMStateDescription*[]) {
 605         &vmstate_kbd_outport,
 606         &vmstate_kbd_extended_state,
 607         NULL
 608     }
 609 };
 610
 611 /* Memory mapped interface */
 612 static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
 613 {
 614     KBDState *s = opaque;
 615
 616     if (addr & s->mask)
 617         return kbd_read_status(s, 0, 1) & 0xff;
 618     else
 619         return kbd_read_data(s, 0, 1) & 0xff;
 620 }
 621
 622 static void kbd_mm_writefn(void *opaque, hwaddr addr,
 623                            uint64_t value, unsigned size)
 624 {
 625     KBDState *s = opaque;
 626
 627     if (addr & s->mask)
 628         kbd_write_command(s, 0, value & 0xff, 1);
 629     else
 630         kbd_write_data(s, 0, value & 0xff, 1);
 631 }
 632
 633
 634 static const MemoryRegionOps i8042_mmio_ops = {
 635     .read = kbd_mm_readfn,
 636     .write = kbd_mm_writefn,
 637     .valid.min_access_size = 1,
 638     .valid.max_access_size = 4,
 639     .endianness = DEVICE_NATIVE_ENDIAN,
 640 };
 641
 642 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 643                    MemoryRegion *region, ram_addr_t size,
 644                    hwaddr mask)
 645 {
 646     KBDState *s = g_malloc0(sizeof(KBDState));
 647
 648     s->irq_kbd = kbd_irq;
 649     s->irq_mouse = mouse_irq;
 650     s->mask = mask;
 651
 652     s->extended_state = true;
 653
 654     vmstate_register(NULL, 0, &vmstate_kbd, s);
 655
 656     memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
 657
 658     s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
 659     s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
 660     qemu_register_reset(kbd_reset, s);
 661 }
 662
 663 struct ISAKBDState {
 664     ISADevice parent_obj;
 665
 666     KBDState kbd;
 667     bool kbd_throttle;
 668     MemoryRegion io[2];
 669 };
 670
 671 void i8042_isa_mouse_fake_event(ISAKBDState *isa)
 672 {
 673     KBDState *s = &isa->kbd;
 674
 675     ps2_mouse_fake_event(s->mouse);
 676 }
 677
 678 void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
 679 {
 680     qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
 681 }
 682
 683 static const VMStateDescription vmstate_kbd_isa = {
 684     .name = "pckbd",
 685     .version_id = 3,
 686     .minimum_version_id = 3,
 687     .fields = (VMStateField[]) {
 688         VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
 689         VMSTATE_END_OF_LIST()
 690     }
 691 };
 692
 693 static const MemoryRegionOps i8042_data_ops = {
 694     .read = kbd_read_data,
 695     .write = kbd_write_data,
 696     .impl = {
 697         .min_access_size = 1,
 698         .max_access_size = 1,
 699     },
 700     .endianness = DEVICE_LITTLE_ENDIAN,
 701 };
 702
 703 static const MemoryRegionOps i8042_cmd_ops = {
 704     .read = kbd_read_status,
 705     .write = kbd_write_command,
 706     .impl = {
 707         .min_access_size = 1,
 708         .max_access_size = 1,
 709     },
 710     .endianness = DEVICE_LITTLE_ENDIAN,
 711 };
 712
 713 static void i8042_initfn(Object *obj)
 714 {
 715     ISAKBDState *isa_s = I8042(obj);
 716     KBDState *s = &isa_s->kbd;
 717
 718     memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
 719                           "i8042-data", 1);
 720     memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
 721                           "i8042-cmd", 1);
 722
 723     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
 724 }
 725
 726 static void i8042_realizefn(DeviceState *dev, Error **errp)
 727 {
 728     ISADevice *isadev = ISA_DEVICE(dev);
 729     ISAKBDState *isa_s = I8042(dev);
 730     KBDState *s = &isa_s->kbd;
 731
 732     isa_init_irq(isadev, &s->irq_kbd, 1);
 733     isa_init_irq(isadev, &s->irq_mouse, 12);
 734
 735     isa_register_ioport(isadev, isa_s->io + 0, 0x60);
 736     isa_register_ioport(isadev, isa_s->io + 1, 0x64);
 737
 738     s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
 739     s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
 740     if (isa_s->kbd_throttle && !isa_s->kbd.extended_state) {
 741         warn_report(TYPE_I8042 ": can't enable kbd-throttle without"
 742                     " extended-state, disabling kbd-throttle");
 743     } else if (isa_s->kbd_throttle) {
 744         s->throttle_timer = timer_new_us(QEMU_CLOCK_VIRTUAL,
 745                                          kbd_throttle_timeout, s);
 746     }
 747     qemu_register_reset(kbd_reset, s);
 748 }
 749
 750 static void i8042_build_aml(ISADevice *isadev, Aml *scope)
 751 {
 752     Aml *kbd;
 753     Aml *mou;
 754     Aml *crs;
 755
 756     crs = aml_resource_template();
 757     aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
 758     aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
 759     aml_append(crs, aml_irq_no_flags(1));
 760
 761     kbd = aml_device("KBD");
 762     aml_append(kbd, aml_name_decl("_HID", aml_eisaid("PNP0303")));
 763     aml_append(kbd, aml_name_decl("_STA", aml_int(0xf)));
 764     aml_append(kbd, aml_name_decl("_CRS", crs));
 765
 766     crs = aml_resource_template();
 767     aml_append(crs, aml_irq_no_flags(12));
 768
 769     mou = aml_device("MOU");
 770     aml_append(mou, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
 771     aml_append(mou, aml_name_decl("_STA", aml_int(0xf)));
 772     aml_append(mou, aml_name_decl("_CRS", crs));
 773
 774     aml_append(scope, kbd);
 775     aml_append(scope, mou);
 776 }
 777
 778 static Property i8042_properties[] = {
 779     DEFINE_PROP_BOOL("extended-state", ISAKBDState, kbd.extended_state, true),
 780     DEFINE_PROP_BOOL("kbd-throttle", ISAKBDState, kbd_throttle, false),
 781     DEFINE_PROP_END_OF_LIST(),
 782 };
 783
 784 static void i8042_class_initfn(ObjectClass *klass, void *data)
 785 {
 786     DeviceClass *dc = DEVICE_CLASS(klass);
 787     ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
 788
 789     device_class_set_props(dc, i8042_properties);
 790     dc->realize = i8042_realizefn;
 791     dc->vmsd = &vmstate_kbd_isa;
 792     isa->build_aml = i8042_build_aml;
 793     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 794 }
 795
 796 static const TypeInfo i8042_info = {
 797     .name          = TYPE_I8042,
 798     .parent        = TYPE_ISA_DEVICE,
 799     .instance_size = sizeof(ISAKBDState),
 800     .instance_init = i8042_initfn,
 801     .class_init    = i8042_class_initfn,
 802 };
 803
 804 static void i8042_register_types(void)
 805 {
 806     type_register_static(&i8042_info);
 807 }
 808
 809 type_init(i8042_register_types)