8 #include "qemu-common.h"
9 #include "host-utils.h"
10 #if !defined(CONFIG_USER_ONLY)
11 #include "hw/loader.h"
14 static uint32_t cortexa9_cp15_c0_c1
[8] =
15 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
17 static uint32_t cortexa9_cp15_c0_c2
[8] =
18 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
20 static uint32_t cortexa8_cp15_c0_c1
[8] =
21 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
23 static uint32_t cortexa8_cp15_c0_c2
[8] =
24 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
26 static uint32_t mpcore_cp15_c0_c1
[8] =
27 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
29 static uint32_t mpcore_cp15_c0_c2
[8] =
30 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
32 static uint32_t arm1136_cp15_c0_c1
[8] =
33 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
35 static uint32_t arm1136_cp15_c0_c2
[8] =
36 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
38 static uint32_t arm1176_cp15_c0_c1
[8] =
39 { 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
41 static uint32_t arm1176_cp15_c0_c2
[8] =
42 { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
44 static uint32_t cpu_arm_find_by_name(const char *name
);
46 static inline void set_feature(CPUARMState
*env
, int feature
)
48 env
->features
|= 1u << feature
;
51 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
53 env
->cp15
.c0_cpuid
= id
;
55 case ARM_CPUID_ARM926
:
56 set_feature(env
, ARM_FEATURE_V5
);
57 set_feature(env
, ARM_FEATURE_VFP
);
58 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
59 env
->cp15
.c0_cachetype
= 0x1dd20d2;
60 env
->cp15
.c1_sys
= 0x00090078;
62 case ARM_CPUID_ARM946
:
63 set_feature(env
, ARM_FEATURE_V5
);
64 set_feature(env
, ARM_FEATURE_MPU
);
65 env
->cp15
.c0_cachetype
= 0x0f004006;
66 env
->cp15
.c1_sys
= 0x00000078;
68 case ARM_CPUID_ARM1026
:
69 set_feature(env
, ARM_FEATURE_V5
);
70 set_feature(env
, ARM_FEATURE_VFP
);
71 set_feature(env
, ARM_FEATURE_AUXCR
);
72 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
73 env
->cp15
.c0_cachetype
= 0x1dd20d2;
74 env
->cp15
.c1_sys
= 0x00090078;
76 case ARM_CPUID_ARM1136
:
77 /* This is the 1136 r1, which is a v6K core */
78 set_feature(env
, ARM_FEATURE_V6K
);
80 case ARM_CPUID_ARM1136_R2
:
81 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
82 * older core than plain "arm1136". In particular this does not
83 * have the v6K features.
85 set_feature(env
, ARM_FEATURE_V6
);
86 set_feature(env
, ARM_FEATURE_VFP
);
87 /* These ID register values are correct for 1136 but may be wrong
88 * for 1136_r2 (in particular r0p2 does not actually implement most
89 * of the ID registers).
91 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
92 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
93 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
94 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
95 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
96 env
->cp15
.c0_cachetype
= 0x1dd20d2;
97 env
->cp15
.c1_sys
= 0x00050078;
99 case ARM_CPUID_ARM1176
:
100 set_feature(env
, ARM_FEATURE_V6K
);
101 set_feature(env
, ARM_FEATURE_VFP
);
102 set_feature(env
, ARM_FEATURE_VAPA
);
103 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b5;
104 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
105 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
106 memcpy(env
->cp15
.c0_c1
, arm1176_cp15_c0_c1
, 8 * sizeof(uint32_t));
107 memcpy(env
->cp15
.c0_c2
, arm1176_cp15_c0_c2
, 8 * sizeof(uint32_t));
108 env
->cp15
.c0_cachetype
= 0x1dd20d2;
109 env
->cp15
.c1_sys
= 0x00050078;
111 case ARM_CPUID_ARM11MPCORE
:
112 set_feature(env
, ARM_FEATURE_V6K
);
113 set_feature(env
, ARM_FEATURE_VFP
);
114 set_feature(env
, ARM_FEATURE_VAPA
);
115 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
116 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
117 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
118 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
119 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
120 env
->cp15
.c0_cachetype
= 0x1dd20d2;
122 case ARM_CPUID_CORTEXA8
:
123 set_feature(env
, ARM_FEATURE_V7
);
124 set_feature(env
, ARM_FEATURE_VFP3
);
125 set_feature(env
, ARM_FEATURE_NEON
);
126 set_feature(env
, ARM_FEATURE_THUMB2EE
);
127 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
128 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
129 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
130 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
131 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
132 env
->cp15
.c0_cachetype
= 0x82048004;
133 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
134 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
135 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
136 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
137 env
->cp15
.c1_sys
= 0x00c50078;
139 case ARM_CPUID_CORTEXA9
:
140 set_feature(env
, ARM_FEATURE_V7
);
141 set_feature(env
, ARM_FEATURE_VFP3
);
142 set_feature(env
, ARM_FEATURE_VFP_FP16
);
143 set_feature(env
, ARM_FEATURE_NEON
);
144 set_feature(env
, ARM_FEATURE_THUMB2EE
);
145 /* Note that A9 supports the MP extensions even for
146 * A9UP and single-core A9MP (which are both different
147 * and valid configurations; we don't model A9UP).
149 set_feature(env
, ARM_FEATURE_V7MP
);
150 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41034000; /* Guess */
151 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
152 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x01111111;
153 memcpy(env
->cp15
.c0_c1
, cortexa9_cp15_c0_c1
, 8 * sizeof(uint32_t));
154 memcpy(env
->cp15
.c0_c2
, cortexa9_cp15_c0_c2
, 8 * sizeof(uint32_t));
155 env
->cp15
.c0_cachetype
= 0x80038003;
156 env
->cp15
.c0_clid
= (1 << 27) | (1 << 24) | 3;
157 env
->cp15
.c0_ccsid
[0] = 0xe00fe015; /* 16k L1 dcache. */
158 env
->cp15
.c0_ccsid
[1] = 0x200fe015; /* 16k L1 icache. */
159 env
->cp15
.c1_sys
= 0x00c50078;
161 case ARM_CPUID_CORTEXM3
:
162 set_feature(env
, ARM_FEATURE_V7
);
163 set_feature(env
, ARM_FEATURE_M
);
165 case ARM_CPUID_ANY
: /* For userspace emulation. */
166 set_feature(env
, ARM_FEATURE_V7
);
167 set_feature(env
, ARM_FEATURE_VFP4
);
168 set_feature(env
, ARM_FEATURE_VFP_FP16
);
169 set_feature(env
, ARM_FEATURE_NEON
);
170 set_feature(env
, ARM_FEATURE_THUMB2EE
);
171 set_feature(env
, ARM_FEATURE_ARM_DIV
);
172 set_feature(env
, ARM_FEATURE_V7MP
);
174 case ARM_CPUID_TI915T
:
175 case ARM_CPUID_TI925T
:
176 set_feature(env
, ARM_FEATURE_V4T
);
177 set_feature(env
, ARM_FEATURE_OMAPCP
);
178 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
179 env
->cp15
.c0_cachetype
= 0x5109149;
180 env
->cp15
.c1_sys
= 0x00000070;
181 env
->cp15
.c15_i_max
= 0x000;
182 env
->cp15
.c15_i_min
= 0xff0;
184 case ARM_CPUID_PXA250
:
185 case ARM_CPUID_PXA255
:
186 case ARM_CPUID_PXA260
:
187 case ARM_CPUID_PXA261
:
188 case ARM_CPUID_PXA262
:
189 set_feature(env
, ARM_FEATURE_V5
);
190 set_feature(env
, ARM_FEATURE_XSCALE
);
191 /* JTAG_ID is ((id << 28) | 0x09265013) */
192 env
->cp15
.c0_cachetype
= 0xd172172;
193 env
->cp15
.c1_sys
= 0x00000078;
195 case ARM_CPUID_PXA270_A0
:
196 case ARM_CPUID_PXA270_A1
:
197 case ARM_CPUID_PXA270_B0
:
198 case ARM_CPUID_PXA270_B1
:
199 case ARM_CPUID_PXA270_C0
:
200 case ARM_CPUID_PXA270_C5
:
201 set_feature(env
, ARM_FEATURE_V5
);
202 set_feature(env
, ARM_FEATURE_XSCALE
);
203 /* JTAG_ID is ((id << 28) | 0x09265013) */
204 set_feature(env
, ARM_FEATURE_IWMMXT
);
205 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
206 env
->cp15
.c0_cachetype
= 0xd172172;
207 env
->cp15
.c1_sys
= 0x00000078;
209 case ARM_CPUID_SA1100
:
210 case ARM_CPUID_SA1110
:
211 set_feature(env
, ARM_FEATURE_STRONGARM
);
212 env
->cp15
.c1_sys
= 0x00000070;
215 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
219 /* Some features automatically imply others: */
220 if (arm_feature(env
, ARM_FEATURE_V7
)) {
221 set_feature(env
, ARM_FEATURE_VAPA
);
222 set_feature(env
, ARM_FEATURE_THUMB2
);
223 if (!arm_feature(env
, ARM_FEATURE_M
)) {
224 set_feature(env
, ARM_FEATURE_V6K
);
226 set_feature(env
, ARM_FEATURE_V6
);
229 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
230 set_feature(env
, ARM_FEATURE_V6
);
232 if (arm_feature(env
, ARM_FEATURE_V6
)) {
233 set_feature(env
, ARM_FEATURE_V5
);
234 if (!arm_feature(env
, ARM_FEATURE_M
)) {
235 set_feature(env
, ARM_FEATURE_AUXCR
);
238 if (arm_feature(env
, ARM_FEATURE_V5
)) {
239 set_feature(env
, ARM_FEATURE_V4T
);
241 if (arm_feature(env
, ARM_FEATURE_M
)) {
242 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
244 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
245 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
247 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
248 set_feature(env
, ARM_FEATURE_VFP3
);
250 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
251 set_feature(env
, ARM_FEATURE_VFP
);
255 void cpu_reset(CPUARMState
*env
)
259 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
260 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
261 log_cpu_state(env
, 0);
264 id
= env
->cp15
.c0_cpuid
;
265 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
267 cpu_reset_model_id(env
, id
);
268 #if defined (CONFIG_USER_ONLY)
269 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
270 /* For user mode we must enable access to coprocessors */
271 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
272 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
273 env
->cp15
.c15_cpar
= 3;
274 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
275 env
->cp15
.c15_cpar
= 1;
278 /* SVC mode with interrupts disabled. */
279 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
280 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
281 clear at reset. Initial SP and PC are loaded from ROM. */
285 env
->uncached_cpsr
&= ~CPSR_I
;
288 /* We should really use ldl_phys here, in case the guest
289 modified flash and reset itself. However images
290 loaded via -kernel have not been copied yet, so load the
291 values directly from there. */
292 env
->regs
[13] = ldl_p(rom
);
295 env
->regs
[15] = pc
& ~1;
298 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
299 env
->cp15
.c2_base_mask
= 0xffffc000u
;
300 /* v7 performance monitor control register: same implementor
301 * field as main ID register, and we implement no event counters.
303 env
->cp15
.c9_pmcr
= (id
& 0xff000000);
305 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
306 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
307 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
308 set_float_detect_tininess(float_tininess_before_rounding
,
309 &env
->vfp
.fp_status
);
310 set_float_detect_tininess(float_tininess_before_rounding
,
311 &env
->vfp
.standard_fp_status
);
315 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
319 /* VFP data registers are always little-endian. */
320 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
322 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
325 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
326 /* Aliases for Q regs. */
329 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
330 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
334 switch (reg
- nregs
) {
335 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
336 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
337 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
342 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
346 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
348 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
351 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
354 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
355 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
359 switch (reg
- nregs
) {
360 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
361 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
362 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
367 CPUARMState
*cpu_arm_init(const char *cpu_model
)
371 static int inited
= 0;
373 id
= cpu_arm_find_by_name(cpu_model
);
376 env
= g_malloc0(sizeof(CPUARMState
));
378 if (tcg_enabled() && !inited
) {
380 arm_translate_init();
383 env
->cpu_model_str
= cpu_model
;
384 env
->cp15
.c0_cpuid
= id
;
386 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
387 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
388 51, "arm-neon.xml", 0);
389 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
390 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
391 35, "arm-vfp3.xml", 0);
392 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
393 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
394 19, "arm-vfp.xml", 0);
405 static const struct arm_cpu_t arm_cpu_names
[] = {
406 { ARM_CPUID_ARM926
, "arm926"},
407 { ARM_CPUID_ARM946
, "arm946"},
408 { ARM_CPUID_ARM1026
, "arm1026"},
409 { ARM_CPUID_ARM1136
, "arm1136"},
410 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
411 { ARM_CPUID_ARM1176
, "arm1176"},
412 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
413 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
414 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
415 { ARM_CPUID_CORTEXA9
, "cortex-a9"},
416 { ARM_CPUID_TI925T
, "ti925t" },
417 { ARM_CPUID_PXA250
, "pxa250" },
418 { ARM_CPUID_SA1100
, "sa1100" },
419 { ARM_CPUID_SA1110
, "sa1110" },
420 { ARM_CPUID_PXA255
, "pxa255" },
421 { ARM_CPUID_PXA260
, "pxa260" },
422 { ARM_CPUID_PXA261
, "pxa261" },
423 { ARM_CPUID_PXA262
, "pxa262" },
424 { ARM_CPUID_PXA270
, "pxa270" },
425 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
426 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
427 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
428 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
429 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
430 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
431 { ARM_CPUID_ANY
, "any"},
435 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
439 (*cpu_fprintf
)(f
, "Available CPUs:\n");
440 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
441 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
445 /* return 0 if not found */
446 static uint32_t cpu_arm_find_by_name(const char *name
)
452 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
453 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
454 id
= arm_cpu_names
[i
].id
;
461 void cpu_arm_close(CPUARMState
*env
)
466 static int bad_mode_switch(CPUState
*env
, int mode
)
468 /* Return true if it is not valid for us to switch to
469 * this CPU mode (ie all the UNPREDICTABLE cases in
470 * the ARM ARM CPSRWriteByInstr pseudocode).
473 case ARM_CPU_MODE_USR
:
474 case ARM_CPU_MODE_SYS
:
475 case ARM_CPU_MODE_SVC
:
476 case ARM_CPU_MODE_ABT
:
477 case ARM_CPU_MODE_UND
:
478 case ARM_CPU_MODE_IRQ
:
479 case ARM_CPU_MODE_FIQ
:
486 uint32_t cpsr_read(CPUARMState
*env
)
490 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
491 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
492 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
493 | ((env
->condexec_bits
& 0xfc) << 8)
497 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
499 if (mask
& CPSR_NZCV
) {
500 env
->ZF
= (~val
) & CPSR_Z
;
502 env
->CF
= (val
>> 29) & 1;
503 env
->VF
= (val
<< 3) & 0x80000000;
506 env
->QF
= ((val
& CPSR_Q
) != 0);
508 env
->thumb
= ((val
& CPSR_T
) != 0);
509 if (mask
& CPSR_IT_0_1
) {
510 env
->condexec_bits
&= ~3;
511 env
->condexec_bits
|= (val
>> 25) & 3;
513 if (mask
& CPSR_IT_2_7
) {
514 env
->condexec_bits
&= 3;
515 env
->condexec_bits
|= (val
>> 8) & 0xfc;
517 if (mask
& CPSR_GE
) {
518 env
->GE
= (val
>> 16) & 0xf;
521 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
522 if (bad_mode_switch(env
, val
& CPSR_M
)) {
523 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
524 * We choose to ignore the attempt and leave the CPSR M field
529 switch_mode(env
, val
& CPSR_M
);
532 mask
&= ~CACHED_CPSR_BITS
;
533 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
536 /* Sign/zero extend */
537 uint32_t HELPER(sxtb16
)(uint32_t x
)
540 res
= (uint16_t)(int8_t)x
;
541 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
545 uint32_t HELPER(uxtb16
)(uint32_t x
)
548 res
= (uint16_t)(uint8_t)x
;
549 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
553 uint32_t HELPER(clz
)(uint32_t x
)
558 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
562 if (num
== INT_MIN
&& den
== -1)
567 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
574 uint32_t HELPER(rbit
)(uint32_t x
)
576 x
= ((x
& 0xff000000) >> 24)
577 | ((x
& 0x00ff0000) >> 8)
578 | ((x
& 0x0000ff00) << 8)
579 | ((x
& 0x000000ff) << 24);
580 x
= ((x
& 0xf0f0f0f0) >> 4)
581 | ((x
& 0x0f0f0f0f) << 4);
582 x
= ((x
& 0x88888888) >> 3)
583 | ((x
& 0x44444444) >> 1)
584 | ((x
& 0x22222222) << 1)
585 | ((x
& 0x11111111) << 3);
589 uint32_t HELPER(abs
)(uint32_t x
)
591 return ((int32_t)x
< 0) ? -x
: x
;
594 #if defined(CONFIG_USER_ONLY)
596 void do_interrupt (CPUState
*env
)
598 env
->exception_index
= -1;
601 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
605 env
->exception_index
= EXCP_PREFETCH_ABORT
;
606 env
->cp15
.c6_insn
= address
;
608 env
->exception_index
= EXCP_DATA_ABORT
;
609 env
->cp15
.c6_data
= address
;
614 /* These should probably raise undefined insn exceptions. */
615 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
617 int op1
= (insn
>> 8) & 0xf;
618 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
622 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
624 int op1
= (insn
>> 8) & 0xf;
625 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
629 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
631 cpu_abort(env
, "cp15 insn %08x\n", insn
);
634 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
636 cpu_abort(env
, "cp15 insn %08x\n", insn
);
639 /* These should probably raise undefined insn exceptions. */
640 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
642 cpu_abort(env
, "v7m_mrs %d\n", reg
);
645 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
647 cpu_abort(env
, "v7m_mrs %d\n", reg
);
651 void switch_mode(CPUState
*env
, int mode
)
653 if (mode
!= ARM_CPU_MODE_USR
)
654 cpu_abort(env
, "Tried to switch out of user mode\n");
657 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
659 cpu_abort(env
, "banked r13 write\n");
662 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
664 cpu_abort(env
, "banked r13 read\n");
670 extern int semihosting_enabled
;
672 /* Map CPU modes onto saved register banks. */
673 static inline int bank_number(CPUState
*env
, int mode
)
676 case ARM_CPU_MODE_USR
:
677 case ARM_CPU_MODE_SYS
:
679 case ARM_CPU_MODE_SVC
:
681 case ARM_CPU_MODE_ABT
:
683 case ARM_CPU_MODE_UND
:
685 case ARM_CPU_MODE_IRQ
:
687 case ARM_CPU_MODE_FIQ
:
690 cpu_abort(env
, "Bad mode %x\n", mode
);
694 void switch_mode(CPUState
*env
, int mode
)
699 old_mode
= env
->uncached_cpsr
& CPSR_M
;
700 if (mode
== old_mode
)
703 if (old_mode
== ARM_CPU_MODE_FIQ
) {
704 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
705 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
706 } else if (mode
== ARM_CPU_MODE_FIQ
) {
707 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
708 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
711 i
= bank_number(env
, old_mode
);
712 env
->banked_r13
[i
] = env
->regs
[13];
713 env
->banked_r14
[i
] = env
->regs
[14];
714 env
->banked_spsr
[i
] = env
->spsr
;
716 i
= bank_number(env
, mode
);
717 env
->regs
[13] = env
->banked_r13
[i
];
718 env
->regs
[14] = env
->banked_r14
[i
];
719 env
->spsr
= env
->banked_spsr
[i
];
722 static void v7m_push(CPUARMState
*env
, uint32_t val
)
725 stl_phys(env
->regs
[13], val
);
728 static uint32_t v7m_pop(CPUARMState
*env
)
731 val
= ldl_phys(env
->regs
[13]);
736 /* Switch to V7M main or process stack pointer. */
737 static void switch_v7m_sp(CPUARMState
*env
, int process
)
740 if (env
->v7m
.current_sp
!= process
) {
741 tmp
= env
->v7m
.other_sp
;
742 env
->v7m
.other_sp
= env
->regs
[13];
744 env
->v7m
.current_sp
= process
;
748 static void do_v7m_exception_exit(CPUARMState
*env
)
753 type
= env
->regs
[15];
754 if (env
->v7m
.exception
!= 0)
755 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
757 /* Switch to the target stack. */
758 switch_v7m_sp(env
, (type
& 4) != 0);
760 env
->regs
[0] = v7m_pop(env
);
761 env
->regs
[1] = v7m_pop(env
);
762 env
->regs
[2] = v7m_pop(env
);
763 env
->regs
[3] = v7m_pop(env
);
764 env
->regs
[12] = v7m_pop(env
);
765 env
->regs
[14] = v7m_pop(env
);
766 env
->regs
[15] = v7m_pop(env
);
768 xpsr_write(env
, xpsr
, 0xfffffdff);
769 /* Undo stack alignment. */
772 /* ??? The exception return type specifies Thread/Handler mode. However
773 this is also implied by the xPSR value. Not sure what to do
774 if there is a mismatch. */
775 /* ??? Likewise for mismatches between the CONTROL register and the stack
779 static void do_interrupt_v7m(CPUARMState
*env
)
781 uint32_t xpsr
= xpsr_read(env
);
786 if (env
->v7m
.current_sp
)
788 if (env
->v7m
.exception
== 0)
791 /* For exceptions we just mark as pending on the NVIC, and let that
793 /* TODO: Need to escalate if the current priority is higher than the
794 one we're raising. */
795 switch (env
->exception_index
) {
797 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
801 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
803 case EXCP_PREFETCH_ABORT
:
804 case EXCP_DATA_ABORT
:
805 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
808 if (semihosting_enabled
) {
810 nr
= lduw_code(env
->regs
[15]) & 0xff;
813 env
->regs
[0] = do_arm_semihosting(env
);
817 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
820 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
822 case EXCP_EXCEPTION_EXIT
:
823 do_v7m_exception_exit(env
);
826 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
827 return; /* Never happens. Keep compiler happy. */
830 /* Align stack pointer. */
831 /* ??? Should only do this if Configuration Control Register
832 STACKALIGN bit is set. */
833 if (env
->regs
[13] & 4) {
837 /* Switch to the handler mode. */
839 v7m_push(env
, env
->regs
[15]);
840 v7m_push(env
, env
->regs
[14]);
841 v7m_push(env
, env
->regs
[12]);
842 v7m_push(env
, env
->regs
[3]);
843 v7m_push(env
, env
->regs
[2]);
844 v7m_push(env
, env
->regs
[1]);
845 v7m_push(env
, env
->regs
[0]);
846 switch_v7m_sp(env
, 0);
847 env
->uncached_cpsr
&= ~CPSR_IT
;
849 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
850 env
->regs
[15] = addr
& 0xfffffffe;
851 env
->thumb
= addr
& 1;
854 /* Handle a CPU exception. */
855 void do_interrupt(CPUARMState
*env
)
863 do_interrupt_v7m(env
);
866 /* TODO: Vectored interrupt controller. */
867 switch (env
->exception_index
) {
869 new_mode
= ARM_CPU_MODE_UND
;
878 if (semihosting_enabled
) {
879 /* Check for semihosting interrupt. */
881 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
883 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
885 /* Only intercept calls from privileged modes, to provide some
886 semblance of security. */
887 if (((mask
== 0x123456 && !env
->thumb
)
888 || (mask
== 0xab && env
->thumb
))
889 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
890 env
->regs
[0] = do_arm_semihosting(env
);
894 new_mode
= ARM_CPU_MODE_SVC
;
897 /* The PC already points to the next instruction. */
901 /* See if this is a semihosting syscall. */
902 if (env
->thumb
&& semihosting_enabled
) {
903 mask
= lduw_code(env
->regs
[15]) & 0xff;
905 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
907 env
->regs
[0] = do_arm_semihosting(env
);
911 env
->cp15
.c5_insn
= 2;
912 /* Fall through to prefetch abort. */
913 case EXCP_PREFETCH_ABORT
:
914 new_mode
= ARM_CPU_MODE_ABT
;
916 mask
= CPSR_A
| CPSR_I
;
919 case EXCP_DATA_ABORT
:
920 new_mode
= ARM_CPU_MODE_ABT
;
922 mask
= CPSR_A
| CPSR_I
;
926 new_mode
= ARM_CPU_MODE_IRQ
;
928 /* Disable IRQ and imprecise data aborts. */
929 mask
= CPSR_A
| CPSR_I
;
933 new_mode
= ARM_CPU_MODE_FIQ
;
935 /* Disable FIQ, IRQ and imprecise data aborts. */
936 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
940 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
941 return; /* Never happens. Keep compiler happy. */
944 if (env
->cp15
.c1_sys
& (1 << 13)) {
947 switch_mode (env
, new_mode
);
948 env
->spsr
= cpsr_read(env
);
950 env
->condexec_bits
= 0;
951 /* Switch to the new mode, and to the correct instruction set. */
952 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
953 env
->uncached_cpsr
|= mask
;
954 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
955 * and we should just guard the thumb mode on V4 */
956 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
957 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
959 env
->regs
[14] = env
->regs
[15] + offset
;
960 env
->regs
[15] = addr
;
961 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
964 /* Check section/page access permissions.
965 Returns the page protection flags, or zero if the access is not
967 static inline int check_ap(CPUState
*env
, int ap
, int domain_prot
,
968 int access_type
, int is_user
)
972 if (domain_prot
== 3) {
973 return PAGE_READ
| PAGE_WRITE
;
976 if (access_type
== 1)
983 if (access_type
== 1)
985 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
987 return is_user
? 0 : PAGE_READ
;
994 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
999 return PAGE_READ
| PAGE_WRITE
;
1001 return PAGE_READ
| PAGE_WRITE
;
1002 case 4: /* Reserved. */
1005 return is_user
? 0 : prot_ro
;
1009 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1017 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
1021 if (address
& env
->cp15
.c2_mask
)
1022 table
= env
->cp15
.c2_base1
& 0xffffc000;
1024 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1026 table
|= (address
>> 18) & 0x3ffc;
1030 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
1031 int is_user
, uint32_t *phys_ptr
, int *prot
,
1032 target_ulong
*page_size
)
1043 /* Pagetable walk. */
1044 /* Lookup l1 descriptor. */
1045 table
= get_level1_table_address(env
, address
);
1046 desc
= ldl_phys(table
);
1048 domain
= (desc
>> 5) & 0x0f;
1049 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1051 /* Section translation fault. */
1055 if (domain_prot
== 0 || domain_prot
== 2) {
1057 code
= 9; /* Section domain fault. */
1059 code
= 11; /* Page domain fault. */
1064 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1065 ap
= (desc
>> 10) & 3;
1067 *page_size
= 1024 * 1024;
1069 /* Lookup l2 entry. */
1071 /* Coarse pagetable. */
1072 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1074 /* Fine pagetable. */
1075 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1077 desc
= ldl_phys(table
);
1079 case 0: /* Page translation fault. */
1082 case 1: /* 64k page. */
1083 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1084 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1085 *page_size
= 0x10000;
1087 case 2: /* 4k page. */
1088 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1089 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1090 *page_size
= 0x1000;
1092 case 3: /* 1k page. */
1094 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1095 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1097 /* Page translation fault. */
1102 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1104 ap
= (desc
>> 4) & 3;
1108 /* Never happens, but compiler isn't smart enough to tell. */
1113 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1115 /* Access permission fault. */
1119 *phys_ptr
= phys_addr
;
1122 return code
| (domain
<< 4);
1125 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1126 int is_user
, uint32_t *phys_ptr
, int *prot
,
1127 target_ulong
*page_size
)
1139 /* Pagetable walk. */
1140 /* Lookup l1 descriptor. */
1141 table
= get_level1_table_address(env
, address
);
1142 desc
= ldl_phys(table
);
1145 /* Section translation fault. */
1149 } else if (type
== 2 && (desc
& (1 << 18))) {
1153 /* Section or page. */
1154 domain
= (desc
>> 5) & 0x0f;
1156 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1157 if (domain_prot
== 0 || domain_prot
== 2) {
1159 code
= 9; /* Section domain fault. */
1161 code
= 11; /* Page domain fault. */
1165 if (desc
& (1 << 18)) {
1167 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1168 *page_size
= 0x1000000;
1171 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1172 *page_size
= 0x100000;
1174 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1175 xn
= desc
& (1 << 4);
1178 /* Lookup l2 entry. */
1179 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1180 desc
= ldl_phys(table
);
1181 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1183 case 0: /* Page translation fault. */
1186 case 1: /* 64k page. */
1187 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1188 xn
= desc
& (1 << 15);
1189 *page_size
= 0x10000;
1191 case 2: case 3: /* 4k page. */
1192 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1194 *page_size
= 0x1000;
1197 /* Never happens, but compiler isn't smart enough to tell. */
1202 if (domain_prot
== 3) {
1203 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1205 if (xn
&& access_type
== 2)
1208 /* The simplified model uses AP[0] as an access control bit. */
1209 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1210 /* Access flag fault. */
1211 code
= (code
== 15) ? 6 : 3;
1214 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1216 /* Access permission fault. */
1223 *phys_ptr
= phys_addr
;
1226 return code
| (domain
<< 4);
1229 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1230 int is_user
, uint32_t *phys_ptr
, int *prot
)
1236 *phys_ptr
= address
;
1237 for (n
= 7; n
>= 0; n
--) {
1238 base
= env
->cp15
.c6_region
[n
];
1239 if ((base
& 1) == 0)
1241 mask
= 1 << ((base
>> 1) & 0x1f);
1242 /* Keep this shift separate from the above to avoid an
1243 (undefined) << 32. */
1244 mask
= (mask
<< 1) - 1;
1245 if (((base
^ address
) & ~mask
) == 0)
1251 if (access_type
== 2) {
1252 mask
= env
->cp15
.c5_insn
;
1254 mask
= env
->cp15
.c5_data
;
1256 mask
= (mask
>> (n
* 4)) & 0xf;
1263 *prot
= PAGE_READ
| PAGE_WRITE
;
1268 *prot
|= PAGE_WRITE
;
1271 *prot
= PAGE_READ
| PAGE_WRITE
;
1282 /* Bad permission. */
1289 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1290 int access_type
, int is_user
,
1291 uint32_t *phys_ptr
, int *prot
,
1292 target_ulong
*page_size
)
1294 /* Fast Context Switch Extension. */
1295 if (address
< 0x02000000)
1296 address
+= env
->cp15
.c13_fcse
;
1298 if ((env
->cp15
.c1_sys
& 1) == 0) {
1299 /* MMU/MPU disabled. */
1300 *phys_ptr
= address
;
1301 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1302 *page_size
= TARGET_PAGE_SIZE
;
1304 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1305 *page_size
= TARGET_PAGE_SIZE
;
1306 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1308 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1309 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1312 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1317 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1318 int access_type
, int mmu_idx
)
1321 target_ulong page_size
;
1325 is_user
= mmu_idx
== MMU_USER_IDX
;
1326 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1329 /* Map a single [sub]page. */
1330 phys_addr
&= ~(uint32_t)0x3ff;
1331 address
&= ~(uint32_t)0x3ff;
1332 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1336 if (access_type
== 2) {
1337 env
->cp15
.c5_insn
= ret
;
1338 env
->cp15
.c6_insn
= address
;
1339 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1341 env
->cp15
.c5_data
= ret
;
1342 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1343 env
->cp15
.c5_data
|= (1 << 11);
1344 env
->cp15
.c6_data
= address
;
1345 env
->exception_index
= EXCP_DATA_ABORT
;
1350 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1353 target_ulong page_size
;
1357 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1365 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1367 int cp_num
= (insn
>> 8) & 0xf;
1368 int cp_info
= (insn
>> 5) & 7;
1369 int src
= (insn
>> 16) & 0xf;
1370 int operand
= insn
& 0xf;
1372 if (env
->cp
[cp_num
].cp_write
)
1373 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1374 cp_info
, src
, operand
, val
);
1377 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1379 int cp_num
= (insn
>> 8) & 0xf;
1380 int cp_info
= (insn
>> 5) & 7;
1381 int dest
= (insn
>> 16) & 0xf;
1382 int operand
= insn
& 0xf;
1384 if (env
->cp
[cp_num
].cp_read
)
1385 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1386 cp_info
, dest
, operand
);
1390 /* Return basic MPU access permission bits. */
1391 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1398 for (i
= 0; i
< 16; i
+= 2) {
1399 ret
|= (val
>> i
) & mask
;
1405 /* Pad basic MPU access permission bits to extended format. */
1406 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1413 for (i
= 0; i
< 16; i
+= 2) {
1414 ret
|= (val
& mask
) << i
;
1420 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1426 op1
= (insn
>> 21) & 7;
1427 op2
= (insn
>> 5) & 7;
1429 switch ((insn
>> 16) & 0xf) {
1432 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1434 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1436 if (arm_feature(env
, ARM_FEATURE_V7
)
1437 && op1
== 2 && crm
== 0 && op2
== 0) {
1438 env
->cp15
.c0_cssel
= val
& 0xf;
1442 case 1: /* System configuration. */
1443 if (arm_feature(env
, ARM_FEATURE_V7
)
1444 && op1
== 0 && crm
== 1 && op2
== 0) {
1445 env
->cp15
.c1_scr
= val
;
1448 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1452 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1453 env
->cp15
.c1_sys
= val
;
1454 /* ??? Lots of these bits are not implemented. */
1455 /* This may enable/disable the MMU, so do a TLB flush. */
1458 case 1: /* Auxiliary control register. */
1459 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1460 env
->cp15
.c1_xscaleauxcr
= val
;
1463 /* Not implemented. */
1466 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1468 if (env
->cp15
.c1_coproc
!= val
) {
1469 env
->cp15
.c1_coproc
= val
;
1470 /* ??? Is this safe when called from within a TB? */
1478 case 2: /* MMU Page table control / MPU cache control. */
1479 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1482 env
->cp15
.c2_data
= val
;
1485 env
->cp15
.c2_insn
= val
;
1493 env
->cp15
.c2_base0
= val
;
1496 env
->cp15
.c2_base1
= val
;
1500 env
->cp15
.c2_control
= val
;
1501 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1502 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1509 case 3: /* MMU Domain access control / MPU write buffer control. */
1511 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1513 case 4: /* Reserved. */
1515 case 5: /* MMU Fault status / MPU access permission. */
1516 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1520 if (arm_feature(env
, ARM_FEATURE_MPU
))
1521 val
= extended_mpu_ap_bits(val
);
1522 env
->cp15
.c5_data
= val
;
1525 if (arm_feature(env
, ARM_FEATURE_MPU
))
1526 val
= extended_mpu_ap_bits(val
);
1527 env
->cp15
.c5_insn
= val
;
1530 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1532 env
->cp15
.c5_data
= val
;
1535 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1537 env
->cp15
.c5_insn
= val
;
1543 case 6: /* MMU Fault address / MPU base/size. */
1544 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1547 env
->cp15
.c6_region
[crm
] = val
;
1549 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1553 env
->cp15
.c6_data
= val
;
1555 case 1: /* ??? This is WFAR on armv6 */
1557 env
->cp15
.c6_insn
= val
;
1564 case 7: /* Cache control. */
1565 env
->cp15
.c15_i_max
= 0x000;
1566 env
->cp15
.c15_i_min
= 0xff0;
1570 /* No cache, so nothing to do except VA->PA translations. */
1571 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1574 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1575 env
->cp15
.c7_par
= val
& 0xfffff6ff;
1577 env
->cp15
.c7_par
= val
& 0xfffff1ff;
1582 target_ulong page_size
;
1584 int ret
, is_user
= op2
& 2;
1585 int access_type
= op2
& 1;
1588 /* Other states are only available with TrustZone */
1591 ret
= get_phys_addr(env
, val
, access_type
, is_user
,
1592 &phys_addr
, &prot
, &page_size
);
1594 /* We do not set any attribute bits in the PAR */
1595 if (page_size
== (1 << 24)
1596 && arm_feature(env
, ARM_FEATURE_V7
)) {
1597 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1599 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1602 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
1603 ((ret
& (12 << 1)) >> 6) |
1604 ((ret
& 0xf) << 1) | 1;
1611 case 8: /* MMU TLB control. */
1613 case 0: /* Invalidate all. */
1616 case 1: /* Invalidate single TLB entry. */
1617 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1619 case 2: /* Invalidate on ASID. */
1620 tlb_flush(env
, val
== 0);
1622 case 3: /* Invalidate single entry on MVA. */
1623 /* ??? This is like case 1, but ignores ASID. */
1631 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1633 if (arm_feature(env
, ARM_FEATURE_STRONGARM
))
1634 break; /* Ignore ReadBuffer access */
1636 case 0: /* Cache lockdown. */
1638 case 0: /* L1 cache. */
1641 env
->cp15
.c9_data
= val
;
1644 env
->cp15
.c9_insn
= val
;
1650 case 1: /* L2 cache. */
1651 /* Ignore writes to L2 lockdown/auxiliary registers. */
1657 case 1: /* TCM memory region registers. */
1658 /* Not implemented. */
1660 case 12: /* Performance monitor control */
1661 /* Performance monitors are implementation defined in v7,
1662 * but with an ARM recommended set of registers, which we
1663 * follow (although we don't actually implement any counters)
1665 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1669 case 0: /* performance monitor control register */
1670 /* only the DP, X, D and E bits are writable */
1671 env
->cp15
.c9_pmcr
&= ~0x39;
1672 env
->cp15
.c9_pmcr
|= (val
& 0x39);
1674 case 1: /* Count enable set register */
1676 env
->cp15
.c9_pmcnten
|= val
;
1678 case 2: /* Count enable clear */
1680 env
->cp15
.c9_pmcnten
&= ~val
;
1682 case 3: /* Overflow flag status */
1683 env
->cp15
.c9_pmovsr
&= ~val
;
1685 case 4: /* Software increment */
1686 /* RAZ/WI since we don't implement the software-count event */
1688 case 5: /* Event counter selection register */
1689 /* Since we don't implement any events, writing to this register
1690 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1697 case 13: /* Performance counters */
1698 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1702 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1704 case 1: /* Event type select */
1705 env
->cp15
.c9_pmxevtyper
= val
& 0xff;
1707 case 2: /* Event count register */
1708 /* Unimplemented (we have no events), RAZ/WI */
1714 case 14: /* Performance monitor control */
1715 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1719 case 0: /* user enable */
1720 env
->cp15
.c9_pmuserenr
= val
& 1;
1721 /* changes access rights for cp registers, so flush tbs */
1724 case 1: /* interrupt enable set */
1725 /* We have no event counters so only the C bit can be changed */
1727 env
->cp15
.c9_pminten
|= val
;
1729 case 2: /* interrupt enable clear */
1731 env
->cp15
.c9_pminten
&= ~val
;
1739 case 10: /* MMU TLB lockdown. */
1740 /* ??? TLB lockdown not implemented. */
1742 case 12: /* Reserved. */
1744 case 13: /* Process ID. */
1747 /* Unlike real hardware the qemu TLB uses virtual addresses,
1748 not modified virtual addresses, so this causes a TLB flush.
1750 if (env
->cp15
.c13_fcse
!= val
)
1752 env
->cp15
.c13_fcse
= val
;
1755 /* This changes the ASID, so do a TLB flush. */
1756 if (env
->cp15
.c13_context
!= val
1757 && !arm_feature(env
, ARM_FEATURE_MPU
))
1759 env
->cp15
.c13_context
= val
;
1765 case 14: /* Reserved. */
1767 case 15: /* Implementation specific. */
1768 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1769 if (op2
== 0 && crm
== 1) {
1770 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1771 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1773 env
->cp15
.c15_cpar
= val
& 0x3fff;
1779 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1783 case 1: /* Set TI925T configuration. */
1784 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1785 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1786 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1788 case 2: /* Set I_max. */
1789 env
->cp15
.c15_i_max
= val
;
1791 case 3: /* Set I_min. */
1792 env
->cp15
.c15_i_min
= val
;
1794 case 4: /* Set thread-ID. */
1795 env
->cp15
.c15_threadid
= val
& 0xffff;
1797 case 8: /* Wait-for-interrupt (deprecated). */
1798 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1804 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
1807 if ((op1
== 0) && (op2
== 0)) {
1808 env
->cp15
.c15_power_control
= val
;
1809 } else if ((op1
== 0) && (op2
== 1)) {
1810 env
->cp15
.c15_diagnostic
= val
;
1811 } else if ((op1
== 0) && (op2
== 2)) {
1812 env
->cp15
.c15_power_diagnostic
= val
;
1822 /* ??? For debugging only. Should raise illegal instruction exception. */
1823 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1824 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1827 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1833 op1
= (insn
>> 21) & 7;
1834 op2
= (insn
>> 5) & 7;
1836 switch ((insn
>> 16) & 0xf) {
1837 case 0: /* ID codes. */
1843 case 0: /* Device ID. */
1844 return env
->cp15
.c0_cpuid
;
1845 case 1: /* Cache Type. */
1846 return env
->cp15
.c0_cachetype
;
1847 case 2: /* TCM status. */
1849 case 3: /* TLB type register. */
1850 return 0; /* No lockable TLB entries. */
1852 /* The MPIDR was standardised in v7; prior to
1853 * this it was implemented only in the 11MPCore.
1854 * For all other pre-v7 cores it does not exist.
1856 if (arm_feature(env
, ARM_FEATURE_V7
) ||
1857 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
1858 int mpidr
= env
->cpu_index
;
1859 /* We don't support setting cluster ID ([8..11])
1860 * so these bits always RAZ.
1862 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1864 /* Cores which are uniprocessor (non-coherent)
1865 * but still implement the MP extensions set
1866 * bit 30. (For instance, A9UP.) However we do
1867 * not currently model any of those cores.
1872 /* otherwise fall through to the unimplemented-reg case */
1877 if (!arm_feature(env
, ARM_FEATURE_V6
))
1879 return env
->cp15
.c0_c1
[op2
];
1881 if (!arm_feature(env
, ARM_FEATURE_V6
))
1883 return env
->cp15
.c0_c2
[op2
];
1884 case 3: case 4: case 5: case 6: case 7:
1890 /* These registers aren't documented on arm11 cores. However
1891 Linux looks at them anyway. */
1892 if (!arm_feature(env
, ARM_FEATURE_V6
))
1896 if (!arm_feature(env
, ARM_FEATURE_V7
))
1901 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1903 return env
->cp15
.c0_clid
;
1909 if (op2
!= 0 || crm
!= 0)
1911 return env
->cp15
.c0_cssel
;
1915 case 1: /* System configuration. */
1916 if (arm_feature(env
, ARM_FEATURE_V7
)
1917 && op1
== 0 && crm
== 1 && op2
== 0) {
1918 return env
->cp15
.c1_scr
;
1920 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1923 case 0: /* Control register. */
1924 return env
->cp15
.c1_sys
;
1925 case 1: /* Auxiliary control register. */
1926 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1927 return env
->cp15
.c1_xscaleauxcr
;
1928 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1930 switch (ARM_CPUID(env
)) {
1931 case ARM_CPUID_ARM1026
:
1933 case ARM_CPUID_ARM1136
:
1934 case ARM_CPUID_ARM1136_R2
:
1935 case ARM_CPUID_ARM1176
:
1937 case ARM_CPUID_ARM11MPCORE
:
1939 case ARM_CPUID_CORTEXA8
:
1941 case ARM_CPUID_CORTEXA9
:
1946 case 2: /* Coprocessor access register. */
1947 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1949 return env
->cp15
.c1_coproc
;
1953 case 2: /* MMU Page table control / MPU cache control. */
1954 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1957 return env
->cp15
.c2_data
;
1960 return env
->cp15
.c2_insn
;
1968 return env
->cp15
.c2_base0
;
1970 return env
->cp15
.c2_base1
;
1972 return env
->cp15
.c2_control
;
1977 case 3: /* MMU Domain access control / MPU write buffer control. */
1978 return env
->cp15
.c3
;
1979 case 4: /* Reserved. */
1981 case 5: /* MMU Fault status / MPU access permission. */
1982 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1986 if (arm_feature(env
, ARM_FEATURE_MPU
))
1987 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1988 return env
->cp15
.c5_data
;
1990 if (arm_feature(env
, ARM_FEATURE_MPU
))
1991 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1992 return env
->cp15
.c5_insn
;
1994 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1996 return env
->cp15
.c5_data
;
1998 if (!arm_feature(env
, ARM_FEATURE_MPU
))
2000 return env
->cp15
.c5_insn
;
2004 case 6: /* MMU Fault address. */
2005 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2008 return env
->cp15
.c6_region
[crm
];
2010 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
2014 return env
->cp15
.c6_data
;
2016 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2017 /* Watchpoint Fault Adrress. */
2018 return 0; /* Not implemented. */
2020 /* Instruction Fault Adrress. */
2021 /* Arm9 doesn't have an IFAR, but implementing it anyway
2022 shouldn't do any harm. */
2023 return env
->cp15
.c6_insn
;
2026 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2027 /* Instruction Fault Adrress. */
2028 return env
->cp15
.c6_insn
;
2036 case 7: /* Cache control. */
2037 if (crm
== 4 && op1
== 0 && op2
== 0) {
2038 return env
->cp15
.c7_par
;
2040 /* FIXME: Should only clear Z flag if destination is r15. */
2043 case 8: /* MMU TLB control. */
2047 case 0: /* Cache lockdown */
2049 case 0: /* L1 cache. */
2050 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2055 return env
->cp15
.c9_data
;
2057 return env
->cp15
.c9_insn
;
2061 case 1: /* L2 cache */
2065 /* L2 Lockdown and Auxiliary control. */
2071 case 12: /* Performance monitor control */
2072 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2076 case 0: /* performance monitor control register */
2077 return env
->cp15
.c9_pmcr
;
2078 case 1: /* count enable set */
2079 case 2: /* count enable clear */
2080 return env
->cp15
.c9_pmcnten
;
2081 case 3: /* overflow flag status */
2082 return env
->cp15
.c9_pmovsr
;
2083 case 4: /* software increment */
2084 case 5: /* event counter selection register */
2085 return 0; /* Unimplemented, RAZ/WI */
2089 case 13: /* Performance counters */
2090 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2094 case 1: /* Event type select */
2095 return env
->cp15
.c9_pmxevtyper
;
2096 case 0: /* Cycle count register */
2097 case 2: /* Event count register */
2098 /* Unimplemented, so RAZ/WI */
2103 case 14: /* Performance monitor control */
2104 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2108 case 0: /* user enable */
2109 return env
->cp15
.c9_pmuserenr
;
2110 case 1: /* interrupt enable set */
2111 case 2: /* interrupt enable clear */
2112 return env
->cp15
.c9_pminten
;
2120 case 10: /* MMU TLB lockdown. */
2121 /* ??? TLB lockdown not implemented. */
2123 case 11: /* TCM DMA control. */
2124 case 12: /* Reserved. */
2126 case 13: /* Process ID. */
2129 return env
->cp15
.c13_fcse
;
2131 return env
->cp15
.c13_context
;
2135 case 14: /* Reserved. */
2137 case 15: /* Implementation specific. */
2138 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2139 if (op2
== 0 && crm
== 1)
2140 return env
->cp15
.c15_cpar
;
2144 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2148 case 1: /* Read TI925T configuration. */
2149 return env
->cp15
.c15_ticonfig
;
2150 case 2: /* Read I_max. */
2151 return env
->cp15
.c15_i_max
;
2152 case 3: /* Read I_min. */
2153 return env
->cp15
.c15_i_min
;
2154 case 4: /* Read thread-ID. */
2155 return env
->cp15
.c15_threadid
;
2156 case 8: /* TI925T_status */
2159 /* TODO: Peripheral port remap register:
2160 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2161 * controller base address at $rn & ~0xfff and map size of
2162 * 0x200 << ($rn & 0xfff), when MMU is off. */
2165 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
2168 if ((op1
== 4) && (op2
== 0)) {
2169 /* The config_base_address should hold the value of
2170 * the peripheral base. ARM should get this from a CPU
2171 * object property, but that support isn't available in
2172 * December 2011. Default to 0 for now and board models
2173 * that care can set it by a private hook */
2174 return env
->cp15
.c15_config_base_address
;
2175 } else if ((op1
== 0) && (op2
== 0)) {
2176 /* power_control should be set to maximum latency. Again,
2177 default to 0 and set by private hook */
2178 return env
->cp15
.c15_power_control
;
2179 } else if ((op1
== 0) && (op2
== 1)) {
2180 return env
->cp15
.c15_diagnostic
;
2181 } else if ((op1
== 0) && (op2
== 2)) {
2182 return env
->cp15
.c15_power_diagnostic
;
2185 case 1: /* NEON Busy */
2187 case 5: /* tlb lockdown */
2190 if ((op1
== 5) && (op2
== 2)) {
2202 /* ??? For debugging only. Should raise illegal instruction exception. */
2203 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2204 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2208 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
2210 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2211 env
->regs
[13] = val
;
2213 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2217 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
2219 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2220 return env
->regs
[13];
2222 return env
->banked_r13
[bank_number(env
, mode
)];
2226 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
2230 return xpsr_read(env
) & 0xf8000000;
2232 return xpsr_read(env
) & 0xf80001ff;
2234 return xpsr_read(env
) & 0xff00fc00;
2236 return xpsr_read(env
) & 0xff00fdff;
2238 return xpsr_read(env
) & 0x000001ff;
2240 return xpsr_read(env
) & 0x0700fc00;
2242 return xpsr_read(env
) & 0x0700edff;
2244 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2246 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2247 case 16: /* PRIMASK */
2248 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2249 case 17: /* BASEPRI */
2250 case 18: /* BASEPRI_MAX */
2251 return env
->v7m
.basepri
;
2252 case 19: /* FAULTMASK */
2253 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2254 case 20: /* CONTROL */
2255 return env
->v7m
.control
;
2257 /* ??? For debugging only. */
2258 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2263 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
2267 xpsr_write(env
, val
, 0xf8000000);
2270 xpsr_write(env
, val
, 0xf8000000);
2273 xpsr_write(env
, val
, 0xfe00fc00);
2276 xpsr_write(env
, val
, 0xfe00fc00);
2279 /* IPSR bits are readonly. */
2282 xpsr_write(env
, val
, 0x0600fc00);
2285 xpsr_write(env
, val
, 0x0600fc00);
2288 if (env
->v7m
.current_sp
)
2289 env
->v7m
.other_sp
= val
;
2291 env
->regs
[13] = val
;
2294 if (env
->v7m
.current_sp
)
2295 env
->regs
[13] = val
;
2297 env
->v7m
.other_sp
= val
;
2299 case 16: /* PRIMASK */
2301 env
->uncached_cpsr
|= CPSR_I
;
2303 env
->uncached_cpsr
&= ~CPSR_I
;
2305 case 17: /* BASEPRI */
2306 env
->v7m
.basepri
= val
& 0xff;
2308 case 18: /* BASEPRI_MAX */
2310 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2311 env
->v7m
.basepri
= val
;
2313 case 19: /* FAULTMASK */
2315 env
->uncached_cpsr
|= CPSR_F
;
2317 env
->uncached_cpsr
&= ~CPSR_F
;
2319 case 20: /* CONTROL */
2320 env
->v7m
.control
= val
& 3;
2321 switch_v7m_sp(env
, (val
& 2) != 0);
2324 /* ??? For debugging only. */
2325 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2330 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
2331 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
2334 if (cpnum
< 0 || cpnum
> 14) {
2335 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2339 env
->cp
[cpnum
].cp_read
= cp_read
;
2340 env
->cp
[cpnum
].cp_write
= cp_write
;
2341 env
->cp
[cpnum
].opaque
= opaque
;
2346 /* Note that signed overflow is undefined in C. The following routines are
2347 careful to use unsigned types where modulo arithmetic is required.
2348 Failure to do so _will_ break on newer gcc. */
2350 /* Signed saturating arithmetic. */
2352 /* Perform 16-bit signed saturating addition. */
2353 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2358 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2367 /* Perform 8-bit signed saturating addition. */
2368 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2373 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2382 /* Perform 16-bit signed saturating subtraction. */
2383 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2388 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2397 /* Perform 8-bit signed saturating subtraction. */
2398 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2403 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2412 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2413 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2414 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2415 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2418 #include "op_addsub.h"
2420 /* Unsigned saturating arithmetic. */
2421 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2430 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2438 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2447 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2455 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2456 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2457 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2458 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2461 #include "op_addsub.h"
2463 /* Signed modulo arithmetic. */
2464 #define SARITH16(a, b, n, op) do { \
2466 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2467 RESULT(sum, n, 16); \
2469 ge |= 3 << (n * 2); \
2472 #define SARITH8(a, b, n, op) do { \
2474 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2475 RESULT(sum, n, 8); \
2481 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2482 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2483 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2484 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2488 #include "op_addsub.h"
2490 /* Unsigned modulo arithmetic. */
2491 #define ADD16(a, b, n) do { \
2493 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2494 RESULT(sum, n, 16); \
2495 if ((sum >> 16) == 1) \
2496 ge |= 3 << (n * 2); \
2499 #define ADD8(a, b, n) do { \
2501 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2502 RESULT(sum, n, 8); \
2503 if ((sum >> 8) == 1) \
2507 #define SUB16(a, b, n) do { \
2509 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2510 RESULT(sum, n, 16); \
2511 if ((sum >> 16) == 0) \
2512 ge |= 3 << (n * 2); \
2515 #define SUB8(a, b, n) do { \
2517 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2518 RESULT(sum, n, 8); \
2519 if ((sum >> 8) == 0) \
2526 #include "op_addsub.h"
2528 /* Halved signed arithmetic. */
2529 #define ADD16(a, b, n) \
2530 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2531 #define SUB16(a, b, n) \
2532 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2533 #define ADD8(a, b, n) \
2534 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2535 #define SUB8(a, b, n) \
2536 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2539 #include "op_addsub.h"
2541 /* Halved unsigned arithmetic. */
2542 #define ADD16(a, b, n) \
2543 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2544 #define SUB16(a, b, n) \
2545 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2546 #define ADD8(a, b, n) \
2547 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2548 #define SUB8(a, b, n) \
2549 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2552 #include "op_addsub.h"
2554 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2562 /* Unsigned sum of absolute byte differences. */
2563 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2566 sum
= do_usad(a
, b
);
2567 sum
+= do_usad(a
>> 8, b
>> 8);
2568 sum
+= do_usad(a
>> 16, b
>>16);
2569 sum
+= do_usad(a
>> 24, b
>> 24);
2573 /* For ARMv6 SEL instruction. */
2574 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2587 return (a
& mask
) | (b
& ~mask
);
2590 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2592 return (val
>> 32) | (val
!= 0);
2595 /* VFP support. We follow the convention used for VFP instrunctions:
2596 Single precition routines have a "s" suffix, double precision a
2599 /* Convert host exception flags to vfp form. */
2600 static inline int vfp_exceptbits_from_host(int host_bits
)
2602 int target_bits
= 0;
2604 if (host_bits
& float_flag_invalid
)
2606 if (host_bits
& float_flag_divbyzero
)
2608 if (host_bits
& float_flag_overflow
)
2610 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2612 if (host_bits
& float_flag_inexact
)
2613 target_bits
|= 0x10;
2614 if (host_bits
& float_flag_input_denormal
)
2615 target_bits
|= 0x80;
2619 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2624 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2625 | (env
->vfp
.vec_len
<< 16)
2626 | (env
->vfp
.vec_stride
<< 20);
2627 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2628 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2629 fpscr
|= vfp_exceptbits_from_host(i
);
2633 uint32_t vfp_get_fpscr(CPUState
*env
)
2635 return HELPER(vfp_get_fpscr
)(env
);
2638 /* Convert vfp exception flags to target form. */
2639 static inline int vfp_exceptbits_to_host(int target_bits
)
2643 if (target_bits
& 1)
2644 host_bits
|= float_flag_invalid
;
2645 if (target_bits
& 2)
2646 host_bits
|= float_flag_divbyzero
;
2647 if (target_bits
& 4)
2648 host_bits
|= float_flag_overflow
;
2649 if (target_bits
& 8)
2650 host_bits
|= float_flag_underflow
;
2651 if (target_bits
& 0x10)
2652 host_bits
|= float_flag_inexact
;
2653 if (target_bits
& 0x80)
2654 host_bits
|= float_flag_input_denormal
;
2658 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2663 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2664 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2665 env
->vfp
.vec_len
= (val
>> 16) & 7;
2666 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2669 if (changed
& (3 << 22)) {
2670 i
= (val
>> 22) & 3;
2673 i
= float_round_nearest_even
;
2679 i
= float_round_down
;
2682 i
= float_round_to_zero
;
2685 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2687 if (changed
& (1 << 24)) {
2688 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2689 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2691 if (changed
& (1 << 25))
2692 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2694 i
= vfp_exceptbits_to_host(val
);
2695 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2696 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2699 void vfp_set_fpscr(CPUState
*env
, uint32_t val
)
2701 HELPER(vfp_set_fpscr
)(env
, val
);
2704 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2706 #define VFP_BINOP(name) \
2707 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2709 float_status *fpst = fpstp; \
2710 return float32_ ## name(a, b, fpst); \
2712 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2714 float_status *fpst = fpstp; \
2715 return float64_ ## name(a, b, fpst); \
2723 float32
VFP_HELPER(neg
, s
)(float32 a
)
2725 return float32_chs(a
);
2728 float64
VFP_HELPER(neg
, d
)(float64 a
)
2730 return float64_chs(a
);
2733 float32
VFP_HELPER(abs
, s
)(float32 a
)
2735 return float32_abs(a
);
2738 float64
VFP_HELPER(abs
, d
)(float64 a
)
2740 return float64_abs(a
);
2743 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2745 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2748 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2750 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2753 /* XXX: check quiet/signaling case */
2754 #define DO_VFP_cmp(p, type) \
2755 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2758 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2759 case 0: flags = 0x6; break; \
2760 case -1: flags = 0x8; break; \
2761 case 1: flags = 0x2; break; \
2762 default: case 2: flags = 0x3; break; \
2764 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2765 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2767 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2770 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2771 case 0: flags = 0x6; break; \
2772 case -1: flags = 0x8; break; \
2773 case 1: flags = 0x2; break; \
2774 default: case 2: flags = 0x3; break; \
2776 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2777 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2779 DO_VFP_cmp(s
, float32
)
2780 DO_VFP_cmp(d
, float64
)
2783 /* Integer to float and float to integer conversions */
2785 #define CONV_ITOF(name, fsz, sign) \
2786 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2788 float_status *fpst = fpstp; \
2789 return sign##int32_to_##float##fsz(x, fpst); \
2792 #define CONV_FTOI(name, fsz, sign, round) \
2793 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2795 float_status *fpst = fpstp; \
2796 if (float##fsz##_is_any_nan(x)) { \
2797 float_raise(float_flag_invalid, fpst); \
2800 return float##fsz##_to_##sign##int32##round(x, fpst); \
2803 #define FLOAT_CONVS(name, p, fsz, sign) \
2804 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2805 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2806 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2808 FLOAT_CONVS(si
, s
, 32, )
2809 FLOAT_CONVS(si
, d
, 64, )
2810 FLOAT_CONVS(ui
, s
, 32, u
)
2811 FLOAT_CONVS(ui
, d
, 64, u
)
2817 /* floating point conversion */
2818 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2820 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2821 /* ARM requires that S<->D conversion of any kind of NaN generates
2822 * a quiet NaN by forcing the most significant frac bit to 1.
2824 return float64_maybe_silence_nan(r
);
2827 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2829 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2830 /* ARM requires that S<->D conversion of any kind of NaN generates
2831 * a quiet NaN by forcing the most significant frac bit to 1.
2833 return float32_maybe_silence_nan(r
);
2836 /* VFP3 fixed point conversion. */
2837 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2838 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2841 float_status *fpst = fpstp; \
2843 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2844 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2846 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2849 float_status *fpst = fpstp; \
2851 if (float##fsz##_is_any_nan(x)) { \
2852 float_raise(float_flag_invalid, fpst); \
2855 tmp = float##fsz##_scalbn(x, shift, fpst); \
2856 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2859 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2860 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2861 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2862 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2863 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2864 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2865 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2866 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2869 /* Half precision conversions. */
2870 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUState
*env
, float_status
*s
)
2872 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2873 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2875 return float32_maybe_silence_nan(r
);
2880 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUState
*env
, float_status
*s
)
2882 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2883 float16 r
= float32_to_float16(a
, ieee
, s
);
2885 r
= float16_maybe_silence_nan(r
);
2887 return float16_val(r
);
2890 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2892 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2895 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2897 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2900 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2902 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2905 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2907 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2910 #define float32_two make_float32(0x40000000)
2911 #define float32_three make_float32(0x40400000)
2912 #define float32_one_point_five make_float32(0x3fc00000)
2914 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2916 float_status
*s
= &env
->vfp
.standard_fp_status
;
2917 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2918 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2919 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2920 float_raise(float_flag_input_denormal
, s
);
2924 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2927 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2929 float_status
*s
= &env
->vfp
.standard_fp_status
;
2931 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2932 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2933 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2934 float_raise(float_flag_input_denormal
, s
);
2936 return float32_one_point_five
;
2938 product
= float32_mul(a
, b
, s
);
2939 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2944 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2945 * int->float conversions at run-time. */
2946 #define float64_256 make_float64(0x4070000000000000LL)
2947 #define float64_512 make_float64(0x4080000000000000LL)
2949 /* The algorithm that must be used to calculate the estimate
2950 * is specified by the ARM ARM.
2952 static float64
recip_estimate(float64 a
, CPUState
*env
)
2954 /* These calculations mustn't set any fp exception flags,
2955 * so we use a local copy of the fp_status.
2957 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2958 float_status
*s
= &dummy_status
;
2959 /* q = (int)(a * 512.0) */
2960 float64 q
= float64_mul(float64_512
, a
, s
);
2961 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2963 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2964 q
= int64_to_float64(q_int
, s
);
2965 q
= float64_add(q
, float64_half
, s
);
2966 q
= float64_div(q
, float64_512
, s
);
2967 q
= float64_div(float64_one
, q
, s
);
2969 /* s = (int)(256.0 * r + 0.5) */
2970 q
= float64_mul(q
, float64_256
, s
);
2971 q
= float64_add(q
, float64_half
, s
);
2972 q_int
= float64_to_int64_round_to_zero(q
, s
);
2974 /* return (double)s / 256.0 */
2975 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2978 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2980 float_status
*s
= &env
->vfp
.standard_fp_status
;
2982 uint32_t val32
= float32_val(a
);
2985 int a_exp
= (val32
& 0x7f800000) >> 23;
2986 int sign
= val32
& 0x80000000;
2988 if (float32_is_any_nan(a
)) {
2989 if (float32_is_signaling_nan(a
)) {
2990 float_raise(float_flag_invalid
, s
);
2992 return float32_default_nan
;
2993 } else if (float32_is_infinity(a
)) {
2994 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2995 } else if (float32_is_zero_or_denormal(a
)) {
2996 if (!float32_is_zero(a
)) {
2997 float_raise(float_flag_input_denormal
, s
);
2999 float_raise(float_flag_divbyzero
, s
);
3000 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3001 } else if (a_exp
>= 253) {
3002 float_raise(float_flag_underflow
, s
);
3003 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3006 f64
= make_float64((0x3feULL
<< 52)
3007 | ((int64_t)(val32
& 0x7fffff) << 29));
3009 result_exp
= 253 - a_exp
;
3011 f64
= recip_estimate(f64
, env
);
3014 | ((result_exp
& 0xff) << 23)
3015 | ((float64_val(f64
) >> 29) & 0x7fffff);
3016 return make_float32(val32
);
3019 /* The algorithm that must be used to calculate the estimate
3020 * is specified by the ARM ARM.
3022 static float64
recip_sqrt_estimate(float64 a
, CPUState
*env
)
3024 /* These calculations mustn't set any fp exception flags,
3025 * so we use a local copy of the fp_status.
3027 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3028 float_status
*s
= &dummy_status
;
3032 if (float64_lt(a
, float64_half
, s
)) {
3033 /* range 0.25 <= a < 0.5 */
3035 /* a in units of 1/512 rounded down */
3036 /* q0 = (int)(a * 512.0); */
3037 q
= float64_mul(float64_512
, a
, s
);
3038 q_int
= float64_to_int64_round_to_zero(q
, s
);
3040 /* reciprocal root r */
3041 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3042 q
= int64_to_float64(q_int
, s
);
3043 q
= float64_add(q
, float64_half
, s
);
3044 q
= float64_div(q
, float64_512
, s
);
3045 q
= float64_sqrt(q
, s
);
3046 q
= float64_div(float64_one
, q
, s
);
3048 /* range 0.5 <= a < 1.0 */
3050 /* a in units of 1/256 rounded down */
3051 /* q1 = (int)(a * 256.0); */
3052 q
= float64_mul(float64_256
, a
, s
);
3053 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3055 /* reciprocal root r */
3056 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3057 q
= int64_to_float64(q_int
, s
);
3058 q
= float64_add(q
, float64_half
, s
);
3059 q
= float64_div(q
, float64_256
, s
);
3060 q
= float64_sqrt(q
, s
);
3061 q
= float64_div(float64_one
, q
, s
);
3063 /* r in units of 1/256 rounded to nearest */
3064 /* s = (int)(256.0 * r + 0.5); */
3066 q
= float64_mul(q
, float64_256
,s
);
3067 q
= float64_add(q
, float64_half
, s
);
3068 q_int
= float64_to_int64_round_to_zero(q
, s
);
3070 /* return (double)s / 256.0;*/
3071 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3074 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
3076 float_status
*s
= &env
->vfp
.standard_fp_status
;
3082 val
= float32_val(a
);
3084 if (float32_is_any_nan(a
)) {
3085 if (float32_is_signaling_nan(a
)) {
3086 float_raise(float_flag_invalid
, s
);
3088 return float32_default_nan
;
3089 } else if (float32_is_zero_or_denormal(a
)) {
3090 if (!float32_is_zero(a
)) {
3091 float_raise(float_flag_input_denormal
, s
);
3093 float_raise(float_flag_divbyzero
, s
);
3094 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3095 } else if (float32_is_neg(a
)) {
3096 float_raise(float_flag_invalid
, s
);
3097 return float32_default_nan
;
3098 } else if (float32_is_infinity(a
)) {
3099 return float32_zero
;
3102 /* Normalize to a double-precision value between 0.25 and 1.0,
3103 * preserving the parity of the exponent. */
3104 if ((val
& 0x800000) == 0) {
3105 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3107 | ((uint64_t)(val
& 0x7fffff) << 29));
3109 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3111 | ((uint64_t)(val
& 0x7fffff) << 29));
3114 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3116 f64
= recip_sqrt_estimate(f64
, env
);
3118 val64
= float64_val(f64
);
3120 val
= ((result_exp
& 0xff) << 23)
3121 | ((val64
>> 29) & 0x7fffff);
3122 return make_float32(val
);
3125 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
3129 if ((a
& 0x80000000) == 0) {
3133 f64
= make_float64((0x3feULL
<< 52)
3134 | ((int64_t)(a
& 0x7fffffff) << 21));
3136 f64
= recip_estimate (f64
, env
);
3138 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3141 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
3145 if ((a
& 0xc0000000) == 0) {
3149 if (a
& 0x80000000) {
3150 f64
= make_float64((0x3feULL
<< 52)
3151 | ((uint64_t)(a
& 0x7fffffff) << 21));
3152 } else { /* bits 31-30 == '01' */
3153 f64
= make_float64((0x3fdULL
<< 52)
3154 | ((uint64_t)(a
& 0x3fffffff) << 22));
3157 f64
= recip_sqrt_estimate(f64
, env
);
3159 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3162 /* VFPv4 fused multiply-accumulate */
3163 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3165 float_status
*fpst
= fpstp
;
3166 return float32_muladd(a
, b
, c
, 0, fpst
);
3169 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3171 float_status
*fpst
= fpstp
;
3172 return float64_muladd(a
, b
, c
, 0, fpst
);
3175 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
3178 if (env
->teecr
!= val
) {