2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "qemu/osdep.h"
31 #include "qemu-common.h"
33 #include "hw/boards.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/sysbus.h"
37 #include "migration/vmstate.h"
38 #include "strongarm.h"
39 #include "qemu/error-report.h"
40 #include "hw/arm/boot.h"
41 #include "chardev/char-fe.h"
42 #include "chardev/char-serial.h"
43 #include "sysemu/sysemu.h"
44 #include "hw/ssi/ssi.h"
45 #include "qemu/cutils.h"
52 - Implement cp15, c14 ?
53 - Implement cp15, c15 !!! (idle used in L)
54 - Implement idle mode handling/DIM
55 - Implement sleep mode/Wake sources
56 - Implement reset control
57 - Implement memory control regs
59 - Maybe support MBGNT/MBREQ
64 - Enhance UART with modem signals
68 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
70 # define DPRINTF(format, ...) do { } while (0)
77 { 0x80010000, SA_PIC_UART1
},
78 { 0x80030000, SA_PIC_UART2
},
79 { 0x80050000, SA_PIC_UART3
},
83 /* Interrupt Controller */
85 #define TYPE_STRONGARM_PIC "strongarm_pic"
86 #define STRONGARM_PIC(obj) \
87 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
89 typedef struct StrongARMPICState
{
90 SysBusDevice parent_obj
;
109 #define SA_PIC_SRCS 32
112 static void strongarm_pic_update(void *opaque
)
114 StrongARMPICState
*s
= opaque
;
116 /* FIXME: reflect DIM */
117 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
118 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
121 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
123 StrongARMPICState
*s
= opaque
;
126 s
->pending
|= 1 << irq
;
128 s
->pending
&= ~(1 << irq
);
131 strongarm_pic_update(s
);
134 static uint64_t strongarm_pic_mem_read(void *opaque
, hwaddr offset
,
137 StrongARMPICState
*s
= opaque
;
141 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
147 return s
->int_idle
== 0;
149 return s
->pending
& s
->is_fiq
& s
->enabled
;
153 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
159 static void strongarm_pic_mem_write(void *opaque
, hwaddr offset
,
160 uint64_t value
, unsigned size
)
162 StrongARMPICState
*s
= opaque
;
172 s
->int_idle
= (value
& 1) ? 0 : ~0;
175 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
179 strongarm_pic_update(s
);
182 static const MemoryRegionOps strongarm_pic_ops
= {
183 .read
= strongarm_pic_mem_read
,
184 .write
= strongarm_pic_mem_write
,
185 .endianness
= DEVICE_NATIVE_ENDIAN
,
188 static void strongarm_pic_initfn(Object
*obj
)
190 DeviceState
*dev
= DEVICE(obj
);
191 StrongARMPICState
*s
= STRONGARM_PIC(obj
);
192 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
194 qdev_init_gpio_in(dev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
195 memory_region_init_io(&s
->iomem
, obj
, &strongarm_pic_ops
, s
,
197 sysbus_init_mmio(sbd
, &s
->iomem
);
198 sysbus_init_irq(sbd
, &s
->irq
);
199 sysbus_init_irq(sbd
, &s
->fiq
);
202 static int strongarm_pic_post_load(void *opaque
, int version_id
)
204 strongarm_pic_update(opaque
);
208 static VMStateDescription vmstate_strongarm_pic_regs
= {
209 .name
= "strongarm_pic",
211 .minimum_version_id
= 0,
212 .post_load
= strongarm_pic_post_load
,
213 .fields
= (VMStateField
[]) {
214 VMSTATE_UINT32(pending
, StrongARMPICState
),
215 VMSTATE_UINT32(enabled
, StrongARMPICState
),
216 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
217 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
218 VMSTATE_END_OF_LIST(),
222 static void strongarm_pic_class_init(ObjectClass
*klass
, void *data
)
224 DeviceClass
*dc
= DEVICE_CLASS(klass
);
226 dc
->desc
= "StrongARM PIC";
227 dc
->vmsd
= &vmstate_strongarm_pic_regs
;
230 static const TypeInfo strongarm_pic_info
= {
231 .name
= TYPE_STRONGARM_PIC
,
232 .parent
= TYPE_SYS_BUS_DEVICE
,
233 .instance_size
= sizeof(StrongARMPICState
),
234 .instance_init
= strongarm_pic_initfn
,
235 .class_init
= strongarm_pic_class_init
,
238 /* Real-Time Clock */
239 #define RTAR 0x00 /* RTC Alarm register */
240 #define RCNR 0x04 /* RTC Counter register */
241 #define RTTR 0x08 /* RTC Timer Trim register */
242 #define RTSR 0x10 /* RTC Status register */
244 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
245 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
246 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
247 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
249 /* 16 LSB of RTTR are clockdiv for internal trim logic,
250 * trim delete isn't emulated, so
251 * f = 32 768 / (RTTR_trim + 1) */
253 #define TYPE_STRONGARM_RTC "strongarm-rtc"
254 #define STRONGARM_RTC(obj) \
255 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
257 typedef struct StrongARMRTCState
{
258 SysBusDevice parent_obj
;
266 QEMUTimer
*rtc_alarm
;
272 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
274 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
275 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
278 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
280 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
281 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
282 (1000 * ((s
->rttr
& 0xffff) + 1));
286 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
288 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
289 timer_mod(s
->rtc_hz
, s
->last_hz
+ 1000);
291 timer_del(s
->rtc_hz
);
294 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
295 timer_mod(s
->rtc_alarm
, s
->last_hz
+
296 (((s
->rtar
- s
->last_rcnr
) * 1000 *
297 ((s
->rttr
& 0xffff) + 1)) >> 15));
299 timer_del(s
->rtc_alarm
);
303 static inline void strongarm_rtc_alarm_tick(void *opaque
)
305 StrongARMRTCState
*s
= opaque
;
307 strongarm_rtc_timer_update(s
);
308 strongarm_rtc_int_update(s
);
311 static inline void strongarm_rtc_hz_tick(void *opaque
)
313 StrongARMRTCState
*s
= opaque
;
315 strongarm_rtc_timer_update(s
);
316 strongarm_rtc_int_update(s
);
319 static uint64_t strongarm_rtc_read(void *opaque
, hwaddr addr
,
322 StrongARMRTCState
*s
= opaque
;
332 return s
->last_rcnr
+
333 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
334 (1000 * ((s
->rttr
& 0xffff) + 1));
336 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
341 static void strongarm_rtc_write(void *opaque
, hwaddr addr
,
342 uint64_t value
, unsigned size
)
344 StrongARMRTCState
*s
= opaque
;
349 strongarm_rtc_hzupdate(s
);
351 strongarm_rtc_timer_update(s
);
356 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
357 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
359 if (s
->rtsr
!= old_rtsr
) {
360 strongarm_rtc_timer_update(s
);
363 strongarm_rtc_int_update(s
);
368 strongarm_rtc_timer_update(s
);
372 strongarm_rtc_hzupdate(s
);
373 s
->last_rcnr
= value
;
374 strongarm_rtc_timer_update(s
);
378 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
382 static const MemoryRegionOps strongarm_rtc_ops
= {
383 .read
= strongarm_rtc_read
,
384 .write
= strongarm_rtc_write
,
385 .endianness
= DEVICE_NATIVE_ENDIAN
,
388 static void strongarm_rtc_init(Object
*obj
)
390 StrongARMRTCState
*s
= STRONGARM_RTC(obj
);
391 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
397 qemu_get_timedate(&tm
, 0);
399 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
400 s
->last_hz
= qemu_clock_get_ms(rtc_clock
);
402 sysbus_init_irq(dev
, &s
->rtc_irq
);
403 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
405 memory_region_init_io(&s
->iomem
, obj
, &strongarm_rtc_ops
, s
,
407 sysbus_init_mmio(dev
, &s
->iomem
);
410 static void strongarm_rtc_realize(DeviceState
*dev
, Error
**errp
)
412 StrongARMRTCState
*s
= STRONGARM_RTC(dev
);
413 s
->rtc_alarm
= timer_new_ms(rtc_clock
, strongarm_rtc_alarm_tick
, s
);
414 s
->rtc_hz
= timer_new_ms(rtc_clock
, strongarm_rtc_hz_tick
, s
);
417 static int strongarm_rtc_pre_save(void *opaque
)
419 StrongARMRTCState
*s
= opaque
;
421 strongarm_rtc_hzupdate(s
);
426 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
428 StrongARMRTCState
*s
= opaque
;
430 strongarm_rtc_timer_update(s
);
431 strongarm_rtc_int_update(s
);
436 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
437 .name
= "strongarm-rtc",
439 .minimum_version_id
= 0,
440 .pre_save
= strongarm_rtc_pre_save
,
441 .post_load
= strongarm_rtc_post_load
,
442 .fields
= (VMStateField
[]) {
443 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
444 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
445 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
446 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
447 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
448 VMSTATE_END_OF_LIST(),
452 static void strongarm_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
454 DeviceClass
*dc
= DEVICE_CLASS(klass
);
456 dc
->desc
= "StrongARM RTC Controller";
457 dc
->vmsd
= &vmstate_strongarm_rtc_regs
;
458 dc
->realize
= strongarm_rtc_realize
;
461 static const TypeInfo strongarm_rtc_sysbus_info
= {
462 .name
= TYPE_STRONGARM_RTC
,
463 .parent
= TYPE_SYS_BUS_DEVICE
,
464 .instance_size
= sizeof(StrongARMRTCState
),
465 .instance_init
= strongarm_rtc_init
,
466 .class_init
= strongarm_rtc_sysbus_class_init
,
479 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
480 #define STRONGARM_GPIO(obj) \
481 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
483 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo
;
484 struct StrongARMGPIOInfo
{
487 qemu_irq handler
[28];
503 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
506 for (i
= 0; i
< 11; i
++) {
507 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
510 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
513 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
515 StrongARMGPIOInfo
*s
= opaque
;
521 s
->status
|= s
->rising
& mask
&
522 ~s
->ilevel
& ~s
->dir
;
525 s
->status
|= s
->falling
& mask
&
530 if (s
->status
& mask
) {
531 strongarm_gpio_irq_update(s
);
535 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
537 uint32_t level
, diff
;
540 level
= s
->olevel
& s
->dir
;
542 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
544 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
547 s
->prev_level
= level
;
550 static uint64_t strongarm_gpio_read(void *opaque
, hwaddr offset
,
553 StrongARMGPIOInfo
*s
= opaque
;
556 case GPDR
: /* GPIO Pin-Direction registers */
559 case GPSR
: /* GPIO Pin-Output Set registers */
560 qemu_log_mask(LOG_GUEST_ERROR
,
561 "strongarm GPIO: read from write only register GPSR\n");
564 case GPCR
: /* GPIO Pin-Output Clear registers */
565 qemu_log_mask(LOG_GUEST_ERROR
,
566 "strongarm GPIO: read from write only register GPCR\n");
569 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
572 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
575 case GAFR
: /* GPIO Alternate Function registers */
578 case GPLR
: /* GPIO Pin-Level registers */
579 return (s
->olevel
& s
->dir
) |
580 (s
->ilevel
& ~s
->dir
);
582 case GEDR
: /* GPIO Edge Detect Status registers */
586 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
592 static void strongarm_gpio_write(void *opaque
, hwaddr offset
,
593 uint64_t value
, unsigned size
)
595 StrongARMGPIOInfo
*s
= opaque
;
598 case GPDR
: /* GPIO Pin-Direction registers */
599 s
->dir
= value
& 0x0fffffff;
600 strongarm_gpio_handler_update(s
);
603 case GPSR
: /* GPIO Pin-Output Set registers */
604 s
->olevel
|= value
& 0x0fffffff;
605 strongarm_gpio_handler_update(s
);
608 case GPCR
: /* GPIO Pin-Output Clear registers */
610 strongarm_gpio_handler_update(s
);
613 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
617 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
621 case GAFR
: /* GPIO Alternate Function registers */
625 case GEDR
: /* GPIO Edge Detect Status registers */
627 strongarm_gpio_irq_update(s
);
631 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
635 static const MemoryRegionOps strongarm_gpio_ops
= {
636 .read
= strongarm_gpio_read
,
637 .write
= strongarm_gpio_write
,
638 .endianness
= DEVICE_NATIVE_ENDIAN
,
641 static DeviceState
*strongarm_gpio_init(hwaddr base
,
647 dev
= qdev_create(NULL
, TYPE_STRONGARM_GPIO
);
648 qdev_init_nofail(dev
);
650 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
651 for (i
= 0; i
< 12; i
++)
652 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
653 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
658 static void strongarm_gpio_initfn(Object
*obj
)
660 DeviceState
*dev
= DEVICE(obj
);
661 StrongARMGPIOInfo
*s
= STRONGARM_GPIO(obj
);
662 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
665 qdev_init_gpio_in(dev
, strongarm_gpio_set
, 28);
666 qdev_init_gpio_out(dev
, s
->handler
, 28);
668 memory_region_init_io(&s
->iomem
, obj
, &strongarm_gpio_ops
, s
,
671 sysbus_init_mmio(sbd
, &s
->iomem
);
672 for (i
= 0; i
< 11; i
++) {
673 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
675 sysbus_init_irq(sbd
, &s
->irqX
);
678 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
679 .name
= "strongarm-gpio",
681 .minimum_version_id
= 0,
682 .fields
= (VMStateField
[]) {
683 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
684 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
685 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
686 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
687 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
688 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
689 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
690 VMSTATE_UINT32(prev_level
, StrongARMGPIOInfo
),
691 VMSTATE_END_OF_LIST(),
695 static void strongarm_gpio_class_init(ObjectClass
*klass
, void *data
)
697 DeviceClass
*dc
= DEVICE_CLASS(klass
);
699 dc
->desc
= "StrongARM GPIO controller";
700 dc
->vmsd
= &vmstate_strongarm_gpio_regs
;
703 static const TypeInfo strongarm_gpio_info
= {
704 .name
= TYPE_STRONGARM_GPIO
,
705 .parent
= TYPE_SYS_BUS_DEVICE
,
706 .instance_size
= sizeof(StrongARMGPIOInfo
),
707 .instance_init
= strongarm_gpio_initfn
,
708 .class_init
= strongarm_gpio_class_init
,
711 /* Peripheral Pin Controller */
718 #define TYPE_STRONGARM_PPC "strongarm-ppc"
719 #define STRONGARM_PPC(obj) \
720 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
722 typedef struct StrongARMPPCInfo StrongARMPPCInfo
;
723 struct StrongARMPPCInfo
{
724 SysBusDevice parent_obj
;
727 qemu_irq handler
[28];
739 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
741 StrongARMPPCInfo
*s
= opaque
;
744 s
->ilevel
|= 1 << line
;
746 s
->ilevel
&= ~(1 << line
);
750 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
752 uint32_t level
, diff
;
755 level
= s
->olevel
& s
->dir
;
757 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
759 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
762 s
->prev_level
= level
;
765 static uint64_t strongarm_ppc_read(void *opaque
, hwaddr offset
,
768 StrongARMPPCInfo
*s
= opaque
;
771 case PPDR
: /* PPC Pin Direction registers */
772 return s
->dir
| ~0x3fffff;
774 case PPSR
: /* PPC Pin State registers */
775 return (s
->olevel
& s
->dir
) |
776 (s
->ilevel
& ~s
->dir
) |
780 return s
->ppar
| ~0x41000;
786 return s
->ppfr
| ~0x7f001;
789 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
795 static void strongarm_ppc_write(void *opaque
, hwaddr offset
,
796 uint64_t value
, unsigned size
)
798 StrongARMPPCInfo
*s
= opaque
;
801 case PPDR
: /* PPC Pin Direction registers */
802 s
->dir
= value
& 0x3fffff;
803 strongarm_ppc_handler_update(s
);
806 case PPSR
: /* PPC Pin State registers */
807 s
->olevel
= value
& s
->dir
& 0x3fffff;
808 strongarm_ppc_handler_update(s
);
812 s
->ppar
= value
& 0x41000;
816 s
->psdr
= value
& 0x3fffff;
820 s
->ppfr
= value
& 0x7f001;
824 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
828 static const MemoryRegionOps strongarm_ppc_ops
= {
829 .read
= strongarm_ppc_read
,
830 .write
= strongarm_ppc_write
,
831 .endianness
= DEVICE_NATIVE_ENDIAN
,
834 static void strongarm_ppc_init(Object
*obj
)
836 DeviceState
*dev
= DEVICE(obj
);
837 StrongARMPPCInfo
*s
= STRONGARM_PPC(obj
);
838 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
840 qdev_init_gpio_in(dev
, strongarm_ppc_set
, 22);
841 qdev_init_gpio_out(dev
, s
->handler
, 22);
843 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ppc_ops
, s
,
846 sysbus_init_mmio(sbd
, &s
->iomem
);
849 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
850 .name
= "strongarm-ppc",
852 .minimum_version_id
= 0,
853 .fields
= (VMStateField
[]) {
854 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
855 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
856 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
857 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
858 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
859 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
860 VMSTATE_UINT32(prev_level
, StrongARMPPCInfo
),
861 VMSTATE_END_OF_LIST(),
865 static void strongarm_ppc_class_init(ObjectClass
*klass
, void *data
)
867 DeviceClass
*dc
= DEVICE_CLASS(klass
);
869 dc
->desc
= "StrongARM PPC controller";
870 dc
->vmsd
= &vmstate_strongarm_ppc_regs
;
873 static const TypeInfo strongarm_ppc_info
= {
874 .name
= TYPE_STRONGARM_PPC
,
875 .parent
= TYPE_SYS_BUS_DEVICE
,
876 .instance_size
= sizeof(StrongARMPPCInfo
),
877 .instance_init
= strongarm_ppc_init
,
878 .class_init
= strongarm_ppc_class_init
,
890 #define UTCR0_PE (1 << 0) /* Parity enable */
891 #define UTCR0_OES (1 << 1) /* Even parity */
892 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
893 #define UTCR0_DSS (1 << 3) /* 8-bit data */
895 #define UTCR3_RXE (1 << 0) /* Rx enable */
896 #define UTCR3_TXE (1 << 1) /* Tx enable */
897 #define UTCR3_BRK (1 << 2) /* Force Break */
898 #define UTCR3_RIE (1 << 3) /* Rx int enable */
899 #define UTCR3_TIE (1 << 4) /* Tx int enable */
900 #define UTCR3_LBM (1 << 5) /* Loopback */
902 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
903 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
904 #define UTSR0_RID (1 << 2) /* Receiver Idle */
905 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
906 #define UTSR0_REB (1 << 4) /* Receiver end break */
907 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
909 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
910 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
911 #define UTSR1_PRE (1 << 3) /* Parity error */
912 #define UTSR1_FRE (1 << 4) /* Frame error */
913 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
915 #define RX_FIFO_PRE (1 << 8)
916 #define RX_FIFO_FRE (1 << 9)
917 #define RX_FIFO_ROR (1 << 10)
919 #define TYPE_STRONGARM_UART "strongarm-uart"
920 #define STRONGARM_UART(obj) \
921 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
923 typedef struct StrongARMUARTState
{
924 SysBusDevice parent_obj
;
939 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
943 uint64_t char_transmit_time
; /* time to transmit a char in ticks*/
945 QEMUTimer
*rx_timeout_timer
;
947 } StrongARMUARTState
;
949 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
953 if (s
->tx_len
!= 8) {
957 if (s
->rx_len
!= 0) {
958 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
961 if (ent
& RX_FIFO_PRE
) {
962 s
->utsr1
|= UTSR1_PRE
;
964 if (ent
& RX_FIFO_FRE
) {
965 s
->utsr1
|= UTSR1_FRE
;
967 if (ent
& RX_FIFO_ROR
) {
968 s
->utsr1
|= UTSR1_ROR
;
975 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
977 uint16_t utsr0
= s
->utsr0
&
978 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
981 if ((s
->utcr3
& UTCR3_TXE
) &&
982 (s
->utcr3
& UTCR3_TIE
) &&
987 if ((s
->utcr3
& UTCR3_RXE
) &&
988 (s
->utcr3
& UTCR3_RIE
) &&
993 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
994 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
1000 qemu_set_irq(s
->irq
, utsr0
);
1003 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
1005 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
1006 QEMUSerialSetParams ssp
;
1010 if (s
->utcr0
& UTCR0_PE
) {
1013 if (s
->utcr0
& UTCR0_OES
) {
1021 if (s
->utcr0
& UTCR0_SBS
) {
1027 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
1028 frame_size
+= data_bits
+ stop_bits
;
1029 speed
= 3686400 / 16 / (s
->brd
+ 1);
1031 ssp
.parity
= parity
;
1032 ssp
.data_bits
= data_bits
;
1033 ssp
.stop_bits
= stop_bits
;
1034 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
1035 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1037 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
1038 speed
, parity
, data_bits
, stop_bits
);
1041 static void strongarm_uart_rx_to(void *opaque
)
1043 StrongARMUARTState
*s
= opaque
;
1046 s
->utsr0
|= UTSR0_RID
;
1047 strongarm_uart_update_int_status(s
);
1051 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
1053 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1058 if (s
->wait_break_end
) {
1059 s
->utsr0
|= UTSR0_REB
;
1060 s
->wait_break_end
= false;
1063 if (s
->rx_len
< 12) {
1064 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
1067 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
1070 static int strongarm_uart_can_receive(void *opaque
)
1072 StrongARMUARTState
*s
= opaque
;
1074 if (s
->rx_len
== 12) {
1077 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1078 if (s
->rx_len
< 8) {
1079 return 8 - s
->rx_len
;
1084 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1086 StrongARMUARTState
*s
= opaque
;
1089 for (i
= 0; i
< size
; i
++) {
1090 strongarm_uart_rx_push(s
, buf
[i
]);
1093 /* call the timeout receive callback in 3 char transmit time */
1094 timer_mod(s
->rx_timeout_timer
,
1095 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1097 strongarm_uart_update_status(s
);
1098 strongarm_uart_update_int_status(s
);
1101 static void strongarm_uart_event(void *opaque
, QEMUChrEvent event
)
1103 StrongARMUARTState
*s
= opaque
;
1104 if (event
== CHR_EVENT_BREAK
) {
1105 s
->utsr0
|= UTSR0_RBB
;
1106 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1107 s
->wait_break_end
= true;
1108 strongarm_uart_update_status(s
);
1109 strongarm_uart_update_int_status(s
);
1113 static void strongarm_uart_tx(void *opaque
)
1115 StrongARMUARTState
*s
= opaque
;
1116 uint64_t new_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1118 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1119 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1120 } else if (qemu_chr_fe_backend_connected(&s
->chr
)) {
1121 /* XXX this blocks entire thread. Rewrite to use
1122 * qemu_chr_fe_write and background I/O callbacks */
1123 qemu_chr_fe_write_all(&s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1126 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1129 timer_mod(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1131 strongarm_uart_update_status(s
);
1132 strongarm_uart_update_int_status(s
);
1135 static uint64_t strongarm_uart_read(void *opaque
, hwaddr addr
,
1138 StrongARMUARTState
*s
= opaque
;
1149 return s
->brd
& 0xff;
1155 if (s
->rx_len
!= 0) {
1156 ret
= s
->rx_fifo
[s
->rx_start
];
1157 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1159 strongarm_uart_update_status(s
);
1160 strongarm_uart_update_int_status(s
);
1172 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1177 static void strongarm_uart_write(void *opaque
, hwaddr addr
,
1178 uint64_t value
, unsigned size
)
1180 StrongARMUARTState
*s
= opaque
;
1184 s
->utcr0
= value
& 0x7f;
1185 strongarm_uart_update_parameters(s
);
1189 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1190 strongarm_uart_update_parameters(s
);
1194 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1195 strongarm_uart_update_parameters(s
);
1199 s
->utcr3
= value
& 0x3f;
1200 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1203 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1206 strongarm_uart_update_status(s
);
1207 strongarm_uart_update_int_status(s
);
1211 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1212 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1214 strongarm_uart_update_status(s
);
1215 strongarm_uart_update_int_status(s
);
1216 if (s
->tx_len
== 1) {
1217 strongarm_uart_tx(s
);
1223 s
->utsr0
= s
->utsr0
& ~(value
&
1224 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1225 strongarm_uart_update_int_status(s
);
1229 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1233 static const MemoryRegionOps strongarm_uart_ops
= {
1234 .read
= strongarm_uart_read
,
1235 .write
= strongarm_uart_write
,
1236 .endianness
= DEVICE_NATIVE_ENDIAN
,
1239 static void strongarm_uart_init(Object
*obj
)
1241 StrongARMUARTState
*s
= STRONGARM_UART(obj
);
1242 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1244 memory_region_init_io(&s
->iomem
, obj
, &strongarm_uart_ops
, s
,
1246 sysbus_init_mmio(dev
, &s
->iomem
);
1247 sysbus_init_irq(dev
, &s
->irq
);
1250 static void strongarm_uart_realize(DeviceState
*dev
, Error
**errp
)
1252 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1254 s
->rx_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
1255 strongarm_uart_rx_to
,
1257 s
->tx_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_tx
, s
);
1258 qemu_chr_fe_set_handlers(&s
->chr
,
1259 strongarm_uart_can_receive
,
1260 strongarm_uart_receive
,
1261 strongarm_uart_event
,
1262 NULL
, s
, NULL
, true);
1265 static void strongarm_uart_reset(DeviceState
*dev
)
1267 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1269 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1270 s
->brd
= 23; /* 9600 */
1271 /* enable send & recv - this actually violates spec */
1272 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1274 s
->rx_len
= s
->tx_len
= 0;
1276 strongarm_uart_update_parameters(s
);
1277 strongarm_uart_update_status(s
);
1278 strongarm_uart_update_int_status(s
);
1281 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1283 StrongARMUARTState
*s
= opaque
;
1285 strongarm_uart_update_parameters(s
);
1286 strongarm_uart_update_status(s
);
1287 strongarm_uart_update_int_status(s
);
1289 /* tx and restart timer */
1291 strongarm_uart_tx(s
);
1294 /* restart rx timeout timer */
1296 timer_mod(s
->rx_timeout_timer
,
1297 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1303 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1304 .name
= "strongarm-uart",
1306 .minimum_version_id
= 0,
1307 .post_load
= strongarm_uart_post_load
,
1308 .fields
= (VMStateField
[]) {
1309 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1310 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1311 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1312 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1313 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1314 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1315 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1316 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1317 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1318 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1319 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1320 VMSTATE_END_OF_LIST(),
1324 static Property strongarm_uart_properties
[] = {
1325 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1326 DEFINE_PROP_END_OF_LIST(),
1329 static void strongarm_uart_class_init(ObjectClass
*klass
, void *data
)
1331 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1333 dc
->desc
= "StrongARM UART controller";
1334 dc
->reset
= strongarm_uart_reset
;
1335 dc
->vmsd
= &vmstate_strongarm_uart_regs
;
1336 device_class_set_props(dc
, strongarm_uart_properties
);
1337 dc
->realize
= strongarm_uart_realize
;
1340 static const TypeInfo strongarm_uart_info
= {
1341 .name
= TYPE_STRONGARM_UART
,
1342 .parent
= TYPE_SYS_BUS_DEVICE
,
1343 .instance_size
= sizeof(StrongARMUARTState
),
1344 .instance_init
= strongarm_uart_init
,
1345 .class_init
= strongarm_uart_class_init
,
1348 /* Synchronous Serial Ports */
1350 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1351 #define STRONGARM_SSP(obj) \
1352 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1354 typedef struct StrongARMSSPState
{
1355 SysBusDevice parent_obj
;
1364 uint16_t rx_fifo
[8];
1367 } StrongARMSSPState
;
1369 #define SSCR0 0x60 /* SSP Control register 0 */
1370 #define SSCR1 0x64 /* SSP Control register 1 */
1371 #define SSDR 0x6c /* SSP Data register */
1372 #define SSSR 0x74 /* SSP Status register */
1374 /* Bitfields for above registers */
1375 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1376 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1377 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1378 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1379 #define SSCR0_SSE (1 << 7)
1380 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1381 #define SSCR1_RIE (1 << 0)
1382 #define SSCR1_TIE (1 << 1)
1383 #define SSCR1_LBM (1 << 2)
1384 #define SSSR_TNF (1 << 2)
1385 #define SSSR_RNE (1 << 3)
1386 #define SSSR_TFS (1 << 5)
1387 #define SSSR_RFS (1 << 6)
1388 #define SSSR_ROR (1 << 7)
1389 #define SSSR_RW 0x0080
1391 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1395 level
|= (s
->sssr
& SSSR_ROR
);
1396 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1397 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1398 qemu_set_irq(s
->irq
, level
);
1401 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1403 s
->sssr
&= ~SSSR_TFS
;
1404 s
->sssr
&= ~SSSR_TNF
;
1405 if (s
->sscr
[0] & SSCR0_SSE
) {
1406 if (s
->rx_level
>= 4) {
1407 s
->sssr
|= SSSR_RFS
;
1409 s
->sssr
&= ~SSSR_RFS
;
1412 s
->sssr
|= SSSR_RNE
;
1414 s
->sssr
&= ~SSSR_RNE
;
1416 /* TX FIFO is never filled, so it is always in underrun
1417 condition if SSP is enabled */
1418 s
->sssr
|= SSSR_TFS
;
1419 s
->sssr
|= SSSR_TNF
;
1422 strongarm_ssp_int_update(s
);
1425 static uint64_t strongarm_ssp_read(void *opaque
, hwaddr addr
,
1428 StrongARMSSPState
*s
= opaque
;
1439 if (~s
->sscr
[0] & SSCR0_SSE
) {
1442 if (s
->rx_level
< 1) {
1443 printf("%s: SSP Rx Underrun\n", __func__
);
1447 retval
= s
->rx_fifo
[s
->rx_start
++];
1449 strongarm_ssp_fifo_update(s
);
1452 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1458 static void strongarm_ssp_write(void *opaque
, hwaddr addr
,
1459 uint64_t value
, unsigned size
)
1461 StrongARMSSPState
*s
= opaque
;
1465 s
->sscr
[0] = value
& 0xffbf;
1466 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1467 printf("%s: Wrong data size: %i bits\n", __func__
,
1468 (int)SSCR0_DSS(value
));
1470 if (!(value
& SSCR0_SSE
)) {
1474 strongarm_ssp_fifo_update(s
);
1478 s
->sscr
[1] = value
& 0x2f;
1479 if (value
& SSCR1_LBM
) {
1480 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1482 strongarm_ssp_fifo_update(s
);
1486 s
->sssr
&= ~(value
& SSSR_RW
);
1487 strongarm_ssp_int_update(s
);
1491 if (SSCR0_UWIRE(s
->sscr
[0])) {
1494 /* Note how 32bits overflow does no harm here */
1495 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1497 /* Data goes from here to the Tx FIFO and is shifted out from
1498 * there directly to the slave, no need to buffer it.
1500 if (s
->sscr
[0] & SSCR0_SSE
) {
1502 if (s
->sscr
[1] & SSCR1_LBM
) {
1505 readval
= ssi_transfer(s
->bus
, value
);
1508 if (s
->rx_level
< 0x08) {
1509 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1511 s
->sssr
|= SSSR_ROR
;
1514 strongarm_ssp_fifo_update(s
);
1518 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1523 static const MemoryRegionOps strongarm_ssp_ops
= {
1524 .read
= strongarm_ssp_read
,
1525 .write
= strongarm_ssp_write
,
1526 .endianness
= DEVICE_NATIVE_ENDIAN
,
1529 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1531 StrongARMSSPState
*s
= opaque
;
1533 strongarm_ssp_fifo_update(s
);
1538 static void strongarm_ssp_init(Object
*obj
)
1540 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1541 DeviceState
*dev
= DEVICE(sbd
);
1542 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1544 sysbus_init_irq(sbd
, &s
->irq
);
1546 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ssp_ops
, s
,
1548 sysbus_init_mmio(sbd
, &s
->iomem
);
1550 s
->bus
= ssi_create_bus(dev
, "ssi");
1553 static void strongarm_ssp_reset(DeviceState
*dev
)
1555 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1557 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1562 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1563 .name
= "strongarm-ssp",
1565 .minimum_version_id
= 0,
1566 .post_load
= strongarm_ssp_post_load
,
1567 .fields
= (VMStateField
[]) {
1568 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1569 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1570 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1571 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1572 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1573 VMSTATE_END_OF_LIST(),
1577 static void strongarm_ssp_class_init(ObjectClass
*klass
, void *data
)
1579 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1581 dc
->desc
= "StrongARM SSP controller";
1582 dc
->reset
= strongarm_ssp_reset
;
1583 dc
->vmsd
= &vmstate_strongarm_ssp_regs
;
1586 static const TypeInfo strongarm_ssp_info
= {
1587 .name
= TYPE_STRONGARM_SSP
,
1588 .parent
= TYPE_SYS_BUS_DEVICE
,
1589 .instance_size
= sizeof(StrongARMSSPState
),
1590 .instance_init
= strongarm_ssp_init
,
1591 .class_init
= strongarm_ssp_class_init
,
1594 /* Main CPU functions */
1595 StrongARMState
*sa1110_init(const char *cpu_type
)
1600 s
= g_new0(StrongARMState
, 1);
1602 if (strncmp(cpu_type
, "sa1110", 6)) {
1603 error_report("Machine requires a SA1110 processor.");
1607 s
->cpu
= ARM_CPU(cpu_create(cpu_type
));
1609 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1610 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
),
1611 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
),
1614 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1615 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1616 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1617 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1618 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1621 sysbus_create_simple(TYPE_STRONGARM_RTC
, 0x90010000,
1622 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1624 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1626 s
->ppc
= sysbus_create_varargs(TYPE_STRONGARM_PPC
, 0x90060000, NULL
);
1628 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1629 DeviceState
*dev
= qdev_create(NULL
, TYPE_STRONGARM_UART
);
1630 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
1631 qdev_init_nofail(dev
);
1632 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1633 sa_serial
[i
].io_base
);
1634 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
1635 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1638 s
->ssp
= sysbus_create_varargs(TYPE_STRONGARM_SSP
, 0x80070000,
1639 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1640 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1645 static void strongarm_register_types(void)
1647 type_register_static(&strongarm_pic_info
);
1648 type_register_static(&strongarm_rtc_sysbus_info
);
1649 type_register_static(&strongarm_gpio_info
);
1650 type_register_static(&strongarm_ppc_info
);
1651 type_register_static(&strongarm_uart_info
);
1652 type_register_static(&strongarm_ssp_info
);
1655 type_init(strongarm_register_types
)