4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline int get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
111 switch (s
->mmu_idx
) {
112 case ARMMMUIdx_S12NSE1
:
113 useridx
= ARMMMUIdx_S12NSE0
;
115 case ARMMMUIdx_S1SE1
:
116 useridx
= ARMMMUIdx_S1SE0
;
119 g_assert_not_reached();
121 useridx
= s
->mmu_idx
;
124 return arm_to_core_mmu_idx(useridx
);
127 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
128 fprintf_function cpu_fprintf
, int flags
)
130 ARMCPU
*cpu
= ARM_CPU(cs
);
131 CPUARMState
*env
= &cpu
->env
;
132 uint32_t psr
= pstate_read(env
);
134 int el
= arm_current_el(env
);
135 const char *ns_status
;
137 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
138 env
->pc
, env
->xregs
[31]);
139 for (i
= 0; i
< 31; i
++) {
140 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
142 cpu_fprintf(f
, "\n");
148 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
149 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
154 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
156 psr
& PSTATE_N
? 'N' : '-',
157 psr
& PSTATE_Z
? 'Z' : '-',
158 psr
& PSTATE_C
? 'C' : '-',
159 psr
& PSTATE_V
? 'V' : '-',
162 psr
& PSTATE_SP
? 'h' : 't');
164 if (flags
& CPU_DUMP_FPU
) {
166 for (i
= 0; i
< numvfpregs
; i
+= 2) {
167 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
168 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
169 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
171 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
172 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
173 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
176 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
177 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
181 void gen_a64_set_pc_im(uint64_t val
)
183 tcg_gen_movi_i64(cpu_pc
, val
);
186 /* Load the PC from a generic TCG variable.
188 * If address tagging is enabled via the TCR TBI bits, then loading
189 * an address into the PC will clear out any tag in the it:
190 * + for EL2 and EL3 there is only one TBI bit, and if it is set
191 * then the address is zero-extended, clearing bits [63:56]
192 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
193 * and TBI1 controls addressses with bit 55 == 1.
194 * If the appropriate TBI bit is set for the address then
195 * the address is sign-extended from bit 55 into bits [63:56]
197 * We can avoid doing this for relative-branches, because the
198 * PC + offset can never overflow into the tag bits (assuming
199 * that virtual addresses are less than 56 bits wide, as they
200 * are currently), but we must handle it for branch-to-register.
202 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
205 if (s
->current_el
<= 1) {
206 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
207 * examine bit 55 of address, can just generate code.
208 * If mixed, then test via generated code
210 if (s
->tbi0
&& s
->tbi1
) {
211 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
212 /* Both bits set, sign extension from bit 55 into [63:56] will
215 tcg_gen_shli_i64(tmp_reg
, src
, 8);
216 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
217 tcg_temp_free_i64(tmp_reg
);
218 } else if (!s
->tbi0
&& !s
->tbi1
) {
219 /* Neither bit set, just load it as-is */
220 tcg_gen_mov_i64(cpu_pc
, src
);
222 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
223 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
224 TCGv_i64 tcg_zero
= tcg_const_i64(0);
226 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
229 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
230 tcg_gen_andi_i64(tcg_tmpval
, src
,
231 0x00FFFFFFFFFFFFFFull
);
232 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
236 tcg_gen_ori_i64(tcg_tmpval
, src
,
237 0xFF00000000000000ull
);
238 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
241 tcg_temp_free_i64(tcg_zero
);
242 tcg_temp_free_i64(tcg_bit55
);
243 tcg_temp_free_i64(tcg_tmpval
);
245 } else { /* EL > 1 */
247 /* Force tag byte to all zero */
248 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
250 /* Load unmodified address */
251 tcg_gen_mov_i64(cpu_pc
, src
);
256 typedef struct DisasCompare64
{
261 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
265 arm_test_cc(&c32
, cc
);
267 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
268 * properly. The NE/EQ comparisons are also fine with this choice. */
269 c64
->cond
= c32
.cond
;
270 c64
->value
= tcg_temp_new_i64();
271 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
276 static void a64_free_cc(DisasCompare64
*c64
)
278 tcg_temp_free_i64(c64
->value
);
281 static void gen_exception_internal(int excp
)
283 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
285 assert(excp_is_internal(excp
));
286 gen_helper_exception_internal(cpu_env
, tcg_excp
);
287 tcg_temp_free_i32(tcg_excp
);
290 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
292 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
293 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
294 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
296 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
298 tcg_temp_free_i32(tcg_el
);
299 tcg_temp_free_i32(tcg_syn
);
300 tcg_temp_free_i32(tcg_excp
);
303 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
305 gen_a64_set_pc_im(s
->pc
- offset
);
306 gen_exception_internal(excp
);
307 s
->is_jmp
= DISAS_EXC
;
310 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
311 uint32_t syndrome
, uint32_t target_el
)
313 gen_a64_set_pc_im(s
->pc
- offset
);
314 gen_exception(excp
, syndrome
, target_el
);
315 s
->is_jmp
= DISAS_EXC
;
318 static void gen_ss_advance(DisasContext
*s
)
320 /* If the singlestep state is Active-not-pending, advance to
325 gen_helper_clear_pstate_ss(cpu_env
);
329 static void gen_step_complete_exception(DisasContext
*s
)
331 /* We just completed step of an insn. Move from Active-not-pending
332 * to Active-pending, and then also take the swstep exception.
333 * This corresponds to making the (IMPDEF) choice to prioritize
334 * swstep exceptions over asynchronous exceptions taken to an exception
335 * level where debug is disabled. This choice has the advantage that
336 * we do not need to maintain internal state corresponding to the
337 * ISV/EX syndrome bits between completion of the step and generation
338 * of the exception, and our syndrome information is always correct.
341 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
342 default_exception_el(s
));
343 s
->is_jmp
= DISAS_EXC
;
346 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
348 /* No direct tb linking with singlestep (either QEMU's or the ARM
349 * debug architecture kind) or deterministic io
351 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
355 #ifndef CONFIG_USER_ONLY
356 /* Only link tbs from inside the same guest page */
357 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
365 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
367 TranslationBlock
*tb
;
370 if (use_goto_tb(s
, n
, dest
)) {
372 gen_a64_set_pc_im(dest
);
373 tcg_gen_exit_tb((intptr_t)tb
+ n
);
374 s
->is_jmp
= DISAS_TB_JUMP
;
376 gen_a64_set_pc_im(dest
);
378 gen_step_complete_exception(s
);
379 } else if (s
->singlestep_enabled
) {
380 gen_exception_internal(EXCP_DEBUG
);
382 tcg_gen_lookup_and_goto_ptr(cpu_pc
);
383 s
->is_jmp
= DISAS_TB_JUMP
;
388 static void unallocated_encoding(DisasContext
*s
)
390 /* Unallocated and reserved encodings are uncategorized */
391 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
392 default_exception_el(s
));
395 #define unsupported_encoding(s, insn) \
397 qemu_log_mask(LOG_UNIMP, \
398 "%s:%d: unsupported instruction encoding 0x%08x " \
399 "at pc=%016" PRIx64 "\n", \
400 __FILE__, __LINE__, insn, s->pc - 4); \
401 unallocated_encoding(s); \
404 static void init_tmp_a64_array(DisasContext
*s
)
406 #ifdef CONFIG_DEBUG_TCG
408 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
409 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
412 s
->tmp_a64_count
= 0;
415 static void free_tmp_a64(DisasContext
*s
)
418 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
419 tcg_temp_free_i64(s
->tmp_a64
[i
]);
421 init_tmp_a64_array(s
);
424 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
426 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
427 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
430 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
432 TCGv_i64 t
= new_tmp_a64(s
);
433 tcg_gen_movi_i64(t
, 0);
438 * Register access functions
440 * These functions are used for directly accessing a register in where
441 * changes to the final register value are likely to be made. If you
442 * need to use a register for temporary calculation (e.g. index type
443 * operations) use the read_* form.
445 * B1.2.1 Register mappings
447 * In instruction register encoding 31 can refer to ZR (zero register) or
448 * the SP (stack pointer) depending on context. In QEMU's case we map SP
449 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
450 * This is the point of the _sp forms.
452 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
455 return new_tmp_a64_zero(s
);
461 /* register access for when 31 == SP */
462 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
467 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
468 * representing the register contents. This TCGv is an auto-freed
469 * temporary so it need not be explicitly freed, and may be modified.
471 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
473 TCGv_i64 v
= new_tmp_a64(s
);
476 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
478 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
481 tcg_gen_movi_i64(v
, 0);
486 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
488 TCGv_i64 v
= new_tmp_a64(s
);
490 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
492 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
497 /* We should have at some point before trying to access an FP register
498 * done the necessary access check, so assert that
499 * (a) we did the check and
500 * (b) we didn't then just plough ahead anyway if it failed.
501 * Print the instruction pattern in the abort message so we can figure
502 * out what we need to fix if a user encounters this problem in the wild.
504 static inline void assert_fp_access_checked(DisasContext
*s
)
506 #ifdef CONFIG_DEBUG_TCG
507 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
508 fprintf(stderr
, "target-arm: FP access check missing for "
509 "instruction 0x%08x\n", s
->insn
);
515 /* Return the offset into CPUARMState of an element of specified
516 * size, 'element' places in from the least significant end of
517 * the FP/vector register Qn.
519 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
520 int element
, TCGMemOp size
)
523 #ifdef HOST_WORDS_BIGENDIAN
524 /* This is complicated slightly because vfp.regs[2n] is
525 * still the low half and vfp.regs[2n+1] the high half
526 * of the 128 bit vector, even on big endian systems.
527 * Calculate the offset assuming a fully bigendian 128 bits,
528 * then XOR to account for the order of the two 64 bit halves.
530 offs
+= (16 - ((element
+ 1) * (1 << size
)));
533 offs
+= element
* (1 << size
);
535 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
536 assert_fp_access_checked(s
);
540 /* Return the offset into CPUARMState of a slice (from
541 * the least significant end) of FP register Qn (ie
543 * (Note that this is not the same mapping as for A32; see cpu.h)
545 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
547 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
548 #ifdef HOST_WORDS_BIGENDIAN
549 offs
+= (8 - (1 << size
));
551 assert_fp_access_checked(s
);
555 /* Offset of the high half of the 128 bit vector Qn */
556 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
558 assert_fp_access_checked(s
);
559 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
562 /* Convenience accessors for reading and writing single and double
563 * FP registers. Writing clears the upper parts of the associated
564 * 128 bit vector register, as required by the architecture.
565 * Note that unlike the GP register accessors, the values returned
566 * by the read functions must be manually freed.
568 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
570 TCGv_i64 v
= tcg_temp_new_i64();
572 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
576 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
578 TCGv_i32 v
= tcg_temp_new_i32();
580 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
584 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
586 TCGv_i64 tcg_zero
= tcg_const_i64(0);
588 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
589 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
590 tcg_temp_free_i64(tcg_zero
);
593 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
595 TCGv_i64 tmp
= tcg_temp_new_i64();
597 tcg_gen_extu_i32_i64(tmp
, v
);
598 write_fp_dreg(s
, reg
, tmp
);
599 tcg_temp_free_i64(tmp
);
602 static TCGv_ptr
get_fpstatus_ptr(void)
604 TCGv_ptr statusptr
= tcg_temp_new_ptr();
607 /* In A64 all instructions (both FP and Neon) use the FPCR;
608 * there is no equivalent of the A32 Neon "standard FPSCR value"
609 * and all operations use vfp.fp_status.
611 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
612 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
616 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
617 * than the 32 bit equivalent.
619 static inline void gen_set_NZ64(TCGv_i64 result
)
621 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
622 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
625 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
626 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
629 gen_set_NZ64(result
);
631 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
632 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
634 tcg_gen_movi_i32(cpu_CF
, 0);
635 tcg_gen_movi_i32(cpu_VF
, 0);
638 /* dest = T0 + T1; compute C, N, V and Z flags */
639 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
642 TCGv_i64 result
, flag
, tmp
;
643 result
= tcg_temp_new_i64();
644 flag
= tcg_temp_new_i64();
645 tmp
= tcg_temp_new_i64();
647 tcg_gen_movi_i64(tmp
, 0);
648 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
650 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
652 gen_set_NZ64(result
);
654 tcg_gen_xor_i64(flag
, result
, t0
);
655 tcg_gen_xor_i64(tmp
, t0
, t1
);
656 tcg_gen_andc_i64(flag
, flag
, tmp
);
657 tcg_temp_free_i64(tmp
);
658 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
660 tcg_gen_mov_i64(dest
, result
);
661 tcg_temp_free_i64(result
);
662 tcg_temp_free_i64(flag
);
664 /* 32 bit arithmetic */
665 TCGv_i32 t0_32
= tcg_temp_new_i32();
666 TCGv_i32 t1_32
= tcg_temp_new_i32();
667 TCGv_i32 tmp
= tcg_temp_new_i32();
669 tcg_gen_movi_i32(tmp
, 0);
670 tcg_gen_extrl_i64_i32(t0_32
, t0
);
671 tcg_gen_extrl_i64_i32(t1_32
, t1
);
672 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
673 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
674 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
675 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
676 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
677 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
679 tcg_temp_free_i32(tmp
);
680 tcg_temp_free_i32(t0_32
);
681 tcg_temp_free_i32(t1_32
);
685 /* dest = T0 - T1; compute C, N, V and Z flags */
686 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
689 /* 64 bit arithmetic */
690 TCGv_i64 result
, flag
, tmp
;
692 result
= tcg_temp_new_i64();
693 flag
= tcg_temp_new_i64();
694 tcg_gen_sub_i64(result
, t0
, t1
);
696 gen_set_NZ64(result
);
698 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
699 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
701 tcg_gen_xor_i64(flag
, result
, t0
);
702 tmp
= tcg_temp_new_i64();
703 tcg_gen_xor_i64(tmp
, t0
, t1
);
704 tcg_gen_and_i64(flag
, flag
, tmp
);
705 tcg_temp_free_i64(tmp
);
706 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
707 tcg_gen_mov_i64(dest
, result
);
708 tcg_temp_free_i64(flag
);
709 tcg_temp_free_i64(result
);
711 /* 32 bit arithmetic */
712 TCGv_i32 t0_32
= tcg_temp_new_i32();
713 TCGv_i32 t1_32
= tcg_temp_new_i32();
716 tcg_gen_extrl_i64_i32(t0_32
, t0
);
717 tcg_gen_extrl_i64_i32(t1_32
, t1
);
718 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
719 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
720 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
721 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
722 tmp
= tcg_temp_new_i32();
723 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
724 tcg_temp_free_i32(t0_32
);
725 tcg_temp_free_i32(t1_32
);
726 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
727 tcg_temp_free_i32(tmp
);
728 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
732 /* dest = T0 + T1 + CF; do not compute flags. */
733 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
735 TCGv_i64 flag
= tcg_temp_new_i64();
736 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
737 tcg_gen_add_i64(dest
, t0
, t1
);
738 tcg_gen_add_i64(dest
, dest
, flag
);
739 tcg_temp_free_i64(flag
);
742 tcg_gen_ext32u_i64(dest
, dest
);
746 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
747 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
750 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
751 result
= tcg_temp_new_i64();
752 cf_64
= tcg_temp_new_i64();
753 vf_64
= tcg_temp_new_i64();
754 tmp
= tcg_const_i64(0);
756 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
757 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
758 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
759 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
760 gen_set_NZ64(result
);
762 tcg_gen_xor_i64(vf_64
, result
, t0
);
763 tcg_gen_xor_i64(tmp
, t0
, t1
);
764 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
765 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
767 tcg_gen_mov_i64(dest
, result
);
769 tcg_temp_free_i64(tmp
);
770 tcg_temp_free_i64(vf_64
);
771 tcg_temp_free_i64(cf_64
);
772 tcg_temp_free_i64(result
);
774 TCGv_i32 t0_32
, t1_32
, tmp
;
775 t0_32
= tcg_temp_new_i32();
776 t1_32
= tcg_temp_new_i32();
777 tmp
= tcg_const_i32(0);
779 tcg_gen_extrl_i64_i32(t0_32
, t0
);
780 tcg_gen_extrl_i64_i32(t1_32
, t1
);
781 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
782 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
784 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
785 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
786 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
787 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
788 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
790 tcg_temp_free_i32(tmp
);
791 tcg_temp_free_i32(t1_32
);
792 tcg_temp_free_i32(t0_32
);
797 * Load/Store generators
801 * Store from GPR register to memory.
803 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
804 TCGv_i64 tcg_addr
, int size
, int memidx
,
806 unsigned int iss_srt
,
807 bool iss_sf
, bool iss_ar
)
810 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
815 syn
= syn_data_abort_with_iss(0,
821 0, 0, 0, 0, 0, false);
822 disas_set_insn_syndrome(s
, syn
);
826 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
827 TCGv_i64 tcg_addr
, int size
,
829 unsigned int iss_srt
,
830 bool iss_sf
, bool iss_ar
)
832 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
833 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
837 * Load from memory to GPR register
839 static void do_gpr_ld_memidx(DisasContext
*s
,
840 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
841 int size
, bool is_signed
,
842 bool extend
, int memidx
,
843 bool iss_valid
, unsigned int iss_srt
,
844 bool iss_sf
, bool iss_ar
)
846 TCGMemOp memop
= s
->be_data
+ size
;
854 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
856 if (extend
&& is_signed
) {
858 tcg_gen_ext32u_i64(dest
, dest
);
864 syn
= syn_data_abort_with_iss(0,
870 0, 0, 0, 0, 0, false);
871 disas_set_insn_syndrome(s
, syn
);
875 static void do_gpr_ld(DisasContext
*s
,
876 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
877 int size
, bool is_signed
, bool extend
,
878 bool iss_valid
, unsigned int iss_srt
,
879 bool iss_sf
, bool iss_ar
)
881 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
883 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
887 * Store from FP register to memory
889 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
891 /* This writes the bottom N bits of a 128 bit wide vector to memory */
892 TCGv_i64 tmp
= tcg_temp_new_i64();
893 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
895 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
898 bool be
= s
->be_data
== MO_BE
;
899 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
901 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
902 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
904 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
905 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
907 tcg_temp_free_i64(tcg_hiaddr
);
910 tcg_temp_free_i64(tmp
);
914 * Load from memory to FP register
916 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
918 /* This always zero-extends and writes to a full 128 bit wide vector */
919 TCGv_i64 tmplo
= tcg_temp_new_i64();
923 TCGMemOp memop
= s
->be_data
+ size
;
924 tmphi
= tcg_const_i64(0);
925 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
927 bool be
= s
->be_data
== MO_BE
;
930 tmphi
= tcg_temp_new_i64();
931 tcg_hiaddr
= tcg_temp_new_i64();
933 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
934 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
936 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
938 tcg_temp_free_i64(tcg_hiaddr
);
941 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
942 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
944 tcg_temp_free_i64(tmplo
);
945 tcg_temp_free_i64(tmphi
);
949 * Vector load/store helpers.
951 * The principal difference between this and a FP load is that we don't
952 * zero extend as we are filling a partial chunk of the vector register.
953 * These functions don't support 128 bit loads/stores, which would be
954 * normal load/store operations.
956 * The _i32 versions are useful when operating on 32 bit quantities
957 * (eg for floating point single or using Neon helper functions).
960 /* Get value of an element within a vector register */
961 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
962 int element
, TCGMemOp memop
)
964 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
967 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
979 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
982 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
986 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
989 g_assert_not_reached();
993 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
994 int element
, TCGMemOp memop
)
996 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
999 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1005 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1008 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1015 g_assert_not_reached();
1019 /* Set value of an element within a vector register */
1020 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1021 int element
, TCGMemOp memop
)
1023 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1026 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1032 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1035 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1038 g_assert_not_reached();
1042 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1043 int destidx
, int element
, TCGMemOp memop
)
1045 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1048 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1051 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1054 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1057 g_assert_not_reached();
1061 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1062 * vector ops all need to do this).
1064 static void clear_vec_high(DisasContext
*s
, int rd
)
1066 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1068 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1069 tcg_temp_free_i64(tcg_zero
);
1072 /* Store from vector register to memory */
1073 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1074 TCGv_i64 tcg_addr
, int size
)
1076 TCGMemOp memop
= s
->be_data
+ size
;
1077 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1079 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1080 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1082 tcg_temp_free_i64(tcg_tmp
);
1085 /* Load from memory to vector register */
1086 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1087 TCGv_i64 tcg_addr
, int size
)
1089 TCGMemOp memop
= s
->be_data
+ size
;
1090 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1092 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1093 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1095 tcg_temp_free_i64(tcg_tmp
);
1098 /* Check that FP/Neon access is enabled. If it is, return
1099 * true. If not, emit code to generate an appropriate exception,
1100 * and return false; the caller should not emit any code for
1101 * the instruction. Note that this check must happen after all
1102 * unallocated-encoding checks (otherwise the syndrome information
1103 * for the resulting exception will be incorrect).
1105 static inline bool fp_access_check(DisasContext
*s
)
1107 assert(!s
->fp_access_checked
);
1108 s
->fp_access_checked
= true;
1110 if (!s
->fp_excp_el
) {
1114 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1120 * This utility function is for doing register extension with an
1121 * optional shift. You will likely want to pass a temporary for the
1122 * destination register. See DecodeRegExtend() in the ARM ARM.
1124 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1125 int option
, unsigned int shift
)
1127 int extsize
= extract32(option
, 0, 2);
1128 bool is_signed
= extract32(option
, 2, 1);
1133 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1139 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1142 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1154 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1157 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1163 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1167 static inline void gen_check_sp_alignment(DisasContext
*s
)
1169 /* The AArch64 architecture mandates that (if enabled via PSTATE
1170 * or SCTLR bits) there is a check that SP is 16-aligned on every
1171 * SP-relative load or store (with an exception generated if it is not).
1172 * In line with general QEMU practice regarding misaligned accesses,
1173 * we omit these checks for the sake of guest program performance.
1174 * This function is provided as a hook so we can more easily add these
1175 * checks in future (possibly as a "favour catching guest program bugs
1176 * over speed" user selectable option).
1181 * This provides a simple table based table lookup decoder. It is
1182 * intended to be used when the relevant bits for decode are too
1183 * awkwardly placed and switch/if based logic would be confusing and
1184 * deeply nested. Since it's a linear search through the table, tables
1185 * should be kept small.
1187 * It returns the first handler where insn & mask == pattern, or
1188 * NULL if there is no match.
1189 * The table is terminated by an empty mask (i.e. 0)
1191 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1194 const AArch64DecodeTable
*tptr
= table
;
1196 while (tptr
->mask
) {
1197 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1198 return tptr
->disas_fn
;
1206 * the instruction disassembly implemented here matches
1207 * the instruction encoding classifications in chapter 3 (C3)
1208 * of the ARM Architecture Reference Manual (DDI0487A_a)
1211 /* C3.2.7 Unconditional branch (immediate)
1213 * +----+-----------+-------------------------------------+
1214 * | op | 0 0 1 0 1 | imm26 |
1215 * +----+-----------+-------------------------------------+
1217 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1219 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1221 if (insn
& (1U << 31)) {
1222 /* C5.6.26 BL Branch with link */
1223 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1226 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1227 gen_goto_tb(s
, 0, addr
);
1230 /* C3.2.1 Compare & branch (immediate)
1231 * 31 30 25 24 23 5 4 0
1232 * +----+-------------+----+---------------------+--------+
1233 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1234 * +----+-------------+----+---------------------+--------+
1236 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1238 unsigned int sf
, op
, rt
;
1240 TCGLabel
*label_match
;
1243 sf
= extract32(insn
, 31, 1);
1244 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1245 rt
= extract32(insn
, 0, 5);
1246 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1248 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1249 label_match
= gen_new_label();
1251 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1252 tcg_cmp
, 0, label_match
);
1254 gen_goto_tb(s
, 0, s
->pc
);
1255 gen_set_label(label_match
);
1256 gen_goto_tb(s
, 1, addr
);
1259 /* C3.2.5 Test & branch (immediate)
1260 * 31 30 25 24 23 19 18 5 4 0
1261 * +----+-------------+----+-------+-------------+------+
1262 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1263 * +----+-------------+----+-------+-------------+------+
1265 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1267 unsigned int bit_pos
, op
, rt
;
1269 TCGLabel
*label_match
;
1272 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1273 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1274 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1275 rt
= extract32(insn
, 0, 5);
1277 tcg_cmp
= tcg_temp_new_i64();
1278 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1279 label_match
= gen_new_label();
1280 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1281 tcg_cmp
, 0, label_match
);
1282 tcg_temp_free_i64(tcg_cmp
);
1283 gen_goto_tb(s
, 0, s
->pc
);
1284 gen_set_label(label_match
);
1285 gen_goto_tb(s
, 1, addr
);
1288 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1289 * 31 25 24 23 5 4 3 0
1290 * +---------------+----+---------------------+----+------+
1291 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1292 * +---------------+----+---------------------+----+------+
1294 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1299 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1300 unallocated_encoding(s
);
1303 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1304 cond
= extract32(insn
, 0, 4);
1307 /* genuinely conditional branches */
1308 TCGLabel
*label_match
= gen_new_label();
1309 arm_gen_test_cc(cond
, label_match
);
1310 gen_goto_tb(s
, 0, s
->pc
);
1311 gen_set_label(label_match
);
1312 gen_goto_tb(s
, 1, addr
);
1314 /* 0xe and 0xf are both "always" conditions */
1315 gen_goto_tb(s
, 0, addr
);
1320 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1321 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1323 unsigned int selector
= crm
<< 3 | op2
;
1326 unallocated_encoding(s
);
1334 s
->is_jmp
= DISAS_WFI
;
1337 if (!parallel_cpus
) {
1338 s
->is_jmp
= DISAS_YIELD
;
1342 if (!parallel_cpus
) {
1343 s
->is_jmp
= DISAS_WFE
;
1348 /* we treat all as NOP at least for now */
1351 /* default specified as NOP equivalent */
1356 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1358 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1361 /* CLREX, DSB, DMB, ISB */
1362 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1363 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1368 unallocated_encoding(s
);
1379 case 1: /* MBReqTypes_Reads */
1380 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1382 case 2: /* MBReqTypes_Writes */
1383 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1385 default: /* MBReqTypes_All */
1386 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1392 /* We need to break the TB after this insn to execute
1393 * a self-modified code correctly and also to take
1394 * any pending interrupts immediately.
1396 gen_goto_tb(s
, 0, s
->pc
);
1399 unallocated_encoding(s
);
1404 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1405 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1406 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1408 int op
= op1
<< 3 | op2
;
1410 case 0x05: /* SPSel */
1411 if (s
->current_el
== 0) {
1412 unallocated_encoding(s
);
1416 case 0x1e: /* DAIFSet */
1417 case 0x1f: /* DAIFClear */
1419 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1420 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1421 gen_a64_set_pc_im(s
->pc
- 4);
1422 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1423 tcg_temp_free_i32(tcg_imm
);
1424 tcg_temp_free_i32(tcg_op
);
1425 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1426 gen_a64_set_pc_im(s
->pc
);
1427 s
->is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1431 unallocated_encoding(s
);
1436 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1438 TCGv_i32 tmp
= tcg_temp_new_i32();
1439 TCGv_i32 nzcv
= tcg_temp_new_i32();
1441 /* build bit 31, N */
1442 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1443 /* build bit 30, Z */
1444 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1445 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1446 /* build bit 29, C */
1447 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1448 /* build bit 28, V */
1449 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1450 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1451 /* generate result */
1452 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1454 tcg_temp_free_i32(nzcv
);
1455 tcg_temp_free_i32(tmp
);
1458 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1461 TCGv_i32 nzcv
= tcg_temp_new_i32();
1463 /* take NZCV from R[t] */
1464 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1467 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1469 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1470 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1472 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1473 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1475 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1476 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1477 tcg_temp_free_i32(nzcv
);
1480 /* C5.6.129 MRS - move from system register
1481 * C5.6.131 MSR (register) - move to system register
1484 * These are all essentially the same insn in 'read' and 'write'
1485 * versions, with varying op0 fields.
1487 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1488 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1489 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1491 const ARMCPRegInfo
*ri
;
1494 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1495 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1496 crn
, crm
, op0
, op1
, op2
));
1499 /* Unknown register; this might be a guest error or a QEMU
1500 * unimplemented feature.
1502 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1503 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1504 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1505 unallocated_encoding(s
);
1509 /* Check access permissions */
1510 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1511 unallocated_encoding(s
);
1516 /* Emit code to perform further access permissions checks at
1517 * runtime; this may result in an exception.
1520 TCGv_i32 tcg_syn
, tcg_isread
;
1523 gen_a64_set_pc_im(s
->pc
- 4);
1524 tmpptr
= tcg_const_ptr(ri
);
1525 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1526 tcg_syn
= tcg_const_i32(syndrome
);
1527 tcg_isread
= tcg_const_i32(isread
);
1528 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1529 tcg_temp_free_ptr(tmpptr
);
1530 tcg_temp_free_i32(tcg_syn
);
1531 tcg_temp_free_i32(tcg_isread
);
1534 /* Handle special cases first */
1535 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1539 tcg_rt
= cpu_reg(s
, rt
);
1541 gen_get_nzcv(tcg_rt
);
1543 gen_set_nzcv(tcg_rt
);
1546 case ARM_CP_CURRENTEL
:
1547 /* Reads as current EL value from pstate, which is
1548 * guaranteed to be constant by the tb flags.
1550 tcg_rt
= cpu_reg(s
, rt
);
1551 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1554 /* Writes clear the aligned block of memory which rt points into. */
1555 tcg_rt
= cpu_reg(s
, rt
);
1556 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1562 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1566 tcg_rt
= cpu_reg(s
, rt
);
1569 if (ri
->type
& ARM_CP_CONST
) {
1570 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1571 } else if (ri
->readfn
) {
1573 tmpptr
= tcg_const_ptr(ri
);
1574 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1575 tcg_temp_free_ptr(tmpptr
);
1577 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1580 if (ri
->type
& ARM_CP_CONST
) {
1581 /* If not forbidden by access permissions, treat as WI */
1583 } else if (ri
->writefn
) {
1585 tmpptr
= tcg_const_ptr(ri
);
1586 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1587 tcg_temp_free_ptr(tmpptr
);
1589 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1593 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1594 /* I/O operations must end the TB here (whether read or write) */
1596 s
->is_jmp
= DISAS_UPDATE
;
1597 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1598 /* We default to ending the TB on a coprocessor register write,
1599 * but allow this to be suppressed by the register definition
1600 * (usually only necessary to work around guest bugs).
1602 s
->is_jmp
= DISAS_UPDATE
;
1607 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1608 * +---------------------+---+-----+-----+-------+-------+-----+------+
1609 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1610 * +---------------------+---+-----+-----+-------+-------+-----+------+
1612 static void disas_system(DisasContext
*s
, uint32_t insn
)
1614 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1615 l
= extract32(insn
, 21, 1);
1616 op0
= extract32(insn
, 19, 2);
1617 op1
= extract32(insn
, 16, 3);
1618 crn
= extract32(insn
, 12, 4);
1619 crm
= extract32(insn
, 8, 4);
1620 op2
= extract32(insn
, 5, 3);
1621 rt
= extract32(insn
, 0, 5);
1624 if (l
|| rt
!= 31) {
1625 unallocated_encoding(s
);
1629 case 2: /* C5.6.68 HINT */
1630 handle_hint(s
, insn
, op1
, op2
, crm
);
1632 case 3: /* CLREX, DSB, DMB, ISB */
1633 handle_sync(s
, insn
, op1
, op2
, crm
);
1635 case 4: /* C5.6.130 MSR (immediate) */
1636 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1639 unallocated_encoding(s
);
1644 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1647 /* C3.2.3 Exception generation
1649 * 31 24 23 21 20 5 4 2 1 0
1650 * +-----------------+-----+------------------------+-----+----+
1651 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1652 * +-----------------------+------------------------+----------+
1654 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1656 int opc
= extract32(insn
, 21, 3);
1657 int op2_ll
= extract32(insn
, 0, 5);
1658 int imm16
= extract32(insn
, 5, 16);
1663 /* For SVC, HVC and SMC we advance the single-step state
1664 * machine before taking the exception. This is architecturally
1665 * mandated, to ensure that single-stepping a system call
1666 * instruction works properly.
1671 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1672 default_exception_el(s
));
1675 if (s
->current_el
== 0) {
1676 unallocated_encoding(s
);
1679 /* The pre HVC helper handles cases when HVC gets trapped
1680 * as an undefined insn by runtime configuration.
1682 gen_a64_set_pc_im(s
->pc
- 4);
1683 gen_helper_pre_hvc(cpu_env
);
1685 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1688 if (s
->current_el
== 0) {
1689 unallocated_encoding(s
);
1692 gen_a64_set_pc_im(s
->pc
- 4);
1693 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1694 gen_helper_pre_smc(cpu_env
, tmp
);
1695 tcg_temp_free_i32(tmp
);
1697 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1700 unallocated_encoding(s
);
1706 unallocated_encoding(s
);
1710 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1711 default_exception_el(s
));
1715 unallocated_encoding(s
);
1718 /* HLT. This has two purposes.
1719 * Architecturally, it is an external halting debug instruction.
1720 * Since QEMU doesn't implement external debug, we treat this as
1721 * it is required for halting debug disabled: it will UNDEF.
1722 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1724 if (semihosting_enabled() && imm16
== 0xf000) {
1725 #ifndef CONFIG_USER_ONLY
1726 /* In system mode, don't allow userspace access to semihosting,
1727 * to provide some semblance of security (and for consistency
1728 * with our 32-bit semihosting).
1730 if (s
->current_el
== 0) {
1731 unsupported_encoding(s
, insn
);
1735 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1737 unsupported_encoding(s
, insn
);
1741 if (op2_ll
< 1 || op2_ll
> 3) {
1742 unallocated_encoding(s
);
1745 /* DCPS1, DCPS2, DCPS3 */
1746 unsupported_encoding(s
, insn
);
1749 unallocated_encoding(s
);
1754 /* C3.2.7 Unconditional branch (register)
1755 * 31 25 24 21 20 16 15 10 9 5 4 0
1756 * +---------------+-------+-------+-------+------+-------+
1757 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1758 * +---------------+-------+-------+-------+------+-------+
1760 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1762 unsigned int opc
, op2
, op3
, rn
, op4
;
1764 opc
= extract32(insn
, 21, 4);
1765 op2
= extract32(insn
, 16, 5);
1766 op3
= extract32(insn
, 10, 6);
1767 rn
= extract32(insn
, 5, 5);
1768 op4
= extract32(insn
, 0, 5);
1770 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1771 unallocated_encoding(s
);
1779 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1780 /* BLR also needs to load return address */
1782 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1786 if (s
->current_el
== 0) {
1787 unallocated_encoding(s
);
1790 gen_helper_exception_return(cpu_env
);
1791 /* Must exit loop to check un-masked IRQs */
1792 s
->is_jmp
= DISAS_EXIT
;
1796 unallocated_encoding(s
);
1798 unsupported_encoding(s
, insn
);
1802 unallocated_encoding(s
);
1806 s
->is_jmp
= DISAS_JUMP
;
1809 /* C3.2 Branches, exception generating and system instructions */
1810 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1812 switch (extract32(insn
, 25, 7)) {
1813 case 0x0a: case 0x0b:
1814 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1815 disas_uncond_b_imm(s
, insn
);
1817 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1818 disas_comp_b_imm(s
, insn
);
1820 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1821 disas_test_b_imm(s
, insn
);
1823 case 0x2a: /* Conditional branch (immediate) */
1824 disas_cond_b_imm(s
, insn
);
1826 case 0x6a: /* Exception generation / System */
1827 if (insn
& (1 << 24)) {
1828 disas_system(s
, insn
);
1833 case 0x6b: /* Unconditional branch (register) */
1834 disas_uncond_b_reg(s
, insn
);
1837 unallocated_encoding(s
);
1843 * Load/Store exclusive instructions are implemented by remembering
1844 * the value/address loaded, and seeing if these are the same
1845 * when the store is performed. This is not actually the architecturally
1846 * mandated semantics, but it works for typical guest code sequences
1847 * and avoids having to monitor regular stores.
1849 * The store exclusive uses the atomic cmpxchg primitives to avoid
1850 * races in multi-threaded linux-user and when MTTCG softmmu is
1853 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1854 TCGv_i64 addr
, int size
, bool is_pair
)
1856 TCGv_i64 tmp
= tcg_temp_new_i64();
1857 TCGMemOp memop
= s
->be_data
+ size
;
1859 g_assert(size
<= 3);
1860 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1863 TCGv_i64 addr2
= tcg_temp_new_i64();
1864 TCGv_i64 hitmp
= tcg_temp_new_i64();
1866 g_assert(size
>= 2);
1867 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1868 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1869 tcg_temp_free_i64(addr2
);
1870 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1871 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1872 tcg_temp_free_i64(hitmp
);
1875 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1876 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1878 tcg_temp_free_i64(tmp
);
1879 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1882 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1883 TCGv_i64 inaddr
, int size
, int is_pair
)
1885 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1886 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1889 * [addr + datasize] = {Rt2};
1895 * env->exclusive_addr = -1;
1897 TCGLabel
*fail_label
= gen_new_label();
1898 TCGLabel
*done_label
= gen_new_label();
1899 TCGv_i64 addr
= tcg_temp_local_new_i64();
1902 /* Copy input into a local temp so it is not trashed when the
1903 * basic block ends at the branch insn.
1905 tcg_gen_mov_i64(addr
, inaddr
);
1906 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1908 tmp
= tcg_temp_new_i64();
1911 TCGv_i64 val
= tcg_temp_new_i64();
1912 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1913 tcg_gen_concat32_i64(val
, cpu_exclusive_val
, cpu_exclusive_high
);
1914 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, val
, tmp
,
1916 size
| MO_ALIGN
| s
->be_data
);
1917 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, val
);
1918 tcg_temp_free_i64(val
);
1919 } else if (s
->be_data
== MO_LE
) {
1920 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1923 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1927 TCGv_i64 val
= cpu_reg(s
, rt
);
1928 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, cpu_exclusive_val
, val
,
1930 size
| MO_ALIGN
| s
->be_data
);
1931 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1934 tcg_temp_free_i64(addr
);
1936 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1937 tcg_temp_free_i64(tmp
);
1938 tcg_gen_br(done_label
);
1940 gen_set_label(fail_label
);
1941 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1942 gen_set_label(done_label
);
1943 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1946 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1947 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1949 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1951 int opc0
= extract32(opc
, 0, 1);
1955 regsize
= opc0
? 32 : 64;
1957 regsize
= size
== 3 ? 64 : 32;
1959 return regsize
== 64;
1962 /* C3.3.6 Load/store exclusive
1964 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1965 * +-----+-------------+----+---+----+------+----+-------+------+------+
1966 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1967 * +-----+-------------+----+---+----+------+----+-------+------+------+
1969 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1970 * L: 0 -> store, 1 -> load
1971 * o2: 0 -> exclusive, 1 -> not
1972 * o1: 0 -> single register, 1 -> register pair
1973 * o0: 1 -> load-acquire/store-release, 0 -> not
1975 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1977 int rt
= extract32(insn
, 0, 5);
1978 int rn
= extract32(insn
, 5, 5);
1979 int rt2
= extract32(insn
, 10, 5);
1980 int is_lasr
= extract32(insn
, 15, 1);
1981 int rs
= extract32(insn
, 16, 5);
1982 int is_pair
= extract32(insn
, 21, 1);
1983 int is_store
= !extract32(insn
, 22, 1);
1984 int is_excl
= !extract32(insn
, 23, 1);
1985 int size
= extract32(insn
, 30, 2);
1988 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1989 (!is_excl
&& is_pair
) ||
1990 (is_pair
&& size
< 2)) {
1991 unallocated_encoding(s
);
1996 gen_check_sp_alignment(s
);
1998 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2000 /* Note that since TCG is single threaded load-acquire/store-release
2001 * semantics require no extra if (is_lasr) { ... } handling.
2007 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2009 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2013 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2015 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2018 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2019 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2021 /* Generate ISS for non-exclusive accesses including LASR. */
2024 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2026 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2027 true, rt
, iss_sf
, is_lasr
);
2029 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2030 true, rt
, iss_sf
, is_lasr
);
2032 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2039 * C3.3.5 Load register (literal)
2041 * 31 30 29 27 26 25 24 23 5 4 0
2042 * +-----+-------+---+-----+-------------------+-------+
2043 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2044 * +-----+-------+---+-----+-------------------+-------+
2046 * V: 1 -> vector (simd/fp)
2047 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2048 * 10-> 32 bit signed, 11 -> prefetch
2049 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2051 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2053 int rt
= extract32(insn
, 0, 5);
2054 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2055 bool is_vector
= extract32(insn
, 26, 1);
2056 int opc
= extract32(insn
, 30, 2);
2057 bool is_signed
= false;
2059 TCGv_i64 tcg_rt
, tcg_addr
;
2063 unallocated_encoding(s
);
2067 if (!fp_access_check(s
)) {
2072 /* PRFM (literal) : prefetch */
2075 size
= 2 + extract32(opc
, 0, 1);
2076 is_signed
= extract32(opc
, 1, 1);
2079 tcg_rt
= cpu_reg(s
, rt
);
2081 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2083 do_fp_ld(s
, rt
, tcg_addr
, size
);
2085 /* Only unsigned 32bit loads target 32bit registers. */
2086 bool iss_sf
= opc
!= 0;
2088 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2089 true, rt
, iss_sf
, false);
2091 tcg_temp_free_i64(tcg_addr
);
2095 * C5.6.80 LDNP (Load Pair - non-temporal hint)
2096 * C5.6.81 LDP (Load Pair - non vector)
2097 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
2098 * C5.6.176 STNP (Store Pair - non-temporal hint)
2099 * C5.6.177 STP (Store Pair - non vector)
2100 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
2101 * C6.3.165 LDP (Load Pair of SIMD&FP)
2102 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
2103 * C6.3.284 STP (Store Pair of SIMD&FP)
2105 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2106 * +-----+-------+---+---+-------+---+-----------------------------+
2107 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2108 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2110 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2112 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2113 * V: 0 -> GPR, 1 -> Vector
2114 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2115 * 10 -> signed offset, 11 -> pre-index
2116 * L: 0 -> Store 1 -> Load
2118 * Rt, Rt2 = GPR or SIMD registers to be stored
2119 * Rn = general purpose register containing address
2120 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2122 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2124 int rt
= extract32(insn
, 0, 5);
2125 int rn
= extract32(insn
, 5, 5);
2126 int rt2
= extract32(insn
, 10, 5);
2127 uint64_t offset
= sextract64(insn
, 15, 7);
2128 int index
= extract32(insn
, 23, 2);
2129 bool is_vector
= extract32(insn
, 26, 1);
2130 bool is_load
= extract32(insn
, 22, 1);
2131 int opc
= extract32(insn
, 30, 2);
2133 bool is_signed
= false;
2134 bool postindex
= false;
2137 TCGv_i64 tcg_addr
; /* calculated address */
2141 unallocated_encoding(s
);
2148 size
= 2 + extract32(opc
, 1, 1);
2149 is_signed
= extract32(opc
, 0, 1);
2150 if (!is_load
&& is_signed
) {
2151 unallocated_encoding(s
);
2157 case 1: /* post-index */
2162 /* signed offset with "non-temporal" hint. Since we don't emulate
2163 * caches we don't care about hints to the cache system about
2164 * data access patterns, and handle this identically to plain
2168 /* There is no non-temporal-hint version of LDPSW */
2169 unallocated_encoding(s
);
2174 case 2: /* signed offset, rn not updated */
2177 case 3: /* pre-index */
2183 if (is_vector
&& !fp_access_check(s
)) {
2190 gen_check_sp_alignment(s
);
2193 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2196 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2201 do_fp_ld(s
, rt
, tcg_addr
, size
);
2203 do_fp_st(s
, rt
, tcg_addr
, size
);
2206 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2208 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2209 false, 0, false, false);
2211 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2212 false, 0, false, false);
2215 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2218 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2220 do_fp_st(s
, rt2
, tcg_addr
, size
);
2223 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2225 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2226 false, 0, false, false);
2228 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2229 false, 0, false, false);
2235 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2237 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2239 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2244 * C3.3.8 Load/store (immediate post-indexed)
2245 * C3.3.9 Load/store (immediate pre-indexed)
2246 * C3.3.12 Load/store (unscaled immediate)
2248 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2249 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2250 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2251 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2253 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2255 * V = 0 -> non-vector
2256 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2257 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2259 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2265 int rn
= extract32(insn
, 5, 5);
2266 int imm9
= sextract32(insn
, 12, 9);
2267 int idx
= extract32(insn
, 10, 2);
2268 bool is_signed
= false;
2269 bool is_store
= false;
2270 bool is_extended
= false;
2271 bool is_unpriv
= (idx
== 2);
2272 bool iss_valid
= !is_vector
;
2279 size
|= (opc
& 2) << 1;
2280 if (size
> 4 || is_unpriv
) {
2281 unallocated_encoding(s
);
2284 is_store
= ((opc
& 1) == 0);
2285 if (!fp_access_check(s
)) {
2289 if (size
== 3 && opc
== 2) {
2290 /* PRFM - prefetch */
2292 unallocated_encoding(s
);
2297 if (opc
== 3 && size
> 1) {
2298 unallocated_encoding(s
);
2301 is_store
= (opc
== 0);
2302 is_signed
= extract32(opc
, 1, 1);
2303 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2323 gen_check_sp_alignment(s
);
2325 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2328 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2333 do_fp_st(s
, rt
, tcg_addr
, size
);
2335 do_fp_ld(s
, rt
, tcg_addr
, size
);
2338 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2339 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2340 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2343 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2344 iss_valid
, rt
, iss_sf
, false);
2346 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2347 is_signed
, is_extended
, memidx
,
2348 iss_valid
, rt
, iss_sf
, false);
2353 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2355 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2357 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2362 * C3.3.10 Load/store (register offset)
2364 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2365 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2366 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2367 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2370 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2371 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2373 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2374 * opc<0>: 0 -> store, 1 -> load
2375 * V: 1 -> vector/simd
2376 * opt: extend encoding (see DecodeRegExtend)
2377 * S: if S=1 then scale (essentially index by sizeof(size))
2378 * Rt: register to transfer into/out of
2379 * Rn: address register or SP for base
2380 * Rm: offset register or ZR for offset
2382 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2388 int rn
= extract32(insn
, 5, 5);
2389 int shift
= extract32(insn
, 12, 1);
2390 int rm
= extract32(insn
, 16, 5);
2391 int opt
= extract32(insn
, 13, 3);
2392 bool is_signed
= false;
2393 bool is_store
= false;
2394 bool is_extended
= false;
2399 if (extract32(opt
, 1, 1) == 0) {
2400 unallocated_encoding(s
);
2405 size
|= (opc
& 2) << 1;
2407 unallocated_encoding(s
);
2410 is_store
= !extract32(opc
, 0, 1);
2411 if (!fp_access_check(s
)) {
2415 if (size
== 3 && opc
== 2) {
2416 /* PRFM - prefetch */
2419 if (opc
== 3 && size
> 1) {
2420 unallocated_encoding(s
);
2423 is_store
= (opc
== 0);
2424 is_signed
= extract32(opc
, 1, 1);
2425 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2429 gen_check_sp_alignment(s
);
2431 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2433 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2434 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2436 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2440 do_fp_st(s
, rt
, tcg_addr
, size
);
2442 do_fp_ld(s
, rt
, tcg_addr
, size
);
2445 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2446 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2448 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2449 true, rt
, iss_sf
, false);
2451 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2452 is_signed
, is_extended
,
2453 true, rt
, iss_sf
, false);
2459 * C3.3.13 Load/store (unsigned immediate)
2461 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2462 * +----+-------+---+-----+-----+------------+-------+------+
2463 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2464 * +----+-------+---+-----+-----+------------+-------+------+
2467 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2468 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2470 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2471 * opc<0>: 0 -> store, 1 -> load
2472 * Rn: base address register (inc SP)
2473 * Rt: target register
2475 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2481 int rn
= extract32(insn
, 5, 5);
2482 unsigned int imm12
= extract32(insn
, 10, 12);
2483 unsigned int offset
;
2488 bool is_signed
= false;
2489 bool is_extended
= false;
2492 size
|= (opc
& 2) << 1;
2494 unallocated_encoding(s
);
2497 is_store
= !extract32(opc
, 0, 1);
2498 if (!fp_access_check(s
)) {
2502 if (size
== 3 && opc
== 2) {
2503 /* PRFM - prefetch */
2506 if (opc
== 3 && size
> 1) {
2507 unallocated_encoding(s
);
2510 is_store
= (opc
== 0);
2511 is_signed
= extract32(opc
, 1, 1);
2512 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2516 gen_check_sp_alignment(s
);
2518 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2519 offset
= imm12
<< size
;
2520 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2524 do_fp_st(s
, rt
, tcg_addr
, size
);
2526 do_fp_ld(s
, rt
, tcg_addr
, size
);
2529 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2530 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2532 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2533 true, rt
, iss_sf
, false);
2535 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2536 true, rt
, iss_sf
, false);
2541 /* Load/store register (all forms) */
2542 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2544 int rt
= extract32(insn
, 0, 5);
2545 int opc
= extract32(insn
, 22, 2);
2546 bool is_vector
= extract32(insn
, 26, 1);
2547 int size
= extract32(insn
, 30, 2);
2549 switch (extract32(insn
, 24, 2)) {
2551 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2552 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2554 /* Load/store register (unscaled immediate)
2555 * Load/store immediate pre/post-indexed
2556 * Load/store register unprivileged
2558 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2562 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2565 unallocated_encoding(s
);
2570 /* C3.3.1 AdvSIMD load/store multiple structures
2572 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2573 * +---+---+---------------+---+-------------+--------+------+------+------+
2574 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2575 * +---+---+---------------+---+-------------+--------+------+------+------+
2577 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2579 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2580 * +---+---+---------------+---+---+---------+--------+------+------+------+
2581 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2582 * +---+---+---------------+---+---+---------+--------+------+------+------+
2584 * Rt: first (or only) SIMD&FP register to be transferred
2585 * Rn: base address or SP
2586 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2588 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2590 int rt
= extract32(insn
, 0, 5);
2591 int rn
= extract32(insn
, 5, 5);
2592 int size
= extract32(insn
, 10, 2);
2593 int opcode
= extract32(insn
, 12, 4);
2594 bool is_store
= !extract32(insn
, 22, 1);
2595 bool is_postidx
= extract32(insn
, 23, 1);
2596 bool is_q
= extract32(insn
, 30, 1);
2597 TCGv_i64 tcg_addr
, tcg_rn
;
2599 int ebytes
= 1 << size
;
2600 int elements
= (is_q
? 128 : 64) / (8 << size
);
2601 int rpt
; /* num iterations */
2602 int selem
; /* structure elements */
2605 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2606 unallocated_encoding(s
);
2610 /* From the shared decode logic */
2641 unallocated_encoding(s
);
2645 if (size
== 3 && !is_q
&& selem
!= 1) {
2647 unallocated_encoding(s
);
2651 if (!fp_access_check(s
)) {
2656 gen_check_sp_alignment(s
);
2659 tcg_rn
= cpu_reg_sp(s
, rn
);
2660 tcg_addr
= tcg_temp_new_i64();
2661 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2663 for (r
= 0; r
< rpt
; r
++) {
2665 for (e
= 0; e
< elements
; e
++) {
2666 int tt
= (rt
+ r
) % 32;
2668 for (xs
= 0; xs
< selem
; xs
++) {
2670 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2672 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2674 /* For non-quad operations, setting a slice of the low
2675 * 64 bits of the register clears the high 64 bits (in
2676 * the ARM ARM pseudocode this is implicit in the fact
2677 * that 'rval' is a 64 bit wide variable). We optimize
2678 * by noticing that we only need to do this the first
2679 * time we touch a register.
2681 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2682 clear_vec_high(s
, tt
);
2685 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2692 int rm
= extract32(insn
, 16, 5);
2694 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2696 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2699 tcg_temp_free_i64(tcg_addr
);
2702 /* C3.3.3 AdvSIMD load/store single structure
2704 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2705 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2706 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2707 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2709 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2711 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2712 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2713 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2714 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2716 * Rt: first (or only) SIMD&FP register to be transferred
2717 * Rn: base address or SP
2718 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2719 * index = encoded in Q:S:size dependent on size
2721 * lane_size = encoded in R, opc
2722 * transfer width = encoded in opc, S, size
2724 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2726 int rt
= extract32(insn
, 0, 5);
2727 int rn
= extract32(insn
, 5, 5);
2728 int size
= extract32(insn
, 10, 2);
2729 int S
= extract32(insn
, 12, 1);
2730 int opc
= extract32(insn
, 13, 3);
2731 int R
= extract32(insn
, 21, 1);
2732 int is_load
= extract32(insn
, 22, 1);
2733 int is_postidx
= extract32(insn
, 23, 1);
2734 int is_q
= extract32(insn
, 30, 1);
2736 int scale
= extract32(opc
, 1, 2);
2737 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2738 bool replicate
= false;
2739 int index
= is_q
<< 3 | S
<< 2 | size
;
2741 TCGv_i64 tcg_addr
, tcg_rn
;
2745 if (!is_load
|| S
) {
2746 unallocated_encoding(s
);
2755 if (extract32(size
, 0, 1)) {
2756 unallocated_encoding(s
);
2762 if (extract32(size
, 1, 1)) {
2763 unallocated_encoding(s
);
2766 if (!extract32(size
, 0, 1)) {
2770 unallocated_encoding(s
);
2778 g_assert_not_reached();
2781 if (!fp_access_check(s
)) {
2785 ebytes
= 1 << scale
;
2788 gen_check_sp_alignment(s
);
2791 tcg_rn
= cpu_reg_sp(s
, rn
);
2792 tcg_addr
= tcg_temp_new_i64();
2793 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2795 for (xs
= 0; xs
< selem
; xs
++) {
2797 /* Load and replicate to all elements */
2799 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2801 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2802 get_mem_index(s
), s
->be_data
+ scale
);
2805 mulconst
= 0x0101010101010101ULL
;
2808 mulconst
= 0x0001000100010001ULL
;
2811 mulconst
= 0x0000000100000001ULL
;
2817 g_assert_not_reached();
2820 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2822 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2824 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2826 clear_vec_high(s
, rt
);
2828 tcg_temp_free_i64(tcg_tmp
);
2830 /* Load/store one element per register */
2832 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2834 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2837 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2842 int rm
= extract32(insn
, 16, 5);
2844 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2846 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2849 tcg_temp_free_i64(tcg_addr
);
2852 /* C3.3 Loads and stores */
2853 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2855 switch (extract32(insn
, 24, 6)) {
2856 case 0x08: /* Load/store exclusive */
2857 disas_ldst_excl(s
, insn
);
2859 case 0x18: case 0x1c: /* Load register (literal) */
2860 disas_ld_lit(s
, insn
);
2862 case 0x28: case 0x29:
2863 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2864 disas_ldst_pair(s
, insn
);
2866 case 0x38: case 0x39:
2867 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2868 disas_ldst_reg(s
, insn
);
2870 case 0x0c: /* AdvSIMD load/store multiple structures */
2871 disas_ldst_multiple_struct(s
, insn
);
2873 case 0x0d: /* AdvSIMD load/store single structure */
2874 disas_ldst_single_struct(s
, insn
);
2877 unallocated_encoding(s
);
2882 /* C3.4.6 PC-rel. addressing
2883 * 31 30 29 28 24 23 5 4 0
2884 * +----+-------+-----------+-------------------+------+
2885 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2886 * +----+-------+-----------+-------------------+------+
2888 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2890 unsigned int page
, rd
;
2894 page
= extract32(insn
, 31, 1);
2895 /* SignExtend(immhi:immlo) -> offset */
2896 offset
= sextract64(insn
, 5, 19);
2897 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2898 rd
= extract32(insn
, 0, 5);
2902 /* ADRP (page based) */
2907 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2911 * C3.4.1 Add/subtract (immediate)
2913 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2914 * +--+--+--+-----------+-----+-------------+-----+-----+
2915 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2916 * +--+--+--+-----------+-----+-------------+-----+-----+
2918 * sf: 0 -> 32bit, 1 -> 64bit
2919 * op: 0 -> add , 1 -> sub
2921 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2923 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2925 int rd
= extract32(insn
, 0, 5);
2926 int rn
= extract32(insn
, 5, 5);
2927 uint64_t imm
= extract32(insn
, 10, 12);
2928 int shift
= extract32(insn
, 22, 2);
2929 bool setflags
= extract32(insn
, 29, 1);
2930 bool sub_op
= extract32(insn
, 30, 1);
2931 bool is_64bit
= extract32(insn
, 31, 1);
2933 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2934 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2935 TCGv_i64 tcg_result
;
2944 unallocated_encoding(s
);
2948 tcg_result
= tcg_temp_new_i64();
2951 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2953 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2956 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2958 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2960 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2962 tcg_temp_free_i64(tcg_imm
);
2966 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2968 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2971 tcg_temp_free_i64(tcg_result
);
2974 /* The input should be a value in the bottom e bits (with higher
2975 * bits zero); returns that value replicated into every element
2976 * of size e in a 64 bit integer.
2978 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2988 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2989 static inline uint64_t bitmask64(unsigned int length
)
2991 assert(length
> 0 && length
<= 64);
2992 return ~0ULL >> (64 - length
);
2995 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2996 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2997 * value (ie should cause a guest UNDEF exception), and true if they are
2998 * valid, in which case the decoded bit pattern is written to result.
3000 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3001 unsigned int imms
, unsigned int immr
)
3004 unsigned e
, levels
, s
, r
;
3007 assert(immn
< 2 && imms
< 64 && immr
< 64);
3009 /* The bit patterns we create here are 64 bit patterns which
3010 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3011 * 64 bits each. Each element contains the same value: a run
3012 * of between 1 and e-1 non-zero bits, rotated within the
3013 * element by between 0 and e-1 bits.
3015 * The element size and run length are encoded into immn (1 bit)
3016 * and imms (6 bits) as follows:
3017 * 64 bit elements: immn = 1, imms = <length of run - 1>
3018 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3019 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3020 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3021 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3022 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3023 * Notice that immn = 0, imms = 11111x is the only combination
3024 * not covered by one of the above options; this is reserved.
3025 * Further, <length of run - 1> all-ones is a reserved pattern.
3027 * In all cases the rotation is by immr % e (and immr is 6 bits).
3030 /* First determine the element size */
3031 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3033 /* This is the immn == 0, imms == 0x11111x case */
3043 /* <length of run - 1> mustn't be all-ones. */
3047 /* Create the value of one element: s+1 set bits rotated
3048 * by r within the element (which is e bits wide)...
3050 mask
= bitmask64(s
+ 1);
3052 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3053 mask
&= bitmask64(e
);
3055 /* ...then replicate the element over the whole 64 bit value */
3056 mask
= bitfield_replicate(mask
, e
);
3061 /* C3.4.4 Logical (immediate)
3062 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3063 * +----+-----+-------------+---+------+------+------+------+
3064 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3065 * +----+-----+-------------+---+------+------+------+------+
3067 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3069 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3070 TCGv_i64 tcg_rd
, tcg_rn
;
3072 bool is_and
= false;
3074 sf
= extract32(insn
, 31, 1);
3075 opc
= extract32(insn
, 29, 2);
3076 is_n
= extract32(insn
, 22, 1);
3077 immr
= extract32(insn
, 16, 6);
3078 imms
= extract32(insn
, 10, 6);
3079 rn
= extract32(insn
, 5, 5);
3080 rd
= extract32(insn
, 0, 5);
3083 unallocated_encoding(s
);
3087 if (opc
== 0x3) { /* ANDS */
3088 tcg_rd
= cpu_reg(s
, rd
);
3090 tcg_rd
= cpu_reg_sp(s
, rd
);
3092 tcg_rn
= cpu_reg(s
, rn
);
3094 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3095 /* some immediate field values are reserved */
3096 unallocated_encoding(s
);
3101 wmask
&= 0xffffffff;
3105 case 0x3: /* ANDS */
3107 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3111 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3114 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3117 assert(FALSE
); /* must handle all above */
3121 if (!sf
&& !is_and
) {
3122 /* zero extend final result; we know we can skip this for AND
3123 * since the immediate had the high 32 bits clear.
3125 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3128 if (opc
== 3) { /* ANDS */
3129 gen_logic_CC(sf
, tcg_rd
);
3134 * C3.4.5 Move wide (immediate)
3136 * 31 30 29 28 23 22 21 20 5 4 0
3137 * +--+-----+-------------+-----+----------------+------+
3138 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3139 * +--+-----+-------------+-----+----------------+------+
3141 * sf: 0 -> 32 bit, 1 -> 64 bit
3142 * opc: 00 -> N, 10 -> Z, 11 -> K
3143 * hw: shift/16 (0,16, and sf only 32, 48)
3145 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3147 int rd
= extract32(insn
, 0, 5);
3148 uint64_t imm
= extract32(insn
, 5, 16);
3149 int sf
= extract32(insn
, 31, 1);
3150 int opc
= extract32(insn
, 29, 2);
3151 int pos
= extract32(insn
, 21, 2) << 4;
3152 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3155 if (!sf
&& (pos
>= 32)) {
3156 unallocated_encoding(s
);
3170 tcg_gen_movi_i64(tcg_rd
, imm
);
3173 tcg_imm
= tcg_const_i64(imm
);
3174 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3175 tcg_temp_free_i64(tcg_imm
);
3177 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3181 unallocated_encoding(s
);
3187 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3188 * +----+-----+-------------+---+------+------+------+------+
3189 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3190 * +----+-----+-------------+---+------+------+------+------+
3192 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3194 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3195 TCGv_i64 tcg_rd
, tcg_tmp
;
3197 sf
= extract32(insn
, 31, 1);
3198 opc
= extract32(insn
, 29, 2);
3199 n
= extract32(insn
, 22, 1);
3200 ri
= extract32(insn
, 16, 6);
3201 si
= extract32(insn
, 10, 6);
3202 rn
= extract32(insn
, 5, 5);
3203 rd
= extract32(insn
, 0, 5);
3204 bitsize
= sf
? 64 : 32;
3206 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3207 unallocated_encoding(s
);
3211 tcg_rd
= cpu_reg(s
, rd
);
3213 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3214 to be smaller than bitsize, we'll never reference data outside the
3215 low 32-bits anyway. */
3216 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3218 /* Recognize simple(r) extractions. */
3220 /* Wd<s-r:0> = Wn<s:r> */
3221 len
= (si
- ri
) + 1;
3222 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3223 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3225 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3226 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3229 /* opc == 1, BXFIL fall through to deposit */
3230 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3233 /* Handle the ri > si case with a deposit
3234 * Wd<32+s-r,32-r> = Wn<s:0>
3237 pos
= (bitsize
- ri
) & (bitsize
- 1);
3240 if (opc
== 0 && len
< ri
) {
3241 /* SBFM: sign extend the destination field from len to fill
3242 the balance of the word. Let the deposit below insert all
3243 of those sign bits. */
3244 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3248 if (opc
== 1) { /* BFM, BXFIL */
3249 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3251 /* SBFM or UBFM: We start with zero, and we haven't modified
3252 any bits outside bitsize, therefore the zero-extension
3253 below is unneeded. */
3254 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3259 if (!sf
) { /* zero extend final result */
3260 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3265 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3266 * +----+------+-------------+---+----+------+--------+------+------+
3267 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3268 * +----+------+-------------+---+----+------+--------+------+------+
3270 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3272 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3274 sf
= extract32(insn
, 31, 1);
3275 n
= extract32(insn
, 22, 1);
3276 rm
= extract32(insn
, 16, 5);
3277 imm
= extract32(insn
, 10, 6);
3278 rn
= extract32(insn
, 5, 5);
3279 rd
= extract32(insn
, 0, 5);
3280 op21
= extract32(insn
, 29, 2);
3281 op0
= extract32(insn
, 21, 1);
3282 bitsize
= sf
? 64 : 32;
3284 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3285 unallocated_encoding(s
);
3287 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3289 tcg_rd
= cpu_reg(s
, rd
);
3291 if (unlikely(imm
== 0)) {
3292 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3293 * so an extract from bit 0 is a special case.
3296 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3298 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3300 } else if (rm
== rn
) { /* ROR */
3301 tcg_rm
= cpu_reg(s
, rm
);
3303 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3305 TCGv_i32 tmp
= tcg_temp_new_i32();
3306 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3307 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3308 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3309 tcg_temp_free_i32(tmp
);
3312 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3313 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3314 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3315 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3316 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3318 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3324 /* C3.4 Data processing - immediate */
3325 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3327 switch (extract32(insn
, 23, 6)) {
3328 case 0x20: case 0x21: /* PC-rel. addressing */
3329 disas_pc_rel_adr(s
, insn
);
3331 case 0x22: case 0x23: /* Add/subtract (immediate) */
3332 disas_add_sub_imm(s
, insn
);
3334 case 0x24: /* Logical (immediate) */
3335 disas_logic_imm(s
, insn
);
3337 case 0x25: /* Move wide (immediate) */
3338 disas_movw_imm(s
, insn
);
3340 case 0x26: /* Bitfield */
3341 disas_bitfield(s
, insn
);
3343 case 0x27: /* Extract */
3344 disas_extract(s
, insn
);
3347 unallocated_encoding(s
);
3352 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3353 * Note that it is the caller's responsibility to ensure that the
3354 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3355 * mandated semantics for out of range shifts.
3357 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3358 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3360 switch (shift_type
) {
3361 case A64_SHIFT_TYPE_LSL
:
3362 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3364 case A64_SHIFT_TYPE_LSR
:
3365 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3367 case A64_SHIFT_TYPE_ASR
:
3369 tcg_gen_ext32s_i64(dst
, src
);
3371 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3373 case A64_SHIFT_TYPE_ROR
:
3375 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3378 t0
= tcg_temp_new_i32();
3379 t1
= tcg_temp_new_i32();
3380 tcg_gen_extrl_i64_i32(t0
, src
);
3381 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3382 tcg_gen_rotr_i32(t0
, t0
, t1
);
3383 tcg_gen_extu_i32_i64(dst
, t0
);
3384 tcg_temp_free_i32(t0
);
3385 tcg_temp_free_i32(t1
);
3389 assert(FALSE
); /* all shift types should be handled */
3393 if (!sf
) { /* zero extend final result */
3394 tcg_gen_ext32u_i64(dst
, dst
);
3398 /* Shift a TCGv src by immediate, put result in dst.
3399 * The shift amount must be in range (this should always be true as the
3400 * relevant instructions will UNDEF on bad shift immediates).
3402 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3403 enum a64_shift_type shift_type
, unsigned int shift_i
)
3405 assert(shift_i
< (sf
? 64 : 32));
3408 tcg_gen_mov_i64(dst
, src
);
3410 TCGv_i64 shift_const
;
3412 shift_const
= tcg_const_i64(shift_i
);
3413 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3414 tcg_temp_free_i64(shift_const
);
3418 /* C3.5.10 Logical (shifted register)
3419 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3420 * +----+-----+-----------+-------+---+------+--------+------+------+
3421 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3422 * +----+-----+-----------+-------+---+------+--------+------+------+
3424 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3426 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3427 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3429 sf
= extract32(insn
, 31, 1);
3430 opc
= extract32(insn
, 29, 2);
3431 shift_type
= extract32(insn
, 22, 2);
3432 invert
= extract32(insn
, 21, 1);
3433 rm
= extract32(insn
, 16, 5);
3434 shift_amount
= extract32(insn
, 10, 6);
3435 rn
= extract32(insn
, 5, 5);
3436 rd
= extract32(insn
, 0, 5);
3438 if (!sf
&& (shift_amount
& (1 << 5))) {
3439 unallocated_encoding(s
);
3443 tcg_rd
= cpu_reg(s
, rd
);
3445 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3446 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3447 * register-register MOV and MVN, so it is worth special casing.
3449 tcg_rm
= cpu_reg(s
, rm
);
3451 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3453 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3457 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3459 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3465 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3468 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3471 tcg_rn
= cpu_reg(s
, rn
);
3473 switch (opc
| (invert
<< 2)) {
3476 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3479 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3482 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3486 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3489 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3492 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3500 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3504 gen_logic_CC(sf
, tcg_rd
);
3509 * C3.5.1 Add/subtract (extended register)
3511 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3512 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3513 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3514 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3516 * sf: 0 -> 32bit, 1 -> 64bit
3517 * op: 0 -> add , 1 -> sub
3520 * option: extension type (see DecodeRegExtend)
3521 * imm3: optional shift to Rm
3523 * Rd = Rn + LSL(extend(Rm), amount)
3525 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3527 int rd
= extract32(insn
, 0, 5);
3528 int rn
= extract32(insn
, 5, 5);
3529 int imm3
= extract32(insn
, 10, 3);
3530 int option
= extract32(insn
, 13, 3);
3531 int rm
= extract32(insn
, 16, 5);
3532 bool setflags
= extract32(insn
, 29, 1);
3533 bool sub_op
= extract32(insn
, 30, 1);
3534 bool sf
= extract32(insn
, 31, 1);
3536 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3538 TCGv_i64 tcg_result
;
3541 unallocated_encoding(s
);
3545 /* non-flag setting ops may use SP */
3547 tcg_rd
= cpu_reg_sp(s
, rd
);
3549 tcg_rd
= cpu_reg(s
, rd
);
3551 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3553 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3554 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3556 tcg_result
= tcg_temp_new_i64();
3560 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3562 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3566 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3568 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3573 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3575 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3578 tcg_temp_free_i64(tcg_result
);
3582 * C3.5.2 Add/subtract (shifted register)
3584 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3585 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3586 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3587 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3589 * sf: 0 -> 32bit, 1 -> 64bit
3590 * op: 0 -> add , 1 -> sub
3592 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3593 * imm6: Shift amount to apply to Rm before the add/sub
3595 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3597 int rd
= extract32(insn
, 0, 5);
3598 int rn
= extract32(insn
, 5, 5);
3599 int imm6
= extract32(insn
, 10, 6);
3600 int rm
= extract32(insn
, 16, 5);
3601 int shift_type
= extract32(insn
, 22, 2);
3602 bool setflags
= extract32(insn
, 29, 1);
3603 bool sub_op
= extract32(insn
, 30, 1);
3604 bool sf
= extract32(insn
, 31, 1);
3606 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3607 TCGv_i64 tcg_rn
, tcg_rm
;
3608 TCGv_i64 tcg_result
;
3610 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3611 unallocated_encoding(s
);
3615 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3616 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3618 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3620 tcg_result
= tcg_temp_new_i64();
3624 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3626 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3630 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3632 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3637 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3639 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3642 tcg_temp_free_i64(tcg_result
);
3645 /* C3.5.9 Data-processing (3 source)
3647 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3648 +--+------+-----------+------+------+----+------+------+------+
3649 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3650 +--+------+-----------+------+------+----+------+------+------+
3653 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3655 int rd
= extract32(insn
, 0, 5);
3656 int rn
= extract32(insn
, 5, 5);
3657 int ra
= extract32(insn
, 10, 5);
3658 int rm
= extract32(insn
, 16, 5);
3659 int op_id
= (extract32(insn
, 29, 3) << 4) |
3660 (extract32(insn
, 21, 3) << 1) |
3661 extract32(insn
, 15, 1);
3662 bool sf
= extract32(insn
, 31, 1);
3663 bool is_sub
= extract32(op_id
, 0, 1);
3664 bool is_high
= extract32(op_id
, 2, 1);
3665 bool is_signed
= false;
3670 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3672 case 0x42: /* SMADDL */
3673 case 0x43: /* SMSUBL */
3674 case 0x44: /* SMULH */
3677 case 0x0: /* MADD (32bit) */
3678 case 0x1: /* MSUB (32bit) */
3679 case 0x40: /* MADD (64bit) */
3680 case 0x41: /* MSUB (64bit) */
3681 case 0x4a: /* UMADDL */
3682 case 0x4b: /* UMSUBL */
3683 case 0x4c: /* UMULH */
3686 unallocated_encoding(s
);
3691 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3692 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3693 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3694 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3697 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3699 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3702 tcg_temp_free_i64(low_bits
);
3706 tcg_op1
= tcg_temp_new_i64();
3707 tcg_op2
= tcg_temp_new_i64();
3708 tcg_tmp
= tcg_temp_new_i64();
3711 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3712 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3715 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3716 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3718 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3719 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3723 if (ra
== 31 && !is_sub
) {
3724 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3725 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3727 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3729 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3731 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3736 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3739 tcg_temp_free_i64(tcg_op1
);
3740 tcg_temp_free_i64(tcg_op2
);
3741 tcg_temp_free_i64(tcg_tmp
);
3744 /* C3.5.3 - Add/subtract (with carry)
3745 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3746 * +--+--+--+------------------------+------+---------+------+-----+
3747 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3748 * +--+--+--+------------------------+------+---------+------+-----+
3752 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3754 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3755 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3757 if (extract32(insn
, 10, 6) != 0) {
3758 unallocated_encoding(s
);
3762 sf
= extract32(insn
, 31, 1);
3763 op
= extract32(insn
, 30, 1);
3764 setflags
= extract32(insn
, 29, 1);
3765 rm
= extract32(insn
, 16, 5);
3766 rn
= extract32(insn
, 5, 5);
3767 rd
= extract32(insn
, 0, 5);
3769 tcg_rd
= cpu_reg(s
, rd
);
3770 tcg_rn
= cpu_reg(s
, rn
);
3773 tcg_y
= new_tmp_a64(s
);
3774 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3776 tcg_y
= cpu_reg(s
, rm
);
3780 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3782 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3786 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3787 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3788 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3789 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3790 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3793 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3795 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3796 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3797 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3800 if (!extract32(insn
, 29, 1)) {
3801 unallocated_encoding(s
);
3804 if (insn
& (1 << 10 | 1 << 4)) {
3805 unallocated_encoding(s
);
3808 sf
= extract32(insn
, 31, 1);
3809 op
= extract32(insn
, 30, 1);
3810 is_imm
= extract32(insn
, 11, 1);
3811 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3812 cond
= extract32(insn
, 12, 4);
3813 rn
= extract32(insn
, 5, 5);
3814 nzcv
= extract32(insn
, 0, 4);
3816 /* Set T0 = !COND. */
3817 tcg_t0
= tcg_temp_new_i32();
3818 arm_test_cc(&c
, cond
);
3819 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3822 /* Load the arguments for the new comparison. */
3824 tcg_y
= new_tmp_a64(s
);
3825 tcg_gen_movi_i64(tcg_y
, y
);
3827 tcg_y
= cpu_reg(s
, y
);
3829 tcg_rn
= cpu_reg(s
, rn
);
3831 /* Set the flags for the new comparison. */
3832 tcg_tmp
= tcg_temp_new_i64();
3834 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3836 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3838 tcg_temp_free_i64(tcg_tmp
);
3840 /* If COND was false, force the flags to #nzcv. Compute two masks
3841 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3842 * For tcg hosts that support ANDC, we can make do with just T1.
3843 * In either case, allow the tcg optimizer to delete any unused mask.
3845 tcg_t1
= tcg_temp_new_i32();
3846 tcg_t2
= tcg_temp_new_i32();
3847 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3848 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3850 if (nzcv
& 8) { /* N */
3851 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3853 if (TCG_TARGET_HAS_andc_i32
) {
3854 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3856 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3859 if (nzcv
& 4) { /* Z */
3860 if (TCG_TARGET_HAS_andc_i32
) {
3861 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3863 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3866 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3868 if (nzcv
& 2) { /* C */
3869 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3871 if (TCG_TARGET_HAS_andc_i32
) {
3872 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3874 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3877 if (nzcv
& 1) { /* V */
3878 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3880 if (TCG_TARGET_HAS_andc_i32
) {
3881 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3883 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3886 tcg_temp_free_i32(tcg_t0
);
3887 tcg_temp_free_i32(tcg_t1
);
3888 tcg_temp_free_i32(tcg_t2
);
3891 /* C3.5.6 Conditional select
3892 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3893 * +----+----+---+-----------------+------+------+-----+------+------+
3894 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3895 * +----+----+---+-----------------+------+------+-----+------+------+
3897 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3899 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3900 TCGv_i64 tcg_rd
, zero
;
3903 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3904 /* S == 1 or op2<1> == 1 */
3905 unallocated_encoding(s
);
3908 sf
= extract32(insn
, 31, 1);
3909 else_inv
= extract32(insn
, 30, 1);
3910 rm
= extract32(insn
, 16, 5);
3911 cond
= extract32(insn
, 12, 4);
3912 else_inc
= extract32(insn
, 10, 1);
3913 rn
= extract32(insn
, 5, 5);
3914 rd
= extract32(insn
, 0, 5);
3916 tcg_rd
= cpu_reg(s
, rd
);
3918 a64_test_cc(&c
, cond
);
3919 zero
= tcg_const_i64(0);
3921 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3923 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3925 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3928 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3929 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3930 if (else_inv
&& else_inc
) {
3931 tcg_gen_neg_i64(t_false
, t_false
);
3932 } else if (else_inv
) {
3933 tcg_gen_not_i64(t_false
, t_false
);
3934 } else if (else_inc
) {
3935 tcg_gen_addi_i64(t_false
, t_false
, 1);
3937 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3940 tcg_temp_free_i64(zero
);
3944 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3948 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3949 unsigned int rn
, unsigned int rd
)
3951 TCGv_i64 tcg_rd
, tcg_rn
;
3952 tcg_rd
= cpu_reg(s
, rd
);
3953 tcg_rn
= cpu_reg(s
, rn
);
3956 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3958 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3959 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3960 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3961 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3962 tcg_temp_free_i32(tcg_tmp32
);
3966 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3967 unsigned int rn
, unsigned int rd
)
3969 TCGv_i64 tcg_rd
, tcg_rn
;
3970 tcg_rd
= cpu_reg(s
, rd
);
3971 tcg_rn
= cpu_reg(s
, rn
);
3974 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
3976 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3977 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3978 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
3979 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3980 tcg_temp_free_i32(tcg_tmp32
);
3984 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3985 unsigned int rn
, unsigned int rd
)
3987 TCGv_i64 tcg_rd
, tcg_rn
;
3988 tcg_rd
= cpu_reg(s
, rd
);
3989 tcg_rn
= cpu_reg(s
, rn
);
3992 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3994 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3995 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3996 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3997 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3998 tcg_temp_free_i32(tcg_tmp32
);
4002 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
4003 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4004 unsigned int rn
, unsigned int rd
)
4007 unallocated_encoding(s
);
4010 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4013 /* C5.6.149 REV with sf==0, opcode==2
4014 * C5.6.151 REV32 (sf==1, opcode==2)
4016 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4017 unsigned int rn
, unsigned int rd
)
4019 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4022 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4023 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4025 /* bswap32_i64 requires zero high word */
4026 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4027 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4028 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4029 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4030 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4032 tcg_temp_free_i64(tcg_tmp
);
4034 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4035 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4039 /* C5.6.150 REV16 (opcode==1) */
4040 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4041 unsigned int rn
, unsigned int rd
)
4043 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4044 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4045 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4046 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4048 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4049 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4050 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4051 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4052 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4054 tcg_temp_free_i64(mask
);
4055 tcg_temp_free_i64(tcg_tmp
);
4058 /* C3.5.7 Data-processing (1 source)
4059 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4060 * +----+---+---+-----------------+---------+--------+------+------+
4061 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4062 * +----+---+---+-----------------+---------+--------+------+------+
4064 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4066 unsigned int sf
, opcode
, rn
, rd
;
4068 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4069 unallocated_encoding(s
);
4073 sf
= extract32(insn
, 31, 1);
4074 opcode
= extract32(insn
, 10, 6);
4075 rn
= extract32(insn
, 5, 5);
4076 rd
= extract32(insn
, 0, 5);
4080 handle_rbit(s
, sf
, rn
, rd
);
4083 handle_rev16(s
, sf
, rn
, rd
);
4086 handle_rev32(s
, sf
, rn
, rd
);
4089 handle_rev64(s
, sf
, rn
, rd
);
4092 handle_clz(s
, sf
, rn
, rd
);
4095 handle_cls(s
, sf
, rn
, rd
);
4100 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4101 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4103 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4104 tcg_rd
= cpu_reg(s
, rd
);
4106 if (!sf
&& is_signed
) {
4107 tcg_n
= new_tmp_a64(s
);
4108 tcg_m
= new_tmp_a64(s
);
4109 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4110 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4112 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4113 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4117 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4119 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4122 if (!sf
) { /* zero extend final result */
4123 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4127 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
4128 static void handle_shift_reg(DisasContext
*s
,
4129 enum a64_shift_type shift_type
, unsigned int sf
,
4130 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4132 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4133 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4134 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4136 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4137 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4138 tcg_temp_free_i64(tcg_shift
);
4141 /* CRC32[BHWX], CRC32C[BHWX] */
4142 static void handle_crc32(DisasContext
*s
,
4143 unsigned int sf
, unsigned int sz
, bool crc32c
,
4144 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4146 TCGv_i64 tcg_acc
, tcg_val
;
4149 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4150 || (sf
== 1 && sz
!= 3)
4151 || (sf
== 0 && sz
== 3)) {
4152 unallocated_encoding(s
);
4157 tcg_val
= cpu_reg(s
, rm
);
4171 g_assert_not_reached();
4173 tcg_val
= new_tmp_a64(s
);
4174 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4177 tcg_acc
= cpu_reg(s
, rn
);
4178 tcg_bytes
= tcg_const_i32(1 << sz
);
4181 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4183 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4186 tcg_temp_free_i32(tcg_bytes
);
4189 /* C3.5.8 Data-processing (2 source)
4190 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4191 * +----+---+---+-----------------+------+--------+------+------+
4192 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4193 * +----+---+---+-----------------+------+--------+------+------+
4195 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4197 unsigned int sf
, rm
, opcode
, rn
, rd
;
4198 sf
= extract32(insn
, 31, 1);
4199 rm
= extract32(insn
, 16, 5);
4200 opcode
= extract32(insn
, 10, 6);
4201 rn
= extract32(insn
, 5, 5);
4202 rd
= extract32(insn
, 0, 5);
4204 if (extract32(insn
, 29, 1)) {
4205 unallocated_encoding(s
);
4211 handle_div(s
, false, sf
, rm
, rn
, rd
);
4214 handle_div(s
, true, sf
, rm
, rn
, rd
);
4217 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4220 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4223 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4226 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4235 case 23: /* CRC32 */
4237 int sz
= extract32(opcode
, 0, 2);
4238 bool crc32c
= extract32(opcode
, 2, 1);
4239 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4243 unallocated_encoding(s
);
4248 /* C3.5 Data processing - register */
4249 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4251 switch (extract32(insn
, 24, 5)) {
4252 case 0x0a: /* Logical (shifted register) */
4253 disas_logic_reg(s
, insn
);
4255 case 0x0b: /* Add/subtract */
4256 if (insn
& (1 << 21)) { /* (extended register) */
4257 disas_add_sub_ext_reg(s
, insn
);
4259 disas_add_sub_reg(s
, insn
);
4262 case 0x1b: /* Data-processing (3 source) */
4263 disas_data_proc_3src(s
, insn
);
4266 switch (extract32(insn
, 21, 3)) {
4267 case 0x0: /* Add/subtract (with carry) */
4268 disas_adc_sbc(s
, insn
);
4270 case 0x2: /* Conditional compare */
4271 disas_cc(s
, insn
); /* both imm and reg forms */
4273 case 0x4: /* Conditional select */
4274 disas_cond_select(s
, insn
);
4276 case 0x6: /* Data-processing */
4277 if (insn
& (1 << 30)) { /* (1 source) */
4278 disas_data_proc_1src(s
, insn
);
4279 } else { /* (2 source) */
4280 disas_data_proc_2src(s
, insn
);
4284 unallocated_encoding(s
);
4289 unallocated_encoding(s
);
4294 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4295 unsigned int rn
, unsigned int rm
,
4296 bool cmp_with_zero
, bool signal_all_nans
)
4298 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4299 TCGv_ptr fpst
= get_fpstatus_ptr();
4302 TCGv_i64 tcg_vn
, tcg_vm
;
4304 tcg_vn
= read_fp_dreg(s
, rn
);
4305 if (cmp_with_zero
) {
4306 tcg_vm
= tcg_const_i64(0);
4308 tcg_vm
= read_fp_dreg(s
, rm
);
4310 if (signal_all_nans
) {
4311 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4313 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4315 tcg_temp_free_i64(tcg_vn
);
4316 tcg_temp_free_i64(tcg_vm
);
4318 TCGv_i32 tcg_vn
, tcg_vm
;
4320 tcg_vn
= read_fp_sreg(s
, rn
);
4321 if (cmp_with_zero
) {
4322 tcg_vm
= tcg_const_i32(0);
4324 tcg_vm
= read_fp_sreg(s
, rm
);
4326 if (signal_all_nans
) {
4327 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4329 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4331 tcg_temp_free_i32(tcg_vn
);
4332 tcg_temp_free_i32(tcg_vm
);
4335 tcg_temp_free_ptr(fpst
);
4337 gen_set_nzcv(tcg_flags
);
4339 tcg_temp_free_i64(tcg_flags
);
4342 /* C3.6.22 Floating point compare
4343 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4344 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4345 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4346 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4348 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4350 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4352 mos
= extract32(insn
, 29, 3);
4353 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4354 rm
= extract32(insn
, 16, 5);
4355 op
= extract32(insn
, 14, 2);
4356 rn
= extract32(insn
, 5, 5);
4357 opc
= extract32(insn
, 3, 2);
4358 op2r
= extract32(insn
, 0, 3);
4360 if (mos
|| op
|| op2r
|| type
> 1) {
4361 unallocated_encoding(s
);
4365 if (!fp_access_check(s
)) {
4369 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4372 /* C3.6.23 Floating point conditional compare
4373 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4374 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4375 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4376 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4378 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4380 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4382 TCGLabel
*label_continue
= NULL
;
4384 mos
= extract32(insn
, 29, 3);
4385 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4386 rm
= extract32(insn
, 16, 5);
4387 cond
= extract32(insn
, 12, 4);
4388 rn
= extract32(insn
, 5, 5);
4389 op
= extract32(insn
, 4, 1);
4390 nzcv
= extract32(insn
, 0, 4);
4392 if (mos
|| type
> 1) {
4393 unallocated_encoding(s
);
4397 if (!fp_access_check(s
)) {
4401 if (cond
< 0x0e) { /* not always */
4402 TCGLabel
*label_match
= gen_new_label();
4403 label_continue
= gen_new_label();
4404 arm_gen_test_cc(cond
, label_match
);
4406 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4407 gen_set_nzcv(tcg_flags
);
4408 tcg_temp_free_i64(tcg_flags
);
4409 tcg_gen_br(label_continue
);
4410 gen_set_label(label_match
);
4413 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4416 gen_set_label(label_continue
);
4420 /* C3.6.24 Floating point conditional select
4421 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4422 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4423 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4424 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4426 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4428 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4429 TCGv_i64 t_true
, t_false
, t_zero
;
4432 mos
= extract32(insn
, 29, 3);
4433 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4434 rm
= extract32(insn
, 16, 5);
4435 cond
= extract32(insn
, 12, 4);
4436 rn
= extract32(insn
, 5, 5);
4437 rd
= extract32(insn
, 0, 5);
4439 if (mos
|| type
> 1) {
4440 unallocated_encoding(s
);
4444 if (!fp_access_check(s
)) {
4448 /* Zero extend sreg inputs to 64 bits now. */
4449 t_true
= tcg_temp_new_i64();
4450 t_false
= tcg_temp_new_i64();
4451 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4452 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4454 a64_test_cc(&c
, cond
);
4455 t_zero
= tcg_const_i64(0);
4456 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4457 tcg_temp_free_i64(t_zero
);
4458 tcg_temp_free_i64(t_false
);
4461 /* Note that sregs write back zeros to the high bits,
4462 and we've already done the zero-extension. */
4463 write_fp_dreg(s
, rd
, t_true
);
4464 tcg_temp_free_i64(t_true
);
4467 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4468 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4474 fpst
= get_fpstatus_ptr();
4475 tcg_op
= read_fp_sreg(s
, rn
);
4476 tcg_res
= tcg_temp_new_i32();
4479 case 0x0: /* FMOV */
4480 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4482 case 0x1: /* FABS */
4483 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4485 case 0x2: /* FNEG */
4486 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4488 case 0x3: /* FSQRT */
4489 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4491 case 0x8: /* FRINTN */
4492 case 0x9: /* FRINTP */
4493 case 0xa: /* FRINTM */
4494 case 0xb: /* FRINTZ */
4495 case 0xc: /* FRINTA */
4497 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4499 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4500 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4502 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4503 tcg_temp_free_i32(tcg_rmode
);
4506 case 0xe: /* FRINTX */
4507 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4509 case 0xf: /* FRINTI */
4510 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4516 write_fp_sreg(s
, rd
, tcg_res
);
4518 tcg_temp_free_ptr(fpst
);
4519 tcg_temp_free_i32(tcg_op
);
4520 tcg_temp_free_i32(tcg_res
);
4523 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4524 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4530 fpst
= get_fpstatus_ptr();
4531 tcg_op
= read_fp_dreg(s
, rn
);
4532 tcg_res
= tcg_temp_new_i64();
4535 case 0x0: /* FMOV */
4536 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4538 case 0x1: /* FABS */
4539 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4541 case 0x2: /* FNEG */
4542 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4544 case 0x3: /* FSQRT */
4545 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4547 case 0x8: /* FRINTN */
4548 case 0x9: /* FRINTP */
4549 case 0xa: /* FRINTM */
4550 case 0xb: /* FRINTZ */
4551 case 0xc: /* FRINTA */
4553 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4555 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4556 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4558 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4559 tcg_temp_free_i32(tcg_rmode
);
4562 case 0xe: /* FRINTX */
4563 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4565 case 0xf: /* FRINTI */
4566 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4572 write_fp_dreg(s
, rd
, tcg_res
);
4574 tcg_temp_free_ptr(fpst
);
4575 tcg_temp_free_i64(tcg_op
);
4576 tcg_temp_free_i64(tcg_res
);
4579 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4580 int rd
, int rn
, int dtype
, int ntype
)
4585 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4587 /* Single to double */
4588 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4589 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4590 write_fp_dreg(s
, rd
, tcg_rd
);
4591 tcg_temp_free_i64(tcg_rd
);
4593 /* Single to half */
4594 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4595 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4596 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4597 write_fp_sreg(s
, rd
, tcg_rd
);
4598 tcg_temp_free_i32(tcg_rd
);
4600 tcg_temp_free_i32(tcg_rn
);
4605 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4606 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4608 /* Double to single */
4609 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4611 /* Double to half */
4612 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4613 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4615 write_fp_sreg(s
, rd
, tcg_rd
);
4616 tcg_temp_free_i32(tcg_rd
);
4617 tcg_temp_free_i64(tcg_rn
);
4622 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4623 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4625 /* Half to single */
4626 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4627 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4628 write_fp_sreg(s
, rd
, tcg_rd
);
4629 tcg_temp_free_i32(tcg_rd
);
4631 /* Half to double */
4632 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4633 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4634 write_fp_dreg(s
, rd
, tcg_rd
);
4635 tcg_temp_free_i64(tcg_rd
);
4637 tcg_temp_free_i32(tcg_rn
);
4645 /* C3.6.25 Floating point data-processing (1 source)
4646 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4647 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4648 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4649 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4651 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4653 int type
= extract32(insn
, 22, 2);
4654 int opcode
= extract32(insn
, 15, 6);
4655 int rn
= extract32(insn
, 5, 5);
4656 int rd
= extract32(insn
, 0, 5);
4659 case 0x4: case 0x5: case 0x7:
4661 /* FCVT between half, single and double precision */
4662 int dtype
= extract32(opcode
, 0, 2);
4663 if (type
== 2 || dtype
== type
) {
4664 unallocated_encoding(s
);
4667 if (!fp_access_check(s
)) {
4671 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4677 /* 32-to-32 and 64-to-64 ops */
4680 if (!fp_access_check(s
)) {
4684 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4687 if (!fp_access_check(s
)) {
4691 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4694 unallocated_encoding(s
);
4698 unallocated_encoding(s
);
4703 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4704 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4705 int rd
, int rn
, int rm
)
4712 tcg_res
= tcg_temp_new_i32();
4713 fpst
= get_fpstatus_ptr();
4714 tcg_op1
= read_fp_sreg(s
, rn
);
4715 tcg_op2
= read_fp_sreg(s
, rm
);
4718 case 0x0: /* FMUL */
4719 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4721 case 0x1: /* FDIV */
4722 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4724 case 0x2: /* FADD */
4725 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4727 case 0x3: /* FSUB */
4728 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4730 case 0x4: /* FMAX */
4731 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4733 case 0x5: /* FMIN */
4734 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4736 case 0x6: /* FMAXNM */
4737 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4739 case 0x7: /* FMINNM */
4740 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4742 case 0x8: /* FNMUL */
4743 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4744 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4748 write_fp_sreg(s
, rd
, tcg_res
);
4750 tcg_temp_free_ptr(fpst
);
4751 tcg_temp_free_i32(tcg_op1
);
4752 tcg_temp_free_i32(tcg_op2
);
4753 tcg_temp_free_i32(tcg_res
);
4756 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4757 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4758 int rd
, int rn
, int rm
)
4765 tcg_res
= tcg_temp_new_i64();
4766 fpst
= get_fpstatus_ptr();
4767 tcg_op1
= read_fp_dreg(s
, rn
);
4768 tcg_op2
= read_fp_dreg(s
, rm
);
4771 case 0x0: /* FMUL */
4772 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4774 case 0x1: /* FDIV */
4775 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4777 case 0x2: /* FADD */
4778 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4780 case 0x3: /* FSUB */
4781 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4783 case 0x4: /* FMAX */
4784 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4786 case 0x5: /* FMIN */
4787 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4789 case 0x6: /* FMAXNM */
4790 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4792 case 0x7: /* FMINNM */
4793 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4795 case 0x8: /* FNMUL */
4796 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4797 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4801 write_fp_dreg(s
, rd
, tcg_res
);
4803 tcg_temp_free_ptr(fpst
);
4804 tcg_temp_free_i64(tcg_op1
);
4805 tcg_temp_free_i64(tcg_op2
);
4806 tcg_temp_free_i64(tcg_res
);
4809 /* C3.6.26 Floating point data-processing (2 source)
4810 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4811 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4812 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4813 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4815 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4817 int type
= extract32(insn
, 22, 2);
4818 int rd
= extract32(insn
, 0, 5);
4819 int rn
= extract32(insn
, 5, 5);
4820 int rm
= extract32(insn
, 16, 5);
4821 int opcode
= extract32(insn
, 12, 4);
4824 unallocated_encoding(s
);
4830 if (!fp_access_check(s
)) {
4833 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4836 if (!fp_access_check(s
)) {
4839 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4842 unallocated_encoding(s
);
4846 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4847 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4848 int rd
, int rn
, int rm
, int ra
)
4850 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4851 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4852 TCGv_ptr fpst
= get_fpstatus_ptr();
4854 tcg_op1
= read_fp_sreg(s
, rn
);
4855 tcg_op2
= read_fp_sreg(s
, rm
);
4856 tcg_op3
= read_fp_sreg(s
, ra
);
4858 /* These are fused multiply-add, and must be done as one
4859 * floating point operation with no rounding between the
4860 * multiplication and addition steps.
4861 * NB that doing the negations here as separate steps is
4862 * correct : an input NaN should come out with its sign bit
4863 * flipped if it is a negated-input.
4866 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4870 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4873 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4875 write_fp_sreg(s
, rd
, tcg_res
);
4877 tcg_temp_free_ptr(fpst
);
4878 tcg_temp_free_i32(tcg_op1
);
4879 tcg_temp_free_i32(tcg_op2
);
4880 tcg_temp_free_i32(tcg_op3
);
4881 tcg_temp_free_i32(tcg_res
);
4884 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4885 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4886 int rd
, int rn
, int rm
, int ra
)
4888 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4889 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4890 TCGv_ptr fpst
= get_fpstatus_ptr();
4892 tcg_op1
= read_fp_dreg(s
, rn
);
4893 tcg_op2
= read_fp_dreg(s
, rm
);
4894 tcg_op3
= read_fp_dreg(s
, ra
);
4896 /* These are fused multiply-add, and must be done as one
4897 * floating point operation with no rounding between the
4898 * multiplication and addition steps.
4899 * NB that doing the negations here as separate steps is
4900 * correct : an input NaN should come out with its sign bit
4901 * flipped if it is a negated-input.
4904 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4908 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4911 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4913 write_fp_dreg(s
, rd
, tcg_res
);
4915 tcg_temp_free_ptr(fpst
);
4916 tcg_temp_free_i64(tcg_op1
);
4917 tcg_temp_free_i64(tcg_op2
);
4918 tcg_temp_free_i64(tcg_op3
);
4919 tcg_temp_free_i64(tcg_res
);
4922 /* C3.6.27 Floating point data-processing (3 source)
4923 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4924 * +---+---+---+-----------+------+----+------+----+------+------+------+
4925 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4926 * +---+---+---+-----------+------+----+------+----+------+------+------+
4928 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4930 int type
= extract32(insn
, 22, 2);
4931 int rd
= extract32(insn
, 0, 5);
4932 int rn
= extract32(insn
, 5, 5);
4933 int ra
= extract32(insn
, 10, 5);
4934 int rm
= extract32(insn
, 16, 5);
4935 bool o0
= extract32(insn
, 15, 1);
4936 bool o1
= extract32(insn
, 21, 1);
4940 if (!fp_access_check(s
)) {
4943 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4946 if (!fp_access_check(s
)) {
4949 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4952 unallocated_encoding(s
);
4956 /* C3.6.28 Floating point immediate
4957 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4958 * +---+---+---+-----------+------+---+------------+-------+------+------+
4959 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4960 * +---+---+---+-----------+------+---+------------+-------+------+------+
4962 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4964 int rd
= extract32(insn
, 0, 5);
4965 int imm8
= extract32(insn
, 13, 8);
4966 int is_double
= extract32(insn
, 22, 2);
4970 if (is_double
> 1) {
4971 unallocated_encoding(s
);
4975 if (!fp_access_check(s
)) {
4979 /* The imm8 encodes the sign bit, enough bits to represent
4980 * an exponent in the range 01....1xx to 10....0xx,
4981 * and the most significant 4 bits of the mantissa; see
4982 * VFPExpandImm() in the v8 ARM ARM.
4985 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4986 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4987 extract32(imm8
, 0, 6);
4990 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4991 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4992 (extract32(imm8
, 0, 6) << 3);
4996 tcg_res
= tcg_const_i64(imm
);
4997 write_fp_dreg(s
, rd
, tcg_res
);
4998 tcg_temp_free_i64(tcg_res
);
5001 /* Handle floating point <=> fixed point conversions. Note that we can
5002 * also deal with fp <=> integer conversions as a special case (scale == 64)
5003 * OPTME: consider handling that special case specially or at least skipping
5004 * the call to scalbn in the helpers for zero shifts.
5006 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5007 bool itof
, int rmode
, int scale
, int sf
, int type
)
5009 bool is_signed
= !(opcode
& 1);
5010 bool is_double
= type
;
5011 TCGv_ptr tcg_fpstatus
;
5014 tcg_fpstatus
= get_fpstatus_ptr();
5016 tcg_shift
= tcg_const_i32(64 - scale
);
5019 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5021 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5024 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5026 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5029 tcg_int
= tcg_extend
;
5033 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5035 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5036 tcg_shift
, tcg_fpstatus
);
5038 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5039 tcg_shift
, tcg_fpstatus
);
5041 write_fp_dreg(s
, rd
, tcg_double
);
5042 tcg_temp_free_i64(tcg_double
);
5044 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5046 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5047 tcg_shift
, tcg_fpstatus
);
5049 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5050 tcg_shift
, tcg_fpstatus
);
5052 write_fp_sreg(s
, rd
, tcg_single
);
5053 tcg_temp_free_i32(tcg_single
);
5056 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5059 if (extract32(opcode
, 2, 1)) {
5060 /* There are too many rounding modes to all fit into rmode,
5061 * so FCVTA[US] is a special case.
5063 rmode
= FPROUNDING_TIEAWAY
;
5066 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5068 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5071 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5074 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5075 tcg_shift
, tcg_fpstatus
);
5077 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5078 tcg_shift
, tcg_fpstatus
);
5082 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5083 tcg_shift
, tcg_fpstatus
);
5085 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5086 tcg_shift
, tcg_fpstatus
);
5089 tcg_temp_free_i64(tcg_double
);
5091 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5094 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5095 tcg_shift
, tcg_fpstatus
);
5097 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5098 tcg_shift
, tcg_fpstatus
);
5101 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5103 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5104 tcg_shift
, tcg_fpstatus
);
5106 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5107 tcg_shift
, tcg_fpstatus
);
5109 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5110 tcg_temp_free_i32(tcg_dest
);
5112 tcg_temp_free_i32(tcg_single
);
5115 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5116 tcg_temp_free_i32(tcg_rmode
);
5119 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5123 tcg_temp_free_ptr(tcg_fpstatus
);
5124 tcg_temp_free_i32(tcg_shift
);
5127 /* C3.6.29 Floating point <-> fixed point conversions
5128 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5129 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5130 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5131 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5133 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5135 int rd
= extract32(insn
, 0, 5);
5136 int rn
= extract32(insn
, 5, 5);
5137 int scale
= extract32(insn
, 10, 6);
5138 int opcode
= extract32(insn
, 16, 3);
5139 int rmode
= extract32(insn
, 19, 2);
5140 int type
= extract32(insn
, 22, 2);
5141 bool sbit
= extract32(insn
, 29, 1);
5142 bool sf
= extract32(insn
, 31, 1);
5145 if (sbit
|| (type
> 1)
5146 || (!sf
&& scale
< 32)) {
5147 unallocated_encoding(s
);
5151 switch ((rmode
<< 3) | opcode
) {
5152 case 0x2: /* SCVTF */
5153 case 0x3: /* UCVTF */
5156 case 0x18: /* FCVTZS */
5157 case 0x19: /* FCVTZU */
5161 unallocated_encoding(s
);
5165 if (!fp_access_check(s
)) {
5169 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5172 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5174 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5175 * without conversion.
5179 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5185 TCGv_i64 tmp
= tcg_temp_new_i64();
5186 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5187 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5188 tcg_gen_movi_i64(tmp
, 0);
5189 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5190 tcg_temp_free_i64(tmp
);
5196 TCGv_i64 tmp
= tcg_const_i64(0);
5197 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5198 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5199 tcg_temp_free_i64(tmp
);
5203 /* 64 bit to top half. */
5204 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5208 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5213 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5217 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5220 /* 64 bits from top half */
5221 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5227 /* C3.6.30 Floating point <-> integer conversions
5228 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5229 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5230 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5231 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5233 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5235 int rd
= extract32(insn
, 0, 5);
5236 int rn
= extract32(insn
, 5, 5);
5237 int opcode
= extract32(insn
, 16, 3);
5238 int rmode
= extract32(insn
, 19, 2);
5239 int type
= extract32(insn
, 22, 2);
5240 bool sbit
= extract32(insn
, 29, 1);
5241 bool sf
= extract32(insn
, 31, 1);
5244 unallocated_encoding(s
);
5250 bool itof
= opcode
& 1;
5253 unallocated_encoding(s
);
5257 switch (sf
<< 3 | type
<< 1 | rmode
) {
5258 case 0x0: /* 32 bit */
5259 case 0xa: /* 64 bit */
5260 case 0xd: /* 64 bit to top half of quad */
5263 /* all other sf/type/rmode combinations are invalid */
5264 unallocated_encoding(s
);
5268 if (!fp_access_check(s
)) {
5271 handle_fmov(s
, rd
, rn
, type
, itof
);
5273 /* actual FP conversions */
5274 bool itof
= extract32(opcode
, 1, 1);
5276 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5277 unallocated_encoding(s
);
5281 if (!fp_access_check(s
)) {
5284 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5288 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5289 * 31 30 29 28 25 24 0
5290 * +---+---+---+---------+-----------------------------+
5291 * | | 0 | | 1 1 1 1 | |
5292 * +---+---+---+---------+-----------------------------+
5294 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5296 if (extract32(insn
, 24, 1)) {
5297 /* Floating point data-processing (3 source) */
5298 disas_fp_3src(s
, insn
);
5299 } else if (extract32(insn
, 21, 1) == 0) {
5300 /* Floating point to fixed point conversions */
5301 disas_fp_fixed_conv(s
, insn
);
5303 switch (extract32(insn
, 10, 2)) {
5305 /* Floating point conditional compare */
5306 disas_fp_ccomp(s
, insn
);
5309 /* Floating point data-processing (2 source) */
5310 disas_fp_2src(s
, insn
);
5313 /* Floating point conditional select */
5314 disas_fp_csel(s
, insn
);
5317 switch (ctz32(extract32(insn
, 12, 4))) {
5318 case 0: /* [15:12] == xxx1 */
5319 /* Floating point immediate */
5320 disas_fp_imm(s
, insn
);
5322 case 1: /* [15:12] == xx10 */
5323 /* Floating point compare */
5324 disas_fp_compare(s
, insn
);
5326 case 2: /* [15:12] == x100 */
5327 /* Floating point data-processing (1 source) */
5328 disas_fp_1src(s
, insn
);
5330 case 3: /* [15:12] == 1000 */
5331 unallocated_encoding(s
);
5333 default: /* [15:12] == 0000 */
5334 /* Floating point <-> integer conversions */
5335 disas_fp_int_conv(s
, insn
);
5343 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5346 /* Extract 64 bits from the middle of two concatenated 64 bit
5347 * vector register slices left:right. The extracted bits start
5348 * at 'pos' bits into the right (least significant) side.
5349 * We return the result in tcg_right, and guarantee not to
5352 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5353 assert(pos
> 0 && pos
< 64);
5355 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5356 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5357 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5359 tcg_temp_free_i64(tcg_tmp
);
5363 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5364 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5365 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5366 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5368 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5370 int is_q
= extract32(insn
, 30, 1);
5371 int op2
= extract32(insn
, 22, 2);
5372 int imm4
= extract32(insn
, 11, 4);
5373 int rm
= extract32(insn
, 16, 5);
5374 int rn
= extract32(insn
, 5, 5);
5375 int rd
= extract32(insn
, 0, 5);
5376 int pos
= imm4
<< 3;
5377 TCGv_i64 tcg_resl
, tcg_resh
;
5379 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5380 unallocated_encoding(s
);
5384 if (!fp_access_check(s
)) {
5388 tcg_resh
= tcg_temp_new_i64();
5389 tcg_resl
= tcg_temp_new_i64();
5391 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5392 * either extracting 128 bits from a 128:128 concatenation, or
5393 * extracting 64 bits from a 64:64 concatenation.
5396 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5398 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5399 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5401 tcg_gen_movi_i64(tcg_resh
, 0);
5408 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5409 EltPosns
*elt
= eltposns
;
5416 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5418 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5421 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5422 tcg_hh
= tcg_temp_new_i64();
5423 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5424 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5425 tcg_temp_free_i64(tcg_hh
);
5429 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5430 tcg_temp_free_i64(tcg_resl
);
5431 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5432 tcg_temp_free_i64(tcg_resh
);
5436 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5437 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5438 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5439 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5441 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5443 int op2
= extract32(insn
, 22, 2);
5444 int is_q
= extract32(insn
, 30, 1);
5445 int rm
= extract32(insn
, 16, 5);
5446 int rn
= extract32(insn
, 5, 5);
5447 int rd
= extract32(insn
, 0, 5);
5448 int is_tblx
= extract32(insn
, 12, 1);
5449 int len
= extract32(insn
, 13, 2);
5450 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5451 TCGv_i32 tcg_regno
, tcg_numregs
;
5454 unallocated_encoding(s
);
5458 if (!fp_access_check(s
)) {
5462 /* This does a table lookup: for every byte element in the input
5463 * we index into a table formed from up to four vector registers,
5464 * and then the output is the result of the lookups. Our helper
5465 * function does the lookup operation for a single 64 bit part of
5468 tcg_resl
= tcg_temp_new_i64();
5469 tcg_resh
= tcg_temp_new_i64();
5472 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5474 tcg_gen_movi_i64(tcg_resl
, 0);
5476 if (is_tblx
&& is_q
) {
5477 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5479 tcg_gen_movi_i64(tcg_resh
, 0);
5482 tcg_idx
= tcg_temp_new_i64();
5483 tcg_regno
= tcg_const_i32(rn
);
5484 tcg_numregs
= tcg_const_i32(len
+ 1);
5485 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5486 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5487 tcg_regno
, tcg_numregs
);
5489 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5490 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5491 tcg_regno
, tcg_numregs
);
5493 tcg_temp_free_i64(tcg_idx
);
5494 tcg_temp_free_i32(tcg_regno
);
5495 tcg_temp_free_i32(tcg_numregs
);
5497 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5498 tcg_temp_free_i64(tcg_resl
);
5499 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5500 tcg_temp_free_i64(tcg_resh
);
5503 /* C3.6.3 ZIP/UZP/TRN
5504 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5505 * +---+---+-------------+------+---+------+---+------------------+------+
5506 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5507 * +---+---+-------------+------+---+------+---+------------------+------+
5509 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5511 int rd
= extract32(insn
, 0, 5);
5512 int rn
= extract32(insn
, 5, 5);
5513 int rm
= extract32(insn
, 16, 5);
5514 int size
= extract32(insn
, 22, 2);
5515 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5516 * bit 2 indicates 1 vs 2 variant of the insn.
5518 int opcode
= extract32(insn
, 12, 2);
5519 bool part
= extract32(insn
, 14, 1);
5520 bool is_q
= extract32(insn
, 30, 1);
5521 int esize
= 8 << size
;
5523 int datasize
= is_q
? 128 : 64;
5524 int elements
= datasize
/ esize
;
5525 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5527 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5528 unallocated_encoding(s
);
5532 if (!fp_access_check(s
)) {
5536 tcg_resl
= tcg_const_i64(0);
5537 tcg_resh
= tcg_const_i64(0);
5538 tcg_res
= tcg_temp_new_i64();
5540 for (i
= 0; i
< elements
; i
++) {
5542 case 1: /* UZP1/2 */
5544 int midpoint
= elements
/ 2;
5546 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5548 read_vec_element(s
, tcg_res
, rm
,
5549 2 * (i
- midpoint
) + part
, size
);
5553 case 2: /* TRN1/2 */
5555 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5557 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5560 case 3: /* ZIP1/2 */
5562 int base
= part
* elements
/ 2;
5564 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5566 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5571 g_assert_not_reached();
5576 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5577 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5579 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5580 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5584 tcg_temp_free_i64(tcg_res
);
5586 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5587 tcg_temp_free_i64(tcg_resl
);
5588 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5589 tcg_temp_free_i64(tcg_resh
);
5592 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5593 int opc
, bool is_min
, TCGv_ptr fpst
)
5595 /* Helper function for disas_simd_across_lanes: do a single precision
5596 * min/max operation on the specified two inputs,
5597 * and return the result in tcg_elt1.
5601 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5603 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5608 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5610 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5615 /* C3.6.4 AdvSIMD across lanes
5616 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5617 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5618 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5619 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5621 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5623 int rd
= extract32(insn
, 0, 5);
5624 int rn
= extract32(insn
, 5, 5);
5625 int size
= extract32(insn
, 22, 2);
5626 int opcode
= extract32(insn
, 12, 5);
5627 bool is_q
= extract32(insn
, 30, 1);
5628 bool is_u
= extract32(insn
, 29, 1);
5630 bool is_min
= false;
5634 TCGv_i64 tcg_res
, tcg_elt
;
5637 case 0x1b: /* ADDV */
5639 unallocated_encoding(s
);
5643 case 0x3: /* SADDLV, UADDLV */
5644 case 0xa: /* SMAXV, UMAXV */
5645 case 0x1a: /* SMINV, UMINV */
5646 if (size
== 3 || (size
== 2 && !is_q
)) {
5647 unallocated_encoding(s
);
5651 case 0xc: /* FMAXNMV, FMINNMV */
5652 case 0xf: /* FMAXV, FMINV */
5653 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5654 unallocated_encoding(s
);
5657 /* Bit 1 of size field encodes min vs max, and actual size is always
5658 * 32 bits: adjust the size variable so following code can rely on it
5660 is_min
= extract32(size
, 1, 1);
5665 unallocated_encoding(s
);
5669 if (!fp_access_check(s
)) {
5674 elements
= (is_q
? 128 : 64) / esize
;
5676 tcg_res
= tcg_temp_new_i64();
5677 tcg_elt
= tcg_temp_new_i64();
5679 /* These instructions operate across all lanes of a vector
5680 * to produce a single result. We can guarantee that a 64
5681 * bit intermediate is sufficient:
5682 * + for [US]ADDLV the maximum element size is 32 bits, and
5683 * the result type is 64 bits
5684 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5685 * same as the element size, which is 32 bits at most
5686 * For the integer operations we can choose to work at 64
5687 * or 32 bits and truncate at the end; for simplicity
5688 * we use 64 bits always. The floating point
5689 * ops do require 32 bit intermediates, though.
5692 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5694 for (i
= 1; i
< elements
; i
++) {
5695 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5698 case 0x03: /* SADDLV / UADDLV */
5699 case 0x1b: /* ADDV */
5700 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5702 case 0x0a: /* SMAXV / UMAXV */
5703 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5705 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5707 case 0x1a: /* SMINV / UMINV */
5708 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5710 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5714 g_assert_not_reached();
5719 /* Floating point ops which work on 32 bit (single) intermediates.
5720 * Note that correct NaN propagation requires that we do these
5721 * operations in exactly the order specified by the pseudocode.
5723 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5724 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5725 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5726 TCGv_ptr fpst
= get_fpstatus_ptr();
5728 assert(esize
== 32);
5729 assert(elements
== 4);
5731 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5732 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5733 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5734 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5736 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5738 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5739 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5740 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5741 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5743 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5745 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5747 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5748 tcg_temp_free_i32(tcg_elt1
);
5749 tcg_temp_free_i32(tcg_elt2
);
5750 tcg_temp_free_i32(tcg_elt3
);
5751 tcg_temp_free_ptr(fpst
);
5754 tcg_temp_free_i64(tcg_elt
);
5756 /* Now truncate the result to the width required for the final output */
5757 if (opcode
== 0x03) {
5758 /* SADDLV, UADDLV: result is 2*esize */
5764 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5767 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5770 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5775 g_assert_not_reached();
5778 write_fp_dreg(s
, rd
, tcg_res
);
5779 tcg_temp_free_i64(tcg_res
);
5782 /* C6.3.31 DUP (Element, Vector)
5784 * 31 30 29 21 20 16 15 10 9 5 4 0
5785 * +---+---+-------------------+--------+-------------+------+------+
5786 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5787 * +---+---+-------------------+--------+-------------+------+------+
5789 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5791 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5794 int size
= ctz32(imm5
);
5795 int esize
= 8 << size
;
5796 int elements
= (is_q
? 128 : 64) / esize
;
5800 if (size
> 3 || (size
== 3 && !is_q
)) {
5801 unallocated_encoding(s
);
5805 if (!fp_access_check(s
)) {
5809 index
= imm5
>> (size
+ 1);
5811 tmp
= tcg_temp_new_i64();
5812 read_vec_element(s
, tmp
, rn
, index
, size
);
5814 for (i
= 0; i
< elements
; i
++) {
5815 write_vec_element(s
, tmp
, rd
, i
, size
);
5819 clear_vec_high(s
, rd
);
5822 tcg_temp_free_i64(tmp
);
5825 /* C6.3.31 DUP (element, scalar)
5826 * 31 21 20 16 15 10 9 5 4 0
5827 * +-----------------------+--------+-------------+------+------+
5828 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5829 * +-----------------------+--------+-------------+------+------+
5831 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5834 int size
= ctz32(imm5
);
5839 unallocated_encoding(s
);
5843 if (!fp_access_check(s
)) {
5847 index
= imm5
>> (size
+ 1);
5849 /* This instruction just extracts the specified element and
5850 * zero-extends it into the bottom of the destination register.
5852 tmp
= tcg_temp_new_i64();
5853 read_vec_element(s
, tmp
, rn
, index
, size
);
5854 write_fp_dreg(s
, rd
, tmp
);
5855 tcg_temp_free_i64(tmp
);
5858 /* C6.3.32 DUP (General)
5860 * 31 30 29 21 20 16 15 10 9 5 4 0
5861 * +---+---+-------------------+--------+-------------+------+------+
5862 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5863 * +---+---+-------------------+--------+-------------+------+------+
5865 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5867 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5870 int size
= ctz32(imm5
);
5871 int esize
= 8 << size
;
5872 int elements
= (is_q
? 128 : 64)/esize
;
5875 if (size
> 3 || ((size
== 3) && !is_q
)) {
5876 unallocated_encoding(s
);
5880 if (!fp_access_check(s
)) {
5884 for (i
= 0; i
< elements
; i
++) {
5885 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5888 clear_vec_high(s
, rd
);
5892 /* C6.3.150 INS (Element)
5894 * 31 21 20 16 15 14 11 10 9 5 4 0
5895 * +-----------------------+--------+------------+---+------+------+
5896 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5897 * +-----------------------+--------+------------+---+------+------+
5899 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5900 * index: encoded in imm5<4:size+1>
5902 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5905 int size
= ctz32(imm5
);
5906 int src_index
, dst_index
;
5910 unallocated_encoding(s
);
5914 if (!fp_access_check(s
)) {
5918 dst_index
= extract32(imm5
, 1+size
, 5);
5919 src_index
= extract32(imm4
, size
, 4);
5921 tmp
= tcg_temp_new_i64();
5923 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5924 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5926 tcg_temp_free_i64(tmp
);
5930 /* C6.3.151 INS (General)
5932 * 31 21 20 16 15 10 9 5 4 0
5933 * +-----------------------+--------+-------------+------+------+
5934 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5935 * +-----------------------+--------+-------------+------+------+
5937 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5938 * index: encoded in imm5<4:size+1>
5940 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5942 int size
= ctz32(imm5
);
5946 unallocated_encoding(s
);
5950 if (!fp_access_check(s
)) {
5954 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5955 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5959 * C6.3.321 UMOV (General)
5960 * C6.3.237 SMOV (General)
5962 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5963 * +---+---+-------------------+--------+-------------+------+------+
5964 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5965 * +---+---+-------------------+--------+-------------+------+------+
5967 * U: unsigned when set
5968 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5970 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5971 int rn
, int rd
, int imm5
)
5973 int size
= ctz32(imm5
);
5977 /* Check for UnallocatedEncodings */
5979 if (size
> 2 || (size
== 2 && !is_q
)) {
5980 unallocated_encoding(s
);
5985 || (size
< 3 && is_q
)
5986 || (size
== 3 && !is_q
)) {
5987 unallocated_encoding(s
);
5992 if (!fp_access_check(s
)) {
5996 element
= extract32(imm5
, 1+size
, 4);
5998 tcg_rd
= cpu_reg(s
, rd
);
5999 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6000 if (is_signed
&& !is_q
) {
6001 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6005 /* C3.6.5 AdvSIMD copy
6006 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6007 * +---+---+----+-----------------+------+---+------+---+------+------+
6008 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6009 * +---+---+----+-----------------+------+---+------+---+------+------+
6011 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6013 int rd
= extract32(insn
, 0, 5);
6014 int rn
= extract32(insn
, 5, 5);
6015 int imm4
= extract32(insn
, 11, 4);
6016 int op
= extract32(insn
, 29, 1);
6017 int is_q
= extract32(insn
, 30, 1);
6018 int imm5
= extract32(insn
, 16, 5);
6023 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6025 unallocated_encoding(s
);
6030 /* DUP (element - vector) */
6031 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6035 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6040 handle_simd_insg(s
, rd
, rn
, imm5
);
6042 unallocated_encoding(s
);
6047 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6048 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6051 unallocated_encoding(s
);
6057 /* C3.6.6 AdvSIMD modified immediate
6058 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6059 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6060 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6061 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6063 * There are a number of operations that can be carried out here:
6064 * MOVI - move (shifted) imm into register
6065 * MVNI - move inverted (shifted) imm into register
6066 * ORR - bitwise OR of (shifted) imm with register
6067 * BIC - bitwise clear of (shifted) imm with register
6069 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6071 int rd
= extract32(insn
, 0, 5);
6072 int cmode
= extract32(insn
, 12, 4);
6073 int cmode_3_1
= extract32(cmode
, 1, 3);
6074 int cmode_0
= extract32(cmode
, 0, 1);
6075 int o2
= extract32(insn
, 11, 1);
6076 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6077 bool is_neg
= extract32(insn
, 29, 1);
6078 bool is_q
= extract32(insn
, 30, 1);
6080 TCGv_i64 tcg_rd
, tcg_imm
;
6083 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6084 unallocated_encoding(s
);
6088 if (!fp_access_check(s
)) {
6092 /* See AdvSIMDExpandImm() in ARM ARM */
6093 switch (cmode_3_1
) {
6094 case 0: /* Replicate(Zeros(24):imm8, 2) */
6095 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6096 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6097 case 3: /* Replicate(imm8:Zeros(24), 2) */
6099 int shift
= cmode_3_1
* 8;
6100 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6103 case 4: /* Replicate(Zeros(8):imm8, 4) */
6104 case 5: /* Replicate(imm8:Zeros(8), 4) */
6106 int shift
= (cmode_3_1
& 0x1) * 8;
6107 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6112 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6113 imm
= (abcdefgh
<< 16) | 0xffff;
6115 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6116 imm
= (abcdefgh
<< 8) | 0xff;
6118 imm
= bitfield_replicate(imm
, 32);
6121 if (!cmode_0
&& !is_neg
) {
6122 imm
= bitfield_replicate(abcdefgh
, 8);
6123 } else if (!cmode_0
&& is_neg
) {
6126 for (i
= 0; i
< 8; i
++) {
6127 if ((abcdefgh
) & (1 << i
)) {
6128 imm
|= 0xffULL
<< (i
* 8);
6131 } else if (cmode_0
) {
6133 imm
= (abcdefgh
& 0x3f) << 48;
6134 if (abcdefgh
& 0x80) {
6135 imm
|= 0x8000000000000000ULL
;
6137 if (abcdefgh
& 0x40) {
6138 imm
|= 0x3fc0000000000000ULL
;
6140 imm
|= 0x4000000000000000ULL
;
6143 imm
= (abcdefgh
& 0x3f) << 19;
6144 if (abcdefgh
& 0x80) {
6147 if (abcdefgh
& 0x40) {
6158 if (cmode_3_1
!= 7 && is_neg
) {
6162 tcg_imm
= tcg_const_i64(imm
);
6163 tcg_rd
= new_tmp_a64(s
);
6165 for (i
= 0; i
< 2; i
++) {
6166 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6168 if (i
== 1 && !is_q
) {
6169 /* non-quad ops clear high half of vector */
6170 tcg_gen_movi_i64(tcg_rd
, 0);
6171 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6172 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6175 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6178 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6182 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6184 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6187 tcg_temp_free_i64(tcg_imm
);
6190 /* C3.6.7 AdvSIMD scalar copy
6191 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6192 * +-----+----+-----------------+------+---+------+---+------+------+
6193 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6194 * +-----+----+-----------------+------+---+------+---+------+------+
6196 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6198 int rd
= extract32(insn
, 0, 5);
6199 int rn
= extract32(insn
, 5, 5);
6200 int imm4
= extract32(insn
, 11, 4);
6201 int imm5
= extract32(insn
, 16, 5);
6202 int op
= extract32(insn
, 29, 1);
6204 if (op
!= 0 || imm4
!= 0) {
6205 unallocated_encoding(s
);
6209 /* DUP (element, scalar) */
6210 handle_simd_dupes(s
, rd
, rn
, imm5
);
6213 /* C3.6.8 AdvSIMD scalar pairwise
6214 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6215 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6216 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6217 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6219 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6221 int u
= extract32(insn
, 29, 1);
6222 int size
= extract32(insn
, 22, 2);
6223 int opcode
= extract32(insn
, 12, 5);
6224 int rn
= extract32(insn
, 5, 5);
6225 int rd
= extract32(insn
, 0, 5);
6228 /* For some ops (the FP ones), size[1] is part of the encoding.
6229 * For ADDP strictly it is not but size[1] is always 1 for valid
6232 opcode
|= (extract32(size
, 1, 1) << 5);
6235 case 0x3b: /* ADDP */
6236 if (u
|| size
!= 3) {
6237 unallocated_encoding(s
);
6240 if (!fp_access_check(s
)) {
6244 TCGV_UNUSED_PTR(fpst
);
6246 case 0xc: /* FMAXNMP */
6247 case 0xd: /* FADDP */
6248 case 0xf: /* FMAXP */
6249 case 0x2c: /* FMINNMP */
6250 case 0x2f: /* FMINP */
6251 /* FP op, size[0] is 32 or 64 bit */
6253 unallocated_encoding(s
);
6256 if (!fp_access_check(s
)) {
6260 size
= extract32(size
, 0, 1) ? 3 : 2;
6261 fpst
= get_fpstatus_ptr();
6264 unallocated_encoding(s
);
6269 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6270 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6271 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6273 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6274 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6277 case 0x3b: /* ADDP */
6278 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6280 case 0xc: /* FMAXNMP */
6281 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6283 case 0xd: /* FADDP */
6284 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6286 case 0xf: /* FMAXP */
6287 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6289 case 0x2c: /* FMINNMP */
6290 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6292 case 0x2f: /* FMINP */
6293 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6296 g_assert_not_reached();
6299 write_fp_dreg(s
, rd
, tcg_res
);
6301 tcg_temp_free_i64(tcg_op1
);
6302 tcg_temp_free_i64(tcg_op2
);
6303 tcg_temp_free_i64(tcg_res
);
6305 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6306 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6307 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6309 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6310 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6313 case 0xc: /* FMAXNMP */
6314 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6316 case 0xd: /* FADDP */
6317 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6319 case 0xf: /* FMAXP */
6320 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6322 case 0x2c: /* FMINNMP */
6323 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6325 case 0x2f: /* FMINP */
6326 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6329 g_assert_not_reached();
6332 write_fp_sreg(s
, rd
, tcg_res
);
6334 tcg_temp_free_i32(tcg_op1
);
6335 tcg_temp_free_i32(tcg_op2
);
6336 tcg_temp_free_i32(tcg_res
);
6339 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6340 tcg_temp_free_ptr(fpst
);
6345 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6347 * This code is handles the common shifting code and is used by both
6348 * the vector and scalar code.
6350 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6351 TCGv_i64 tcg_rnd
, bool accumulate
,
6352 bool is_u
, int size
, int shift
)
6354 bool extended_result
= false;
6355 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6357 TCGv_i64 tcg_src_hi
;
6359 if (round
&& size
== 3) {
6360 extended_result
= true;
6361 ext_lshift
= 64 - shift
;
6362 tcg_src_hi
= tcg_temp_new_i64();
6363 } else if (shift
== 64) {
6364 if (!accumulate
&& is_u
) {
6365 /* result is zero */
6366 tcg_gen_movi_i64(tcg_res
, 0);
6371 /* Deal with the rounding step */
6373 if (extended_result
) {
6374 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6376 /* take care of sign extending tcg_res */
6377 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6378 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6379 tcg_src
, tcg_src_hi
,
6382 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6386 tcg_temp_free_i64(tcg_zero
);
6388 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6392 /* Now do the shift right */
6393 if (round
&& extended_result
) {
6394 /* extended case, >64 bit precision required */
6395 if (ext_lshift
== 0) {
6396 /* special case, only high bits matter */
6397 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6399 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6400 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6401 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6406 /* essentially shifting in 64 zeros */
6407 tcg_gen_movi_i64(tcg_src
, 0);
6409 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6413 /* effectively extending the sign-bit */
6414 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6416 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6422 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6424 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6427 if (extended_result
) {
6428 tcg_temp_free_i64(tcg_src_hi
);
6432 /* Common SHL/SLI - Shift left with an optional insert */
6433 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6434 bool insert
, int shift
)
6436 if (insert
) { /* SLI */
6437 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6439 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6443 /* SRI: shift right with insert */
6444 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6445 int size
, int shift
)
6447 int esize
= 8 << size
;
6449 /* shift count same as element size is valid but does nothing;
6450 * special case to avoid potential shift by 64.
6452 if (shift
!= esize
) {
6453 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6454 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6458 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6459 static void handle_scalar_simd_shri(DisasContext
*s
,
6460 bool is_u
, int immh
, int immb
,
6461 int opcode
, int rn
, int rd
)
6464 int immhb
= immh
<< 3 | immb
;
6465 int shift
= 2 * (8 << size
) - immhb
;
6466 bool accumulate
= false;
6468 bool insert
= false;
6473 if (!extract32(immh
, 3, 1)) {
6474 unallocated_encoding(s
);
6478 if (!fp_access_check(s
)) {
6483 case 0x02: /* SSRA / USRA (accumulate) */
6486 case 0x04: /* SRSHR / URSHR (rounding) */
6489 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6490 accumulate
= round
= true;
6492 case 0x08: /* SRI */
6498 uint64_t round_const
= 1ULL << (shift
- 1);
6499 tcg_round
= tcg_const_i64(round_const
);
6501 TCGV_UNUSED_I64(tcg_round
);
6504 tcg_rn
= read_fp_dreg(s
, rn
);
6505 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6508 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6510 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6511 accumulate
, is_u
, size
, shift
);
6514 write_fp_dreg(s
, rd
, tcg_rd
);
6516 tcg_temp_free_i64(tcg_rn
);
6517 tcg_temp_free_i64(tcg_rd
);
6519 tcg_temp_free_i64(tcg_round
);
6523 /* SHL/SLI - Scalar shift left */
6524 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6525 int immh
, int immb
, int opcode
,
6528 int size
= 32 - clz32(immh
) - 1;
6529 int immhb
= immh
<< 3 | immb
;
6530 int shift
= immhb
- (8 << size
);
6531 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6532 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6534 if (!extract32(immh
, 3, 1)) {
6535 unallocated_encoding(s
);
6539 if (!fp_access_check(s
)) {
6543 tcg_rn
= read_fp_dreg(s
, rn
);
6544 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6546 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6548 write_fp_dreg(s
, rd
, tcg_rd
);
6550 tcg_temp_free_i64(tcg_rn
);
6551 tcg_temp_free_i64(tcg_rd
);
6554 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6555 * (signed/unsigned) narrowing */
6556 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6557 bool is_u_shift
, bool is_u_narrow
,
6558 int immh
, int immb
, int opcode
,
6561 int immhb
= immh
<< 3 | immb
;
6562 int size
= 32 - clz32(immh
) - 1;
6563 int esize
= 8 << size
;
6564 int shift
= (2 * esize
) - immhb
;
6565 int elements
= is_scalar
? 1 : (64 / esize
);
6566 bool round
= extract32(opcode
, 0, 1);
6567 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6568 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6569 TCGv_i32 tcg_rd_narrowed
;
6572 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6573 { gen_helper_neon_narrow_sat_s8
,
6574 gen_helper_neon_unarrow_sat8
},
6575 { gen_helper_neon_narrow_sat_s16
,
6576 gen_helper_neon_unarrow_sat16
},
6577 { gen_helper_neon_narrow_sat_s32
,
6578 gen_helper_neon_unarrow_sat32
},
6581 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6582 gen_helper_neon_narrow_sat_u8
,
6583 gen_helper_neon_narrow_sat_u16
,
6584 gen_helper_neon_narrow_sat_u32
,
6587 NeonGenNarrowEnvFn
*narrowfn
;
6593 if (extract32(immh
, 3, 1)) {
6594 unallocated_encoding(s
);
6598 if (!fp_access_check(s
)) {
6603 narrowfn
= unsigned_narrow_fns
[size
];
6605 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6608 tcg_rn
= tcg_temp_new_i64();
6609 tcg_rd
= tcg_temp_new_i64();
6610 tcg_rd_narrowed
= tcg_temp_new_i32();
6611 tcg_final
= tcg_const_i64(0);
6614 uint64_t round_const
= 1ULL << (shift
- 1);
6615 tcg_round
= tcg_const_i64(round_const
);
6617 TCGV_UNUSED_I64(tcg_round
);
6620 for (i
= 0; i
< elements
; i
++) {
6621 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6622 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6623 false, is_u_shift
, size
+1, shift
);
6624 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6625 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6626 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6630 clear_vec_high(s
, rd
);
6631 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6633 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6637 tcg_temp_free_i64(tcg_round
);
6639 tcg_temp_free_i64(tcg_rn
);
6640 tcg_temp_free_i64(tcg_rd
);
6641 tcg_temp_free_i32(tcg_rd_narrowed
);
6642 tcg_temp_free_i64(tcg_final
);
6646 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6647 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6648 bool src_unsigned
, bool dst_unsigned
,
6649 int immh
, int immb
, int rn
, int rd
)
6651 int immhb
= immh
<< 3 | immb
;
6652 int size
= 32 - clz32(immh
) - 1;
6653 int shift
= immhb
- (8 << size
);
6657 assert(!(scalar
&& is_q
));
6660 if (!is_q
&& extract32(immh
, 3, 1)) {
6661 unallocated_encoding(s
);
6665 /* Since we use the variable-shift helpers we must
6666 * replicate the shift count into each element of
6667 * the tcg_shift value.
6671 shift
|= shift
<< 8;
6674 shift
|= shift
<< 16;
6680 g_assert_not_reached();
6684 if (!fp_access_check(s
)) {
6689 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6690 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6691 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6692 { NULL
, gen_helper_neon_qshl_u64
},
6694 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6695 int maxpass
= is_q
? 2 : 1;
6697 for (pass
= 0; pass
< maxpass
; pass
++) {
6698 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6700 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6701 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6702 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6704 tcg_temp_free_i64(tcg_op
);
6706 tcg_temp_free_i64(tcg_shift
);
6709 clear_vec_high(s
, rd
);
6712 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6713 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6715 { gen_helper_neon_qshl_s8
,
6716 gen_helper_neon_qshl_s16
,
6717 gen_helper_neon_qshl_s32
},
6718 { gen_helper_neon_qshlu_s8
,
6719 gen_helper_neon_qshlu_s16
,
6720 gen_helper_neon_qshlu_s32
}
6722 { NULL
, NULL
, NULL
},
6723 { gen_helper_neon_qshl_u8
,
6724 gen_helper_neon_qshl_u16
,
6725 gen_helper_neon_qshl_u32
}
6728 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6729 TCGMemOp memop
= scalar
? size
: MO_32
;
6730 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6732 for (pass
= 0; pass
< maxpass
; pass
++) {
6733 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6735 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6736 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6740 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6743 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6748 g_assert_not_reached();
6750 write_fp_sreg(s
, rd
, tcg_op
);
6752 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6755 tcg_temp_free_i32(tcg_op
);
6757 tcg_temp_free_i32(tcg_shift
);
6759 if (!is_q
&& !scalar
) {
6760 clear_vec_high(s
, rd
);
6765 /* Common vector code for handling integer to FP conversion */
6766 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6767 int elements
, int is_signed
,
6768 int fracbits
, int size
)
6770 bool is_double
= size
== 3 ? true : false;
6771 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6772 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6773 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6774 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6777 for (pass
= 0; pass
< elements
; pass
++) {
6778 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6781 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6783 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6784 tcg_shift
, tcg_fpst
);
6786 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6787 tcg_shift
, tcg_fpst
);
6789 if (elements
== 1) {
6790 write_fp_dreg(s
, rd
, tcg_double
);
6792 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6794 tcg_temp_free_i64(tcg_double
);
6796 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6798 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6799 tcg_shift
, tcg_fpst
);
6801 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6802 tcg_shift
, tcg_fpst
);
6804 if (elements
== 1) {
6805 write_fp_sreg(s
, rd
, tcg_single
);
6807 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6809 tcg_temp_free_i32(tcg_single
);
6813 if (!is_double
&& elements
== 2) {
6814 clear_vec_high(s
, rd
);
6817 tcg_temp_free_i64(tcg_int
);
6818 tcg_temp_free_ptr(tcg_fpst
);
6819 tcg_temp_free_i32(tcg_shift
);
6822 /* UCVTF/SCVTF - Integer to FP conversion */
6823 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6824 bool is_q
, bool is_u
,
6825 int immh
, int immb
, int opcode
,
6828 bool is_double
= extract32(immh
, 3, 1);
6829 int size
= is_double
? MO_64
: MO_32
;
6831 int immhb
= immh
<< 3 | immb
;
6832 int fracbits
= (is_double
? 128 : 64) - immhb
;
6834 if (!extract32(immh
, 2, 2)) {
6835 unallocated_encoding(s
);
6842 elements
= is_double
? 2 : is_q
? 4 : 2;
6843 if (is_double
&& !is_q
) {
6844 unallocated_encoding(s
);
6849 if (!fp_access_check(s
)) {
6853 /* immh == 0 would be a failure of the decode logic */
6856 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6859 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6860 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6861 bool is_q
, bool is_u
,
6862 int immh
, int immb
, int rn
, int rd
)
6864 bool is_double
= extract32(immh
, 3, 1);
6865 int immhb
= immh
<< 3 | immb
;
6866 int fracbits
= (is_double
? 128 : 64) - immhb
;
6868 TCGv_ptr tcg_fpstatus
;
6869 TCGv_i32 tcg_rmode
, tcg_shift
;
6871 if (!extract32(immh
, 2, 2)) {
6872 unallocated_encoding(s
);
6876 if (!is_scalar
&& !is_q
&& is_double
) {
6877 unallocated_encoding(s
);
6881 if (!fp_access_check(s
)) {
6885 assert(!(is_scalar
&& is_q
));
6887 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6888 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6889 tcg_fpstatus
= get_fpstatus_ptr();
6890 tcg_shift
= tcg_const_i32(fracbits
);
6893 int maxpass
= is_scalar
? 1 : 2;
6895 for (pass
= 0; pass
< maxpass
; pass
++) {
6896 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6898 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6900 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6902 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6904 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6905 tcg_temp_free_i64(tcg_op
);
6908 clear_vec_high(s
, rd
);
6911 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6912 for (pass
= 0; pass
< maxpass
; pass
++) {
6913 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6915 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6917 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6919 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6922 write_fp_sreg(s
, rd
, tcg_op
);
6924 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6926 tcg_temp_free_i32(tcg_op
);
6928 if (!is_q
&& !is_scalar
) {
6929 clear_vec_high(s
, rd
);
6933 tcg_temp_free_ptr(tcg_fpstatus
);
6934 tcg_temp_free_i32(tcg_shift
);
6935 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6936 tcg_temp_free_i32(tcg_rmode
);
6939 /* C3.6.9 AdvSIMD scalar shift by immediate
6940 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6941 * +-----+---+-------------+------+------+--------+---+------+------+
6942 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6943 * +-----+---+-------------+------+------+--------+---+------+------+
6945 * This is the scalar version so it works on a fixed sized registers
6947 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6949 int rd
= extract32(insn
, 0, 5);
6950 int rn
= extract32(insn
, 5, 5);
6951 int opcode
= extract32(insn
, 11, 5);
6952 int immb
= extract32(insn
, 16, 3);
6953 int immh
= extract32(insn
, 19, 4);
6954 bool is_u
= extract32(insn
, 29, 1);
6957 unallocated_encoding(s
);
6962 case 0x08: /* SRI */
6964 unallocated_encoding(s
);
6968 case 0x00: /* SSHR / USHR */
6969 case 0x02: /* SSRA / USRA */
6970 case 0x04: /* SRSHR / URSHR */
6971 case 0x06: /* SRSRA / URSRA */
6972 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6974 case 0x0a: /* SHL / SLI */
6975 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6977 case 0x1c: /* SCVTF, UCVTF */
6978 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6981 case 0x10: /* SQSHRUN, SQSHRUN2 */
6982 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6984 unallocated_encoding(s
);
6987 handle_vec_simd_sqshrn(s
, true, false, false, true,
6988 immh
, immb
, opcode
, rn
, rd
);
6990 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6991 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6992 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6993 immh
, immb
, opcode
, rn
, rd
);
6995 case 0xc: /* SQSHLU */
6997 unallocated_encoding(s
);
7000 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7002 case 0xe: /* SQSHL, UQSHL */
7003 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7005 case 0x1f: /* FCVTZS, FCVTZU */
7006 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7009 unallocated_encoding(s
);
7014 /* C3.6.10 AdvSIMD scalar three different
7015 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7016 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7017 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7018 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7020 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7022 bool is_u
= extract32(insn
, 29, 1);
7023 int size
= extract32(insn
, 22, 2);
7024 int opcode
= extract32(insn
, 12, 4);
7025 int rm
= extract32(insn
, 16, 5);
7026 int rn
= extract32(insn
, 5, 5);
7027 int rd
= extract32(insn
, 0, 5);
7030 unallocated_encoding(s
);
7035 case 0x9: /* SQDMLAL, SQDMLAL2 */
7036 case 0xb: /* SQDMLSL, SQDMLSL2 */
7037 case 0xd: /* SQDMULL, SQDMULL2 */
7038 if (size
== 0 || size
== 3) {
7039 unallocated_encoding(s
);
7044 unallocated_encoding(s
);
7048 if (!fp_access_check(s
)) {
7053 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7054 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7055 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7057 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7058 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7060 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7061 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7064 case 0xd: /* SQDMULL, SQDMULL2 */
7066 case 0xb: /* SQDMLSL, SQDMLSL2 */
7067 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7069 case 0x9: /* SQDMLAL, SQDMLAL2 */
7070 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7071 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7075 g_assert_not_reached();
7078 write_fp_dreg(s
, rd
, tcg_res
);
7080 tcg_temp_free_i64(tcg_op1
);
7081 tcg_temp_free_i64(tcg_op2
);
7082 tcg_temp_free_i64(tcg_res
);
7084 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7085 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7086 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7088 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7089 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7091 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7092 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7095 case 0xd: /* SQDMULL, SQDMULL2 */
7097 case 0xb: /* SQDMLSL, SQDMLSL2 */
7098 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7100 case 0x9: /* SQDMLAL, SQDMLAL2 */
7102 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7103 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7104 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7106 tcg_temp_free_i64(tcg_op3
);
7110 g_assert_not_reached();
7113 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7114 write_fp_dreg(s
, rd
, tcg_res
);
7116 tcg_temp_free_i32(tcg_op1
);
7117 tcg_temp_free_i32(tcg_op2
);
7118 tcg_temp_free_i64(tcg_res
);
7122 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7123 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7125 /* Handle 64x64->64 opcodes which are shared between the scalar
7126 * and vector 3-same groups. We cover every opcode where size == 3
7127 * is valid in either the three-reg-same (integer, not pairwise)
7128 * or scalar-three-reg-same groups. (Some opcodes are not yet
7134 case 0x1: /* SQADD */
7136 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7138 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7141 case 0x5: /* SQSUB */
7143 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7145 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7148 case 0x6: /* CMGT, CMHI */
7149 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7150 * We implement this using setcond (test) and then negating.
7152 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7154 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7155 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7157 case 0x7: /* CMGE, CMHS */
7158 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7160 case 0x11: /* CMTST, CMEQ */
7165 /* CMTST : test is "if (X & Y != 0)". */
7166 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7167 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7168 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7170 case 0x8: /* SSHL, USHL */
7172 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7174 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7177 case 0x9: /* SQSHL, UQSHL */
7179 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7181 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7184 case 0xa: /* SRSHL, URSHL */
7186 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7188 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7191 case 0xb: /* SQRSHL, UQRSHL */
7193 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7195 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7198 case 0x10: /* ADD, SUB */
7200 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7202 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7206 g_assert_not_reached();
7210 /* Handle the 3-same-operands float operations; shared by the scalar
7211 * and vector encodings. The caller must filter out any encodings
7212 * not allocated for the encoding it is dealing with.
7214 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7215 int fpopcode
, int rd
, int rn
, int rm
)
7218 TCGv_ptr fpst
= get_fpstatus_ptr();
7220 for (pass
= 0; pass
< elements
; pass
++) {
7223 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7224 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7225 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7227 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7228 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7231 case 0x39: /* FMLS */
7232 /* As usual for ARM, separate negation for fused multiply-add */
7233 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7235 case 0x19: /* FMLA */
7236 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7237 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7240 case 0x18: /* FMAXNM */
7241 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7243 case 0x1a: /* FADD */
7244 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7246 case 0x1b: /* FMULX */
7247 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7249 case 0x1c: /* FCMEQ */
7250 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7252 case 0x1e: /* FMAX */
7253 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7255 case 0x1f: /* FRECPS */
7256 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7258 case 0x38: /* FMINNM */
7259 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7261 case 0x3a: /* FSUB */
7262 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7264 case 0x3e: /* FMIN */
7265 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7267 case 0x3f: /* FRSQRTS */
7268 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7270 case 0x5b: /* FMUL */
7271 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7273 case 0x5c: /* FCMGE */
7274 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7276 case 0x5d: /* FACGE */
7277 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7279 case 0x5f: /* FDIV */
7280 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7282 case 0x7a: /* FABD */
7283 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7284 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7286 case 0x7c: /* FCMGT */
7287 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7289 case 0x7d: /* FACGT */
7290 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7293 g_assert_not_reached();
7296 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7298 tcg_temp_free_i64(tcg_res
);
7299 tcg_temp_free_i64(tcg_op1
);
7300 tcg_temp_free_i64(tcg_op2
);
7303 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7304 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7305 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7307 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7308 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7311 case 0x39: /* FMLS */
7312 /* As usual for ARM, separate negation for fused multiply-add */
7313 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7315 case 0x19: /* FMLA */
7316 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7317 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7320 case 0x1a: /* FADD */
7321 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7323 case 0x1b: /* FMULX */
7324 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7326 case 0x1c: /* FCMEQ */
7327 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7329 case 0x1e: /* FMAX */
7330 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7332 case 0x1f: /* FRECPS */
7333 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7335 case 0x18: /* FMAXNM */
7336 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7338 case 0x38: /* FMINNM */
7339 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7341 case 0x3a: /* FSUB */
7342 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7344 case 0x3e: /* FMIN */
7345 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7347 case 0x3f: /* FRSQRTS */
7348 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7350 case 0x5b: /* FMUL */
7351 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7353 case 0x5c: /* FCMGE */
7354 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7356 case 0x5d: /* FACGE */
7357 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7359 case 0x5f: /* FDIV */
7360 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7362 case 0x7a: /* FABD */
7363 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7364 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7366 case 0x7c: /* FCMGT */
7367 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7369 case 0x7d: /* FACGT */
7370 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7373 g_assert_not_reached();
7376 if (elements
== 1) {
7377 /* scalar single so clear high part */
7378 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7380 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7381 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7382 tcg_temp_free_i64(tcg_tmp
);
7384 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7387 tcg_temp_free_i32(tcg_res
);
7388 tcg_temp_free_i32(tcg_op1
);
7389 tcg_temp_free_i32(tcg_op2
);
7393 tcg_temp_free_ptr(fpst
);
7395 if ((elements
<< size
) < 4) {
7396 /* scalar, or non-quad vector op */
7397 clear_vec_high(s
, rd
);
7401 /* C3.6.11 AdvSIMD scalar three same
7402 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7403 * +-----+---+-----------+------+---+------+--------+---+------+------+
7404 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7405 * +-----+---+-----------+------+---+------+--------+---+------+------+
7407 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7409 int rd
= extract32(insn
, 0, 5);
7410 int rn
= extract32(insn
, 5, 5);
7411 int opcode
= extract32(insn
, 11, 5);
7412 int rm
= extract32(insn
, 16, 5);
7413 int size
= extract32(insn
, 22, 2);
7414 bool u
= extract32(insn
, 29, 1);
7417 if (opcode
>= 0x18) {
7418 /* Floating point: U, size[1] and opcode indicate operation */
7419 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7421 case 0x1b: /* FMULX */
7422 case 0x1f: /* FRECPS */
7423 case 0x3f: /* FRSQRTS */
7424 case 0x5d: /* FACGE */
7425 case 0x7d: /* FACGT */
7426 case 0x1c: /* FCMEQ */
7427 case 0x5c: /* FCMGE */
7428 case 0x7c: /* FCMGT */
7429 case 0x7a: /* FABD */
7432 unallocated_encoding(s
);
7436 if (!fp_access_check(s
)) {
7440 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7445 case 0x1: /* SQADD, UQADD */
7446 case 0x5: /* SQSUB, UQSUB */
7447 case 0x9: /* SQSHL, UQSHL */
7448 case 0xb: /* SQRSHL, UQRSHL */
7450 case 0x8: /* SSHL, USHL */
7451 case 0xa: /* SRSHL, URSHL */
7452 case 0x6: /* CMGT, CMHI */
7453 case 0x7: /* CMGE, CMHS */
7454 case 0x11: /* CMTST, CMEQ */
7455 case 0x10: /* ADD, SUB (vector) */
7457 unallocated_encoding(s
);
7461 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7462 if (size
!= 1 && size
!= 2) {
7463 unallocated_encoding(s
);
7468 unallocated_encoding(s
);
7472 if (!fp_access_check(s
)) {
7476 tcg_rd
= tcg_temp_new_i64();
7479 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7480 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7482 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7483 tcg_temp_free_i64(tcg_rn
);
7484 tcg_temp_free_i64(tcg_rm
);
7486 /* Do a single operation on the lowest element in the vector.
7487 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7488 * no side effects for all these operations.
7489 * OPTME: special-purpose helpers would avoid doing some
7490 * unnecessary work in the helper for the 8 and 16 bit cases.
7492 NeonGenTwoOpEnvFn
*genenvfn
;
7493 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7494 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7495 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7497 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7498 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7501 case 0x1: /* SQADD, UQADD */
7503 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7504 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7505 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7506 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7508 genenvfn
= fns
[size
][u
];
7511 case 0x5: /* SQSUB, UQSUB */
7513 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7514 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7515 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7516 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7518 genenvfn
= fns
[size
][u
];
7521 case 0x9: /* SQSHL, UQSHL */
7523 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7524 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7525 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7526 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7528 genenvfn
= fns
[size
][u
];
7531 case 0xb: /* SQRSHL, UQRSHL */
7533 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7534 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7535 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7536 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7538 genenvfn
= fns
[size
][u
];
7541 case 0x16: /* SQDMULH, SQRDMULH */
7543 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7544 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7545 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7547 assert(size
== 1 || size
== 2);
7548 genenvfn
= fns
[size
- 1][u
];
7552 g_assert_not_reached();
7555 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7556 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7557 tcg_temp_free_i32(tcg_rd32
);
7558 tcg_temp_free_i32(tcg_rn
);
7559 tcg_temp_free_i32(tcg_rm
);
7562 write_fp_dreg(s
, rd
, tcg_rd
);
7564 tcg_temp_free_i64(tcg_rd
);
7567 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7568 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7569 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7571 /* Handle 64->64 opcodes which are shared between the scalar and
7572 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7573 * is valid in either group and also the double-precision fp ops.
7574 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7580 case 0x4: /* CLS, CLZ */
7582 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7584 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7588 /* This opcode is shared with CNT and RBIT but we have earlier
7589 * enforced that size == 3 if and only if this is the NOT insn.
7591 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7593 case 0x7: /* SQABS, SQNEG */
7595 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7597 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7600 case 0xa: /* CMLT */
7601 /* 64 bit integer comparison against zero, result is
7602 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7607 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7608 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7610 case 0x8: /* CMGT, CMGE */
7611 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7613 case 0x9: /* CMEQ, CMLE */
7614 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7616 case 0xb: /* ABS, NEG */
7618 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7620 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7621 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7622 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7624 tcg_temp_free_i64(tcg_zero
);
7627 case 0x2f: /* FABS */
7628 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7630 case 0x6f: /* FNEG */
7631 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7633 case 0x7f: /* FSQRT */
7634 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7636 case 0x1a: /* FCVTNS */
7637 case 0x1b: /* FCVTMS */
7638 case 0x1c: /* FCVTAS */
7639 case 0x3a: /* FCVTPS */
7640 case 0x3b: /* FCVTZS */
7642 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7643 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7644 tcg_temp_free_i32(tcg_shift
);
7647 case 0x5a: /* FCVTNU */
7648 case 0x5b: /* FCVTMU */
7649 case 0x5c: /* FCVTAU */
7650 case 0x7a: /* FCVTPU */
7651 case 0x7b: /* FCVTZU */
7653 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7654 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7655 tcg_temp_free_i32(tcg_shift
);
7658 case 0x18: /* FRINTN */
7659 case 0x19: /* FRINTM */
7660 case 0x38: /* FRINTP */
7661 case 0x39: /* FRINTZ */
7662 case 0x58: /* FRINTA */
7663 case 0x79: /* FRINTI */
7664 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7666 case 0x59: /* FRINTX */
7667 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7670 g_assert_not_reached();
7674 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7675 bool is_scalar
, bool is_u
, bool is_q
,
7676 int size
, int rn
, int rd
)
7678 bool is_double
= (size
== 3);
7681 if (!fp_access_check(s
)) {
7685 fpst
= get_fpstatus_ptr();
7688 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7689 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7690 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7691 NeonGenTwoDoubleOPFn
*genfn
;
7696 case 0x2e: /* FCMLT (zero) */
7699 case 0x2c: /* FCMGT (zero) */
7700 genfn
= gen_helper_neon_cgt_f64
;
7702 case 0x2d: /* FCMEQ (zero) */
7703 genfn
= gen_helper_neon_ceq_f64
;
7705 case 0x6d: /* FCMLE (zero) */
7708 case 0x6c: /* FCMGE (zero) */
7709 genfn
= gen_helper_neon_cge_f64
;
7712 g_assert_not_reached();
7715 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7716 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7718 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7720 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7722 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7725 clear_vec_high(s
, rd
);
7728 tcg_temp_free_i64(tcg_res
);
7729 tcg_temp_free_i64(tcg_zero
);
7730 tcg_temp_free_i64(tcg_op
);
7732 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7733 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7734 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7735 NeonGenTwoSingleOPFn
*genfn
;
7737 int pass
, maxpasses
;
7740 case 0x2e: /* FCMLT (zero) */
7743 case 0x2c: /* FCMGT (zero) */
7744 genfn
= gen_helper_neon_cgt_f32
;
7746 case 0x2d: /* FCMEQ (zero) */
7747 genfn
= gen_helper_neon_ceq_f32
;
7749 case 0x6d: /* FCMLE (zero) */
7752 case 0x6c: /* FCMGE (zero) */
7753 genfn
= gen_helper_neon_cge_f32
;
7756 g_assert_not_reached();
7762 maxpasses
= is_q
? 4 : 2;
7765 for (pass
= 0; pass
< maxpasses
; pass
++) {
7766 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7768 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7770 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7773 write_fp_sreg(s
, rd
, tcg_res
);
7775 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7778 tcg_temp_free_i32(tcg_res
);
7779 tcg_temp_free_i32(tcg_zero
);
7780 tcg_temp_free_i32(tcg_op
);
7781 if (!is_q
&& !is_scalar
) {
7782 clear_vec_high(s
, rd
);
7786 tcg_temp_free_ptr(fpst
);
7789 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7790 bool is_scalar
, bool is_u
, bool is_q
,
7791 int size
, int rn
, int rd
)
7793 bool is_double
= (size
== 3);
7794 TCGv_ptr fpst
= get_fpstatus_ptr();
7797 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7798 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7801 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7802 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7804 case 0x3d: /* FRECPE */
7805 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7807 case 0x3f: /* FRECPX */
7808 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7810 case 0x7d: /* FRSQRTE */
7811 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7814 g_assert_not_reached();
7816 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7819 clear_vec_high(s
, rd
);
7822 tcg_temp_free_i64(tcg_res
);
7823 tcg_temp_free_i64(tcg_op
);
7825 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7826 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7827 int pass
, maxpasses
;
7832 maxpasses
= is_q
? 4 : 2;
7835 for (pass
= 0; pass
< maxpasses
; pass
++) {
7836 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7839 case 0x3c: /* URECPE */
7840 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7842 case 0x3d: /* FRECPE */
7843 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7845 case 0x3f: /* FRECPX */
7846 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7848 case 0x7d: /* FRSQRTE */
7849 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7852 g_assert_not_reached();
7856 write_fp_sreg(s
, rd
, tcg_res
);
7858 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7861 tcg_temp_free_i32(tcg_res
);
7862 tcg_temp_free_i32(tcg_op
);
7863 if (!is_q
&& !is_scalar
) {
7864 clear_vec_high(s
, rd
);
7867 tcg_temp_free_ptr(fpst
);
7870 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7871 int opcode
, bool u
, bool is_q
,
7872 int size
, int rn
, int rd
)
7874 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7875 * in the source becomes a size element in the destination).
7878 TCGv_i32 tcg_res
[2];
7879 int destelt
= is_q
? 2 : 0;
7880 int passes
= scalar
? 1 : 2;
7883 tcg_res
[1] = tcg_const_i32(0);
7886 for (pass
= 0; pass
< passes
; pass
++) {
7887 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7888 NeonGenNarrowFn
*genfn
= NULL
;
7889 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7892 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7894 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7896 tcg_res
[pass
] = tcg_temp_new_i32();
7899 case 0x12: /* XTN, SQXTUN */
7901 static NeonGenNarrowFn
* const xtnfns
[3] = {
7902 gen_helper_neon_narrow_u8
,
7903 gen_helper_neon_narrow_u16
,
7904 tcg_gen_extrl_i64_i32
,
7906 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7907 gen_helper_neon_unarrow_sat8
,
7908 gen_helper_neon_unarrow_sat16
,
7909 gen_helper_neon_unarrow_sat32
,
7912 genenvfn
= sqxtunfns
[size
];
7914 genfn
= xtnfns
[size
];
7918 case 0x14: /* SQXTN, UQXTN */
7920 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7921 { gen_helper_neon_narrow_sat_s8
,
7922 gen_helper_neon_narrow_sat_u8
},
7923 { gen_helper_neon_narrow_sat_s16
,
7924 gen_helper_neon_narrow_sat_u16
},
7925 { gen_helper_neon_narrow_sat_s32
,
7926 gen_helper_neon_narrow_sat_u32
},
7928 genenvfn
= fns
[size
][u
];
7931 case 0x16: /* FCVTN, FCVTN2 */
7932 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7934 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7936 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7937 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7938 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7939 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7940 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7941 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7942 tcg_temp_free_i32(tcg_lo
);
7943 tcg_temp_free_i32(tcg_hi
);
7946 case 0x56: /* FCVTXN, FCVTXN2 */
7947 /* 64 bit to 32 bit float conversion
7948 * with von Neumann rounding (round to odd)
7951 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7954 g_assert_not_reached();
7958 genfn(tcg_res
[pass
], tcg_op
);
7959 } else if (genenvfn
) {
7960 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7963 tcg_temp_free_i64(tcg_op
);
7966 for (pass
= 0; pass
< 2; pass
++) {
7967 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7968 tcg_temp_free_i32(tcg_res
[pass
]);
7971 clear_vec_high(s
, rd
);
7975 /* Remaining saturating accumulating ops */
7976 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7977 bool is_q
, int size
, int rn
, int rd
)
7979 bool is_double
= (size
== 3);
7982 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7983 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7986 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7987 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7988 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7990 if (is_u
) { /* USQADD */
7991 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7992 } else { /* SUQADD */
7993 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7995 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7998 clear_vec_high(s
, rd
);
8001 tcg_temp_free_i64(tcg_rd
);
8002 tcg_temp_free_i64(tcg_rn
);
8004 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8005 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8006 int pass
, maxpasses
;
8011 maxpasses
= is_q
? 4 : 2;
8014 for (pass
= 0; pass
< maxpasses
; pass
++) {
8016 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8017 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8019 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8020 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8023 if (is_u
) { /* USQADD */
8026 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8029 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8032 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8035 g_assert_not_reached();
8037 } else { /* SUQADD */
8040 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8043 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8046 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8049 g_assert_not_reached();
8054 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8055 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8056 tcg_temp_free_i64(tcg_zero
);
8058 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8062 clear_vec_high(s
, rd
);
8065 tcg_temp_free_i32(tcg_rd
);
8066 tcg_temp_free_i32(tcg_rn
);
8070 /* C3.6.12 AdvSIMD scalar two reg misc
8071 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8072 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8073 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8074 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8076 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8078 int rd
= extract32(insn
, 0, 5);
8079 int rn
= extract32(insn
, 5, 5);
8080 int opcode
= extract32(insn
, 12, 5);
8081 int size
= extract32(insn
, 22, 2);
8082 bool u
= extract32(insn
, 29, 1);
8083 bool is_fcvt
= false;
8086 TCGv_ptr tcg_fpstatus
;
8089 case 0x3: /* USQADD / SUQADD*/
8090 if (!fp_access_check(s
)) {
8093 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8095 case 0x7: /* SQABS / SQNEG */
8097 case 0xa: /* CMLT */
8099 unallocated_encoding(s
);
8103 case 0x8: /* CMGT, CMGE */
8104 case 0x9: /* CMEQ, CMLE */
8105 case 0xb: /* ABS, NEG */
8107 unallocated_encoding(s
);
8111 case 0x12: /* SQXTUN */
8113 unallocated_encoding(s
);
8117 case 0x14: /* SQXTN, UQXTN */
8119 unallocated_encoding(s
);
8122 if (!fp_access_check(s
)) {
8125 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8130 /* Floating point: U, size[1] and opcode indicate operation;
8131 * size[0] indicates single or double precision.
8133 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8134 size
= extract32(size
, 0, 1) ? 3 : 2;
8136 case 0x2c: /* FCMGT (zero) */
8137 case 0x2d: /* FCMEQ (zero) */
8138 case 0x2e: /* FCMLT (zero) */
8139 case 0x6c: /* FCMGE (zero) */
8140 case 0x6d: /* FCMLE (zero) */
8141 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8143 case 0x1d: /* SCVTF */
8144 case 0x5d: /* UCVTF */
8146 bool is_signed
= (opcode
== 0x1d);
8147 if (!fp_access_check(s
)) {
8150 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8153 case 0x3d: /* FRECPE */
8154 case 0x3f: /* FRECPX */
8155 case 0x7d: /* FRSQRTE */
8156 if (!fp_access_check(s
)) {
8159 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8161 case 0x1a: /* FCVTNS */
8162 case 0x1b: /* FCVTMS */
8163 case 0x3a: /* FCVTPS */
8164 case 0x3b: /* FCVTZS */
8165 case 0x5a: /* FCVTNU */
8166 case 0x5b: /* FCVTMU */
8167 case 0x7a: /* FCVTPU */
8168 case 0x7b: /* FCVTZU */
8170 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8172 case 0x1c: /* FCVTAS */
8173 case 0x5c: /* FCVTAU */
8174 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8176 rmode
= FPROUNDING_TIEAWAY
;
8178 case 0x56: /* FCVTXN, FCVTXN2 */
8180 unallocated_encoding(s
);
8183 if (!fp_access_check(s
)) {
8186 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8189 unallocated_encoding(s
);
8194 unallocated_encoding(s
);
8198 if (!fp_access_check(s
)) {
8203 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8204 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8205 tcg_fpstatus
= get_fpstatus_ptr();
8207 TCGV_UNUSED_I32(tcg_rmode
);
8208 TCGV_UNUSED_PTR(tcg_fpstatus
);
8212 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8213 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8215 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8216 write_fp_dreg(s
, rd
, tcg_rd
);
8217 tcg_temp_free_i64(tcg_rd
);
8218 tcg_temp_free_i64(tcg_rn
);
8220 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8221 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8223 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8226 case 0x7: /* SQABS, SQNEG */
8228 NeonGenOneOpEnvFn
*genfn
;
8229 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8230 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8231 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8232 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8234 genfn
= fns
[size
][u
];
8235 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8238 case 0x1a: /* FCVTNS */
8239 case 0x1b: /* FCVTMS */
8240 case 0x1c: /* FCVTAS */
8241 case 0x3a: /* FCVTPS */
8242 case 0x3b: /* FCVTZS */
8244 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8245 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8246 tcg_temp_free_i32(tcg_shift
);
8249 case 0x5a: /* FCVTNU */
8250 case 0x5b: /* FCVTMU */
8251 case 0x5c: /* FCVTAU */
8252 case 0x7a: /* FCVTPU */
8253 case 0x7b: /* FCVTZU */
8255 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8256 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8257 tcg_temp_free_i32(tcg_shift
);
8261 g_assert_not_reached();
8264 write_fp_sreg(s
, rd
, tcg_rd
);
8265 tcg_temp_free_i32(tcg_rd
);
8266 tcg_temp_free_i32(tcg_rn
);
8270 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8271 tcg_temp_free_i32(tcg_rmode
);
8272 tcg_temp_free_ptr(tcg_fpstatus
);
8276 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8277 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8278 int immh
, int immb
, int opcode
, int rn
, int rd
)
8280 int size
= 32 - clz32(immh
) - 1;
8281 int immhb
= immh
<< 3 | immb
;
8282 int shift
= 2 * (8 << size
) - immhb
;
8283 bool accumulate
= false;
8285 bool insert
= false;
8286 int dsize
= is_q
? 128 : 64;
8287 int esize
= 8 << size
;
8288 int elements
= dsize
/esize
;
8289 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8290 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8291 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8295 if (extract32(immh
, 3, 1) && !is_q
) {
8296 unallocated_encoding(s
);
8300 if (size
> 3 && !is_q
) {
8301 unallocated_encoding(s
);
8305 if (!fp_access_check(s
)) {
8310 case 0x02: /* SSRA / USRA (accumulate) */
8313 case 0x04: /* SRSHR / URSHR (rounding) */
8316 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8317 accumulate
= round
= true;
8319 case 0x08: /* SRI */
8325 uint64_t round_const
= 1ULL << (shift
- 1);
8326 tcg_round
= tcg_const_i64(round_const
);
8328 TCGV_UNUSED_I64(tcg_round
);
8331 for (i
= 0; i
< elements
; i
++) {
8332 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8333 if (accumulate
|| insert
) {
8334 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8338 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8340 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8341 accumulate
, is_u
, size
, shift
);
8344 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8348 clear_vec_high(s
, rd
);
8352 tcg_temp_free_i64(tcg_round
);
8356 /* SHL/SLI - Vector shift left */
8357 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8358 int immh
, int immb
, int opcode
, int rn
, int rd
)
8360 int size
= 32 - clz32(immh
) - 1;
8361 int immhb
= immh
<< 3 | immb
;
8362 int shift
= immhb
- (8 << size
);
8363 int dsize
= is_q
? 128 : 64;
8364 int esize
= 8 << size
;
8365 int elements
= dsize
/esize
;
8366 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8367 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8370 if (extract32(immh
, 3, 1) && !is_q
) {
8371 unallocated_encoding(s
);
8375 if (size
> 3 && !is_q
) {
8376 unallocated_encoding(s
);
8380 if (!fp_access_check(s
)) {
8384 for (i
= 0; i
< elements
; i
++) {
8385 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8387 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8390 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8392 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8396 clear_vec_high(s
, rd
);
8400 /* USHLL/SHLL - Vector shift left with widening */
8401 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8402 int immh
, int immb
, int opcode
, int rn
, int rd
)
8404 int size
= 32 - clz32(immh
) - 1;
8405 int immhb
= immh
<< 3 | immb
;
8406 int shift
= immhb
- (8 << size
);
8408 int esize
= 8 << size
;
8409 int elements
= dsize
/esize
;
8410 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8411 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8415 unallocated_encoding(s
);
8419 if (!fp_access_check(s
)) {
8423 /* For the LL variants the store is larger than the load,
8424 * so if rd == rn we would overwrite parts of our input.
8425 * So load everything right now and use shifts in the main loop.
8427 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8429 for (i
= 0; i
< elements
; i
++) {
8430 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8431 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8432 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8433 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8437 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8438 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8439 int immh
, int immb
, int opcode
, int rn
, int rd
)
8441 int immhb
= immh
<< 3 | immb
;
8442 int size
= 32 - clz32(immh
) - 1;
8444 int esize
= 8 << size
;
8445 int elements
= dsize
/esize
;
8446 int shift
= (2 * esize
) - immhb
;
8447 bool round
= extract32(opcode
, 0, 1);
8448 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8452 if (extract32(immh
, 3, 1)) {
8453 unallocated_encoding(s
);
8457 if (!fp_access_check(s
)) {
8461 tcg_rn
= tcg_temp_new_i64();
8462 tcg_rd
= tcg_temp_new_i64();
8463 tcg_final
= tcg_temp_new_i64();
8464 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8467 uint64_t round_const
= 1ULL << (shift
- 1);
8468 tcg_round
= tcg_const_i64(round_const
);
8470 TCGV_UNUSED_I64(tcg_round
);
8473 for (i
= 0; i
< elements
; i
++) {
8474 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8475 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8476 false, true, size
+1, shift
);
8478 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8482 clear_vec_high(s
, rd
);
8483 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8485 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8489 tcg_temp_free_i64(tcg_round
);
8491 tcg_temp_free_i64(tcg_rn
);
8492 tcg_temp_free_i64(tcg_rd
);
8493 tcg_temp_free_i64(tcg_final
);
8498 /* C3.6.14 AdvSIMD shift by immediate
8499 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8500 * +---+---+---+-------------+------+------+--------+---+------+------+
8501 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8502 * +---+---+---+-------------+------+------+--------+---+------+------+
8504 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8506 int rd
= extract32(insn
, 0, 5);
8507 int rn
= extract32(insn
, 5, 5);
8508 int opcode
= extract32(insn
, 11, 5);
8509 int immb
= extract32(insn
, 16, 3);
8510 int immh
= extract32(insn
, 19, 4);
8511 bool is_u
= extract32(insn
, 29, 1);
8512 bool is_q
= extract32(insn
, 30, 1);
8515 case 0x08: /* SRI */
8517 unallocated_encoding(s
);
8521 case 0x00: /* SSHR / USHR */
8522 case 0x02: /* SSRA / USRA (accumulate) */
8523 case 0x04: /* SRSHR / URSHR (rounding) */
8524 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8525 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8527 case 0x0a: /* SHL / SLI */
8528 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8530 case 0x10: /* SHRN */
8531 case 0x11: /* RSHRN / SQRSHRUN */
8533 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8536 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8539 case 0x12: /* SQSHRN / UQSHRN */
8540 case 0x13: /* SQRSHRN / UQRSHRN */
8541 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8544 case 0x14: /* SSHLL / USHLL */
8545 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8547 case 0x1c: /* SCVTF / UCVTF */
8548 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8551 case 0xc: /* SQSHLU */
8553 unallocated_encoding(s
);
8556 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8558 case 0xe: /* SQSHL, UQSHL */
8559 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8561 case 0x1f: /* FCVTZS/ FCVTZU */
8562 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8565 unallocated_encoding(s
);
8570 /* Generate code to do a "long" addition or subtraction, ie one done in
8571 * TCGv_i64 on vector lanes twice the width specified by size.
8573 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8574 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8576 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8577 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8578 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8579 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8581 NeonGenTwo64OpFn
*genfn
;
8584 genfn
= fns
[size
][is_sub
];
8585 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8588 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8589 int opcode
, int rd
, int rn
, int rm
)
8591 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8592 TCGv_i64 tcg_res
[2];
8595 tcg_res
[0] = tcg_temp_new_i64();
8596 tcg_res
[1] = tcg_temp_new_i64();
8598 /* Does this op do an adding accumulate, a subtracting accumulate,
8599 * or no accumulate at all?
8617 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8618 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8621 /* size == 2 means two 32x32->64 operations; this is worth special
8622 * casing because we can generally handle it inline.
8625 for (pass
= 0; pass
< 2; pass
++) {
8626 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8627 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8628 TCGv_i64 tcg_passres
;
8629 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8631 int elt
= pass
+ is_q
* 2;
8633 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8634 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8637 tcg_passres
= tcg_res
[pass
];
8639 tcg_passres
= tcg_temp_new_i64();
8643 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8644 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8646 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8647 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8649 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8650 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8652 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8653 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8655 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8656 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8657 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8659 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8660 tcg_temp_free_i64(tcg_tmp1
);
8661 tcg_temp_free_i64(tcg_tmp2
);
8664 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8665 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8666 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8667 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8669 case 9: /* SQDMLAL, SQDMLAL2 */
8670 case 11: /* SQDMLSL, SQDMLSL2 */
8671 case 13: /* SQDMULL, SQDMULL2 */
8672 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8673 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8674 tcg_passres
, tcg_passres
);
8677 g_assert_not_reached();
8680 if (opcode
== 9 || opcode
== 11) {
8681 /* saturating accumulate ops */
8683 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8685 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8686 tcg_res
[pass
], tcg_passres
);
8687 } else if (accop
> 0) {
8688 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8689 } else if (accop
< 0) {
8690 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8694 tcg_temp_free_i64(tcg_passres
);
8697 tcg_temp_free_i64(tcg_op1
);
8698 tcg_temp_free_i64(tcg_op2
);
8701 /* size 0 or 1, generally helper functions */
8702 for (pass
= 0; pass
< 2; pass
++) {
8703 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8704 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8705 TCGv_i64 tcg_passres
;
8706 int elt
= pass
+ is_q
* 2;
8708 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8709 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8712 tcg_passres
= tcg_res
[pass
];
8714 tcg_passres
= tcg_temp_new_i64();
8718 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8719 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8721 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8722 static NeonGenWidenFn
* const widenfns
[2][2] = {
8723 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8724 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8726 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8728 widenfn(tcg_op2_64
, tcg_op2
);
8729 widenfn(tcg_passres
, tcg_op1
);
8730 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8731 tcg_passres
, tcg_op2_64
);
8732 tcg_temp_free_i64(tcg_op2_64
);
8735 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8736 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8739 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8741 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8745 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8747 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8751 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8752 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8753 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8756 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8758 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8762 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8764 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8768 case 9: /* SQDMLAL, SQDMLAL2 */
8769 case 11: /* SQDMLSL, SQDMLSL2 */
8770 case 13: /* SQDMULL, SQDMULL2 */
8772 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8773 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8774 tcg_passres
, tcg_passres
);
8776 case 14: /* PMULL */
8778 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8781 g_assert_not_reached();
8783 tcg_temp_free_i32(tcg_op1
);
8784 tcg_temp_free_i32(tcg_op2
);
8787 if (opcode
== 9 || opcode
== 11) {
8788 /* saturating accumulate ops */
8790 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8792 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8796 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8797 tcg_res
[pass
], tcg_passres
);
8799 tcg_temp_free_i64(tcg_passres
);
8804 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8805 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8806 tcg_temp_free_i64(tcg_res
[0]);
8807 tcg_temp_free_i64(tcg_res
[1]);
8810 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8811 int opcode
, int rd
, int rn
, int rm
)
8813 TCGv_i64 tcg_res
[2];
8814 int part
= is_q
? 2 : 0;
8817 for (pass
= 0; pass
< 2; pass
++) {
8818 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8819 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8820 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8821 static NeonGenWidenFn
* const widenfns
[3][2] = {
8822 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8823 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8824 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8826 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8828 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8829 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8830 widenfn(tcg_op2_wide
, tcg_op2
);
8831 tcg_temp_free_i32(tcg_op2
);
8832 tcg_res
[pass
] = tcg_temp_new_i64();
8833 gen_neon_addl(size
, (opcode
== 3),
8834 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8835 tcg_temp_free_i64(tcg_op1
);
8836 tcg_temp_free_i64(tcg_op2_wide
);
8839 for (pass
= 0; pass
< 2; pass
++) {
8840 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8841 tcg_temp_free_i64(tcg_res
[pass
]);
8845 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8847 tcg_gen_addi_i64(in
, in
, 1U << 31);
8848 tcg_gen_extrh_i64_i32(res
, in
);
8851 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8852 int opcode
, int rd
, int rn
, int rm
)
8854 TCGv_i32 tcg_res
[2];
8855 int part
= is_q
? 2 : 0;
8858 for (pass
= 0; pass
< 2; pass
++) {
8859 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8860 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8861 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8862 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8863 { gen_helper_neon_narrow_high_u8
,
8864 gen_helper_neon_narrow_round_high_u8
},
8865 { gen_helper_neon_narrow_high_u16
,
8866 gen_helper_neon_narrow_round_high_u16
},
8867 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8869 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8871 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8872 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8874 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8876 tcg_temp_free_i64(tcg_op1
);
8877 tcg_temp_free_i64(tcg_op2
);
8879 tcg_res
[pass
] = tcg_temp_new_i32();
8880 gennarrow(tcg_res
[pass
], tcg_wideres
);
8881 tcg_temp_free_i64(tcg_wideres
);
8884 for (pass
= 0; pass
< 2; pass
++) {
8885 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8886 tcg_temp_free_i32(tcg_res
[pass
]);
8889 clear_vec_high(s
, rd
);
8893 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8895 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8896 * is the only three-reg-diff instruction which produces a
8897 * 128-bit wide result from a single operation. However since
8898 * it's possible to calculate the two halves more or less
8899 * separately we just use two helper calls.
8901 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8902 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8903 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8905 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8906 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8907 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8908 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8909 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8910 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8912 tcg_temp_free_i64(tcg_op1
);
8913 tcg_temp_free_i64(tcg_op2
);
8914 tcg_temp_free_i64(tcg_res
);
8917 /* C3.6.15 AdvSIMD three different
8918 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8919 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8920 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8921 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8923 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8925 /* Instructions in this group fall into three basic classes
8926 * (in each case with the operation working on each element in
8927 * the input vectors):
8928 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8930 * (2) wide 64 x 128 -> 128
8931 * (3) narrowing 128 x 128 -> 64
8932 * Here we do initial decode, catch unallocated cases and
8933 * dispatch to separate functions for each class.
8935 int is_q
= extract32(insn
, 30, 1);
8936 int is_u
= extract32(insn
, 29, 1);
8937 int size
= extract32(insn
, 22, 2);
8938 int opcode
= extract32(insn
, 12, 4);
8939 int rm
= extract32(insn
, 16, 5);
8940 int rn
= extract32(insn
, 5, 5);
8941 int rd
= extract32(insn
, 0, 5);
8944 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8945 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8946 /* 64 x 128 -> 128 */
8948 unallocated_encoding(s
);
8951 if (!fp_access_check(s
)) {
8954 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8956 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8957 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8958 /* 128 x 128 -> 64 */
8960 unallocated_encoding(s
);
8963 if (!fp_access_check(s
)) {
8966 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8968 case 14: /* PMULL, PMULL2 */
8969 if (is_u
|| size
== 1 || size
== 2) {
8970 unallocated_encoding(s
);
8974 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8975 unallocated_encoding(s
);
8978 if (!fp_access_check(s
)) {
8981 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8985 case 9: /* SQDMLAL, SQDMLAL2 */
8986 case 11: /* SQDMLSL, SQDMLSL2 */
8987 case 13: /* SQDMULL, SQDMULL2 */
8988 if (is_u
|| size
== 0) {
8989 unallocated_encoding(s
);
8993 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8994 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8995 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8996 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8997 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8998 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8999 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9000 /* 64 x 64 -> 128 */
9002 unallocated_encoding(s
);
9006 if (!fp_access_check(s
)) {
9010 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9013 /* opcode 15 not allocated */
9014 unallocated_encoding(s
);
9019 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9020 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9022 int rd
= extract32(insn
, 0, 5);
9023 int rn
= extract32(insn
, 5, 5);
9024 int rm
= extract32(insn
, 16, 5);
9025 int size
= extract32(insn
, 22, 2);
9026 bool is_u
= extract32(insn
, 29, 1);
9027 bool is_q
= extract32(insn
, 30, 1);
9028 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9031 if (!fp_access_check(s
)) {
9035 tcg_op1
= tcg_temp_new_i64();
9036 tcg_op2
= tcg_temp_new_i64();
9037 tcg_res
[0] = tcg_temp_new_i64();
9038 tcg_res
[1] = tcg_temp_new_i64();
9040 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9041 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9042 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9047 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9050 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9053 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9056 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9061 /* B* ops need res loaded to operate on */
9062 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9067 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9069 case 1: /* BSL bitwise select */
9070 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9071 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9072 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9074 case 2: /* BIT, bitwise insert if true */
9075 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9076 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9077 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9079 case 3: /* BIF, bitwise insert if false */
9080 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9081 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9082 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9088 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9090 tcg_gen_movi_i64(tcg_res
[1], 0);
9092 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9094 tcg_temp_free_i64(tcg_op1
);
9095 tcg_temp_free_i64(tcg_op2
);
9096 tcg_temp_free_i64(tcg_res
[0]);
9097 tcg_temp_free_i64(tcg_res
[1]);
9100 /* Helper functions for 32 bit comparisons */
9101 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9103 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9106 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9108 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9111 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9113 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9116 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9118 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9121 /* Pairwise op subgroup of C3.6.16.
9123 * This is called directly or via the handle_3same_float for float pairwise
9124 * operations where the opcode and size are calculated differently.
9126 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9127 int size
, int rn
, int rm
, int rd
)
9132 /* Floating point operations need fpst */
9133 if (opcode
>= 0x58) {
9134 fpst
= get_fpstatus_ptr();
9136 TCGV_UNUSED_PTR(fpst
);
9139 if (!fp_access_check(s
)) {
9143 /* These operations work on the concatenated rm:rn, with each pair of
9144 * adjacent elements being operated on to produce an element in the result.
9147 TCGv_i64 tcg_res
[2];
9149 for (pass
= 0; pass
< 2; pass
++) {
9150 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9151 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9152 int passreg
= (pass
== 0) ? rn
: rm
;
9154 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9155 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9156 tcg_res
[pass
] = tcg_temp_new_i64();
9159 case 0x17: /* ADDP */
9160 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9162 case 0x58: /* FMAXNMP */
9163 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9165 case 0x5a: /* FADDP */
9166 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9168 case 0x5e: /* FMAXP */
9169 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9171 case 0x78: /* FMINNMP */
9172 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9174 case 0x7e: /* FMINP */
9175 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9178 g_assert_not_reached();
9181 tcg_temp_free_i64(tcg_op1
);
9182 tcg_temp_free_i64(tcg_op2
);
9185 for (pass
= 0; pass
< 2; pass
++) {
9186 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9187 tcg_temp_free_i64(tcg_res
[pass
]);
9190 int maxpass
= is_q
? 4 : 2;
9191 TCGv_i32 tcg_res
[4];
9193 for (pass
= 0; pass
< maxpass
; pass
++) {
9194 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9195 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9196 NeonGenTwoOpFn
*genfn
= NULL
;
9197 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9198 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9200 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9201 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9202 tcg_res
[pass
] = tcg_temp_new_i32();
9205 case 0x17: /* ADDP */
9207 static NeonGenTwoOpFn
* const fns
[3] = {
9208 gen_helper_neon_padd_u8
,
9209 gen_helper_neon_padd_u16
,
9215 case 0x14: /* SMAXP, UMAXP */
9217 static NeonGenTwoOpFn
* const fns
[3][2] = {
9218 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9219 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9220 { gen_max_s32
, gen_max_u32
},
9222 genfn
= fns
[size
][u
];
9225 case 0x15: /* SMINP, UMINP */
9227 static NeonGenTwoOpFn
* const fns
[3][2] = {
9228 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9229 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9230 { gen_min_s32
, gen_min_u32
},
9232 genfn
= fns
[size
][u
];
9235 /* The FP operations are all on single floats (32 bit) */
9236 case 0x58: /* FMAXNMP */
9237 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9239 case 0x5a: /* FADDP */
9240 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9242 case 0x5e: /* FMAXP */
9243 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9245 case 0x78: /* FMINNMP */
9246 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9248 case 0x7e: /* FMINP */
9249 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9252 g_assert_not_reached();
9255 /* FP ops called directly, otherwise call now */
9257 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9260 tcg_temp_free_i32(tcg_op1
);
9261 tcg_temp_free_i32(tcg_op2
);
9264 for (pass
= 0; pass
< maxpass
; pass
++) {
9265 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9266 tcg_temp_free_i32(tcg_res
[pass
]);
9269 clear_vec_high(s
, rd
);
9273 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9274 tcg_temp_free_ptr(fpst
);
9278 /* Floating point op subgroup of C3.6.16. */
9279 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9281 /* For floating point ops, the U, size[1] and opcode bits
9282 * together indicate the operation. size[0] indicates single
9285 int fpopcode
= extract32(insn
, 11, 5)
9286 | (extract32(insn
, 23, 1) << 5)
9287 | (extract32(insn
, 29, 1) << 6);
9288 int is_q
= extract32(insn
, 30, 1);
9289 int size
= extract32(insn
, 22, 1);
9290 int rm
= extract32(insn
, 16, 5);
9291 int rn
= extract32(insn
, 5, 5);
9292 int rd
= extract32(insn
, 0, 5);
9294 int datasize
= is_q
? 128 : 64;
9295 int esize
= 32 << size
;
9296 int elements
= datasize
/ esize
;
9298 if (size
== 1 && !is_q
) {
9299 unallocated_encoding(s
);
9304 case 0x58: /* FMAXNMP */
9305 case 0x5a: /* FADDP */
9306 case 0x5e: /* FMAXP */
9307 case 0x78: /* FMINNMP */
9308 case 0x7e: /* FMINP */
9309 if (size
&& !is_q
) {
9310 unallocated_encoding(s
);
9313 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9316 case 0x1b: /* FMULX */
9317 case 0x1f: /* FRECPS */
9318 case 0x3f: /* FRSQRTS */
9319 case 0x5d: /* FACGE */
9320 case 0x7d: /* FACGT */
9321 case 0x19: /* FMLA */
9322 case 0x39: /* FMLS */
9323 case 0x18: /* FMAXNM */
9324 case 0x1a: /* FADD */
9325 case 0x1c: /* FCMEQ */
9326 case 0x1e: /* FMAX */
9327 case 0x38: /* FMINNM */
9328 case 0x3a: /* FSUB */
9329 case 0x3e: /* FMIN */
9330 case 0x5b: /* FMUL */
9331 case 0x5c: /* FCMGE */
9332 case 0x5f: /* FDIV */
9333 case 0x7a: /* FABD */
9334 case 0x7c: /* FCMGT */
9335 if (!fp_access_check(s
)) {
9339 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9342 unallocated_encoding(s
);
9347 /* Integer op subgroup of C3.6.16. */
9348 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9350 int is_q
= extract32(insn
, 30, 1);
9351 int u
= extract32(insn
, 29, 1);
9352 int size
= extract32(insn
, 22, 2);
9353 int opcode
= extract32(insn
, 11, 5);
9354 int rm
= extract32(insn
, 16, 5);
9355 int rn
= extract32(insn
, 5, 5);
9356 int rd
= extract32(insn
, 0, 5);
9360 case 0x13: /* MUL, PMUL */
9361 if (u
&& size
!= 0) {
9362 unallocated_encoding(s
);
9366 case 0x0: /* SHADD, UHADD */
9367 case 0x2: /* SRHADD, URHADD */
9368 case 0x4: /* SHSUB, UHSUB */
9369 case 0xc: /* SMAX, UMAX */
9370 case 0xd: /* SMIN, UMIN */
9371 case 0xe: /* SABD, UABD */
9372 case 0xf: /* SABA, UABA */
9373 case 0x12: /* MLA, MLS */
9375 unallocated_encoding(s
);
9379 case 0x16: /* SQDMULH, SQRDMULH */
9380 if (size
== 0 || size
== 3) {
9381 unallocated_encoding(s
);
9386 if (size
== 3 && !is_q
) {
9387 unallocated_encoding(s
);
9393 if (!fp_access_check(s
)) {
9399 for (pass
= 0; pass
< 2; pass
++) {
9400 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9401 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9402 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9404 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9405 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9407 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9409 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9411 tcg_temp_free_i64(tcg_res
);
9412 tcg_temp_free_i64(tcg_op1
);
9413 tcg_temp_free_i64(tcg_op2
);
9416 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9417 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9418 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9419 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9420 NeonGenTwoOpFn
*genfn
= NULL
;
9421 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9423 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9424 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9427 case 0x0: /* SHADD, UHADD */
9429 static NeonGenTwoOpFn
* const fns
[3][2] = {
9430 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9431 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9432 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9434 genfn
= fns
[size
][u
];
9437 case 0x1: /* SQADD, UQADD */
9439 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9440 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9441 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9442 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9444 genenvfn
= fns
[size
][u
];
9447 case 0x2: /* SRHADD, URHADD */
9449 static NeonGenTwoOpFn
* const fns
[3][2] = {
9450 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9451 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9452 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9454 genfn
= fns
[size
][u
];
9457 case 0x4: /* SHSUB, UHSUB */
9459 static NeonGenTwoOpFn
* const fns
[3][2] = {
9460 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9461 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9462 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9464 genfn
= fns
[size
][u
];
9467 case 0x5: /* SQSUB, UQSUB */
9469 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9470 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9471 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9472 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9474 genenvfn
= fns
[size
][u
];
9477 case 0x6: /* CMGT, CMHI */
9479 static NeonGenTwoOpFn
* const fns
[3][2] = {
9480 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9481 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9482 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9484 genfn
= fns
[size
][u
];
9487 case 0x7: /* CMGE, CMHS */
9489 static NeonGenTwoOpFn
* const fns
[3][2] = {
9490 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9491 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9492 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9494 genfn
= fns
[size
][u
];
9497 case 0x8: /* SSHL, USHL */
9499 static NeonGenTwoOpFn
* const fns
[3][2] = {
9500 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9501 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9502 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9504 genfn
= fns
[size
][u
];
9507 case 0x9: /* SQSHL, UQSHL */
9509 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9510 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9511 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9512 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9514 genenvfn
= fns
[size
][u
];
9517 case 0xa: /* SRSHL, URSHL */
9519 static NeonGenTwoOpFn
* const fns
[3][2] = {
9520 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9521 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9522 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9524 genfn
= fns
[size
][u
];
9527 case 0xb: /* SQRSHL, UQRSHL */
9529 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9530 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9531 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9532 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9534 genenvfn
= fns
[size
][u
];
9537 case 0xc: /* SMAX, UMAX */
9539 static NeonGenTwoOpFn
* const fns
[3][2] = {
9540 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9541 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9542 { gen_max_s32
, gen_max_u32
},
9544 genfn
= fns
[size
][u
];
9548 case 0xd: /* SMIN, UMIN */
9550 static NeonGenTwoOpFn
* const fns
[3][2] = {
9551 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9552 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9553 { gen_min_s32
, gen_min_u32
},
9555 genfn
= fns
[size
][u
];
9558 case 0xe: /* SABD, UABD */
9559 case 0xf: /* SABA, UABA */
9561 static NeonGenTwoOpFn
* const fns
[3][2] = {
9562 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9563 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9564 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9566 genfn
= fns
[size
][u
];
9569 case 0x10: /* ADD, SUB */
9571 static NeonGenTwoOpFn
* const fns
[3][2] = {
9572 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9573 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9574 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9576 genfn
= fns
[size
][u
];
9579 case 0x11: /* CMTST, CMEQ */
9581 static NeonGenTwoOpFn
* const fns
[3][2] = {
9582 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9583 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9584 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9586 genfn
= fns
[size
][u
];
9589 case 0x13: /* MUL, PMUL */
9593 genfn
= gen_helper_neon_mul_p8
;
9596 /* fall through : MUL */
9597 case 0x12: /* MLA, MLS */
9599 static NeonGenTwoOpFn
* const fns
[3] = {
9600 gen_helper_neon_mul_u8
,
9601 gen_helper_neon_mul_u16
,
9607 case 0x16: /* SQDMULH, SQRDMULH */
9609 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9610 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9611 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9613 assert(size
== 1 || size
== 2);
9614 genenvfn
= fns
[size
- 1][u
];
9618 g_assert_not_reached();
9622 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9624 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9627 if (opcode
== 0xf || opcode
== 0x12) {
9628 /* SABA, UABA, MLA, MLS: accumulating ops */
9629 static NeonGenTwoOpFn
* const fns
[3][2] = {
9630 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9631 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9632 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9634 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9636 genfn
= fns
[size
][is_sub
];
9637 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9638 genfn(tcg_res
, tcg_op1
, tcg_res
);
9641 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9643 tcg_temp_free_i32(tcg_res
);
9644 tcg_temp_free_i32(tcg_op1
);
9645 tcg_temp_free_i32(tcg_op2
);
9650 clear_vec_high(s
, rd
);
9654 /* C3.6.16 AdvSIMD three same
9655 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9656 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9657 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9658 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9660 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9662 int opcode
= extract32(insn
, 11, 5);
9665 case 0x3: /* logic ops */
9666 disas_simd_3same_logic(s
, insn
);
9668 case 0x17: /* ADDP */
9669 case 0x14: /* SMAXP, UMAXP */
9670 case 0x15: /* SMINP, UMINP */
9672 /* Pairwise operations */
9673 int is_q
= extract32(insn
, 30, 1);
9674 int u
= extract32(insn
, 29, 1);
9675 int size
= extract32(insn
, 22, 2);
9676 int rm
= extract32(insn
, 16, 5);
9677 int rn
= extract32(insn
, 5, 5);
9678 int rd
= extract32(insn
, 0, 5);
9679 if (opcode
== 0x17) {
9680 if (u
|| (size
== 3 && !is_q
)) {
9681 unallocated_encoding(s
);
9686 unallocated_encoding(s
);
9690 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9694 /* floating point ops, sz[1] and U are part of opcode */
9695 disas_simd_3same_float(s
, insn
);
9698 disas_simd_3same_int(s
, insn
);
9703 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9704 int size
, int rn
, int rd
)
9706 /* Handle 2-reg-misc ops which are widening (so each size element
9707 * in the source becomes a 2*size element in the destination.
9708 * The only instruction like this is FCVTL.
9713 /* 32 -> 64 bit fp conversion */
9714 TCGv_i64 tcg_res
[2];
9715 int srcelt
= is_q
? 2 : 0;
9717 for (pass
= 0; pass
< 2; pass
++) {
9718 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9719 tcg_res
[pass
] = tcg_temp_new_i64();
9721 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9722 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9723 tcg_temp_free_i32(tcg_op
);
9725 for (pass
= 0; pass
< 2; pass
++) {
9726 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9727 tcg_temp_free_i64(tcg_res
[pass
]);
9730 /* 16 -> 32 bit fp conversion */
9731 int srcelt
= is_q
? 4 : 0;
9732 TCGv_i32 tcg_res
[4];
9734 for (pass
= 0; pass
< 4; pass
++) {
9735 tcg_res
[pass
] = tcg_temp_new_i32();
9737 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9738 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9741 for (pass
= 0; pass
< 4; pass
++) {
9742 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9743 tcg_temp_free_i32(tcg_res
[pass
]);
9748 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9749 bool is_q
, int size
, int rn
, int rd
)
9751 int op
= (opcode
<< 1) | u
;
9752 int opsz
= op
+ size
;
9753 int grp_size
= 3 - opsz
;
9754 int dsize
= is_q
? 128 : 64;
9758 unallocated_encoding(s
);
9762 if (!fp_access_check(s
)) {
9767 /* Special case bytes, use bswap op on each group of elements */
9768 int groups
= dsize
/ (8 << grp_size
);
9770 for (i
= 0; i
< groups
; i
++) {
9771 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9773 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9776 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9779 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9782 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9785 g_assert_not_reached();
9787 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9788 tcg_temp_free_i64(tcg_tmp
);
9791 clear_vec_high(s
, rd
);
9794 int revmask
= (1 << grp_size
) - 1;
9795 int esize
= 8 << size
;
9796 int elements
= dsize
/ esize
;
9797 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9798 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9799 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9801 for (i
= 0; i
< elements
; i
++) {
9802 int e_rev
= (i
& 0xf) ^ revmask
;
9803 int off
= e_rev
* esize
;
9804 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9806 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9807 tcg_rn
, off
- 64, esize
);
9809 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9812 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9813 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9815 tcg_temp_free_i64(tcg_rd_hi
);
9816 tcg_temp_free_i64(tcg_rd
);
9817 tcg_temp_free_i64(tcg_rn
);
9821 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9822 bool is_q
, int size
, int rn
, int rd
)
9824 /* Implement the pairwise operations from 2-misc:
9825 * SADDLP, UADDLP, SADALP, UADALP.
9826 * These all add pairs of elements in the input to produce a
9827 * double-width result element in the output (possibly accumulating).
9829 bool accum
= (opcode
== 0x6);
9830 int maxpass
= is_q
? 2 : 1;
9832 TCGv_i64 tcg_res
[2];
9835 /* 32 + 32 -> 64 op */
9836 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9838 for (pass
= 0; pass
< maxpass
; pass
++) {
9839 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9840 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9842 tcg_res
[pass
] = tcg_temp_new_i64();
9844 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9845 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9846 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9848 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9849 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9852 tcg_temp_free_i64(tcg_op1
);
9853 tcg_temp_free_i64(tcg_op2
);
9856 for (pass
= 0; pass
< maxpass
; pass
++) {
9857 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9858 NeonGenOneOpFn
*genfn
;
9859 static NeonGenOneOpFn
* const fns
[2][2] = {
9860 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9861 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9864 genfn
= fns
[size
][u
];
9866 tcg_res
[pass
] = tcg_temp_new_i64();
9868 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9869 genfn(tcg_res
[pass
], tcg_op
);
9872 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9874 gen_helper_neon_addl_u16(tcg_res
[pass
],
9875 tcg_res
[pass
], tcg_op
);
9877 gen_helper_neon_addl_u32(tcg_res
[pass
],
9878 tcg_res
[pass
], tcg_op
);
9881 tcg_temp_free_i64(tcg_op
);
9885 tcg_res
[1] = tcg_const_i64(0);
9887 for (pass
= 0; pass
< 2; pass
++) {
9888 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9889 tcg_temp_free_i64(tcg_res
[pass
]);
9893 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9895 /* Implement SHLL and SHLL2 */
9897 int part
= is_q
? 2 : 0;
9898 TCGv_i64 tcg_res
[2];
9900 for (pass
= 0; pass
< 2; pass
++) {
9901 static NeonGenWidenFn
* const widenfns
[3] = {
9902 gen_helper_neon_widen_u8
,
9903 gen_helper_neon_widen_u16
,
9904 tcg_gen_extu_i32_i64
,
9906 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9907 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9909 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9910 tcg_res
[pass
] = tcg_temp_new_i64();
9911 widenfn(tcg_res
[pass
], tcg_op
);
9912 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9914 tcg_temp_free_i32(tcg_op
);
9917 for (pass
= 0; pass
< 2; pass
++) {
9918 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9919 tcg_temp_free_i64(tcg_res
[pass
]);
9923 /* C3.6.17 AdvSIMD two reg misc
9924 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9925 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9926 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9927 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9929 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9931 int size
= extract32(insn
, 22, 2);
9932 int opcode
= extract32(insn
, 12, 5);
9933 bool u
= extract32(insn
, 29, 1);
9934 bool is_q
= extract32(insn
, 30, 1);
9935 int rn
= extract32(insn
, 5, 5);
9936 int rd
= extract32(insn
, 0, 5);
9937 bool need_fpstatus
= false;
9938 bool need_rmode
= false;
9941 TCGv_ptr tcg_fpstatus
;
9944 case 0x0: /* REV64, REV32 */
9945 case 0x1: /* REV16 */
9946 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9948 case 0x5: /* CNT, NOT, RBIT */
9949 if (u
&& size
== 0) {
9950 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9953 } else if (u
&& size
== 1) {
9956 } else if (!u
&& size
== 0) {
9960 unallocated_encoding(s
);
9962 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9963 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9965 unallocated_encoding(s
);
9968 if (!fp_access_check(s
)) {
9972 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9974 case 0x4: /* CLS, CLZ */
9976 unallocated_encoding(s
);
9980 case 0x2: /* SADDLP, UADDLP */
9981 case 0x6: /* SADALP, UADALP */
9983 unallocated_encoding(s
);
9986 if (!fp_access_check(s
)) {
9989 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9991 case 0x13: /* SHLL, SHLL2 */
9992 if (u
== 0 || size
== 3) {
9993 unallocated_encoding(s
);
9996 if (!fp_access_check(s
)) {
9999 handle_shll(s
, is_q
, size
, rn
, rd
);
10001 case 0xa: /* CMLT */
10003 unallocated_encoding(s
);
10007 case 0x8: /* CMGT, CMGE */
10008 case 0x9: /* CMEQ, CMLE */
10009 case 0xb: /* ABS, NEG */
10010 if (size
== 3 && !is_q
) {
10011 unallocated_encoding(s
);
10015 case 0x3: /* SUQADD, USQADD */
10016 if (size
== 3 && !is_q
) {
10017 unallocated_encoding(s
);
10020 if (!fp_access_check(s
)) {
10023 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10025 case 0x7: /* SQABS, SQNEG */
10026 if (size
== 3 && !is_q
) {
10027 unallocated_encoding(s
);
10032 case 0x16 ... 0x1d:
10035 /* Floating point: U, size[1] and opcode indicate operation;
10036 * size[0] indicates single or double precision.
10038 int is_double
= extract32(size
, 0, 1);
10039 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10040 size
= is_double
? 3 : 2;
10042 case 0x2f: /* FABS */
10043 case 0x6f: /* FNEG */
10044 if (size
== 3 && !is_q
) {
10045 unallocated_encoding(s
);
10049 case 0x1d: /* SCVTF */
10050 case 0x5d: /* UCVTF */
10052 bool is_signed
= (opcode
== 0x1d) ? true : false;
10053 int elements
= is_double
? 2 : is_q
? 4 : 2;
10054 if (is_double
&& !is_q
) {
10055 unallocated_encoding(s
);
10058 if (!fp_access_check(s
)) {
10061 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10064 case 0x2c: /* FCMGT (zero) */
10065 case 0x2d: /* FCMEQ (zero) */
10066 case 0x2e: /* FCMLT (zero) */
10067 case 0x6c: /* FCMGE (zero) */
10068 case 0x6d: /* FCMLE (zero) */
10069 if (size
== 3 && !is_q
) {
10070 unallocated_encoding(s
);
10073 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10075 case 0x7f: /* FSQRT */
10076 if (size
== 3 && !is_q
) {
10077 unallocated_encoding(s
);
10081 case 0x1a: /* FCVTNS */
10082 case 0x1b: /* FCVTMS */
10083 case 0x3a: /* FCVTPS */
10084 case 0x3b: /* FCVTZS */
10085 case 0x5a: /* FCVTNU */
10086 case 0x5b: /* FCVTMU */
10087 case 0x7a: /* FCVTPU */
10088 case 0x7b: /* FCVTZU */
10089 need_fpstatus
= true;
10091 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10092 if (size
== 3 && !is_q
) {
10093 unallocated_encoding(s
);
10097 case 0x5c: /* FCVTAU */
10098 case 0x1c: /* FCVTAS */
10099 need_fpstatus
= true;
10101 rmode
= FPROUNDING_TIEAWAY
;
10102 if (size
== 3 && !is_q
) {
10103 unallocated_encoding(s
);
10107 case 0x3c: /* URECPE */
10109 unallocated_encoding(s
);
10113 case 0x3d: /* FRECPE */
10114 case 0x7d: /* FRSQRTE */
10115 if (size
== 3 && !is_q
) {
10116 unallocated_encoding(s
);
10119 if (!fp_access_check(s
)) {
10122 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10124 case 0x56: /* FCVTXN, FCVTXN2 */
10126 unallocated_encoding(s
);
10130 case 0x16: /* FCVTN, FCVTN2 */
10131 /* handle_2misc_narrow does a 2*size -> size operation, but these
10132 * instructions encode the source size rather than dest size.
10134 if (!fp_access_check(s
)) {
10137 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10139 case 0x17: /* FCVTL, FCVTL2 */
10140 if (!fp_access_check(s
)) {
10143 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10145 case 0x18: /* FRINTN */
10146 case 0x19: /* FRINTM */
10147 case 0x38: /* FRINTP */
10148 case 0x39: /* FRINTZ */
10150 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10152 case 0x59: /* FRINTX */
10153 case 0x79: /* FRINTI */
10154 need_fpstatus
= true;
10155 if (size
== 3 && !is_q
) {
10156 unallocated_encoding(s
);
10160 case 0x58: /* FRINTA */
10162 rmode
= FPROUNDING_TIEAWAY
;
10163 need_fpstatus
= true;
10164 if (size
== 3 && !is_q
) {
10165 unallocated_encoding(s
);
10169 case 0x7c: /* URSQRTE */
10171 unallocated_encoding(s
);
10174 need_fpstatus
= true;
10177 unallocated_encoding(s
);
10183 unallocated_encoding(s
);
10187 if (!fp_access_check(s
)) {
10191 if (need_fpstatus
) {
10192 tcg_fpstatus
= get_fpstatus_ptr();
10194 TCGV_UNUSED_PTR(tcg_fpstatus
);
10197 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10198 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10200 TCGV_UNUSED_I32(tcg_rmode
);
10204 /* All 64-bit element operations can be shared with scalar 2misc */
10207 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10208 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10209 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10211 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10213 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10214 tcg_rmode
, tcg_fpstatus
);
10216 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10218 tcg_temp_free_i64(tcg_res
);
10219 tcg_temp_free_i64(tcg_op
);
10224 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10225 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10226 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10229 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10232 /* Special cases for 32 bit elements */
10234 case 0xa: /* CMLT */
10235 /* 32 bit integer comparison against zero, result is
10236 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10239 cond
= TCG_COND_LT
;
10241 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10242 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10244 case 0x8: /* CMGT, CMGE */
10245 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10247 case 0x9: /* CMEQ, CMLE */
10248 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10250 case 0x4: /* CLS */
10252 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10254 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10257 case 0x7: /* SQABS, SQNEG */
10259 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10261 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10264 case 0xb: /* ABS, NEG */
10266 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10268 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10269 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10270 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10271 tcg_zero
, tcg_op
, tcg_res
);
10272 tcg_temp_free_i32(tcg_zero
);
10275 case 0x2f: /* FABS */
10276 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10278 case 0x6f: /* FNEG */
10279 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10281 case 0x7f: /* FSQRT */
10282 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10284 case 0x1a: /* FCVTNS */
10285 case 0x1b: /* FCVTMS */
10286 case 0x1c: /* FCVTAS */
10287 case 0x3a: /* FCVTPS */
10288 case 0x3b: /* FCVTZS */
10290 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10291 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10292 tcg_shift
, tcg_fpstatus
);
10293 tcg_temp_free_i32(tcg_shift
);
10296 case 0x5a: /* FCVTNU */
10297 case 0x5b: /* FCVTMU */
10298 case 0x5c: /* FCVTAU */
10299 case 0x7a: /* FCVTPU */
10300 case 0x7b: /* FCVTZU */
10302 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10303 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10304 tcg_shift
, tcg_fpstatus
);
10305 tcg_temp_free_i32(tcg_shift
);
10308 case 0x18: /* FRINTN */
10309 case 0x19: /* FRINTM */
10310 case 0x38: /* FRINTP */
10311 case 0x39: /* FRINTZ */
10312 case 0x58: /* FRINTA */
10313 case 0x79: /* FRINTI */
10314 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10316 case 0x59: /* FRINTX */
10317 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10319 case 0x7c: /* URSQRTE */
10320 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10323 g_assert_not_reached();
10326 /* Use helpers for 8 and 16 bit elements */
10328 case 0x5: /* CNT, RBIT */
10329 /* For these two insns size is part of the opcode specifier
10330 * (handled earlier); they always operate on byte elements.
10333 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10335 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10338 case 0x7: /* SQABS, SQNEG */
10340 NeonGenOneOpEnvFn
*genfn
;
10341 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10342 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10343 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10345 genfn
= fns
[size
][u
];
10346 genfn(tcg_res
, cpu_env
, tcg_op
);
10349 case 0x8: /* CMGT, CMGE */
10350 case 0x9: /* CMEQ, CMLE */
10351 case 0xa: /* CMLT */
10353 static NeonGenTwoOpFn
* const fns
[3][2] = {
10354 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10355 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10356 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10358 NeonGenTwoOpFn
*genfn
;
10361 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10363 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10364 comp
= (opcode
- 0x8) * 2 + u
;
10365 /* ...but LE, LT are implemented as reverse GE, GT */
10366 reverse
= (comp
> 2);
10370 genfn
= fns
[comp
][size
];
10372 genfn(tcg_res
, tcg_zero
, tcg_op
);
10374 genfn(tcg_res
, tcg_op
, tcg_zero
);
10376 tcg_temp_free_i32(tcg_zero
);
10379 case 0xb: /* ABS, NEG */
10381 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10383 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10385 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10387 tcg_temp_free_i32(tcg_zero
);
10390 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10392 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10396 case 0x4: /* CLS, CLZ */
10399 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10401 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10405 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10407 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10412 g_assert_not_reached();
10416 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10418 tcg_temp_free_i32(tcg_res
);
10419 tcg_temp_free_i32(tcg_op
);
10423 clear_vec_high(s
, rd
);
10427 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10428 tcg_temp_free_i32(tcg_rmode
);
10430 if (need_fpstatus
) {
10431 tcg_temp_free_ptr(tcg_fpstatus
);
10435 /* C3.6.13 AdvSIMD scalar x indexed element
10436 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10437 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10438 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10439 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10440 * C3.6.18 AdvSIMD vector x indexed element
10441 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10442 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10443 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10444 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10446 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10448 /* This encoding has two kinds of instruction:
10449 * normal, where we perform elt x idxelt => elt for each
10450 * element in the vector
10451 * long, where we perform elt x idxelt and generate a result of
10452 * double the width of the input element
10453 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10455 bool is_scalar
= extract32(insn
, 28, 1);
10456 bool is_q
= extract32(insn
, 30, 1);
10457 bool u
= extract32(insn
, 29, 1);
10458 int size
= extract32(insn
, 22, 2);
10459 int l
= extract32(insn
, 21, 1);
10460 int m
= extract32(insn
, 20, 1);
10461 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10462 int rm
= extract32(insn
, 16, 4);
10463 int opcode
= extract32(insn
, 12, 4);
10464 int h
= extract32(insn
, 11, 1);
10465 int rn
= extract32(insn
, 5, 5);
10466 int rd
= extract32(insn
, 0, 5);
10467 bool is_long
= false;
10468 bool is_fp
= false;
10473 case 0x0: /* MLA */
10474 case 0x4: /* MLS */
10475 if (!u
|| is_scalar
) {
10476 unallocated_encoding(s
);
10480 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10481 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10482 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10484 unallocated_encoding(s
);
10489 case 0x3: /* SQDMLAL, SQDMLAL2 */
10490 case 0x7: /* SQDMLSL, SQDMLSL2 */
10491 case 0xb: /* SQDMULL, SQDMULL2 */
10494 case 0xc: /* SQDMULH */
10495 case 0xd: /* SQRDMULH */
10497 unallocated_encoding(s
);
10501 case 0x8: /* MUL */
10502 if (u
|| is_scalar
) {
10503 unallocated_encoding(s
);
10507 case 0x1: /* FMLA */
10508 case 0x5: /* FMLS */
10510 unallocated_encoding(s
);
10514 case 0x9: /* FMUL, FMULX */
10515 if (!extract32(size
, 1, 1)) {
10516 unallocated_encoding(s
);
10522 unallocated_encoding(s
);
10527 /* low bit of size indicates single/double */
10528 size
= extract32(size
, 0, 1) ? 3 : 2;
10530 index
= h
<< 1 | l
;
10533 unallocated_encoding(s
);
10542 index
= h
<< 2 | l
<< 1 | m
;
10545 index
= h
<< 1 | l
;
10549 unallocated_encoding(s
);
10554 if (!fp_access_check(s
)) {
10559 fpst
= get_fpstatus_ptr();
10561 TCGV_UNUSED_PTR(fpst
);
10565 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10568 assert(is_fp
&& is_q
&& !is_long
);
10570 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10572 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10573 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10574 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10576 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10579 case 0x5: /* FMLS */
10580 /* As usual for ARM, separate negation for fused multiply-add */
10581 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10583 case 0x1: /* FMLA */
10584 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10585 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10587 case 0x9: /* FMUL, FMULX */
10589 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10591 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10595 g_assert_not_reached();
10598 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10599 tcg_temp_free_i64(tcg_op
);
10600 tcg_temp_free_i64(tcg_res
);
10604 clear_vec_high(s
, rd
);
10607 tcg_temp_free_i64(tcg_idx
);
10608 } else if (!is_long
) {
10609 /* 32 bit floating point, or 16 or 32 bit integer.
10610 * For the 16 bit scalar case we use the usual Neon helpers and
10611 * rely on the fact that 0 op 0 == 0 with no side effects.
10613 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10614 int pass
, maxpasses
;
10619 maxpasses
= is_q
? 4 : 2;
10622 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10624 if (size
== 1 && !is_scalar
) {
10625 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10626 * the index into both halves of the 32 bit tcg_idx and then use
10627 * the usual Neon helpers.
10629 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10632 for (pass
= 0; pass
< maxpasses
; pass
++) {
10633 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10634 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10636 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10639 case 0x0: /* MLA */
10640 case 0x4: /* MLS */
10641 case 0x8: /* MUL */
10643 static NeonGenTwoOpFn
* const fns
[2][2] = {
10644 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10645 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10647 NeonGenTwoOpFn
*genfn
;
10648 bool is_sub
= opcode
== 0x4;
10651 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10653 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10655 if (opcode
== 0x8) {
10658 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10659 genfn
= fns
[size
- 1][is_sub
];
10660 genfn(tcg_res
, tcg_op
, tcg_res
);
10663 case 0x5: /* FMLS */
10664 /* As usual for ARM, separate negation for fused multiply-add */
10665 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10667 case 0x1: /* FMLA */
10668 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10669 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10671 case 0x9: /* FMUL, FMULX */
10673 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10675 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10678 case 0xc: /* SQDMULH */
10680 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10683 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10687 case 0xd: /* SQRDMULH */
10689 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10692 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10697 g_assert_not_reached();
10701 write_fp_sreg(s
, rd
, tcg_res
);
10703 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10706 tcg_temp_free_i32(tcg_op
);
10707 tcg_temp_free_i32(tcg_res
);
10710 tcg_temp_free_i32(tcg_idx
);
10713 clear_vec_high(s
, rd
);
10716 /* long ops: 16x16->32 or 32x32->64 */
10717 TCGv_i64 tcg_res
[2];
10719 bool satop
= extract32(opcode
, 0, 1);
10720 TCGMemOp memop
= MO_32
;
10727 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10729 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10731 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10732 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10733 TCGv_i64 tcg_passres
;
10739 passelt
= pass
+ (is_q
* 2);
10742 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10744 tcg_res
[pass
] = tcg_temp_new_i64();
10746 if (opcode
== 0xa || opcode
== 0xb) {
10747 /* Non-accumulating ops */
10748 tcg_passres
= tcg_res
[pass
];
10750 tcg_passres
= tcg_temp_new_i64();
10753 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10754 tcg_temp_free_i64(tcg_op
);
10757 /* saturating, doubling */
10758 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10759 tcg_passres
, tcg_passres
);
10762 if (opcode
== 0xa || opcode
== 0xb) {
10766 /* Accumulating op: handle accumulate step */
10767 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10770 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10771 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10773 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10774 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10776 case 0x7: /* SQDMLSL, SQDMLSL2 */
10777 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10779 case 0x3: /* SQDMLAL, SQDMLAL2 */
10780 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10785 g_assert_not_reached();
10787 tcg_temp_free_i64(tcg_passres
);
10789 tcg_temp_free_i64(tcg_idx
);
10792 clear_vec_high(s
, rd
);
10795 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10798 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10801 /* The simplest way to handle the 16x16 indexed ops is to
10802 * duplicate the index into both halves of the 32 bit tcg_idx
10803 * and then use the usual Neon helpers.
10805 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10808 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10809 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10810 TCGv_i64 tcg_passres
;
10813 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10815 read_vec_element_i32(s
, tcg_op
, rn
,
10816 pass
+ (is_q
* 2), MO_32
);
10819 tcg_res
[pass
] = tcg_temp_new_i64();
10821 if (opcode
== 0xa || opcode
== 0xb) {
10822 /* Non-accumulating ops */
10823 tcg_passres
= tcg_res
[pass
];
10825 tcg_passres
= tcg_temp_new_i64();
10828 if (memop
& MO_SIGN
) {
10829 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10831 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10834 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10835 tcg_passres
, tcg_passres
);
10837 tcg_temp_free_i32(tcg_op
);
10839 if (opcode
== 0xa || opcode
== 0xb) {
10843 /* Accumulating op: handle accumulate step */
10844 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10847 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10848 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10851 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10852 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10855 case 0x7: /* SQDMLSL, SQDMLSL2 */
10856 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10858 case 0x3: /* SQDMLAL, SQDMLAL2 */
10859 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10864 g_assert_not_reached();
10866 tcg_temp_free_i64(tcg_passres
);
10868 tcg_temp_free_i32(tcg_idx
);
10871 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10876 tcg_res
[1] = tcg_const_i64(0);
10879 for (pass
= 0; pass
< 2; pass
++) {
10880 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10881 tcg_temp_free_i64(tcg_res
[pass
]);
10885 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10886 tcg_temp_free_ptr(fpst
);
10890 /* C3.6.19 Crypto AES
10891 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10892 * +-----------------+------+-----------+--------+-----+------+------+
10893 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10894 * +-----------------+------+-----------+--------+-----+------+------+
10896 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10898 int size
= extract32(insn
, 22, 2);
10899 int opcode
= extract32(insn
, 12, 5);
10900 int rn
= extract32(insn
, 5, 5);
10901 int rd
= extract32(insn
, 0, 5);
10903 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10904 CryptoThreeOpEnvFn
*genfn
;
10906 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10908 unallocated_encoding(s
);
10913 case 0x4: /* AESE */
10915 genfn
= gen_helper_crypto_aese
;
10917 case 0x6: /* AESMC */
10919 genfn
= gen_helper_crypto_aesmc
;
10921 case 0x5: /* AESD */
10923 genfn
= gen_helper_crypto_aese
;
10925 case 0x7: /* AESIMC */
10927 genfn
= gen_helper_crypto_aesmc
;
10930 unallocated_encoding(s
);
10934 if (!fp_access_check(s
)) {
10938 /* Note that we convert the Vx register indexes into the
10939 * index within the vfp.regs[] array, so we can share the
10940 * helper with the AArch32 instructions.
10942 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10943 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10944 tcg_decrypt
= tcg_const_i32(decrypt
);
10946 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10948 tcg_temp_free_i32(tcg_rd_regno
);
10949 tcg_temp_free_i32(tcg_rn_regno
);
10950 tcg_temp_free_i32(tcg_decrypt
);
10953 /* C3.6.20 Crypto three-reg SHA
10954 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10955 * +-----------------+------+---+------+---+--------+-----+------+------+
10956 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10957 * +-----------------+------+---+------+---+--------+-----+------+------+
10959 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10961 int size
= extract32(insn
, 22, 2);
10962 int opcode
= extract32(insn
, 12, 3);
10963 int rm
= extract32(insn
, 16, 5);
10964 int rn
= extract32(insn
, 5, 5);
10965 int rd
= extract32(insn
, 0, 5);
10966 CryptoThreeOpEnvFn
*genfn
;
10967 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10968 int feature
= ARM_FEATURE_V8_SHA256
;
10971 unallocated_encoding(s
);
10976 case 0: /* SHA1C */
10977 case 1: /* SHA1P */
10978 case 2: /* SHA1M */
10979 case 3: /* SHA1SU0 */
10981 feature
= ARM_FEATURE_V8_SHA1
;
10983 case 4: /* SHA256H */
10984 genfn
= gen_helper_crypto_sha256h
;
10986 case 5: /* SHA256H2 */
10987 genfn
= gen_helper_crypto_sha256h2
;
10989 case 6: /* SHA256SU1 */
10990 genfn
= gen_helper_crypto_sha256su1
;
10993 unallocated_encoding(s
);
10997 if (!arm_dc_feature(s
, feature
)) {
10998 unallocated_encoding(s
);
11002 if (!fp_access_check(s
)) {
11006 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11007 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11008 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11011 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11013 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11015 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11016 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11017 tcg_temp_free_i32(tcg_opcode
);
11020 tcg_temp_free_i32(tcg_rd_regno
);
11021 tcg_temp_free_i32(tcg_rn_regno
);
11022 tcg_temp_free_i32(tcg_rm_regno
);
11025 /* C3.6.21 Crypto two-reg SHA
11026 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11027 * +-----------------+------+-----------+--------+-----+------+------+
11028 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11029 * +-----------------+------+-----------+--------+-----+------+------+
11031 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11033 int size
= extract32(insn
, 22, 2);
11034 int opcode
= extract32(insn
, 12, 5);
11035 int rn
= extract32(insn
, 5, 5);
11036 int rd
= extract32(insn
, 0, 5);
11037 CryptoTwoOpEnvFn
*genfn
;
11039 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11042 unallocated_encoding(s
);
11047 case 0: /* SHA1H */
11048 feature
= ARM_FEATURE_V8_SHA1
;
11049 genfn
= gen_helper_crypto_sha1h
;
11051 case 1: /* SHA1SU1 */
11052 feature
= ARM_FEATURE_V8_SHA1
;
11053 genfn
= gen_helper_crypto_sha1su1
;
11055 case 2: /* SHA256SU0 */
11056 feature
= ARM_FEATURE_V8_SHA256
;
11057 genfn
= gen_helper_crypto_sha256su0
;
11060 unallocated_encoding(s
);
11064 if (!arm_dc_feature(s
, feature
)) {
11065 unallocated_encoding(s
);
11069 if (!fp_access_check(s
)) {
11073 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11074 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11076 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11078 tcg_temp_free_i32(tcg_rd_regno
);
11079 tcg_temp_free_i32(tcg_rn_regno
);
11082 /* C3.6 Data processing - SIMD, inc Crypto
11084 * As the decode gets a little complex we are using a table based
11085 * approach for this part of the decode.
11087 static const AArch64DecodeTable data_proc_simd
[] = {
11088 /* pattern , mask , fn */
11089 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11090 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11091 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11092 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11093 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11094 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11095 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11096 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11097 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11098 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11099 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11100 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11101 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11102 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11103 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11104 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11105 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11106 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11107 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11108 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11109 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11110 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11111 { 0x00000000, 0x00000000, NULL
}
11114 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11116 /* Note that this is called with all non-FP cases from
11117 * table C3-6 so it must UNDEF for entries not specifically
11118 * allocated to instructions in that table.
11120 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11124 unallocated_encoding(s
);
11128 /* C3.6 Data processing - SIMD and floating point */
11129 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11131 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11132 disas_data_proc_fp(s
, insn
);
11134 /* SIMD, including crypto */
11135 disas_data_proc_simd(s
, insn
);
11139 /* C3.1 A64 instruction index by encoding */
11140 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11144 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11148 s
->fp_access_checked
= false;
11150 switch (extract32(insn
, 25, 4)) {
11151 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11152 unallocated_encoding(s
);
11154 case 0x8: case 0x9: /* Data processing - immediate */
11155 disas_data_proc_imm(s
, insn
);
11157 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11158 disas_b_exc_sys(s
, insn
);
11163 case 0xe: /* Loads and stores */
11164 disas_ldst(s
, insn
);
11167 case 0xd: /* Data processing - register */
11168 disas_data_proc_reg(s
, insn
);
11171 case 0xf: /* Data processing - SIMD and floating point */
11172 disas_data_proc_simd_fp(s
, insn
);
11175 assert(FALSE
); /* all 15 cases should be handled above */
11179 /* if we allocated any temporaries, free them here */
11183 void gen_intermediate_code_a64(CPUState
*cs
, TranslationBlock
*tb
)
11185 CPUARMState
*env
= cs
->env_ptr
;
11186 ARMCPU
*cpu
= arm_env_get_cpu(env
);
11187 DisasContext dc1
, *dc
= &dc1
;
11188 target_ulong pc_start
;
11189 target_ulong next_page_start
;
11197 dc
->is_jmp
= DISAS_NEXT
;
11199 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11203 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11204 * there is no secure EL1, so we route exceptions to EL3.
11206 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11207 !arm_el_is_aa64(env
, 3);
11210 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11211 dc
->condexec_mask
= 0;
11212 dc
->condexec_cond
= 0;
11213 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(tb
->flags
));
11214 dc
->tbi0
= ARM_TBFLAG_TBI0(tb
->flags
);
11215 dc
->tbi1
= ARM_TBFLAG_TBI1(tb
->flags
);
11216 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11217 #if !defined(CONFIG_USER_ONLY)
11218 dc
->user
= (dc
->current_el
== 0);
11220 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11222 dc
->vec_stride
= 0;
11223 dc
->cp_regs
= cpu
->cp_regs
;
11224 dc
->features
= env
->features
;
11226 /* Single step state. The code-generation logic here is:
11228 * generate code with no special handling for single-stepping (except
11229 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11230 * this happens anyway because those changes are all system register or
11232 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11233 * emit code for one insn
11234 * emit code to clear PSTATE.SS
11235 * emit code to generate software step exception for completed step
11236 * end TB (as usual for having generated an exception)
11237 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11238 * emit code to generate a software step exception
11241 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11242 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11243 dc
->is_ldex
= false;
11244 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11246 init_tmp_a64_array(dc
);
11248 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11250 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11251 if (max_insns
== 0) {
11252 max_insns
= CF_COUNT_MASK
;
11254 if (max_insns
> TCG_MAX_INSNS
) {
11255 max_insns
= TCG_MAX_INSNS
;
11260 tcg_clear_temp_count();
11263 dc
->insn_start_idx
= tcg_op_buf_count();
11264 tcg_gen_insn_start(dc
->pc
, 0, 0);
11267 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11269 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11270 if (bp
->pc
== dc
->pc
) {
11271 if (bp
->flags
& BP_CPU
) {
11272 gen_a64_set_pc_im(dc
->pc
);
11273 gen_helper_check_breakpoints(cpu_env
);
11274 /* End the TB early; it likely won't be executed */
11275 dc
->is_jmp
= DISAS_UPDATE
;
11277 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11278 /* The address covered by the breakpoint must be
11279 included in [tb->pc, tb->pc + tb->size) in order
11280 to for it to be properly cleared -- thus we
11281 increment the PC here so that the logic setting
11282 tb->size below does the right thing. */
11284 goto done_generating
;
11291 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11295 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11296 /* Singlestep state is Active-pending.
11297 * If we're in this state at the start of a TB then either
11298 * a) we just took an exception to an EL which is being debugged
11299 * and this is the first insn in the exception handler
11300 * b) debug exceptions were masked and we just unmasked them
11301 * without changing EL (eg by clearing PSTATE.D)
11302 * In either case we're going to take a swstep exception in the
11303 * "did not step an insn" case, and so the syndrome ISV and EX
11304 * bits should be zero.
11306 assert(num_insns
== 1);
11307 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11308 default_exception_el(dc
));
11309 dc
->is_jmp
= DISAS_EXC
;
11313 disas_a64_insn(env
, dc
);
11315 if (tcg_check_temp_count()) {
11316 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11320 /* Translation stops when a conditional branch is encountered.
11321 * Otherwise the subsequent code could get translated several times.
11322 * Also stop translation when a page boundary is reached. This
11323 * ensures prefetch aborts occur at the right place.
11325 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11326 !cs
->singlestep_enabled
&&
11329 dc
->pc
< next_page_start
&&
11330 num_insns
< max_insns
);
11332 if (tb
->cflags
& CF_LAST_IO
) {
11336 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11337 && dc
->is_jmp
!= DISAS_EXC
) {
11338 /* Note that this means single stepping WFI doesn't halt the CPU.
11339 * For conditional branch insns this is harmless unreachable code as
11340 * gen_goto_tb() has already handled emitting the debug exception
11341 * (and thus a tb-jump is not possible when singlestepping).
11343 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11344 if (dc
->is_jmp
!= DISAS_JUMP
) {
11345 gen_a64_set_pc_im(dc
->pc
);
11347 if (cs
->singlestep_enabled
) {
11348 gen_exception_internal(EXCP_DEBUG
);
11350 gen_step_complete_exception(dc
);
11353 switch (dc
->is_jmp
) {
11355 gen_goto_tb(dc
, 1, dc
->pc
);
11358 tcg_gen_lookup_and_goto_ptr(cpu_pc
);
11360 case DISAS_TB_JUMP
:
11365 gen_a64_set_pc_im(dc
->pc
);
11366 gen_helper_wfe(cpu_env
);
11369 gen_a64_set_pc_im(dc
->pc
);
11370 gen_helper_yield(cpu_env
);
11373 /* This is a special case because we don't want to just halt the CPU
11374 * if trying to debug across a WFI.
11376 gen_a64_set_pc_im(dc
->pc
);
11377 gen_helper_wfi(cpu_env
);
11378 /* The helper doesn't necessarily throw an exception, but we
11379 * must go back to the main loop to check for interrupts anyway.
11381 tcg_gen_exit_tb(0);
11384 gen_a64_set_pc_im(dc
->pc
);
11388 tcg_gen_exit_tb(0);
11394 gen_tb_end(tb
, num_insns
);
11397 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
11398 qemu_log_in_addr_range(pc_start
)) {
11400 qemu_log("----------------\n");
11401 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11402 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11403 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11408 tb
->size
= dc
->pc
- pc_start
;
11409 tb
->icount
= num_insns
;