2 * CFI parallel flash with Intel command set emulation
4 * Copyright (c) 2006 Thorsten Zitterell
5 * Copyright (c) 2005 Jocelyn Mayer
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
30 * It does not support timings
31 * It does not support flash interleaving
32 * It does not implement software data protection as found in many real chips
33 * It does not implement erase suspend/resume commands
34 * It does not implement multiple sectors erase
36 * It does not implement much more ...
40 #include "hw/block/flash.h"
41 #include "block/block.h"
42 #include "qemu/timer.h"
43 #include "exec/address-spaces.h"
44 #include "qemu/host-utils.h"
45 #include "hw/sysbus.h"
47 #define PFLASH_BUG(fmt, ...) \
49 fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
53 /* #define PFLASH_DEBUG */
55 #define DPRINTF(fmt, ...) \
57 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
60 #define DPRINTF(fmt, ...) do { } while (0)
63 #define TYPE_CFI_PFLASH01 "cfi.pflash01"
64 #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
68 SysBusDevice parent_obj
;
76 uint8_t wcycle
; /* if 0, the flash is read normally */
85 uint8_t cfi_table
[0x52];
87 unsigned int writeblock_size
;
94 static const VMStateDescription vmstate_pflash
= {
95 .name
= "pflash_cfi01",
97 .minimum_version_id
= 1,
98 .fields
= (VMStateField
[]) {
99 VMSTATE_UINT8(wcycle
, pflash_t
),
100 VMSTATE_UINT8(cmd
, pflash_t
),
101 VMSTATE_UINT8(status
, pflash_t
),
102 VMSTATE_UINT64(counter
, pflash_t
),
103 VMSTATE_END_OF_LIST()
107 static void pflash_timer (void *opaque
)
109 pflash_t
*pfl
= opaque
;
111 DPRINTF("%s: command %02x done\n", __func__
, pfl
->cmd
);
114 memory_region_rom_device_set_romd(&pfl
->mem
, true);
119 static uint32_t pflash_read (pflash_t
*pfl
, hwaddr offset
,
127 boff
= offset
& 0xFF; /* why this here ?? */
131 else if (pfl
->width
== 4)
135 DPRINTF("%s: reading offset " TARGET_FMT_plx
" under cmd %02x width %d\n",
136 __func__
, offset
, pfl
->cmd
, width
);
140 /* This should never happen : reset state & treat it as a read */
141 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
144 /* fall through to read code */
146 /* Flash area read */
151 DPRINTF("%s: data offset " TARGET_FMT_plx
" %02x\n",
152 __func__
, offset
, ret
);
156 ret
= p
[offset
] << 8;
157 ret
|= p
[offset
+ 1];
160 ret
|= p
[offset
+ 1] << 8;
162 DPRINTF("%s: data offset " TARGET_FMT_plx
" %04x\n",
163 __func__
, offset
, ret
);
167 ret
= p
[offset
] << 24;
168 ret
|= p
[offset
+ 1] << 16;
169 ret
|= p
[offset
+ 2] << 8;
170 ret
|= p
[offset
+ 3];
173 ret
|= p
[offset
+ 1] << 8;
174 ret
|= p
[offset
+ 2] << 16;
175 ret
|= p
[offset
+ 3] << 24;
177 DPRINTF("%s: data offset " TARGET_FMT_plx
" %08x\n",
178 __func__
, offset
, ret
);
181 DPRINTF("BUG in %s\n", __func__
);
185 case 0x10: /* Single byte program */
186 case 0x20: /* Block erase */
187 case 0x28: /* Block erase */
188 case 0x40: /* single byte program */
189 case 0x50: /* Clear status register */
190 case 0x60: /* Block /un)lock */
191 case 0x70: /* Status Register */
192 case 0xe8: /* Write block */
193 /* Status register read */
195 DPRINTF("%s: status %x\n", __func__
, ret
);
200 ret
= pfl
->ident0
<< 8 | pfl
->ident1
;
201 DPRINTF("%s: Manufacturer Code %04x\n", __func__
, ret
);
204 ret
= pfl
->ident2
<< 8 | pfl
->ident3
;
205 DPRINTF("%s: Device ID Code %04x\n", __func__
, ret
);
208 DPRINTF("%s: Read Device Information boff=%x\n", __func__
,
214 case 0x98: /* Query mode */
215 if (boff
> pfl
->cfi_len
)
218 ret
= pfl
->cfi_table
[boff
];
224 /* update flash content on disk */
225 static void pflash_update(pflash_t
*pfl
, int offset
,
230 offset_end
= offset
+ size
;
231 /* round to sectors */
232 offset
= offset
>> 9;
233 offset_end
= (offset_end
+ 511) >> 9;
234 bdrv_write(pfl
->bs
, offset
, pfl
->storage
+ (offset
<< 9),
235 offset_end
- offset
);
239 static inline void pflash_data_write(pflash_t
*pfl
, hwaddr offset
,
240 uint32_t value
, int width
, int be
)
242 uint8_t *p
= pfl
->storage
;
244 DPRINTF("%s: block write offset " TARGET_FMT_plx
245 " value %x counter %016" PRIx64
"\n",
246 __func__
, offset
, value
, pfl
->counter
);
253 p
[offset
] = value
>> 8;
254 p
[offset
+ 1] = value
;
257 p
[offset
+ 1] = value
>> 8;
262 p
[offset
] = value
>> 24;
263 p
[offset
+ 1] = value
>> 16;
264 p
[offset
+ 2] = value
>> 8;
265 p
[offset
+ 3] = value
;
268 p
[offset
+ 1] = value
>> 8;
269 p
[offset
+ 2] = value
>> 16;
270 p
[offset
+ 3] = value
>> 24;
277 static void pflash_write(pflash_t
*pfl
, hwaddr offset
,
278 uint32_t value
, int width
, int be
)
285 DPRINTF("%s: writing offset " TARGET_FMT_plx
" value %08x width %d wcycle 0x%x\n",
286 __func__
, offset
, value
, width
, pfl
->wcycle
);
289 /* Set the device in I/O access mode */
290 memory_region_rom_device_set_romd(&pfl
->mem
, false);
293 switch (pfl
->wcycle
) {
299 case 0x10: /* Single Byte Program */
300 case 0x40: /* Single Byte Program */
301 DPRINTF("%s: Single Byte Program\n", __func__
);
303 case 0x20: /* Block erase */
305 offset
&= ~(pfl
->sector_len
- 1);
307 DPRINTF("%s: block erase at " TARGET_FMT_plx
" bytes %x\n",
308 __func__
, offset
, (unsigned)pfl
->sector_len
);
311 memset(p
+ offset
, 0xff, pfl
->sector_len
);
312 pflash_update(pfl
, offset
, pfl
->sector_len
);
314 pfl
->status
|= 0x20; /* Block erase error */
316 pfl
->status
|= 0x80; /* Ready! */
318 case 0x50: /* Clear status bits */
319 DPRINTF("%s: Clear status bits\n", __func__
);
322 case 0x60: /* Block (un)lock */
323 DPRINTF("%s: Block unlock\n", __func__
);
325 case 0x70: /* Status Register */
326 DPRINTF("%s: Read status register\n", __func__
);
329 case 0x90: /* Read Device ID */
330 DPRINTF("%s: Read Device information\n", __func__
);
333 case 0x98: /* CFI query */
334 DPRINTF("%s: CFI query\n", __func__
);
336 case 0xe8: /* Write to buffer */
337 DPRINTF("%s: Write to buffer\n", __func__
);
338 pfl
->status
|= 0x80; /* Ready! */
340 case 0xf0: /* Probe for AMD flash */
341 DPRINTF("%s: Probe for AMD flash\n", __func__
);
343 case 0xff: /* Read array mode */
344 DPRINTF("%s: Read array mode\n", __func__
);
354 case 0x10: /* Single Byte Program */
355 case 0x40: /* Single Byte Program */
356 DPRINTF("%s: Single Byte Program\n", __func__
);
358 pflash_data_write(pfl
, offset
, value
, width
, be
);
359 pflash_update(pfl
, offset
, width
);
361 pfl
->status
|= 0x10; /* Programming error */
363 pfl
->status
|= 0x80; /* Ready! */
366 case 0x20: /* Block erase */
368 if (cmd
== 0xd0) { /* confirm */
371 } else if (cmd
== 0xff) { /* read array mode */
378 DPRINTF("%s: block write of %x bytes\n", __func__
, value
);
379 pfl
->counter
= value
;
386 } else if (cmd
== 0x01) {
389 } else if (cmd
== 0xff) {
392 DPRINTF("%s: Unknown (un)locking command\n", __func__
);
400 DPRINTF("%s: leaving query mode\n", __func__
);
409 case 0xe8: /* Block write */
411 pflash_data_write(pfl
, offset
, value
, width
, be
);
413 pfl
->status
|= 0x10; /* Programming error */
419 hwaddr mask
= pfl
->writeblock_size
- 1;
422 DPRINTF("%s: block write finished\n", __func__
);
425 /* Flush the entire write buffer onto backing storage. */
426 pflash_update(pfl
, offset
& mask
, pfl
->writeblock_size
);
428 pfl
->status
|= 0x10; /* Programming error */
438 case 3: /* Confirm mode */
440 case 0xe8: /* Block write */
445 DPRINTF("%s: unknown command for \"write block\"\n", __func__
);
446 PFLASH_BUG("Write block confirm");
455 /* Should never happen */
456 DPRINTF("%s: invalid write state\n", __func__
);
462 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented flash cmd sequence "
463 "(offset " TARGET_FMT_plx
", wcycle 0x%x cmd 0x%x value 0x%x)"
464 "\n", __func__
, offset
, pfl
->wcycle
, pfl
->cmd
, value
);
467 memory_region_rom_device_set_romd(&pfl
->mem
, true);
474 static uint32_t pflash_readb_be(void *opaque
, hwaddr addr
)
476 return pflash_read(opaque
, addr
, 1, 1);
479 static uint32_t pflash_readb_le(void *opaque
, hwaddr addr
)
481 return pflash_read(opaque
, addr
, 1, 0);
484 static uint32_t pflash_readw_be(void *opaque
, hwaddr addr
)
486 pflash_t
*pfl
= opaque
;
488 return pflash_read(pfl
, addr
, 2, 1);
491 static uint32_t pflash_readw_le(void *opaque
, hwaddr addr
)
493 pflash_t
*pfl
= opaque
;
495 return pflash_read(pfl
, addr
, 2, 0);
498 static uint32_t pflash_readl_be(void *opaque
, hwaddr addr
)
500 pflash_t
*pfl
= opaque
;
502 return pflash_read(pfl
, addr
, 4, 1);
505 static uint32_t pflash_readl_le(void *opaque
, hwaddr addr
)
507 pflash_t
*pfl
= opaque
;
509 return pflash_read(pfl
, addr
, 4, 0);
512 static void pflash_writeb_be(void *opaque
, hwaddr addr
,
515 pflash_write(opaque
, addr
, value
, 1, 1);
518 static void pflash_writeb_le(void *opaque
, hwaddr addr
,
521 pflash_write(opaque
, addr
, value
, 1, 0);
524 static void pflash_writew_be(void *opaque
, hwaddr addr
,
527 pflash_t
*pfl
= opaque
;
529 pflash_write(pfl
, addr
, value
, 2, 1);
532 static void pflash_writew_le(void *opaque
, hwaddr addr
,
535 pflash_t
*pfl
= opaque
;
537 pflash_write(pfl
, addr
, value
, 2, 0);
540 static void pflash_writel_be(void *opaque
, hwaddr addr
,
543 pflash_t
*pfl
= opaque
;
545 pflash_write(pfl
, addr
, value
, 4, 1);
548 static void pflash_writel_le(void *opaque
, hwaddr addr
,
551 pflash_t
*pfl
= opaque
;
553 pflash_write(pfl
, addr
, value
, 4, 0);
556 static const MemoryRegionOps pflash_cfi01_ops_be
= {
558 .read
= { pflash_readb_be
, pflash_readw_be
, pflash_readl_be
, },
559 .write
= { pflash_writeb_be
, pflash_writew_be
, pflash_writel_be
, },
561 .endianness
= DEVICE_NATIVE_ENDIAN
,
564 static const MemoryRegionOps pflash_cfi01_ops_le
= {
566 .read
= { pflash_readb_le
, pflash_readw_le
, pflash_readl_le
, },
567 .write
= { pflash_writeb_le
, pflash_writew_le
, pflash_writel_le
, },
569 .endianness
= DEVICE_NATIVE_ENDIAN
,
572 static void pflash_cfi01_realize(DeviceState
*dev
, Error
**errp
)
574 pflash_t
*pfl
= CFI_PFLASH01(dev
);
578 total_len
= pfl
->sector_len
* pfl
->nb_blocs
;
580 /* XXX: to be fixed */
582 if (total_len
!= (8 * 1024 * 1024) && total_len
!= (16 * 1024 * 1024) &&
583 total_len
!= (32 * 1024 * 1024) && total_len
!= (64 * 1024 * 1024))
587 memory_region_init_rom_device(
588 &pfl
->mem
, OBJECT(dev
),
589 pfl
->be
? &pflash_cfi01_ops_be
: &pflash_cfi01_ops_le
, pfl
,
590 pfl
->name
, total_len
);
591 vmstate_register_ram(&pfl
->mem
, DEVICE(pfl
));
592 pfl
->storage
= memory_region_get_ram_ptr(&pfl
->mem
);
593 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &pfl
->mem
);
596 /* read the initial flash content */
597 ret
= bdrv_read(pfl
->bs
, 0, pfl
->storage
, total_len
>> 9);
600 vmstate_unregister_ram(&pfl
->mem
, DEVICE(pfl
));
601 memory_region_destroy(&pfl
->mem
);
602 error_setg(errp
, "failed to read the initial flash content");
608 pfl
->ro
= bdrv_is_read_only(pfl
->bs
);
613 pfl
->timer
= qemu_new_timer_ns(vm_clock
, pflash_timer
, pfl
);
617 /* Hardcoded CFI table */
619 /* Standard "QRY" string */
620 pfl
->cfi_table
[0x10] = 'Q';
621 pfl
->cfi_table
[0x11] = 'R';
622 pfl
->cfi_table
[0x12] = 'Y';
623 /* Command set (Intel) */
624 pfl
->cfi_table
[0x13] = 0x01;
625 pfl
->cfi_table
[0x14] = 0x00;
626 /* Primary extended table address (none) */
627 pfl
->cfi_table
[0x15] = 0x31;
628 pfl
->cfi_table
[0x16] = 0x00;
629 /* Alternate command set (none) */
630 pfl
->cfi_table
[0x17] = 0x00;
631 pfl
->cfi_table
[0x18] = 0x00;
632 /* Alternate extended table (none) */
633 pfl
->cfi_table
[0x19] = 0x00;
634 pfl
->cfi_table
[0x1A] = 0x00;
636 pfl
->cfi_table
[0x1B] = 0x45;
638 pfl
->cfi_table
[0x1C] = 0x55;
639 /* Vpp min (no Vpp pin) */
640 pfl
->cfi_table
[0x1D] = 0x00;
641 /* Vpp max (no Vpp pin) */
642 pfl
->cfi_table
[0x1E] = 0x00;
644 pfl
->cfi_table
[0x1F] = 0x07;
645 /* Timeout for min size buffer write */
646 pfl
->cfi_table
[0x20] = 0x07;
647 /* Typical timeout for block erase */
648 pfl
->cfi_table
[0x21] = 0x0a;
649 /* Typical timeout for full chip erase (4096 ms) */
650 pfl
->cfi_table
[0x22] = 0x00;
652 pfl
->cfi_table
[0x23] = 0x04;
653 /* Max timeout for buffer write */
654 pfl
->cfi_table
[0x24] = 0x04;
655 /* Max timeout for block erase */
656 pfl
->cfi_table
[0x25] = 0x04;
657 /* Max timeout for chip erase */
658 pfl
->cfi_table
[0x26] = 0x00;
660 pfl
->cfi_table
[0x27] = ctz32(total_len
); // + 1;
661 /* Flash device interface (8 & 16 bits) */
662 pfl
->cfi_table
[0x28] = 0x02;
663 pfl
->cfi_table
[0x29] = 0x00;
664 /* Max number of bytes in multi-bytes write */
665 if (pfl
->width
== 1) {
666 pfl
->cfi_table
[0x2A] = 0x08;
668 pfl
->cfi_table
[0x2A] = 0x0B;
670 pfl
->writeblock_size
= 1 << pfl
->cfi_table
[0x2A];
672 pfl
->cfi_table
[0x2B] = 0x00;
673 /* Number of erase block regions (uniform) */
674 pfl
->cfi_table
[0x2C] = 0x01;
675 /* Erase block region 1 */
676 pfl
->cfi_table
[0x2D] = pfl
->nb_blocs
- 1;
677 pfl
->cfi_table
[0x2E] = (pfl
->nb_blocs
- 1) >> 8;
678 pfl
->cfi_table
[0x2F] = pfl
->sector_len
>> 8;
679 pfl
->cfi_table
[0x30] = pfl
->sector_len
>> 16;
682 pfl
->cfi_table
[0x31] = 'P';
683 pfl
->cfi_table
[0x32] = 'R';
684 pfl
->cfi_table
[0x33] = 'I';
686 pfl
->cfi_table
[0x34] = '1';
687 pfl
->cfi_table
[0x35] = '0';
689 pfl
->cfi_table
[0x36] = 0x00;
690 pfl
->cfi_table
[0x37] = 0x00;
691 pfl
->cfi_table
[0x38] = 0x00;
692 pfl
->cfi_table
[0x39] = 0x00;
694 pfl
->cfi_table
[0x3a] = 0x00;
696 pfl
->cfi_table
[0x3b] = 0x00;
697 pfl
->cfi_table
[0x3c] = 0x00;
699 pfl
->cfi_table
[0x3f] = 0x01; /* Number of protection fields */
702 static Property pflash_cfi01_properties
[] = {
703 DEFINE_PROP_DRIVE("drive", struct pflash_t
, bs
),
704 DEFINE_PROP_UINT32("num-blocks", struct pflash_t
, nb_blocs
, 0),
705 DEFINE_PROP_UINT64("sector-length", struct pflash_t
, sector_len
, 0),
706 DEFINE_PROP_UINT8("width", struct pflash_t
, width
, 0),
707 DEFINE_PROP_UINT8("big-endian", struct pflash_t
, be
, 0),
708 DEFINE_PROP_UINT16("id0", struct pflash_t
, ident0
, 0),
709 DEFINE_PROP_UINT16("id1", struct pflash_t
, ident1
, 0),
710 DEFINE_PROP_UINT16("id2", struct pflash_t
, ident2
, 0),
711 DEFINE_PROP_UINT16("id3", struct pflash_t
, ident3
, 0),
712 DEFINE_PROP_STRING("name", struct pflash_t
, name
),
713 DEFINE_PROP_END_OF_LIST(),
716 static void pflash_cfi01_class_init(ObjectClass
*klass
, void *data
)
718 DeviceClass
*dc
= DEVICE_CLASS(klass
);
720 dc
->realize
= pflash_cfi01_realize
;
721 dc
->props
= pflash_cfi01_properties
;
722 dc
->vmsd
= &vmstate_pflash
;
726 static const TypeInfo pflash_cfi01_info
= {
727 .name
= TYPE_CFI_PFLASH01
,
728 .parent
= TYPE_SYS_BUS_DEVICE
,
729 .instance_size
= sizeof(struct pflash_t
),
730 .class_init
= pflash_cfi01_class_init
,
733 static void pflash_cfi01_register_types(void)
735 type_register_static(&pflash_cfi01_info
);
738 type_init(pflash_cfi01_register_types
)
740 pflash_t
*pflash_cfi01_register(hwaddr base
,
741 DeviceState
*qdev
, const char *name
,
743 BlockDriverState
*bs
,
744 uint32_t sector_len
, int nb_blocs
, int width
,
745 uint16_t id0
, uint16_t id1
,
746 uint16_t id2
, uint16_t id3
, int be
)
748 DeviceState
*dev
= qdev_create(NULL
, TYPE_CFI_PFLASH01
);
750 if (bs
&& qdev_prop_set_drive(dev
, "drive", bs
)) {
753 qdev_prop_set_uint32(dev
, "num-blocks", nb_blocs
);
754 qdev_prop_set_uint64(dev
, "sector-length", sector_len
);
755 qdev_prop_set_uint8(dev
, "width", width
);
756 qdev_prop_set_uint8(dev
, "big-endian", !!be
);
757 qdev_prop_set_uint16(dev
, "id0", id0
);
758 qdev_prop_set_uint16(dev
, "id1", id1
);
759 qdev_prop_set_uint16(dev
, "id2", id2
);
760 qdev_prop_set_uint16(dev
, "id3", id3
);
761 qdev_prop_set_string(dev
, "name", name
);
762 qdev_init_nofail(dev
);
764 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
765 return CFI_PFLASH01(dev
);
768 MemoryRegion
*pflash_cfi01_get_memory(pflash_t
*fl
)