hw/block/nvme.c

   1 /*
   2  * QEMU NVM Express Controller
   3  *
   4  * Copyright (c) 2012, Intel Corporation
   5  *
   6  * Written by Keith Busch <keith.busch@intel.com>
   7  *
   8  * This code is licensed under the GNU GPL v2 or later.
   9  */
  10
  11 /**
  12  * Reference Specs: http://www.nvmexpress.org, 1.1, 1.0e
  13  *
  14  *  http://www.nvmexpress.org/resources/
  15  */
  16
  17 /**
  18  * Usage: add options:
  19  *      -drive file=<file>,if=none,id=<drive_id>
  20  *      -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>
  21  */
  22
  23 #include <hw/block/block.h>
  24 #include <hw/hw.h>
  25 #include <hw/pci/msix.h>
  26 #include <hw/pci/pci.h>
  27 #include "sysemu/sysemu.h"
  28 #include "qapi/visitor.h"
  29 #include "sysemu/block-backend.h"
  30
  31 #include "nvme.h"
  32
  33 static void nvme_process_sq(void *opaque);
  34
  35 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
  36 {
  37     return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
  38 }
  39
  40 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
  41 {
  42     return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
  43 }
  44
  45 static void nvme_inc_cq_tail(NvmeCQueue *cq)
  46 {
  47     cq->tail++;
  48     if (cq->tail >= cq->size) {
  49         cq->tail = 0;
  50         cq->phase = !cq->phase;
  51     }
  52 }
  53
  54 static void nvme_inc_sq_head(NvmeSQueue *sq)
  55 {
  56     sq->head = (sq->head + 1) % sq->size;
  57 }
  58
  59 static uint8_t nvme_cq_full(NvmeCQueue *cq)
  60 {
  61     return (cq->tail + 1) % cq->size == cq->head;
  62 }
  63
  64 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
  65 {
  66     return sq->head == sq->tail;
  67 }
  68
  69 static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *cq)
  70 {
  71     if (cq->irq_enabled) {
  72         if (msix_enabled(&(n->parent_obj))) {
  73             msix_notify(&(n->parent_obj), cq->vector);
  74         } else {
  75             pci_irq_pulse(&n->parent_obj);
  76         }
  77     }
  78 }
  79
  80 static uint16_t nvme_map_prp(QEMUSGList *qsg, uint64_t prp1, uint64_t prp2,
  81     uint32_t len, NvmeCtrl *n)
  82 {
  83     hwaddr trans_len = n->page_size - (prp1 % n->page_size);
  84     trans_len = MIN(len, trans_len);
  85     int num_prps = (len >> n->page_bits) + 1;
  86
  87     if (!prp1) {
  88         return NVME_INVALID_FIELD | NVME_DNR;
  89     }
  90
  91     pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
  92     qemu_sglist_add(qsg, prp1, trans_len);
  93     len -= trans_len;
  94     if (len) {
  95         if (!prp2) {
  96             goto unmap;
  97         }
  98         if (len > n->page_size) {
  99             uint64_t prp_list[n->max_prp_ents];
 100             uint32_t nents, prp_trans;
 101             int i = 0;
 102
 103             nents = (len + n->page_size - 1) >> n->page_bits;
 104             prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 105             pci_dma_read(&n->parent_obj, prp2, (void *)prp_list, prp_trans);
 106             while (len != 0) {
 107                 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
 108
 109                 if (i == n->max_prp_ents - 1 && len > n->page_size) {
 110                     if (!prp_ent || prp_ent & (n->page_size - 1)) {
 111                         goto unmap;
 112                     }
 113
 114                     i = 0;
 115                     nents = (len + n->page_size - 1) >> n->page_bits;
 116                     prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 117                     pci_dma_read(&n->parent_obj, prp_ent, (void *)prp_list,
 118                         prp_trans);
 119                     prp_ent = le64_to_cpu(prp_list[i]);
 120                 }
 121
 122                 if (!prp_ent || prp_ent & (n->page_size - 1)) {
 123                     goto unmap;
 124                 }
 125
 126                 trans_len = MIN(len, n->page_size);
 127                 qemu_sglist_add(qsg, prp_ent, trans_len);
 128                 len -= trans_len;
 129                 i++;
 130             }
 131         } else {
 132             if (prp2 & (n->page_size - 1)) {
 133                 goto unmap;
 134             }
 135             qemu_sglist_add(qsg, prp2, len);
 136         }
 137     }
 138     return NVME_SUCCESS;
 139
 140  unmap:
 141     qemu_sglist_destroy(qsg);
 142     return NVME_INVALID_FIELD | NVME_DNR;
 143 }
 144
 145 static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
 146     uint64_t prp1, uint64_t prp2)
 147 {
 148     QEMUSGList qsg;
 149
 150     if (nvme_map_prp(&qsg, prp1, prp2, len, n)) {
 151         return NVME_INVALID_FIELD | NVME_DNR;
 152     }
 153     if (dma_buf_read(ptr, len, &qsg)) {
 154         qemu_sglist_destroy(&qsg);
 155         return NVME_INVALID_FIELD | NVME_DNR;
 156     }
 157     qemu_sglist_destroy(&qsg);
 158     return NVME_SUCCESS;
 159 }
 160
 161 static void nvme_post_cqes(void *opaque)
 162 {
 163     NvmeCQueue *cq = opaque;
 164     NvmeCtrl *n = cq->ctrl;
 165     NvmeRequest *req, *next;
 166
 167     QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 168         NvmeSQueue *sq;
 169         hwaddr addr;
 170
 171         if (nvme_cq_full(cq)) {
 172             break;
 173         }
 174
 175         QTAILQ_REMOVE(&cq->req_list, req, entry);
 176         sq = req->sq;
 177         req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
 178         req->cqe.sq_id = cpu_to_le16(sq->sqid);
 179         req->cqe.sq_head = cpu_to_le16(sq->head);
 180         addr = cq->dma_addr + cq->tail * n->cqe_size;
 181         nvme_inc_cq_tail(cq);
 182         pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
 183             sizeof(req->cqe));
 184         QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 185     }
 186     nvme_isr_notify(n, cq);
 187 }
 188
 189 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
 190 {
 191     assert(cq->cqid == req->sq->cqid);
 192     QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
 193     QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
 194     timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 195 }
 196
 197 static void nvme_rw_cb(void *opaque, int ret)
 198 {
 199     NvmeRequest *req = opaque;
 200     NvmeSQueue *sq = req->sq;
 201     NvmeCtrl *n = sq->ctrl;
 202     NvmeCQueue *cq = n->cq[sq->cqid];
 203
 204     block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
 205     if (!ret) {
 206         req->status = NVME_SUCCESS;
 207     } else {
 208         req->status = NVME_INTERNAL_DEV_ERROR;
 209     }
 210
 211     qemu_sglist_destroy(&req->qsg);
 212     nvme_enqueue_req_completion(cq, req);
 213 }
 214
 215 static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 216     NvmeRequest *req)
 217 {
 218     NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
 219     uint32_t nlb  = le32_to_cpu(rw->nlb) + 1;
 220     uint64_t slba = le64_to_cpu(rw->slba);
 221     uint64_t prp1 = le64_to_cpu(rw->prp1);
 222     uint64_t prp2 = le64_to_cpu(rw->prp2);
 223
 224     uint8_t lba_index  = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
 225     uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
 226     uint64_t data_size = (uint64_t)nlb << data_shift;
 227     uint64_t aio_slba  = slba << (data_shift - BDRV_SECTOR_BITS);
 228     int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
 229
 230     if ((slba + nlb) > ns->id_ns.nsze) {
 231         return NVME_LBA_RANGE | NVME_DNR;
 232     }
 233     if (nvme_map_prp(&req->qsg, prp1, prp2, data_size, n)) {
 234         return NVME_INVALID_FIELD | NVME_DNR;
 235     }
 236     assert((nlb << data_shift) == req->qsg.size);
 237
 238     dma_acct_start(n->conf.blk, &req->acct, &req->qsg,
 239                    is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ);
 240     req->aiocb = is_write ?
 241         dma_blk_write(n->conf.blk, &req->qsg, aio_slba, nvme_rw_cb, req) :
 242         dma_blk_read(n->conf.blk, &req->qsg, aio_slba, nvme_rw_cb, req);
 243
 244     return NVME_NO_COMPLETE;
 245 }
 246
 247 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 248 {
 249     NvmeNamespace *ns;
 250     uint32_t nsid = le32_to_cpu(cmd->nsid);
 251
 252     if (nsid == 0 || nsid > n->num_namespaces) {
 253         return NVME_INVALID_NSID | NVME_DNR;
 254     }
 255
 256     ns = &n->namespaces[nsid - 1];
 257     switch (cmd->opcode) {
 258     case NVME_CMD_FLUSH:
 259         return NVME_SUCCESS;
 260     case NVME_CMD_WRITE:
 261     case NVME_CMD_READ:
 262         return nvme_rw(n, ns, cmd, req);
 263     default:
 264         return NVME_INVALID_OPCODE | NVME_DNR;
 265     }
 266 }
 267
 268 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
 269 {
 270     n->sq[sq->sqid] = NULL;
 271     timer_del(sq->timer);
 272     timer_free(sq->timer);
 273     g_free(sq->io_req);
 274     if (sq->sqid) {
 275         g_free(sq);
 276     }
 277 }
 278
 279 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd)
 280 {
 281     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 282     NvmeRequest *req, *next;
 283     NvmeSQueue *sq;
 284     NvmeCQueue *cq;
 285     uint16_t qid = le16_to_cpu(c->qid);
 286
 287     if (!qid || nvme_check_sqid(n, qid)) {
 288         return NVME_INVALID_QID | NVME_DNR;
 289     }
 290
 291     sq = n->sq[qid];
 292     while (!QTAILQ_EMPTY(&sq->out_req_list)) {
 293         req = QTAILQ_FIRST(&sq->out_req_list);
 294         assert(req->aiocb);
 295         blk_aio_cancel(req->aiocb);
 296     }
 297     if (!nvme_check_cqid(n, sq->cqid)) {
 298         cq = n->cq[sq->cqid];
 299         QTAILQ_REMOVE(&cq->sq_list, sq, entry);
 300
 301         nvme_post_cqes(cq);
 302         QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 303             if (req->sq == sq) {
 304                 QTAILQ_REMOVE(&cq->req_list, req, entry);
 305                 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 306             }
 307         }
 308     }
 309
 310     nvme_free_sq(sq, n);
 311     return NVME_SUCCESS;
 312 }
 313
 314 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
 315     uint16_t sqid, uint16_t cqid, uint16_t size)
 316 {
 317     int i;
 318     NvmeCQueue *cq;
 319
 320     sq->ctrl = n;
 321     sq->dma_addr = dma_addr;
 322     sq->sqid = sqid;
 323     sq->size = size;
 324     sq->cqid = cqid;
 325     sq->head = sq->tail = 0;
 326     sq->io_req = g_new(NvmeRequest, sq->size);
 327
 328     QTAILQ_INIT(&sq->req_list);
 329     QTAILQ_INIT(&sq->out_req_list);
 330     for (i = 0; i < sq->size; i++) {
 331         sq->io_req[i].sq = sq;
 332         QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
 333     }
 334     sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
 335
 336     assert(n->cq[cqid]);
 337     cq = n->cq[cqid];
 338     QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
 339     n->sq[sqid] = sq;
 340 }
 341
 342 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
 343 {
 344     NvmeSQueue *sq;
 345     NvmeCreateSq *c = (NvmeCreateSq *)cmd;
 346
 347     uint16_t cqid = le16_to_cpu(c->cqid);
 348     uint16_t sqid = le16_to_cpu(c->sqid);
 349     uint16_t qsize = le16_to_cpu(c->qsize);
 350     uint16_t qflags = le16_to_cpu(c->sq_flags);
 351     uint64_t prp1 = le64_to_cpu(c->prp1);
 352
 353     if (!cqid || nvme_check_cqid(n, cqid)) {
 354         return NVME_INVALID_CQID | NVME_DNR;
 355     }
 356     if (!sqid || (sqid && !nvme_check_sqid(n, sqid))) {
 357         return NVME_INVALID_QID | NVME_DNR;
 358     }
 359     if (!qsize || qsize > NVME_CAP_MQES(n->bar.cap)) {
 360         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 361     }
 362     if (!prp1 || prp1 & (n->page_size - 1)) {
 363         return NVME_INVALID_FIELD | NVME_DNR;
 364     }
 365     if (!(NVME_SQ_FLAGS_PC(qflags))) {
 366         return NVME_INVALID_FIELD | NVME_DNR;
 367     }
 368     sq = g_malloc0(sizeof(*sq));
 369     nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
 370     return NVME_SUCCESS;
 371 }
 372
 373 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
 374 {
 375     n->cq[cq->cqid] = NULL;
 376     timer_del(cq->timer);
 377     timer_free(cq->timer);
 378     msix_vector_unuse(&n->parent_obj, cq->vector);
 379     if (cq->cqid) {
 380         g_free(cq);
 381     }
 382 }
 383
 384 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd)
 385 {
 386     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 387     NvmeCQueue *cq;
 388     uint16_t qid = le16_to_cpu(c->qid);
 389
 390     if (!qid || nvme_check_cqid(n, qid)) {
 391         return NVME_INVALID_CQID | NVME_DNR;
 392     }
 393
 394     cq = n->cq[qid];
 395     if (!QTAILQ_EMPTY(&cq->sq_list)) {
 396         return NVME_INVALID_QUEUE_DEL;
 397     }
 398     nvme_free_cq(cq, n);
 399     return NVME_SUCCESS;
 400 }
 401
 402 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
 403     uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
 404 {
 405     cq->ctrl = n;
 406     cq->cqid = cqid;
 407     cq->size = size;
 408     cq->dma_addr = dma_addr;
 409     cq->phase = 1;
 410     cq->irq_enabled = irq_enabled;
 411     cq->vector = vector;
 412     cq->head = cq->tail = 0;
 413     QTAILQ_INIT(&cq->req_list);
 414     QTAILQ_INIT(&cq->sq_list);
 415     msix_vector_use(&n->parent_obj, cq->vector);
 416     n->cq[cqid] = cq;
 417     cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
 418 }
 419
 420 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
 421 {
 422     NvmeCQueue *cq;
 423     NvmeCreateCq *c = (NvmeCreateCq *)cmd;
 424     uint16_t cqid = le16_to_cpu(c->cqid);
 425     uint16_t vector = le16_to_cpu(c->irq_vector);
 426     uint16_t qsize = le16_to_cpu(c->qsize);
 427     uint16_t qflags = le16_to_cpu(c->cq_flags);
 428     uint64_t prp1 = le64_to_cpu(c->prp1);
 429
 430     if (!cqid || (cqid && !nvme_check_cqid(n, cqid))) {
 431         return NVME_INVALID_CQID | NVME_DNR;
 432     }
 433     if (!qsize || qsize > NVME_CAP_MQES(n->bar.cap)) {
 434         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 435     }
 436     if (!prp1) {
 437         return NVME_INVALID_FIELD | NVME_DNR;
 438     }
 439     if (vector > n->num_queues) {
 440         return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
 441     }
 442     if (!(NVME_CQ_FLAGS_PC(qflags))) {
 443         return NVME_INVALID_FIELD | NVME_DNR;
 444     }
 445
 446     cq = g_malloc0(sizeof(*cq));
 447     nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
 448         NVME_CQ_FLAGS_IEN(qflags));
 449     return NVME_SUCCESS;
 450 }
 451
 452 static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
 453 {
 454     NvmeNamespace *ns;
 455     NvmeIdentify *c = (NvmeIdentify *)cmd;
 456     uint32_t cns  = le32_to_cpu(c->cns);
 457     uint32_t nsid = le32_to_cpu(c->nsid);
 458     uint64_t prp1 = le64_to_cpu(c->prp1);
 459     uint64_t prp2 = le64_to_cpu(c->prp2);
 460
 461     if (cns) {
 462         return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
 463             prp1, prp2);
 464     }
 465     if (nsid == 0 || nsid > n->num_namespaces) {
 466         return NVME_INVALID_NSID | NVME_DNR;
 467     }
 468
 469     ns = &n->namespaces[nsid - 1];
 470     return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
 471         prp1, prp2);
 472 }
 473
 474 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 475 {
 476     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 477
 478     switch (dw10) {
 479     case NVME_NUMBER_OF_QUEUES:
 480         req->cqe.result =
 481             cpu_to_le32((n->num_queues - 1) | ((n->num_queues - 1) << 16));
 482         break;
 483     case NVME_VOLATILE_WRITE_CACHE:
 484         req->cqe.result = cpu_to_le32(1);
 485         break;
 486     default:
 487         return NVME_INVALID_FIELD | NVME_DNR;
 488     }
 489     return NVME_SUCCESS;
 490 }
 491
 492 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 493 {
 494     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 495
 496     switch (dw10) {
 497     case NVME_NUMBER_OF_QUEUES:
 498         req->cqe.result =
 499             cpu_to_le32((n->num_queues - 1) | ((n->num_queues - 1) << 16));
 500         break;
 501     default:
 502         return NVME_INVALID_FIELD | NVME_DNR;
 503     }
 504     return NVME_SUCCESS;
 505 }
 506
 507 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 508 {
 509     switch (cmd->opcode) {
 510     case NVME_ADM_CMD_DELETE_SQ:
 511         return nvme_del_sq(n, cmd);
 512     case NVME_ADM_CMD_CREATE_SQ:
 513         return nvme_create_sq(n, cmd);
 514     case NVME_ADM_CMD_DELETE_CQ:
 515         return nvme_del_cq(n, cmd);
 516     case NVME_ADM_CMD_CREATE_CQ:
 517         return nvme_create_cq(n, cmd);
 518     case NVME_ADM_CMD_IDENTIFY:
 519         return nvme_identify(n, cmd);
 520     case NVME_ADM_CMD_SET_FEATURES:
 521         return nvme_set_feature(n, cmd, req);
 522     case NVME_ADM_CMD_GET_FEATURES:
 523         return nvme_get_feature(n, cmd, req);
 524     default:
 525         return NVME_INVALID_OPCODE | NVME_DNR;
 526     }
 527 }
 528
 529 static void nvme_process_sq(void *opaque)
 530 {
 531     NvmeSQueue *sq = opaque;
 532     NvmeCtrl *n = sq->ctrl;
 533     NvmeCQueue *cq = n->cq[sq->cqid];
 534
 535     uint16_t status;
 536     hwaddr addr;
 537     NvmeCmd cmd;
 538     NvmeRequest *req;
 539
 540     while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
 541         addr = sq->dma_addr + sq->head * n->sqe_size;
 542         pci_dma_read(&n->parent_obj, addr, (void *)&cmd, sizeof(cmd));
 543         nvme_inc_sq_head(sq);
 544
 545         req = QTAILQ_FIRST(&sq->req_list);
 546         QTAILQ_REMOVE(&sq->req_list, req, entry);
 547         QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
 548         memset(&req->cqe, 0, sizeof(req->cqe));
 549         req->cqe.cid = cmd.cid;
 550
 551         status = sq->sqid ? nvme_io_cmd(n, &cmd, req) :
 552             nvme_admin_cmd(n, &cmd, req);
 553         if (status != NVME_NO_COMPLETE) {
 554             req->status = status;
 555             nvme_enqueue_req_completion(cq, req);
 556         }
 557     }
 558 }
 559
 560 static void nvme_clear_ctrl(NvmeCtrl *n)
 561 {
 562     int i;
 563
 564     for (i = 0; i < n->num_queues; i++) {
 565         if (n->sq[i] != NULL) {
 566             nvme_free_sq(n->sq[i], n);
 567         }
 568     }
 569     for (i = 0; i < n->num_queues; i++) {
 570         if (n->cq[i] != NULL) {
 571             nvme_free_cq(n->cq[i], n);
 572         }
 573     }
 574
 575     blk_flush(n->conf.blk);
 576     n->bar.cc = 0;
 577 }
 578
 579 static int nvme_start_ctrl(NvmeCtrl *n)
 580 {
 581     uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
 582     uint32_t page_size = 1 << page_bits;
 583
 584     if (n->cq[0] || n->sq[0] || !n->bar.asq || !n->bar.acq ||
 585             n->bar.asq & (page_size - 1) || n->bar.acq & (page_size - 1) ||
 586             NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap) ||
 587             NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap) ||
 588             NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes) ||
 589             NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes) ||
 590             NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes) ||
 591             NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes) ||
 592             !NVME_AQA_ASQS(n->bar.aqa) || !NVME_AQA_ACQS(n->bar.aqa)) {
 593         return -1;
 594     }
 595
 596     n->page_bits = page_bits;
 597     n->page_size = page_size;
 598     n->max_prp_ents = n->page_size / sizeof(uint64_t);
 599     n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
 600     n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
 601     nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
 602         NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
 603     nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
 604         NVME_AQA_ASQS(n->bar.aqa) + 1);
 605
 606     return 0;
 607 }
 608
 609 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
 610     unsigned size)
 611 {
 612     switch (offset) {
 613     case 0xc:
 614         n->bar.intms |= data & 0xffffffff;
 615         n->bar.intmc = n->bar.intms;
 616         break;
 617     case 0x10:
 618         n->bar.intms &= ~(data & 0xffffffff);
 619         n->bar.intmc = n->bar.intms;
 620         break;
 621     case 0x14:
 622         /* Windows first sends data, then sends enable bit */
 623         if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
 624             !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
 625         {
 626             n->bar.cc = data;
 627         }
 628
 629         if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
 630             n->bar.cc = data;
 631             if (nvme_start_ctrl(n)) {
 632                 n->bar.csts = NVME_CSTS_FAILED;
 633             } else {
 634                 n->bar.csts = NVME_CSTS_READY;
 635             }
 636         } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
 637             nvme_clear_ctrl(n);
 638             n->bar.csts &= ~NVME_CSTS_READY;
 639         }
 640         if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
 641                 nvme_clear_ctrl(n);
 642                 n->bar.cc = data;
 643                 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
 644         } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
 645                 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
 646                 n->bar.cc = data;
 647         }
 648         break;
 649     case 0x24:
 650         n->bar.aqa = data & 0xffffffff;
 651         break;
 652     case 0x28:
 653         n->bar.asq = data;
 654         break;
 655     case 0x2c:
 656         n->bar.asq |= data << 32;
 657         break;
 658     case 0x30:
 659         n->bar.acq = data;
 660         break;
 661     case 0x34:
 662         n->bar.acq |= data << 32;
 663         break;
 664     default:
 665         break;
 666     }
 667 }
 668
 669 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
 670 {
 671     NvmeCtrl *n = (NvmeCtrl *)opaque;
 672     uint8_t *ptr = (uint8_t *)&n->bar;
 673     uint64_t val = 0;
 674
 675     if (addr < sizeof(n->bar)) {
 676         memcpy(&val, ptr + addr, size);
 677     }
 678     return val;
 679 }
 680
 681 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
 682 {
 683     uint32_t qid;
 684
 685     if (addr & ((1 << 2) - 1)) {
 686         return;
 687     }
 688
 689     if (((addr - 0x1000) >> 2) & 1) {
 690         uint16_t new_head = val & 0xffff;
 691         int start_sqs;
 692         NvmeCQueue *cq;
 693
 694         qid = (addr - (0x1000 + (1 << 2))) >> 3;
 695         if (nvme_check_cqid(n, qid)) {
 696             return;
 697         }
 698
 699         cq = n->cq[qid];
 700         if (new_head >= cq->size) {
 701             return;
 702         }
 703
 704         start_sqs = nvme_cq_full(cq) ? 1 : 0;
 705         cq->head = new_head;
 706         if (start_sqs) {
 707             NvmeSQueue *sq;
 708             QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
 709                 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 710             }
 711             timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 712         }
 713
 714         if (cq->tail != cq->head) {
 715             nvme_isr_notify(n, cq);
 716         }
 717     } else {
 718         uint16_t new_tail = val & 0xffff;
 719         NvmeSQueue *sq;
 720
 721         qid = (addr - 0x1000) >> 3;
 722         if (nvme_check_sqid(n, qid)) {
 723             return;
 724         }
 725
 726         sq = n->sq[qid];
 727         if (new_tail >= sq->size) {
 728             return;
 729         }
 730
 731         sq->tail = new_tail;
 732         timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 733     }
 734 }
 735
 736 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
 737     unsigned size)
 738 {
 739     NvmeCtrl *n = (NvmeCtrl *)opaque;
 740     if (addr < sizeof(n->bar)) {
 741         nvme_write_bar(n, addr, data, size);
 742     } else if (addr >= 0x1000) {
 743         nvme_process_db(n, addr, data);
 744     }
 745 }
 746
 747 static const MemoryRegionOps nvme_mmio_ops = {
 748     .read = nvme_mmio_read,
 749     .write = nvme_mmio_write,
 750     .endianness = DEVICE_LITTLE_ENDIAN,
 751     .impl = {
 752         .min_access_size = 2,
 753         .max_access_size = 8,
 754     },
 755 };
 756
 757 static int nvme_init(PCIDevice *pci_dev)
 758 {
 759     NvmeCtrl *n = NVME(pci_dev);
 760     NvmeIdCtrl *id = &n->id_ctrl;
 761
 762     int i;
 763     int64_t bs_size;
 764     uint8_t *pci_conf;
 765
 766     if (!n->conf.blk) {
 767         return -1;
 768     }
 769
 770     bs_size = blk_getlength(n->conf.blk);
 771     if (bs_size < 0) {
 772         return -1;
 773     }
 774
 775     blkconf_serial(&n->conf, &n->serial);
 776     if (!n->serial) {
 777         return -1;
 778     }
 779     blkconf_blocksizes(&n->conf);
 780
 781     pci_conf = pci_dev->config;
 782     pci_conf[PCI_INTERRUPT_PIN] = 1;
 783     pci_config_set_prog_interface(pci_dev->config, 0x2);
 784     pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS);
 785     pcie_endpoint_cap_init(&n->parent_obj, 0x80);
 786
 787     n->num_namespaces = 1;
 788     n->num_queues = 64;
 789     n->reg_size = 1 << qemu_fls(0x1004 + 2 * (n->num_queues + 1) * 4);
 790     n->ns_size = bs_size / (uint64_t)n->num_namespaces;
 791
 792     n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
 793     n->sq = g_new0(NvmeSQueue *, n->num_queues);
 794     n->cq = g_new0(NvmeCQueue *, n->num_queues);
 795
 796     memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n,
 797                           "nvme", n->reg_size);
 798     pci_register_bar(&n->parent_obj, 0,
 799         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
 800         &n->iomem);
 801     msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4);
 802
 803     id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
 804     id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
 805     strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
 806     strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
 807     strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' ');
 808     id->rab = 6;
 809     id->ieee[0] = 0x00;
 810     id->ieee[1] = 0x02;
 811     id->ieee[2] = 0xb3;
 812     id->oacs = cpu_to_le16(0);
 813     id->frmw = 7 << 1;
 814     id->lpa = 1 << 0;
 815     id->sqes = (0x6 << 4) | 0x6;
 816     id->cqes = (0x4 << 4) | 0x4;
 817     id->nn = cpu_to_le32(n->num_namespaces);
 818     id->psd[0].mp = cpu_to_le16(0x9c4);
 819     id->psd[0].enlat = cpu_to_le32(0x10);
 820     id->psd[0].exlat = cpu_to_le32(0x4);
 821
 822     n->bar.cap = 0;
 823     NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
 824     NVME_CAP_SET_CQR(n->bar.cap, 1);
 825     NVME_CAP_SET_AMS(n->bar.cap, 1);
 826     NVME_CAP_SET_TO(n->bar.cap, 0xf);
 827     NVME_CAP_SET_CSS(n->bar.cap, 1);
 828     NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
 829
 830     n->bar.vs = 0x00010100;
 831     n->bar.intmc = n->bar.intms = 0;
 832
 833     for (i = 0; i < n->num_namespaces; i++) {
 834         NvmeNamespace *ns = &n->namespaces[i];
 835         NvmeIdNs *id_ns = &ns->id_ns;
 836         id_ns->nsfeat = 0;
 837         id_ns->nlbaf = 0;
 838         id_ns->flbas = 0;
 839         id_ns->mc = 0;
 840         id_ns->dpc = 0;
 841         id_ns->dps = 0;
 842         id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
 843         id_ns->ncap  = id_ns->nuse = id_ns->nsze =
 844             cpu_to_le64(n->ns_size >>
 845                 id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds);
 846     }
 847     return 0;
 848 }
 849
 850 static void nvme_exit(PCIDevice *pci_dev)
 851 {
 852     NvmeCtrl *n = NVME(pci_dev);
 853
 854     nvme_clear_ctrl(n);
 855     g_free(n->namespaces);
 856     g_free(n->cq);
 857     g_free(n->sq);
 858     msix_uninit_exclusive_bar(pci_dev);
 859 }
 860
 861 static Property nvme_props[] = {
 862     DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
 863     DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
 864     DEFINE_PROP_END_OF_LIST(),
 865 };
 866
 867 static const VMStateDescription nvme_vmstate = {
 868     .name = "nvme",
 869     .unmigratable = 1,
 870 };
 871
 872 static void nvme_class_init(ObjectClass *oc, void *data)
 873 {
 874     DeviceClass *dc = DEVICE_CLASS(oc);
 875     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
 876
 877     pc->init = nvme_init;
 878     pc->exit = nvme_exit;
 879     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
 880     pc->vendor_id = PCI_VENDOR_ID_INTEL;
 881     pc->device_id = 0x5845;
 882     pc->revision = 1;
 883     pc->is_express = 1;
 884
 885     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 886     dc->desc = "Non-Volatile Memory Express";
 887     dc->props = nvme_props;
 888     dc->vmsd = &nvme_vmstate;
 889 }
 890
 891 static void nvme_get_bootindex(Object *obj, Visitor *v, void *opaque,
 892                                   const char *name, Error **errp)
 893 {
 894     NvmeCtrl *s = NVME(obj);
 895
 896     visit_type_int32(v, &s->conf.bootindex, name, errp);
 897 }
 898
 899 static void nvme_set_bootindex(Object *obj, Visitor *v, void *opaque,
 900                                   const char *name, Error **errp)
 901 {
 902     NvmeCtrl *s = NVME(obj);
 903     int32_t boot_index;
 904     Error *local_err = NULL;
 905
 906     visit_type_int32(v, &boot_index, name, &local_err);
 907     if (local_err) {
 908         goto out;
 909     }
 910     /* check whether bootindex is present in fw_boot_order list  */
 911     check_boot_index(boot_index, &local_err);
 912     if (local_err) {
 913         goto out;
 914     }
 915     /* change bootindex to a new one */
 916     s->conf.bootindex = boot_index;
 917
 918 out:
 919     if (local_err) {
 920         error_propagate(errp, local_err);
 921     }
 922 }
 923
 924 static void nvme_instance_init(Object *obj)
 925 {
 926     object_property_add(obj, "bootindex", "int32",
 927                         nvme_get_bootindex,
 928                         nvme_set_bootindex, NULL, NULL, NULL);
 929     object_property_set_int(obj, -1, "bootindex", NULL);
 930 }
 931
 932 static const TypeInfo nvme_info = {
 933     .name          = "nvme",
 934     .parent        = TYPE_PCI_DEVICE,
 935     .instance_size = sizeof(NvmeCtrl),
 936     .class_init    = nvme_class_init,
 937     .instance_init = nvme_instance_init,
 938 };
 939
 940 static void nvme_register_types(void)
 941 {
 942     type_register_static(&nvme_info);
 943 }
 944
 945 type_init(nvme_register_types)