hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "cpu.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/xics.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qapi/visitor.h"
  38 #include "migration/vmstate.h"
  39 #include "monitor/monitor.h"
  40 #include "hw/intc/intc.h"
  41 #include "hw/irq.h"
  42 #include "sysemu/kvm.h"
  43 #include "sysemu/reset.h"
  44
  45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  46 {
  47     int cpu_index;
  48
  49     /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
  50      * are hot plugged or unplugged.
  51      */
  52     if (!icp) {
  53         return;
  54     }
  55
  56     cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  57
  58     if (!icp->output) {
  59         return;
  60     }
  61
  62     if (kvm_irqchip_in_kernel()) {
  63         icp_synchronize_state(icp);
  64     }
  65
  66     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  67                    cpu_index, icp->xirr, icp->xirr_owner,
  68                    icp->pending_priority, icp->mfrr);
  69 }
  70
  71 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  72 {
  73     uint32_t i;
  74
  75     monitor_printf(mon, "ICS %4x..%4x %p\n",
  76                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  77
  78     if (!ics->irqs) {
  79         return;
  80     }
  81
  82     if (kvm_irqchip_in_kernel()) {
  83         ics_synchronize_state(ics);
  84     }
  85
  86     for (i = 0; i < ics->nr_irqs; i++) {
  87         ICSIRQState *irq = ics->irqs + i;
  88
  89         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  90             continue;
  91         }
  92         monitor_printf(mon, "  %4x %s %02x %02x\n",
  93                        ics->offset + i,
  94                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  95                        "LSI" : "MSI",
  96                        irq->priority, irq->status);
  97     }
  98 }
  99
 100 /*
 101  * ICP: Presentation layer
 102  */
 103
 104 #define XISR_MASK  0x00ffffff
 105 #define CPPR_MASK  0xff000000
 106
 107 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
 108 #define CPPR(icp)   (((icp)->xirr) >> 24)
 109
 110 static void ics_reject(ICSState *ics, uint32_t nr);
 111 static void ics_eoi(ICSState *ics, uint32_t nr);
 112
 113 static void icp_check_ipi(ICPState *icp)
 114 {
 115     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 116         return;
 117     }
 118
 119     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 120
 121     if (XISR(icp) && icp->xirr_owner) {
 122         ics_reject(icp->xirr_owner, XISR(icp));
 123     }
 124
 125     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 126     icp->pending_priority = icp->mfrr;
 127     icp->xirr_owner = NULL;
 128     qemu_irq_raise(icp->output);
 129 }
 130
 131 void icp_resend(ICPState *icp)
 132 {
 133     XICSFabric *xi = icp->xics;
 134     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 135
 136     if (icp->mfrr < CPPR(icp)) {
 137         icp_check_ipi(icp);
 138     }
 139
 140     xic->ics_resend(xi);
 141 }
 142
 143 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 144 {
 145     uint8_t old_cppr;
 146     uint32_t old_xisr;
 147
 148     old_cppr = CPPR(icp);
 149     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 150
 151     if (cppr < old_cppr) {
 152         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 153             old_xisr = XISR(icp);
 154             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 155             icp->pending_priority = 0xff;
 156             qemu_irq_lower(icp->output);
 157             if (icp->xirr_owner) {
 158                 ics_reject(icp->xirr_owner, old_xisr);
 159                 icp->xirr_owner = NULL;
 160             }
 161         }
 162     } else {
 163         if (!XISR(icp)) {
 164             icp_resend(icp);
 165         }
 166     }
 167 }
 168
 169 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 170 {
 171     icp->mfrr = mfrr;
 172     if (mfrr < CPPR(icp)) {
 173         icp_check_ipi(icp);
 174     }
 175 }
 176
 177 uint32_t icp_accept(ICPState *icp)
 178 {
 179     uint32_t xirr = icp->xirr;
 180
 181     qemu_irq_lower(icp->output);
 182     icp->xirr = icp->pending_priority << 24;
 183     icp->pending_priority = 0xff;
 184     icp->xirr_owner = NULL;
 185
 186     trace_xics_icp_accept(xirr, icp->xirr);
 187
 188     return xirr;
 189 }
 190
 191 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 192 {
 193     if (mfrr) {
 194         *mfrr = icp->mfrr;
 195     }
 196     return icp->xirr;
 197 }
 198
 199 void icp_eoi(ICPState *icp, uint32_t xirr)
 200 {
 201     XICSFabric *xi = icp->xics;
 202     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 203     ICSState *ics;
 204     uint32_t irq;
 205
 206     /* Send EOI -> ICS */
 207     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 208     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 209     irq = xirr & XISR_MASK;
 210
 211     ics = xic->ics_get(xi, irq);
 212     if (ics) {
 213         ics_eoi(ics, irq);
 214     }
 215     if (!XISR(icp)) {
 216         icp_resend(icp);
 217     }
 218 }
 219
 220 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 221 {
 222     ICPState *icp = xics_icp_get(ics->xics, server);
 223
 224     trace_xics_icp_irq(server, nr, priority);
 225
 226     if ((priority >= CPPR(icp))
 227         || (XISR(icp) && (icp->pending_priority <= priority))) {
 228         ics_reject(ics, nr);
 229     } else {
 230         if (XISR(icp) && icp->xirr_owner) {
 231             ics_reject(icp->xirr_owner, XISR(icp));
 232             icp->xirr_owner = NULL;
 233         }
 234         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 235         icp->xirr_owner = ics;
 236         icp->pending_priority = priority;
 237         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 238         qemu_irq_raise(icp->output);
 239     }
 240 }
 241
 242 static int icp_pre_save(void *opaque)
 243 {
 244     ICPState *icp = opaque;
 245
 246     if (kvm_irqchip_in_kernel()) {
 247         icp_get_kvm_state(icp);
 248     }
 249
 250     return 0;
 251 }
 252
 253 static int icp_post_load(void *opaque, int version_id)
 254 {
 255     ICPState *icp = opaque;
 256
 257     if (kvm_irqchip_in_kernel()) {
 258         Error *local_err = NULL;
 259         int ret;
 260
 261         ret = icp_set_kvm_state(icp, &local_err);
 262         if (ret < 0) {
 263             error_report_err(local_err);
 264             return ret;
 265         }
 266     }
 267
 268     return 0;
 269 }
 270
 271 static const VMStateDescription vmstate_icp_server = {
 272     .name = "icp/server",
 273     .version_id = 1,
 274     .minimum_version_id = 1,
 275     .pre_save = icp_pre_save,
 276     .post_load = icp_post_load,
 277     .fields = (VMStateField[]) {
 278         /* Sanity check */
 279         VMSTATE_UINT32(xirr, ICPState),
 280         VMSTATE_UINT8(pending_priority, ICPState),
 281         VMSTATE_UINT8(mfrr, ICPState),
 282         VMSTATE_END_OF_LIST()
 283     },
 284 };
 285
 286 void icp_reset(ICPState *icp)
 287 {
 288     icp->xirr = 0;
 289     icp->pending_priority = 0xff;
 290     icp->mfrr = 0xff;
 291
 292     /* Make all outputs are deasserted */
 293     qemu_set_irq(icp->output, 0);
 294
 295     if (kvm_irqchip_in_kernel()) {
 296         Error *local_err = NULL;
 297
 298         icp_set_kvm_state(icp, &local_err);
 299         if (local_err) {
 300             error_report_err(local_err);
 301         }
 302     }
 303 }
 304
 305 static void icp_realize(DeviceState *dev, Error **errp)
 306 {
 307     ICPState *icp = ICP(dev);
 308     CPUPPCState *env;
 309     Error *err = NULL;
 310
 311     assert(icp->xics);
 312     assert(icp->cs);
 313
 314     env = &POWERPC_CPU(icp->cs)->env;
 315     switch (PPC_INPUT(env)) {
 316     case PPC_FLAGS_INPUT_POWER7:
 317         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 318         break;
 319     case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
 320         icp->output = env->irq_inputs[POWER9_INPUT_INT];
 321         break;
 322
 323     case PPC_FLAGS_INPUT_970:
 324         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 325         break;
 326
 327     default:
 328         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 329         return;
 330     }
 331
 332     /* Connect the presenter to the VCPU (required for CPU hotplug) */
 333     if (kvm_irqchip_in_kernel()) {
 334         icp_kvm_realize(dev, &err);
 335         if (err) {
 336             error_propagate(errp, err);
 337             return;
 338         }
 339     }
 340
 341     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 342 }
 343
 344 static void icp_unrealize(DeviceState *dev, Error **errp)
 345 {
 346     ICPState *icp = ICP(dev);
 347
 348     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 349 }
 350
 351 static Property icp_properties[] = {
 352     DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
 353                      XICSFabric *),
 354     DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *),
 355     DEFINE_PROP_END_OF_LIST(),
 356 };
 357
 358 static void icp_class_init(ObjectClass *klass, void *data)
 359 {
 360     DeviceClass *dc = DEVICE_CLASS(klass);
 361
 362     dc->realize = icp_realize;
 363     dc->unrealize = icp_unrealize;
 364     dc->props = icp_properties;
 365     /*
 366      * Reason: part of XICS interrupt controller, needs to be wired up
 367      * by icp_create().
 368      */
 369     dc->user_creatable = false;
 370 }
 371
 372 static const TypeInfo icp_info = {
 373     .name = TYPE_ICP,
 374     .parent = TYPE_DEVICE,
 375     .instance_size = sizeof(ICPState),
 376     .class_init = icp_class_init,
 377     .class_size = sizeof(ICPStateClass),
 378 };
 379
 380 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 381 {
 382     Error *local_err = NULL;
 383     Object *obj;
 384
 385     obj = object_new(type);
 386     object_property_add_child(cpu, type, obj, &error_abort);
 387     object_unref(obj);
 388     object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort);
 389     object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort);
 390     object_property_set_bool(obj, true, "realized", &local_err);
 391     if (local_err) {
 392         object_unparent(obj);
 393         error_propagate(errp, local_err);
 394         obj = NULL;
 395     }
 396
 397     return obj;
 398 }
 399
 400 void icp_destroy(ICPState *icp)
 401 {
 402     Object *obj = OBJECT(icp);
 403
 404     object_unparent(obj);
 405 }
 406
 407 /*
 408  * ICS: Source layer
 409  */
 410 static void ics_resend_msi(ICSState *ics, int srcno)
 411 {
 412     ICSIRQState *irq = ics->irqs + srcno;
 413
 414     /* FIXME: filter by server#? */
 415     if (irq->status & XICS_STATUS_REJECTED) {
 416         irq->status &= ~XICS_STATUS_REJECTED;
 417         if (irq->priority != 0xff) {
 418             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 419         }
 420     }
 421 }
 422
 423 static void ics_resend_lsi(ICSState *ics, int srcno)
 424 {
 425     ICSIRQState *irq = ics->irqs + srcno;
 426
 427     if ((irq->priority != 0xff)
 428         && (irq->status & XICS_STATUS_ASSERTED)
 429         && !(irq->status & XICS_STATUS_SENT)) {
 430         irq->status |= XICS_STATUS_SENT;
 431         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 432     }
 433 }
 434
 435 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
 436 {
 437     ICSIRQState *irq = ics->irqs + srcno;
 438
 439     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
 440
 441     if (val) {
 442         if (irq->priority == 0xff) {
 443             irq->status |= XICS_STATUS_MASKED_PENDING;
 444             trace_xics_masked_pending();
 445         } else  {
 446             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 447         }
 448     }
 449 }
 450
 451 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
 452 {
 453     ICSIRQState *irq = ics->irqs + srcno;
 454
 455     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
 456     if (val) {
 457         irq->status |= XICS_STATUS_ASSERTED;
 458     } else {
 459         irq->status &= ~XICS_STATUS_ASSERTED;
 460     }
 461     ics_resend_lsi(ics, srcno);
 462 }
 463
 464 void ics_set_irq(void *opaque, int srcno, int val)
 465 {
 466     ICSState *ics = (ICSState *)opaque;
 467
 468     if (kvm_irqchip_in_kernel()) {
 469         ics_kvm_set_irq(ics, srcno, val);
 470         return;
 471     }
 472
 473     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 474         ics_set_irq_lsi(ics, srcno, val);
 475     } else {
 476         ics_set_irq_msi(ics, srcno, val);
 477     }
 478 }
 479
 480 static void ics_write_xive_msi(ICSState *ics, int srcno)
 481 {
 482     ICSIRQState *irq = ics->irqs + srcno;
 483
 484     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 485         || (irq->priority == 0xff)) {
 486         return;
 487     }
 488
 489     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 490     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 491 }
 492
 493 static void ics_write_xive_lsi(ICSState *ics, int srcno)
 494 {
 495     ics_resend_lsi(ics, srcno);
 496 }
 497
 498 void ics_write_xive(ICSState *ics, int srcno, int server,
 499                     uint8_t priority, uint8_t saved_priority)
 500 {
 501     ICSIRQState *irq = ics->irqs + srcno;
 502
 503     irq->server = server;
 504     irq->priority = priority;
 505     irq->saved_priority = saved_priority;
 506
 507     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
 508
 509     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 510         ics_write_xive_lsi(ics, srcno);
 511     } else {
 512         ics_write_xive_msi(ics, srcno);
 513     }
 514 }
 515
 516 static void ics_reject(ICSState *ics, uint32_t nr)
 517 {
 518     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 519
 520     trace_xics_ics_reject(nr, nr - ics->offset);
 521     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 522         irq->status |= XICS_STATUS_REJECTED;
 523     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 524         irq->status &= ~XICS_STATUS_SENT;
 525     }
 526 }
 527
 528 void ics_resend(ICSState *ics)
 529 {
 530     int i;
 531
 532     for (i = 0; i < ics->nr_irqs; i++) {
 533         /* FIXME: filter by server#? */
 534         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 535             ics_resend_lsi(ics, i);
 536         } else {
 537             ics_resend_msi(ics, i);
 538         }
 539     }
 540 }
 541
 542 static void ics_eoi(ICSState *ics, uint32_t nr)
 543 {
 544     int srcno = nr - ics->offset;
 545     ICSIRQState *irq = ics->irqs + srcno;
 546
 547     trace_xics_ics_eoi(nr);
 548
 549     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 550         irq->status &= ~XICS_STATUS_SENT;
 551     }
 552 }
 553
 554 static void ics_reset_irq(ICSIRQState *irq)
 555 {
 556     irq->priority = 0xff;
 557     irq->saved_priority = 0xff;
 558 }
 559
 560 static void ics_reset(DeviceState *dev)
 561 {
 562     ICSState *ics = ICS(dev);
 563     int i;
 564     uint8_t flags[ics->nr_irqs];
 565
 566     for (i = 0; i < ics->nr_irqs; i++) {
 567         flags[i] = ics->irqs[i].flags;
 568     }
 569
 570     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 571
 572     for (i = 0; i < ics->nr_irqs; i++) {
 573         ics_reset_irq(ics->irqs + i);
 574         ics->irqs[i].flags = flags[i];
 575     }
 576
 577     if (kvm_irqchip_in_kernel()) {
 578         Error *local_err = NULL;
 579
 580         ics_set_kvm_state(ICS(dev), &local_err);
 581         if (local_err) {
 582             error_report_err(local_err);
 583         }
 584     }
 585 }
 586
 587 static void ics_reset_handler(void *dev)
 588 {
 589     ics_reset(dev);
 590 }
 591
 592 static void ics_realize(DeviceState *dev, Error **errp)
 593 {
 594     ICSState *ics = ICS(dev);
 595
 596     assert(ics->xics);
 597
 598     if (!ics->nr_irqs) {
 599         error_setg(errp, "Number of interrupts needs to be greater 0");
 600         return;
 601     }
 602     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 603
 604     qemu_register_reset(ics_reset_handler, ics);
 605 }
 606
 607 static void ics_instance_init(Object *obj)
 608 {
 609     ICSState *ics = ICS(obj);
 610
 611     ics->offset = XICS_IRQ_BASE;
 612 }
 613
 614 static int ics_pre_save(void *opaque)
 615 {
 616     ICSState *ics = opaque;
 617
 618     if (kvm_irqchip_in_kernel()) {
 619         ics_get_kvm_state(ics);
 620     }
 621
 622     return 0;
 623 }
 624
 625 static int ics_post_load(void *opaque, int version_id)
 626 {
 627     ICSState *ics = opaque;
 628
 629     if (kvm_irqchip_in_kernel()) {
 630         Error *local_err = NULL;
 631         int ret;
 632
 633         ret = ics_set_kvm_state(ics, &local_err);
 634         if (ret < 0) {
 635             error_report_err(local_err);
 636             return ret;
 637         }
 638     }
 639
 640     return 0;
 641 }
 642
 643 static const VMStateDescription vmstate_ics_irq = {
 644     .name = "ics/irq",
 645     .version_id = 2,
 646     .minimum_version_id = 1,
 647     .fields = (VMStateField[]) {
 648         VMSTATE_UINT32(server, ICSIRQState),
 649         VMSTATE_UINT8(priority, ICSIRQState),
 650         VMSTATE_UINT8(saved_priority, ICSIRQState),
 651         VMSTATE_UINT8(status, ICSIRQState),
 652         VMSTATE_UINT8(flags, ICSIRQState),
 653         VMSTATE_END_OF_LIST()
 654     },
 655 };
 656
 657 static const VMStateDescription vmstate_ics = {
 658     .name = "ics",
 659     .version_id = 1,
 660     .minimum_version_id = 1,
 661     .pre_save = ics_pre_save,
 662     .post_load = ics_post_load,
 663     .fields = (VMStateField[]) {
 664         /* Sanity check */
 665         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 666
 667         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 668                                              vmstate_ics_irq,
 669                                              ICSIRQState),
 670         VMSTATE_END_OF_LIST()
 671     },
 672 };
 673
 674 static Property ics_properties[] = {
 675     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 676     DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
 677                      XICSFabric *),
 678     DEFINE_PROP_END_OF_LIST(),
 679 };
 680
 681 static void ics_class_init(ObjectClass *klass, void *data)
 682 {
 683     DeviceClass *dc = DEVICE_CLASS(klass);
 684
 685     dc->realize = ics_realize;
 686     dc->props = ics_properties;
 687     dc->reset = ics_reset;
 688     dc->vmsd = &vmstate_ics;
 689     /*
 690      * Reason: part of XICS interrupt controller, needs to be wired up,
 691      * e.g. by spapr_irq_init().
 692      */
 693     dc->user_creatable = false;
 694 }
 695
 696 static const TypeInfo ics_info = {
 697     .name = TYPE_ICS,
 698     .parent = TYPE_DEVICE,
 699     .instance_size = sizeof(ICSState),
 700     .instance_init = ics_instance_init,
 701     .class_init = ics_class_init,
 702     .class_size = sizeof(ICSStateClass),
 703 };
 704
 705 static const TypeInfo xics_fabric_info = {
 706     .name = TYPE_XICS_FABRIC,
 707     .parent = TYPE_INTERFACE,
 708     .class_size = sizeof(XICSFabricClass),
 709 };
 710
 711 /*
 712  * Exported functions
 713  */
 714 ICPState *xics_icp_get(XICSFabric *xi, int server)
 715 {
 716     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 717
 718     return xic->icp_get(xi, server);
 719 }
 720
 721 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 722 {
 723     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 724
 725     ics->irqs[srcno].flags |=
 726         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 727
 728     if (kvm_irqchip_in_kernel()) {
 729         Error *local_err = NULL;
 730
 731         ics_reset_irq(ics->irqs + srcno);
 732         ics_set_kvm_state_one(ics, srcno, &local_err);
 733         if (local_err) {
 734             error_report_err(local_err);
 735         }
 736     }
 737 }
 738
 739 static void xics_register_types(void)
 740 {
 741     type_register_static(&ics_info);
 742     type_register_static(&icp_info);
 743     type_register_static(&xics_fabric_info);
 744 }
 745
 746 type_init(xics_register_types)