tests/libqos/virtio-pci.c

   1 /*
   2  * libqos virtio PCI driver
   3  *
   4  * Copyright (c) 2014 Marc Marí
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include <glib.h>
  11 #include <stdio.h>
  12 #include "libqtest.h"
  13 #include "libqos/virtio.h"
  14 #include "libqos/virtio-pci.h"
  15 #include "libqos/pci.h"
  16 #include "libqos/pci-pc.h"
  17 #include "libqos/malloc.h"
  18 #include "libqos/malloc-pc.h"
  19
  20 #include "hw/pci/pci_regs.h"
  21
  22 typedef struct QVirtioPCIForeachData {
  23     void (*func)(QVirtioDevice *d, void *data);
  24     uint16_t device_type;
  25     void *user_data;
  26 } QVirtioPCIForeachData;
  27
  28 static QVirtioPCIDevice *qpcidevice_to_qvirtiodevice(QPCIDevice *pdev)
  29 {
  30     QVirtioPCIDevice *vpcidev;
  31     vpcidev = g_malloc0(sizeof(*vpcidev));
  32
  33     if (pdev) {
  34         vpcidev->pdev = pdev;
  35         vpcidev->vdev.device_type =
  36                             qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID);
  37     }
  38
  39     vpcidev->config_msix_entry = -1;
  40
  41     return vpcidev;
  42 }
  43
  44 static void qvirtio_pci_foreach_callback(
  45                         QPCIDevice *dev, int devfn, void *data)
  46 {
  47     QVirtioPCIForeachData *d = data;
  48     QVirtioPCIDevice *vpcidev = qpcidevice_to_qvirtiodevice(dev);
  49
  50     if (vpcidev->vdev.device_type == d->device_type) {
  51         d->func(&vpcidev->vdev, d->user_data);
  52     } else {
  53         g_free(vpcidev);
  54     }
  55 }
  56
  57 static void qvirtio_pci_assign_device(QVirtioDevice *d, void *data)
  58 {
  59     QVirtioPCIDevice **vpcidev = data;
  60     *vpcidev = (QVirtioPCIDevice *)d;
  61 }
  62
  63 static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, void *addr)
  64 {
  65     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  66     return qpci_io_readb(dev->pdev, addr);
  67 }
  68
  69 static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, void *addr)
  70 {
  71     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  72     return qpci_io_readw(dev->pdev, addr);
  73 }
  74
  75 static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, void *addr)
  76 {
  77     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  78     return qpci_io_readl(dev->pdev, addr);
  79 }
  80
  81 static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, void *addr)
  82 {
  83     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  84     int i;
  85     uint64_t u64 = 0;
  86
  87     if (qtest_big_endian()) {
  88         for (i = 0; i < 8; ++i) {
  89             u64 |= (uint64_t)qpci_io_readb(dev->pdev, addr + i) << (7 - i) * 8;
  90         }
  91     } else {
  92         for (i = 0; i < 8; ++i) {
  93             u64 |= (uint64_t)qpci_io_readb(dev->pdev, addr + i) << i * 8;
  94         }
  95     }
  96
  97     return u64;
  98 }
  99
 100 static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
 101 {
 102     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 103     return qpci_io_readl(dev->pdev, dev->addr + QVIRTIO_DEVICE_FEATURES);
 104 }
 105
 106 static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
 107 {
 108     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 109     qpci_io_writel(dev->pdev, dev->addr + QVIRTIO_GUEST_FEATURES, features);
 110 }
 111
 112 static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
 113 {
 114     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 115     return qpci_io_readl(dev->pdev, dev->addr + QVIRTIO_GUEST_FEATURES);
 116 }
 117
 118 static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
 119 {
 120     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 121     return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_DEVICE_STATUS);
 122 }
 123
 124 static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
 125 {
 126     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 127     qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_DEVICE_STATUS, status);
 128 }
 129
 130 static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
 131 {
 132     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 133     QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
 134     uint32_t data;
 135
 136     if (dev->pdev->msix_enabled) {
 137         g_assert_cmpint(vqpci->msix_entry, !=, -1);
 138         if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
 139             /* No ISR checking should be done if masked, but read anyway */
 140             return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
 141         } else {
 142             data = readl(vqpci->msix_addr);
 143             writel(vqpci->msix_addr, 0);
 144             return data == vqpci->msix_data;
 145         }
 146     } else {
 147         return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS) & 1;
 148     }
 149 }
 150
 151 static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
 152 {
 153     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 154     uint32_t data;
 155
 156     if (dev->pdev->msix_enabled) {
 157         g_assert_cmpint(dev->config_msix_entry, !=, -1);
 158         if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
 159             /* No ISR checking should be done if masked, but read anyway */
 160             return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
 161         } else {
 162             data = readl(dev->config_msix_addr);
 163             writel(dev->config_msix_addr, 0);
 164             return data == dev->config_msix_data;
 165         }
 166     } else {
 167         return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS) & 2;
 168     }
 169 }
 170
 171 static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
 172 {
 173     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 174     qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_QUEUE_SELECT, index);
 175 }
 176
 177 static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
 178 {
 179     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 180     return qpci_io_readw(dev->pdev, dev->addr + QVIRTIO_QUEUE_SIZE);
 181 }
 182
 183 static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
 184 {
 185     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 186     qpci_io_writel(dev->pdev, dev->addr + QVIRTIO_QUEUE_ADDRESS, pfn);
 187 }
 188
 189 static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
 190                                         QGuestAllocator *alloc, uint16_t index)
 191 {
 192     uint32_t feat;
 193     uint64_t addr;
 194     QVirtQueuePCI *vqpci;
 195
 196     vqpci = g_malloc0(sizeof(*vqpci));
 197     feat = qvirtio_pci_get_guest_features(d);
 198
 199     qvirtio_pci_queue_select(d, index);
 200     vqpci->vq.index = index;
 201     vqpci->vq.size = qvirtio_pci_get_queue_size(d);
 202     vqpci->vq.free_head = 0;
 203     vqpci->vq.num_free = vqpci->vq.size;
 204     vqpci->vq.align = QVIRTIO_PCI_ALIGN;
 205     vqpci->vq.indirect = (feat & QVIRTIO_F_RING_INDIRECT_DESC) != 0;
 206     vqpci->vq.event = (feat & QVIRTIO_F_RING_EVENT_IDX) != 0;
 207
 208     vqpci->msix_entry = -1;
 209     vqpci->msix_addr = 0;
 210     vqpci->msix_data = 0x12345678;
 211
 212     /* Check different than 0 */
 213     g_assert_cmpint(vqpci->vq.size, !=, 0);
 214
 215     /* Check power of 2 */
 216     g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
 217
 218     addr = guest_alloc(alloc, qvring_size(vqpci->vq.size, QVIRTIO_PCI_ALIGN));
 219     qvring_init(alloc, &vqpci->vq, addr);
 220     qvirtio_pci_set_queue_address(d, vqpci->vq.desc / QVIRTIO_PCI_ALIGN);
 221
 222     return &vqpci->vq;
 223 }
 224
 225 static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
 226 {
 227     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 228     qpci_io_writew(dev->pdev, dev->addr + QVIRTIO_QUEUE_NOTIFY, vq->index);
 229 }
 230
 231 const QVirtioBus qvirtio_pci = {
 232     .config_readb = qvirtio_pci_config_readb,
 233     .config_readw = qvirtio_pci_config_readw,
 234     .config_readl = qvirtio_pci_config_readl,
 235     .config_readq = qvirtio_pci_config_readq,
 236     .get_features = qvirtio_pci_get_features,
 237     .set_features = qvirtio_pci_set_features,
 238     .get_guest_features = qvirtio_pci_get_guest_features,
 239     .get_status = qvirtio_pci_get_status,
 240     .set_status = qvirtio_pci_set_status,
 241     .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
 242     .get_config_isr_status = qvirtio_pci_get_config_isr_status,
 243     .queue_select = qvirtio_pci_queue_select,
 244     .get_queue_size = qvirtio_pci_get_queue_size,
 245     .set_queue_address = qvirtio_pci_set_queue_address,
 246     .virtqueue_setup = qvirtio_pci_virtqueue_setup,
 247     .virtqueue_kick = qvirtio_pci_virtqueue_kick,
 248 };
 249
 250 void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
 251                 void (*func)(QVirtioDevice *d, void *data), void *data)
 252 {
 253     QVirtioPCIForeachData d = { .func = func,
 254                                 .device_type = device_type,
 255                                 .user_data = data };
 256
 257     qpci_device_foreach(bus, QVIRTIO_VENDOR_ID, -1,
 258                                 qvirtio_pci_foreach_callback, &d);
 259 }
 260
 261 QVirtioPCIDevice *qvirtio_pci_device_find(QPCIBus *bus, uint16_t device_type)
 262 {
 263     QVirtioPCIDevice *dev = NULL;
 264     qvirtio_pci_foreach(bus, device_type, qvirtio_pci_assign_device, &dev);
 265
 266     return dev;
 267 }
 268
 269 void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
 270 {
 271     qpci_device_enable(d->pdev);
 272     d->addr = qpci_iomap(d->pdev, 0, NULL);
 273     g_assert(d->addr != NULL);
 274 }
 275
 276 void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
 277 {
 278     qpci_iounmap(d->pdev, d->addr);
 279     d->addr = NULL;
 280 }
 281
 282 void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
 283                                         QGuestAllocator *alloc, uint16_t entry)
 284 {
 285     uint16_t vector;
 286     uint32_t control;
 287     void *addr;
 288
 289     g_assert(d->pdev->msix_enabled);
 290     addr = d->pdev->msix_table + (entry * 16);
 291
 292     g_assert_cmpint(entry, >=, 0);
 293     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 294     vqpci->msix_entry = entry;
 295
 296     vqpci->msix_addr = guest_alloc(alloc, 4);
 297     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
 298                                                     vqpci->msix_addr & ~0UL);
 299     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
 300                                             (vqpci->msix_addr >> 32) & ~0UL);
 301     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
 302
 303     control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 304     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
 305                                         control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 306
 307     qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
 308     qpci_io_writew(d->pdev, d->addr + QVIRTIO_MSIX_QUEUE_VECTOR, entry);
 309     vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_MSIX_QUEUE_VECTOR);
 310     g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR);
 311 }
 312
 313 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
 314                                         QGuestAllocator *alloc, uint16_t entry)
 315 {
 316     uint16_t vector;
 317     uint32_t control;
 318     void *addr;
 319
 320     g_assert(d->pdev->msix_enabled);
 321     addr = d->pdev->msix_table + (entry * 16);
 322
 323     g_assert_cmpint(entry, >=, 0);
 324     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 325     d->config_msix_entry = entry;
 326
 327     d->config_msix_data = 0x12345678;
 328     d->config_msix_addr = guest_alloc(alloc, 4);
 329
 330     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
 331                                                     d->config_msix_addr & ~0UL);
 332     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
 333                                             (d->config_msix_addr >> 32) & ~0UL);
 334     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
 335
 336     control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 337     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
 338                                         control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 339
 340     qpci_io_writew(d->pdev, d->addr + QVIRTIO_MSIX_CONF_VECTOR, entry);
 341     vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_MSIX_CONF_VECTOR);
 342     g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR);
 343 }