tcg/tcg-opc.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /*
  26  * DEF(name, oargs, iargs, cargs, flags)
  27  */
  28
  29 /* predefined ops */
  30 DEF(end, 0, 0, 0, 0) /* must be kept first */
  31 DEF(nop, 0, 0, 0, 0)
  32 DEF(nop1, 0, 0, 1, 0)
  33 DEF(nop2, 0, 0, 2, 0)
  34 DEF(nop3, 0, 0, 3, 0)
  35 DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
  36
  37 DEF(discard, 1, 0, 0, 0)
  38
  39 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
  40 DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
  41 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
  42
  43 #define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
  44 #if TCG_TARGET_REG_BITS == 32
  45 # define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
  46 #else
  47 # define IMPL64  TCG_OPF_64BIT
  48 #endif
  49
  50 DEF(mov_i32, 1, 1, 0, 0)
  51 DEF(movi_i32, 1, 0, 1, 0)
  52 DEF(setcond_i32, 1, 2, 1, 0)
  53 DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
  54 /* load/store */
  55 DEF(ld8u_i32, 1, 1, 1, 0)
  56 DEF(ld8s_i32, 1, 1, 1, 0)
  57 DEF(ld16u_i32, 1, 1, 1, 0)
  58 DEF(ld16s_i32, 1, 1, 1, 0)
  59 DEF(ld_i32, 1, 1, 1, 0)
  60 DEF(st8_i32, 0, 2, 1, 0)
  61 DEF(st16_i32, 0, 2, 1, 0)
  62 DEF(st_i32, 0, 2, 1, 0)
  63 /* arith */
  64 DEF(add_i32, 1, 2, 0, 0)
  65 DEF(sub_i32, 1, 2, 0, 0)
  66 DEF(mul_i32, 1, 2, 0, 0)
  67 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  68 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  69 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  70 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  71 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  72 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  73 DEF(and_i32, 1, 2, 0, 0)
  74 DEF(or_i32, 1, 2, 0, 0)
  75 DEF(xor_i32, 1, 2, 0, 0)
  76 /* shifts/rotates */
  77 DEF(shl_i32, 1, 2, 0, 0)
  78 DEF(shr_i32, 1, 2, 0, 0)
  79 DEF(sar_i32, 1, 2, 0, 0)
  80 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  81 DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  82 DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
  83
  84 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
  85
  86 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
  87 DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
  88 DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
  89 DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
  90 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
  91 DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
  92
  93 DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
  94 DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
  95 DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
  96 DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
  97 DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
  98 DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
  99 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
 100 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
 101 DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
 102 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
 103 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
 104 DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
 105 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
 106
 107 DEF(mov_i64, 1, 1, 0, IMPL64)
 108 DEF(movi_i64, 1, 0, 1, IMPL64)
 109 DEF(setcond_i64, 1, 2, 1, IMPL64)
 110 DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
 111 /* load/store */
 112 DEF(ld8u_i64, 1, 1, 1, IMPL64)
 113 DEF(ld8s_i64, 1, 1, 1, IMPL64)
 114 DEF(ld16u_i64, 1, 1, 1, IMPL64)
 115 DEF(ld16s_i64, 1, 1, 1, IMPL64)
 116 DEF(ld32u_i64, 1, 1, 1, IMPL64)
 117 DEF(ld32s_i64, 1, 1, 1, IMPL64)
 118 DEF(ld_i64, 1, 1, 1, IMPL64)
 119 DEF(st8_i64, 0, 2, 1, IMPL64)
 120 DEF(st16_i64, 0, 2, 1, IMPL64)
 121 DEF(st32_i64, 0, 2, 1, IMPL64)
 122 DEF(st_i64, 0, 2, 1, IMPL64)
 123 /* arith */
 124 DEF(add_i64, 1, 2, 0, IMPL64)
 125 DEF(sub_i64, 1, 2, 0, IMPL64)
 126 DEF(mul_i64, 1, 2, 0, IMPL64)
 127 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 128 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 129 DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 130 DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 131 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 132 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 133 DEF(and_i64, 1, 2, 0, IMPL64)
 134 DEF(or_i64, 1, 2, 0, IMPL64)
 135 DEF(xor_i64, 1, 2, 0, IMPL64)
 136 /* shifts/rotates */
 137 DEF(shl_i64, 1, 2, 0, IMPL64)
 138 DEF(shr_i64, 1, 2, 0, IMPL64)
 139 DEF(sar_i64, 1, 2, 0, IMPL64)
 140 DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 141 DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 142 DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
 143
 144 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
 145 DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
 146 DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
 147 DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
 148 DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
 149 DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
 150 DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
 151 DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
 152 DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
 153 DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
 154 DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
 155 DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
 156 DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
 157 DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
 158 DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
 159 DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
 160 DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
 161
 162 DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
 163 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
 164 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
 165 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 166
 167 /* QEMU specific */
 168 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
 169 DEF(debug_insn_start, 0, 0, 2, 0)
 170 #else
 171 DEF(debug_insn_start, 0, 0, 1, 0)
 172 #endif
 173 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 174 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
 175 /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
 176    constants must be defined */
 177 #if TCG_TARGET_REG_BITS == 32
 178 #if TARGET_LONG_BITS == 32
 179 DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 180 #else
 181 DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 182 #endif
 183 #if TARGET_LONG_BITS == 32
 184 DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 185 #else
 186 DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 187 #endif
 188 #if TARGET_LONG_BITS == 32
 189 DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 190 #else
 191 DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 192 #endif
 193 #if TARGET_LONG_BITS == 32
 194 DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 195 #else
 196 DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 197 #endif
 198 #if TARGET_LONG_BITS == 32
 199 DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 200 #else
 201 DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 202 #endif
 203 #if TARGET_LONG_BITS == 32
 204 DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 205 #else
 206 DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 207 #endif
 208
 209 #if TARGET_LONG_BITS == 32
 210 DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 211 #else
 212 DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 213 #endif
 214 #if TARGET_LONG_BITS == 32
 215 DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 216 #else
 217 DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 218 #endif
 219 #if TARGET_LONG_BITS == 32
 220 DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 221 #else
 222 DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 223 #endif
 224 #if TARGET_LONG_BITS == 32
 225 DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 226 #else
 227 DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 228 #endif
 229
 230 #else /* TCG_TARGET_REG_BITS == 32 */
 231
 232 DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 233 DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 234 DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 235 DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 236 DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 237 DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 238 DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 239 DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 240
 241 DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 242 DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 243 DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 244 DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 245
 246 #endif /* TCG_TARGET_REG_BITS != 32 */
 247
 248 #undef IMPL
 249 #undef IMPL64
 250 #undef DEF