target/xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef XTENSA_CPU_H
  29 #define XTENSA_CPU_H
  30
  31 #define ALIGNED_ONLY
  32 #define TARGET_LONG_BITS 32
  33
  34 #define CPUArchState struct CPUXtensaState
  35
  36 #include "qemu-common.h"
  37 #include "cpu-qom.h"
  38 #include "exec/cpu-defs.h"
  39 #include "fpu/softfloat.h"
  40
  41 #define NB_MMU_MODES 4
  42
  43 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  44 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  45 #define TARGET_PAGE_BITS 12
  46
  47 enum {
  48     /* Additional instructions */
  49     XTENSA_OPTION_CODE_DENSITY,
  50     XTENSA_OPTION_LOOP,
  51     XTENSA_OPTION_EXTENDED_L32R,
  52     XTENSA_OPTION_16_BIT_IMUL,
  53     XTENSA_OPTION_32_BIT_IMUL,
  54     XTENSA_OPTION_32_BIT_IMUL_HIGH,
  55     XTENSA_OPTION_32_BIT_IDIV,
  56     XTENSA_OPTION_MAC16,
  57     XTENSA_OPTION_MISC_OP_NSA,
  58     XTENSA_OPTION_MISC_OP_MINMAX,
  59     XTENSA_OPTION_MISC_OP_SEXT,
  60     XTENSA_OPTION_MISC_OP_CLAMPS,
  61     XTENSA_OPTION_COPROCESSOR,
  62     XTENSA_OPTION_BOOLEAN,
  63     XTENSA_OPTION_FP_COPROCESSOR,
  64     XTENSA_OPTION_MP_SYNCHRO,
  65     XTENSA_OPTION_CONDITIONAL_STORE,
  66     XTENSA_OPTION_ATOMCTL,
  67     XTENSA_OPTION_DEPBITS,
  68
  69     /* Interrupts and exceptions */
  70     XTENSA_OPTION_EXCEPTION,
  71     XTENSA_OPTION_RELOCATABLE_VECTOR,
  72     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  73     XTENSA_OPTION_INTERRUPT,
  74     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  75     XTENSA_OPTION_TIMER_INTERRUPT,
  76
  77     /* Local memory */
  78     XTENSA_OPTION_ICACHE,
  79     XTENSA_OPTION_ICACHE_TEST,
  80     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  81     XTENSA_OPTION_DCACHE,
  82     XTENSA_OPTION_DCACHE_TEST,
  83     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  84     XTENSA_OPTION_IRAM,
  85     XTENSA_OPTION_IROM,
  86     XTENSA_OPTION_DRAM,
  87     XTENSA_OPTION_DROM,
  88     XTENSA_OPTION_XLMI,
  89     XTENSA_OPTION_HW_ALIGNMENT,
  90     XTENSA_OPTION_MEMORY_ECC_PARITY,
  91
  92     /* Memory protection and translation */
  93     XTENSA_OPTION_REGION_PROTECTION,
  94     XTENSA_OPTION_REGION_TRANSLATION,
  95     XTENSA_OPTION_MMU,
  96     XTENSA_OPTION_CACHEATTR,
  97
  98     /* Other */
  99     XTENSA_OPTION_WINDOWED_REGISTER,
 100     XTENSA_OPTION_PROCESSOR_INTERFACE,
 101     XTENSA_OPTION_MISC_SR,
 102     XTENSA_OPTION_THREAD_POINTER,
 103     XTENSA_OPTION_PROCESSOR_ID,
 104     XTENSA_OPTION_DEBUG,
 105     XTENSA_OPTION_TRACE_PORT,
 106     XTENSA_OPTION_EXTERN_REGS,
 107 };
 108
 109 enum {
 110     THREADPTR = 231,
 111     FCR = 232,
 112     FSR = 233,
 113 };
 114
 115 enum {
 116     LBEG = 0,
 117     LEND = 1,
 118     LCOUNT = 2,
 119     SAR = 3,
 120     BR = 4,
 121     LITBASE = 5,
 122     SCOMPARE1 = 12,
 123     ACCLO = 16,
 124     ACCHI = 17,
 125     MR = 32,
 126     WINDOW_BASE = 72,
 127     WINDOW_START = 73,
 128     PTEVADDR = 83,
 129     RASID = 90,
 130     ITLBCFG = 91,
 131     DTLBCFG = 92,
 132     IBREAKENABLE = 96,
 133     MEMCTL = 97,
 134     CACHEATTR = 98,
 135     ATOMCTL = 99,
 136     IBREAKA = 128,
 137     DBREAKA = 144,
 138     DBREAKC = 160,
 139     CONFIGID0 = 176,
 140     EPC1 = 177,
 141     DEPC = 192,
 142     EPS2 = 194,
 143     CONFIGID1 = 208,
 144     EXCSAVE1 = 209,
 145     CPENABLE = 224,
 146     INTSET = 226,
 147     INTCLEAR = 227,
 148     INTENABLE = 228,
 149     PS = 230,
 150     VECBASE = 231,
 151     EXCCAUSE = 232,
 152     DEBUGCAUSE = 233,
 153     CCOUNT = 234,
 154     PRID = 235,
 155     ICOUNT = 236,
 156     ICOUNTLEVEL = 237,
 157     EXCVADDR = 238,
 158     CCOMPARE = 240,
 159     MISC = 244,
 160 };
 161
 162 #define PS_INTLEVEL 0xf
 163 #define PS_INTLEVEL_SHIFT 0
 164
 165 #define PS_EXCM 0x10
 166 #define PS_UM 0x20
 167
 168 #define PS_RING 0xc0
 169 #define PS_RING_SHIFT 6
 170
 171 #define PS_OWB 0xf00
 172 #define PS_OWB_SHIFT 8
 173
 174 #define PS_CALLINC 0x30000
 175 #define PS_CALLINC_SHIFT 16
 176 #define PS_CALLINC_LEN 2
 177
 178 #define PS_WOE 0x40000
 179
 180 #define DEBUGCAUSE_IC 0x1
 181 #define DEBUGCAUSE_IB 0x2
 182 #define DEBUGCAUSE_DB 0x4
 183 #define DEBUGCAUSE_BI 0x8
 184 #define DEBUGCAUSE_BN 0x10
 185 #define DEBUGCAUSE_DI 0x20
 186 #define DEBUGCAUSE_DBNUM 0xf00
 187 #define DEBUGCAUSE_DBNUM_SHIFT 8
 188
 189 #define DBREAKC_SB 0x80000000
 190 #define DBREAKC_LB 0x40000000
 191 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
 192 #define DBREAKC_MASK 0x3f
 193
 194 #define MEMCTL_INIT 0x00800000
 195 #define MEMCTL_IUSEWAYS_SHIFT 18
 196 #define MEMCTL_IUSEWAYS_LEN 5
 197 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
 198 #define MEMCTL_DALLOCWAYS_SHIFT 13
 199 #define MEMCTL_DALLOCWAYS_LEN 5
 200 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
 201 #define MEMCTL_DUSEWAYS_SHIFT 8
 202 #define MEMCTL_DUSEWAYS_LEN 5
 203 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
 204 #define MEMCTL_ISNP 0x4
 205 #define MEMCTL_DSNP 0x2
 206 #define MEMCTL_IL0EN 0x1
 207
 208 #define MAX_NAREG 64
 209 #define MAX_NINTERRUPT 32
 210 #define MAX_NLEVEL 6
 211 #define MAX_NNMI 1
 212 #define MAX_NCCOMPARE 3
 213 #define MAX_TLB_WAY_SIZE 8
 214 #define MAX_NDBREAK 2
 215
 216 #define REGION_PAGE_MASK 0xe0000000
 217
 218 #define PAGE_CACHE_MASK    0x700
 219 #define PAGE_CACHE_SHIFT   8
 220 #define PAGE_CACHE_INVALID 0x000
 221 #define PAGE_CACHE_BYPASS  0x100
 222 #define PAGE_CACHE_WT      0x200
 223 #define PAGE_CACHE_WB      0x400
 224 #define PAGE_CACHE_ISOLATE 0x600
 225
 226 enum {
 227     /* Static vectors */
 228     EXC_RESET0,
 229     EXC_RESET1,
 230     EXC_MEMORY_ERROR,
 231
 232     /* Dynamic vectors */
 233     EXC_WINDOW_OVERFLOW4,
 234     EXC_WINDOW_UNDERFLOW4,
 235     EXC_WINDOW_OVERFLOW8,
 236     EXC_WINDOW_UNDERFLOW8,
 237     EXC_WINDOW_OVERFLOW12,
 238     EXC_WINDOW_UNDERFLOW12,
 239     EXC_IRQ,
 240     EXC_KERNEL,
 241     EXC_USER,
 242     EXC_DOUBLE,
 243     EXC_DEBUG,
 244     EXC_MAX
 245 };
 246
 247 enum {
 248     ILLEGAL_INSTRUCTION_CAUSE = 0,
 249     SYSCALL_CAUSE,
 250     INSTRUCTION_FETCH_ERROR_CAUSE,
 251     LOAD_STORE_ERROR_CAUSE,
 252     LEVEL1_INTERRUPT_CAUSE,
 253     ALLOCA_CAUSE,
 254     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 255     PRIVILEGED_CAUSE = 8,
 256     LOAD_STORE_ALIGNMENT_CAUSE,
 257
 258     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 259     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 260     INSTR_PIF_ADDR_ERROR_CAUSE,
 261     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 262
 263     INST_TLB_MISS_CAUSE,
 264     INST_TLB_MULTI_HIT_CAUSE,
 265     INST_FETCH_PRIVILEGE_CAUSE,
 266     INST_FETCH_PROHIBITED_CAUSE = 20,
 267     LOAD_STORE_TLB_MISS_CAUSE = 24,
 268     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 269     LOAD_STORE_PRIVILEGE_CAUSE,
 270     LOAD_PROHIBITED_CAUSE = 28,
 271     STORE_PROHIBITED_CAUSE,
 272
 273     COPROCESSOR0_DISABLED = 32,
 274 };
 275
 276 typedef enum {
 277     INTTYPE_LEVEL,
 278     INTTYPE_EDGE,
 279     INTTYPE_NMI,
 280     INTTYPE_SOFTWARE,
 281     INTTYPE_TIMER,
 282     INTTYPE_DEBUG,
 283     INTTYPE_WRITE_ERR,
 284     INTTYPE_PROFILING,
 285     INTTYPE_MAX
 286 } interrupt_type;
 287
 288 struct CPUXtensaState;
 289
 290 typedef struct xtensa_tlb_entry {
 291     uint32_t vaddr;
 292     uint32_t paddr;
 293     uint8_t asid;
 294     uint8_t attr;
 295     bool variable;
 296 } xtensa_tlb_entry;
 297
 298 typedef struct xtensa_tlb {
 299     unsigned nways;
 300     const unsigned way_size[10];
 301     bool varway56;
 302     unsigned nrefillentries;
 303 } xtensa_tlb;
 304
 305 typedef struct XtensaGdbReg {
 306     int targno;
 307     int type;
 308     int group;
 309     unsigned size;
 310 } XtensaGdbReg;
 311
 312 typedef struct XtensaGdbRegmap {
 313     int num_regs;
 314     int num_core_regs;
 315     /* PC + a + ar + sr + ur */
 316     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
 317 } XtensaGdbRegmap;
 318
 319 typedef struct XtensaCcompareTimer {
 320     struct CPUXtensaState *env;
 321     QEMUTimer *timer;
 322 } XtensaCcompareTimer;
 323
 324 struct XtensaConfig {
 325     const char *name;
 326     uint64_t options;
 327     XtensaGdbRegmap gdb_regmap;
 328     unsigned nareg;
 329     int excm_level;
 330     int ndepc;
 331     uint32_t vecbase;
 332     uint32_t exception_vector[EXC_MAX];
 333     unsigned ninterrupt;
 334     unsigned nlevel;
 335     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 336     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 337     uint32_t inttype_mask[INTTYPE_MAX];
 338     struct {
 339         uint32_t level;
 340         interrupt_type inttype;
 341     } interrupt[MAX_NINTERRUPT];
 342     unsigned nccompare;
 343     uint32_t timerint[MAX_NCCOMPARE];
 344     unsigned nextint;
 345     unsigned extint[MAX_NINTERRUPT];
 346
 347     unsigned debug_level;
 348     unsigned nibreak;
 349     unsigned ndbreak;
 350
 351     unsigned icache_ways;
 352     unsigned dcache_ways;
 353     uint32_t memctl_mask;
 354
 355     uint32_t configid[2];
 356
 357     uint32_t clock_freq_khz;
 358
 359     xtensa_tlb itlb;
 360     xtensa_tlb dtlb;
 361 };
 362
 363 typedef struct XtensaConfigList {
 364     const XtensaConfig *config;
 365     struct XtensaConfigList *next;
 366 } XtensaConfigList;
 367
 368 #ifdef HOST_WORDS_BIGENDIAN
 369 enum {
 370     FP_F32_HIGH,
 371     FP_F32_LOW,
 372 };
 373 #else
 374 enum {
 375     FP_F32_LOW,
 376     FP_F32_HIGH,
 377 };
 378 #endif
 379
 380 typedef struct CPUXtensaState {
 381     const XtensaConfig *config;
 382     uint32_t regs[16];
 383     uint32_t pc;
 384     uint32_t sregs[256];
 385     uint32_t uregs[256];
 386     uint32_t phys_regs[MAX_NAREG];
 387     union {
 388         float32 f32[2];
 389         float64 f64;
 390     } fregs[16];
 391     float_status fp_status;
 392
 393     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 394     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
 395     unsigned autorefill_idx;
 396     bool runstall;
 397     AddressSpace *address_space_er;
 398     MemoryRegion *system_er;
 399     int pending_irq_level; /* level of last raised IRQ */
 400     void **irq_inputs;
 401     XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
 402     uint64_t time_base;
 403     uint64_t ccount_time;
 404     uint32_t ccount_base;
 405
 406     int exception_taken;
 407     int yield_needed;
 408     unsigned static_vectors;
 409
 410     /* Watchpoints for DBREAK registers */
 411     struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
 412
 413     CPU_COMMON
 414 } CPUXtensaState;
 415
 416 /**
 417  * XtensaCPU:
 418  * @env: #CPUXtensaState
 419  *
 420  * An Xtensa CPU.
 421  */
 422 struct XtensaCPU {
 423     /*< private >*/
 424     CPUState parent_obj;
 425     /*< public >*/
 426
 427     CPUXtensaState env;
 428 };
 429
 430 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
 431 {
 432     return container_of(env, XtensaCPU, env);
 433 }
 434
 435 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
 436
 437 #define ENV_OFFSET offsetof(XtensaCPU, env)
 438
 439 void xtensa_cpu_do_interrupt(CPUState *cpu);
 440 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
 441 void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
 442                                      bool is_write, bool is_exec, int opaque,
 443                                      unsigned size);
 444 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
 445                            fprintf_function cpu_fprintf, int flags);
 446 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 447 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 448 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 449 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 450                                     MMUAccessType access_type,
 451                                     int mmu_idx, uintptr_t retaddr);
 452
 453 #define cpu_signal_handler cpu_xtensa_signal_handler
 454 #define cpu_list xtensa_cpu_list
 455
 456 #ifdef TARGET_WORDS_BIGENDIAN
 457 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
 458 #else
 459 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
 460 #endif
 461
 462 XtensaCPU *cpu_xtensa_init(const char *cpu_model);
 463
 464 #define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model))
 465
 466 void xtensa_translate_init(void);
 467 void xtensa_breakpoint_handler(CPUState *cs);
 468 void xtensa_finalize_config(XtensaConfig *config);
 469 void xtensa_register_core(XtensaConfigList *node);
 470 void check_interrupts(CPUXtensaState *s);
 471 void xtensa_irq_init(CPUXtensaState *env);
 472 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
 473 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
 474 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 475 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 476 void xtensa_sync_window_from_phys(CPUXtensaState *env);
 477 void xtensa_sync_phys_from_window(CPUXtensaState *env);
 478 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
 479 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 480         uint32_t *vpn, uint32_t wi, uint32_t *ei);
 481 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 482         uint32_t *pwi, uint32_t *pei, uint8_t *pring);
 483 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 484         xtensa_tlb_entry *entry, bool dtlb,
 485         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 486 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 487         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 488 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 489         uint32_t vaddr, int is_write, int mmu_idx,
 490         uint32_t *paddr, uint32_t *page_size, unsigned *access);
 491 void reset_mmu(CPUXtensaState *env);
 492 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
 493 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
 494 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
 495 {
 496     return env->system_er;
 497 }
 498
 499 static inline void xtensa_select_static_vectors(CPUXtensaState *env,
 500                                                 unsigned n)
 501 {
 502     assert(n < 2);
 503     env->static_vectors = n;
 504 }
 505 void xtensa_runstall(CPUXtensaState *env, bool runstall);
 506
 507 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 508 #define XTENSA_OPTION_ALL (~(uint64_t)0)
 509
 510 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
 511         uint64_t opt)
 512 {
 513     return (config->options & opt) != 0;
 514 }
 515
 516 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 517 {
 518     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 519 }
 520
 521 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
 522 {
 523     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 524     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 525         level = env->config->excm_level;
 526     }
 527     return level;
 528 }
 529
 530 static inline int xtensa_get_ring(const CPUXtensaState *env)
 531 {
 532     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 533         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 534     } else {
 535         return 0;
 536     }
 537 }
 538
 539 static inline int xtensa_get_cring(const CPUXtensaState *env)
 540 {
 541     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 542             (env->sregs[PS] & PS_EXCM) == 0) {
 543         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 544     } else {
 545         return 0;
 546     }
 547 }
 548
 549 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
 550         bool dtlb, unsigned wi, unsigned ei)
 551 {
 552     return dtlb ?
 553         env->dtlb[wi] + ei :
 554         env->itlb[wi] + ei;
 555 }
 556
 557 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
 558 {
 559     return env->sregs[WINDOW_START] |
 560         (env->sregs[WINDOW_START] << env->config->nareg / 4);
 561 }
 562
 563 /* MMU modes definitions */
 564 #define MMU_MODE0_SUFFIX _ring0
 565 #define MMU_MODE1_SUFFIX _ring1
 566 #define MMU_MODE2_SUFFIX _ring2
 567 #define MMU_MODE3_SUFFIX _ring3
 568
 569 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
 570 {
 571     return xtensa_get_cring(env);
 572 }
 573
 574 #define XTENSA_TBFLAG_RING_MASK 0x3
 575 #define XTENSA_TBFLAG_EXCM 0x4
 576 #define XTENSA_TBFLAG_LITBASE 0x8
 577 #define XTENSA_TBFLAG_DEBUG 0x10
 578 #define XTENSA_TBFLAG_ICOUNT 0x20
 579 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
 580 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
 581 #define XTENSA_TBFLAG_EXCEPTION 0x4000
 582 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
 583 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
 584 #define XTENSA_TBFLAG_YIELD 0x20000
 585
 586 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 587         target_ulong *cs_base, uint32_t *flags)
 588 {
 589     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 590
 591     *pc = env->pc;
 592     *cs_base = 0;
 593     *flags = 0;
 594     *flags |= xtensa_get_ring(env);
 595     if (env->sregs[PS] & PS_EXCM) {
 596         *flags |= XTENSA_TBFLAG_EXCM;
 597     }
 598     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 599             (env->sregs[LITBASE] & 1)) {
 600         *flags |= XTENSA_TBFLAG_LITBASE;
 601     }
 602     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
 603         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 604             *flags |= XTENSA_TBFLAG_DEBUG;
 605         }
 606         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
 607             *flags |= XTENSA_TBFLAG_ICOUNT;
 608         }
 609     }
 610     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
 611         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
 612     }
 613     if (cs->singlestep_enabled && env->exception_taken) {
 614         *flags |= XTENSA_TBFLAG_EXCEPTION;
 615     }
 616     if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
 617         (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
 618         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 619             (env->sregs[WINDOW_BASE] + 1);
 620         uint32_t w = ctz32(windowstart | 0x8);
 621
 622         *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
 623     } else {
 624         *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
 625     }
 626     if (env->yield_needed) {
 627         *flags |= XTENSA_TBFLAG_YIELD;
 628     }
 629 }
 630
 631 #include "exec/cpu-all.h"
 632
 633 #endif