2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "tcg-pool.inc.c"
28 #if defined _CALL_DARWIN || defined __APPLE__
29 #define TCG_TARGET_CALL_DARWIN
32 # define TCG_TARGET_CALL_ALIGN_ARGS 1
35 /* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
40 # define TCG_REG_TMP1 TCG_REG_R2
42 # define TCG_REG_TMP1 TCG_REG_R12
45 #define TCG_REG_TB TCG_REG_R31
46 #define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
48 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
49 #define SZP ((int)sizeof(void *))
51 /* Shorthand for size of a register. */
52 #define SZR (TCG_TARGET_REG_BITS / 8)
54 #define TCG_CT_CONST_S16 0x100
55 #define TCG_CT_CONST_U16 0x200
56 #define TCG_CT_CONST_S32 0x400
57 #define TCG_CT_CONST_U32 0x800
58 #define TCG_CT_CONST_ZERO 0x1000
59 #define TCG_CT_CONST_MONE 0x2000
60 #define TCG_CT_CONST_WSZ 0x4000
62 static tcg_insn_unit
*tb_ret_addr
;
67 #define HAVE_ISA_2_06 have_isa_2_06
68 #define HAVE_ISEL have_isa_2_06
70 #ifndef CONFIG_SOFTMMU
71 #define TCG_GUEST_BASE_REG 30
74 #ifdef CONFIG_DEBUG_TCG
75 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
111 static const int tcg_target_reg_alloc_order
[] = {
112 TCG_REG_R14
, /* call saved registers */
130 TCG_REG_R12
, /* call clobbered, non-arguments */
134 TCG_REG_R10
, /* call clobbered, arguments */
144 static const int tcg_target_call_iarg_regs
[] = {
155 static const int tcg_target_call_oarg_regs
[] = {
160 static const int tcg_target_callee_save_regs
[] = {
161 #ifdef TCG_TARGET_CALL_DARWIN
177 TCG_REG_R27
, /* currently used for the global env */
184 static inline bool in_range_b(tcg_target_long target
)
186 return target
== sextract64(target
, 0, 26);
189 static uint32_t reloc_pc24_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
191 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
192 tcg_debug_assert(in_range_b(disp
));
193 return disp
& 0x3fffffc;
196 static bool reloc_pc24(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
198 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
199 if (in_range_b(disp
)) {
200 *pc
= (*pc
& ~0x3fffffc) | (disp
& 0x3fffffc);
206 static uint16_t reloc_pc14_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
208 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
209 tcg_debug_assert(disp
== (int16_t) disp
);
210 return disp
& 0xfffc;
213 static bool reloc_pc14(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
215 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
216 if (disp
== (int16_t) disp
) {
217 *pc
= (*pc
& ~0xfffc) | (disp
& 0xfffc);
223 /* parse target specific constraints */
224 static const char *target_parse_constraint(TCGArgConstraint
*ct
,
225 const char *ct_str
, TCGType type
)
228 case 'A': case 'B': case 'C': case 'D':
229 ct
->ct
|= TCG_CT_REG
;
230 tcg_regset_set_reg(ct
->u
.regs
, 3 + ct_str
[0] - 'A');
233 ct
->ct
|= TCG_CT_REG
;
234 ct
->u
.regs
= 0xffffffff;
236 case 'L': /* qemu_ld constraint */
237 ct
->ct
|= TCG_CT_REG
;
238 ct
->u
.regs
= 0xffffffff;
239 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
240 #ifdef CONFIG_SOFTMMU
241 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
242 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
245 case 'S': /* qemu_st constraint */
246 ct
->ct
|= TCG_CT_REG
;
247 ct
->u
.regs
= 0xffffffff;
248 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
249 #ifdef CONFIG_SOFTMMU
250 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
251 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
252 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
256 ct
->ct
|= TCG_CT_CONST_S16
;
259 ct
->ct
|= TCG_CT_CONST_U16
;
262 ct
->ct
|= TCG_CT_CONST_MONE
;
265 ct
->ct
|= TCG_CT_CONST_S32
;
268 ct
->ct
|= TCG_CT_CONST_U32
;
271 ct
->ct
|= TCG_CT_CONST_WSZ
;
274 ct
->ct
|= TCG_CT_CONST_ZERO
;
282 /* test if a constant matches the constraint */
283 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
284 const TCGArgConstraint
*arg_ct
)
287 if (ct
& TCG_CT_CONST
) {
291 /* The only 32-bit constraint we use aside from
292 TCG_CT_CONST is TCG_CT_CONST_S16. */
293 if (type
== TCG_TYPE_I32
) {
297 if ((ct
& TCG_CT_CONST_S16
) && val
== (int16_t)val
) {
299 } else if ((ct
& TCG_CT_CONST_U16
) && val
== (uint16_t)val
) {
301 } else if ((ct
& TCG_CT_CONST_S32
) && val
== (int32_t)val
) {
303 } else if ((ct
& TCG_CT_CONST_U32
) && val
== (uint32_t)val
) {
305 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
307 } else if ((ct
& TCG_CT_CONST_MONE
) && val
== -1) {
309 } else if ((ct
& TCG_CT_CONST_WSZ
)
310 && val
== (type
== TCG_TYPE_I32
? 32 : 64)) {
316 #define OPCD(opc) ((opc)<<26)
317 #define XO19(opc) (OPCD(19)|((opc)<<1))
318 #define MD30(opc) (OPCD(30)|((opc)<<2))
319 #define MDS30(opc) (OPCD(30)|((opc)<<1))
320 #define XO31(opc) (OPCD(31)|((opc)<<1))
321 #define XO58(opc) (OPCD(58)|(opc))
322 #define XO62(opc) (OPCD(62)|(opc))
326 #define LBZ OPCD( 34)
327 #define LHZ OPCD( 40)
328 #define LHA OPCD( 42)
329 #define LWZ OPCD( 32)
330 #define LWZUX XO31( 55)
331 #define STB OPCD( 38)
332 #define STH OPCD( 44)
333 #define STW OPCD( 36)
336 #define STDU XO62( 1)
337 #define STDX XO31(149)
340 #define LDX XO31( 21)
342 #define LDUX XO31( 53)
344 #define LWAX XO31(341)
346 #define ADDIC OPCD( 12)
347 #define ADDI OPCD( 14)
348 #define ADDIS OPCD( 15)
349 #define ORI OPCD( 24)
350 #define ORIS OPCD( 25)
351 #define XORI OPCD( 26)
352 #define XORIS OPCD( 27)
353 #define ANDI OPCD( 28)
354 #define ANDIS OPCD( 29)
355 #define MULLI OPCD( 7)
356 #define CMPLI OPCD( 10)
357 #define CMPI OPCD( 11)
358 #define SUBFIC OPCD( 8)
360 #define LWZU OPCD( 33)
361 #define STWU OPCD( 37)
363 #define RLWIMI OPCD( 20)
364 #define RLWINM OPCD( 21)
365 #define RLWNM OPCD( 23)
367 #define RLDICL MD30( 0)
368 #define RLDICR MD30( 1)
369 #define RLDIMI MD30( 3)
370 #define RLDCL MDS30( 8)
372 #define BCLR XO19( 16)
373 #define BCCTR XO19(528)
374 #define CRAND XO19(257)
375 #define CRANDC XO19(129)
376 #define CRNAND XO19(225)
377 #define CROR XO19(449)
378 #define CRNOR XO19( 33)
380 #define EXTSB XO31(954)
381 #define EXTSH XO31(922)
382 #define EXTSW XO31(986)
383 #define ADD XO31(266)
384 #define ADDE XO31(138)
385 #define ADDME XO31(234)
386 #define ADDZE XO31(202)
387 #define ADDC XO31( 10)
388 #define AND XO31( 28)
389 #define SUBF XO31( 40)
390 #define SUBFC XO31( 8)
391 #define SUBFE XO31(136)
392 #define SUBFME XO31(232)
393 #define SUBFZE XO31(200)
395 #define XOR XO31(316)
396 #define MULLW XO31(235)
397 #define MULHW XO31( 75)
398 #define MULHWU XO31( 11)
399 #define DIVW XO31(491)
400 #define DIVWU XO31(459)
402 #define CMPL XO31( 32)
403 #define LHBRX XO31(790)
404 #define LWBRX XO31(534)
405 #define LDBRX XO31(532)
406 #define STHBRX XO31(918)
407 #define STWBRX XO31(662)
408 #define STDBRX XO31(660)
409 #define MFSPR XO31(339)
410 #define MTSPR XO31(467)
411 #define SRAWI XO31(824)
412 #define NEG XO31(104)
413 #define MFCR XO31( 19)
414 #define MFOCRF (MFCR | (1u << 20))
415 #define NOR XO31(124)
416 #define CNTLZW XO31( 26)
417 #define CNTLZD XO31( 58)
418 #define CNTTZW XO31(538)
419 #define CNTTZD XO31(570)
420 #define CNTPOPW XO31(378)
421 #define CNTPOPD XO31(506)
422 #define ANDC XO31( 60)
423 #define ORC XO31(412)
424 #define EQV XO31(284)
425 #define NAND XO31(476)
426 #define ISEL XO31( 15)
428 #define MULLD XO31(233)
429 #define MULHD XO31( 73)
430 #define MULHDU XO31( 9)
431 #define DIVD XO31(489)
432 #define DIVDU XO31(457)
434 #define LBZX XO31( 87)
435 #define LHZX XO31(279)
436 #define LHAX XO31(343)
437 #define LWZX XO31( 23)
438 #define STBX XO31(215)
439 #define STHX XO31(407)
440 #define STWX XO31(151)
442 #define EIEIO XO31(854)
443 #define HWSYNC XO31(598)
444 #define LWSYNC (HWSYNC | (1u << 21))
446 #define SPR(a, b) ((((a)<<5)|(b))<<11)
448 #define CTR SPR(9, 0)
450 #define SLW XO31( 24)
451 #define SRW XO31(536)
452 #define SRAW XO31(792)
454 #define SLD XO31( 27)
455 #define SRD XO31(539)
456 #define SRAD XO31(794)
457 #define SRADI XO31(413<<1)
460 #define TRAP (TW | TO(31))
462 #define NOP ORI /* ori 0,0,0 */
464 #define RT(r) ((r)<<21)
465 #define RS(r) ((r)<<21)
466 #define RA(r) ((r)<<16)
467 #define RB(r) ((r)<<11)
468 #define TO(t) ((t)<<21)
469 #define SH(s) ((s)<<11)
470 #define MB(b) ((b)<<6)
471 #define ME(e) ((e)<<1)
472 #define BO(o) ((o)<<21)
473 #define MB64(b) ((b)<<5)
474 #define FXM(b) (1 << (19 - (b)))
478 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
479 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
480 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
481 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
483 #define BF(n) ((n)<<23)
484 #define BI(n, c) (((c)+((n)*4))<<16)
485 #define BT(n, c) (((c)+((n)*4))<<21)
486 #define BA(n, c) (((c)+((n)*4))<<16)
487 #define BB(n, c) (((c)+((n)*4))<<11)
488 #define BC_(n, c) (((c)+((n)*4))<<6)
490 #define BO_COND_TRUE BO(12)
491 #define BO_COND_FALSE BO( 4)
492 #define BO_ALWAYS BO(20)
501 static const uint32_t tcg_to_bc
[] = {
502 [TCG_COND_EQ
] = BC
| BI(7, CR_EQ
) | BO_COND_TRUE
,
503 [TCG_COND_NE
] = BC
| BI(7, CR_EQ
) | BO_COND_FALSE
,
504 [TCG_COND_LT
] = BC
| BI(7, CR_LT
) | BO_COND_TRUE
,
505 [TCG_COND_GE
] = BC
| BI(7, CR_LT
) | BO_COND_FALSE
,
506 [TCG_COND_LE
] = BC
| BI(7, CR_GT
) | BO_COND_FALSE
,
507 [TCG_COND_GT
] = BC
| BI(7, CR_GT
) | BO_COND_TRUE
,
508 [TCG_COND_LTU
] = BC
| BI(7, CR_LT
) | BO_COND_TRUE
,
509 [TCG_COND_GEU
] = BC
| BI(7, CR_LT
) | BO_COND_FALSE
,
510 [TCG_COND_LEU
] = BC
| BI(7, CR_GT
) | BO_COND_FALSE
,
511 [TCG_COND_GTU
] = BC
| BI(7, CR_GT
) | BO_COND_TRUE
,
514 /* The low bit here is set if the RA and RB fields must be inverted. */
515 static const uint32_t tcg_to_isel
[] = {
516 [TCG_COND_EQ
] = ISEL
| BC_(7, CR_EQ
),
517 [TCG_COND_NE
] = ISEL
| BC_(7, CR_EQ
) | 1,
518 [TCG_COND_LT
] = ISEL
| BC_(7, CR_LT
),
519 [TCG_COND_GE
] = ISEL
| BC_(7, CR_LT
) | 1,
520 [TCG_COND_LE
] = ISEL
| BC_(7, CR_GT
) | 1,
521 [TCG_COND_GT
] = ISEL
| BC_(7, CR_GT
),
522 [TCG_COND_LTU
] = ISEL
| BC_(7, CR_LT
),
523 [TCG_COND_GEU
] = ISEL
| BC_(7, CR_LT
) | 1,
524 [TCG_COND_LEU
] = ISEL
| BC_(7, CR_GT
) | 1,
525 [TCG_COND_GTU
] = ISEL
| BC_(7, CR_GT
),
528 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
529 intptr_t value
, intptr_t addend
)
531 tcg_insn_unit
*target
;
534 target
= (tcg_insn_unit
*)value
;
538 return reloc_pc14(code_ptr
, target
);
540 return reloc_pc24(code_ptr
, target
);
543 * We are (slightly) abusing this relocation type. In particular,
544 * assert that the low 2 bits are zero, and do not modify them.
545 * That way we can use this with LD et al that have opcode bits
546 * in the low 2 bits of the insn.
548 if ((value
& 3) || value
!= (int16_t)value
) {
551 *code_ptr
= (*code_ptr
& ~0xfffc) | (value
& 0xfffc);
554 g_assert_not_reached();
559 static void tcg_out_mem_long(TCGContext
*s
, int opi
, int opx
, TCGReg rt
,
560 TCGReg base
, tcg_target_long offset
);
562 static bool tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
564 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
566 tcg_out32(s
, OR
| SAB(arg
, ret
, arg
));
571 static inline void tcg_out_rld(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
574 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
575 sh
= SH(sh
& 0x1f) | (((sh
>> 5) & 1) << 1);
576 mb
= MB64((mb
>> 5) | ((mb
<< 1) & 0x3f));
577 tcg_out32(s
, op
| RA(ra
) | RS(rs
) | sh
| mb
);
580 static inline void tcg_out_rlw(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
581 int sh
, int mb
, int me
)
583 tcg_out32(s
, op
| RA(ra
) | RS(rs
) | SH(sh
) | MB(mb
) | ME(me
));
586 static inline void tcg_out_ext32u(TCGContext
*s
, TCGReg dst
, TCGReg src
)
588 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, 32);
591 static inline void tcg_out_shli32(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
593 tcg_out_rlw(s
, RLWINM
, dst
, src
, c
, 0, 31 - c
);
596 static inline void tcg_out_shli64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
598 tcg_out_rld(s
, RLDICR
, dst
, src
, c
, 63 - c
);
601 static inline void tcg_out_shri32(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
603 tcg_out_rlw(s
, RLWINM
, dst
, src
, 32 - c
, c
, 31);
606 static inline void tcg_out_shri64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
608 tcg_out_rld(s
, RLDICL
, dst
, src
, 64 - c
, c
);
611 /* Emit a move into ret of arg, if it can be done in one insn. */
612 static bool tcg_out_movi_one(TCGContext
*s
, TCGReg ret
, tcg_target_long arg
)
614 if (arg
== (int16_t)arg
) {
615 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
618 if (arg
== (int32_t)arg
&& (arg
& 0xffff) == 0) {
619 tcg_out32(s
, ADDIS
| TAI(ret
, 0, arg
>> 16));
625 static void tcg_out_movi_int(TCGContext
*s
, TCGType type
, TCGReg ret
,
626 tcg_target_long arg
, bool in_prologue
)
632 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
634 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
638 /* Load 16-bit immediates with one insn. */
639 if (tcg_out_movi_one(s
, ret
, arg
)) {
643 /* Load addresses within the TB with one insn. */
644 tb_diff
= arg
- (intptr_t)s
->code_gen_ptr
;
645 if (!in_prologue
&& USE_REG_TB
&& tb_diff
== (int16_t)tb_diff
) {
646 tcg_out32(s
, ADDI
| TAI(ret
, TCG_REG_TB
, tb_diff
));
650 /* Load 32-bit immediates with two insns. Note that we've already
651 eliminated bare ADDIS, so we know both insns are required. */
652 if (TCG_TARGET_REG_BITS
== 32 || arg
== (int32_t)arg
) {
653 tcg_out32(s
, ADDIS
| TAI(ret
, 0, arg
>> 16));
654 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
657 if (arg
== (uint32_t)arg
&& !(arg
& 0x8000)) {
658 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
659 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
663 /* Load masked 16-bit value. */
664 if (arg
> 0 && (arg
& 0x8000)) {
666 if ((tmp
& (tmp
+ 1)) == 0) {
667 int mb
= clz64(tmp
+ 1) + 1;
668 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
669 tcg_out_rld(s
, RLDICL
, ret
, ret
, 0, mb
);
674 /* Load common masks with 2 insns. */
677 if (tmp
== (int16_t)tmp
) {
678 tcg_out32(s
, ADDI
| TAI(ret
, 0, tmp
));
679 tcg_out_shli64(s
, ret
, ret
, shift
);
683 if (tcg_out_movi_one(s
, ret
, arg
<< shift
)) {
684 tcg_out_shri64(s
, ret
, ret
, shift
);
688 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
689 if (!in_prologue
&& USE_REG_TB
&& tb_diff
== (int32_t)tb_diff
) {
690 tcg_out_mem_long(s
, ADDI
, ADD
, ret
, TCG_REG_TB
, tb_diff
);
694 /* Use the constant pool, if possible. */
695 if (!in_prologue
&& USE_REG_TB
) {
696 new_pool_label(s
, arg
, R_PPC_ADDR16
, s
->code_ptr
,
697 -(intptr_t)s
->code_gen_ptr
);
698 tcg_out32(s
, LD
| TAI(ret
, TCG_REG_TB
, 0));
702 tmp
= arg
>> 31 >> 1;
703 tcg_out_movi(s
, TCG_TYPE_I32
, ret
, tmp
);
705 tcg_out_shli64(s
, ret
, ret
, 32);
707 if (arg
& 0xffff0000) {
708 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
711 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
715 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
, TCGReg ret
,
718 tcg_out_movi_int(s
, type
, ret
, arg
, false);
721 static bool mask_operand(uint32_t c
, int *mb
, int *me
)
725 /* Accept a bit pattern like:
729 Keep track of the transitions. */
730 if (c
== 0 || c
== -1) {
736 if (test
& (test
- 1)) {
741 *mb
= test
? clz32(test
& -test
) + 1 : 0;
745 static bool mask64_operand(uint64_t c
, int *mb
, int *me
)
754 /* Accept 1..10..0. */
760 /* Accept 0..01..1. */
761 if (lsb
== 1 && (c
& (c
+ 1)) == 0) {
762 *mb
= clz64(c
+ 1) + 1;
769 static void tcg_out_andi32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
773 if (mask_operand(c
, &mb
, &me
)) {
774 tcg_out_rlw(s
, RLWINM
, dst
, src
, 0, mb
, me
);
775 } else if ((c
& 0xffff) == c
) {
776 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
778 } else if ((c
& 0xffff0000) == c
) {
779 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
782 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_R0
, c
);
783 tcg_out32(s
, AND
| SAB(src
, dst
, TCG_REG_R0
));
787 static void tcg_out_andi64(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint64_t c
)
791 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64);
792 if (mask64_operand(c
, &mb
, &me
)) {
794 tcg_out_rld(s
, RLDICR
, dst
, src
, 0, me
);
796 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, mb
);
798 } else if ((c
& 0xffff) == c
) {
799 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
801 } else if ((c
& 0xffff0000) == c
) {
802 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
805 tcg_out_movi(s
, TCG_TYPE_I64
, TCG_REG_R0
, c
);
806 tcg_out32(s
, AND
| SAB(src
, dst
, TCG_REG_R0
));
810 static void tcg_out_zori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
,
811 int op_lo
, int op_hi
)
814 tcg_out32(s
, op_hi
| SAI(src
, dst
, c
>> 16));
818 tcg_out32(s
, op_lo
| SAI(src
, dst
, c
));
823 static void tcg_out_ori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
825 tcg_out_zori32(s
, dst
, src
, c
, ORI
, ORIS
);
828 static void tcg_out_xori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
830 tcg_out_zori32(s
, dst
, src
, c
, XORI
, XORIS
);
833 static void tcg_out_b(TCGContext
*s
, int mask
, tcg_insn_unit
*target
)
835 ptrdiff_t disp
= tcg_pcrel_diff(s
, target
);
836 if (in_range_b(disp
)) {
837 tcg_out32(s
, B
| (disp
& 0x3fffffc) | mask
);
839 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R0
, (uintptr_t)target
);
840 tcg_out32(s
, MTSPR
| RS(TCG_REG_R0
) | CTR
);
841 tcg_out32(s
, BCCTR
| BO_ALWAYS
| mask
);
845 static void tcg_out_mem_long(TCGContext
*s
, int opi
, int opx
, TCGReg rt
,
846 TCGReg base
, tcg_target_long offset
)
848 tcg_target_long orig
= offset
, l0
, l1
, extra
= 0, align
= 0;
849 bool is_store
= false;
850 TCGReg rs
= TCG_REG_TMP1
;
857 if (rt
!= TCG_REG_R0
) {
865 case STB
: case STH
: case STW
:
870 /* For unaligned, or very large offsets, use the indexed form. */
871 if (offset
& align
|| offset
!= (int32_t)offset
) {
875 tcg_debug_assert(!is_store
|| rs
!= rt
);
876 tcg_out_movi(s
, TCG_TYPE_PTR
, rs
, orig
);
877 tcg_out32(s
, opx
| TAB(rt
, base
, rs
));
881 l0
= (int16_t)offset
;
882 offset
= (offset
- l0
) >> 16;
883 l1
= (int16_t)offset
;
885 if (l1
< 0 && orig
>= 0) {
887 l1
= (int16_t)(offset
- 0x4000);
890 tcg_out32(s
, ADDIS
| TAI(rs
, base
, l1
));
894 tcg_out32(s
, ADDIS
| TAI(rs
, base
, extra
));
897 if (opi
!= ADDI
|| base
!= rt
|| l0
!= 0) {
898 tcg_out32(s
, opi
| TAI(rt
, base
, l0
));
902 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
,
903 TCGReg arg1
, intptr_t arg2
)
907 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
908 if (type
== TCG_TYPE_I32
) {
909 opi
= LWZ
, opx
= LWZX
;
913 tcg_out_mem_long(s
, opi
, opx
, ret
, arg1
, arg2
);
916 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
917 TCGReg arg1
, intptr_t arg2
)
921 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
922 if (type
== TCG_TYPE_I32
) {
923 opi
= STW
, opx
= STWX
;
925 opi
= STD
, opx
= STDX
;
927 tcg_out_mem_long(s
, opi
, opx
, arg
, arg1
, arg2
);
930 static inline bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
931 TCGReg base
, intptr_t ofs
)
936 static void tcg_out_cmp(TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
937 int const_arg2
, int cr
, TCGType type
)
942 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
944 /* Simplify the comparisons below wrt CMPI. */
945 if (type
== TCG_TYPE_I32
) {
946 arg2
= (int32_t)arg2
;
953 if ((int16_t) arg2
== arg2
) {
957 } else if ((uint16_t) arg2
== arg2
) {
972 if ((int16_t) arg2
== arg2
) {
987 if ((uint16_t) arg2
== arg2
) {
1000 op
|= BF(cr
) | ((type
== TCG_TYPE_I64
) << 21);
1003 tcg_out32(s
, op
| RA(arg1
) | (arg2
& 0xffff));
1006 tcg_out_movi(s
, type
, TCG_REG_R0
, arg2
);
1009 tcg_out32(s
, op
| RA(arg1
) | RB(arg2
));
1013 static void tcg_out_setcond_eq0(TCGContext
*s
, TCGType type
,
1014 TCGReg dst
, TCGReg src
)
1016 if (type
== TCG_TYPE_I32
) {
1017 tcg_out32(s
, CNTLZW
| RS(src
) | RA(dst
));
1018 tcg_out_shri32(s
, dst
, dst
, 5);
1020 tcg_out32(s
, CNTLZD
| RS(src
) | RA(dst
));
1021 tcg_out_shri64(s
, dst
, dst
, 6);
1025 static void tcg_out_setcond_ne0(TCGContext
*s
, TCGReg dst
, TCGReg src
)
1027 /* X != 0 implies X + -1 generates a carry. Extra addition
1028 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1030 tcg_out32(s
, ADDIC
| TAI(dst
, src
, -1));
1031 tcg_out32(s
, SUBFE
| TAB(dst
, dst
, src
));
1033 tcg_out32(s
, ADDIC
| TAI(TCG_REG_R0
, src
, -1));
1034 tcg_out32(s
, SUBFE
| TAB(dst
, TCG_REG_R0
, src
));
1038 static TCGReg
tcg_gen_setcond_xor(TCGContext
*s
, TCGReg arg1
, TCGArg arg2
,
1042 if ((uint32_t)arg2
== arg2
) {
1043 tcg_out_xori32(s
, TCG_REG_R0
, arg1
, arg2
);
1045 tcg_out_movi(s
, TCG_TYPE_I64
, TCG_REG_R0
, arg2
);
1046 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, TCG_REG_R0
));
1049 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, arg2
));
1054 static void tcg_out_setcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
1055 TCGArg arg0
, TCGArg arg1
, TCGArg arg2
,
1060 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
1062 /* Ignore high bits of a potential constant arg2. */
1063 if (type
== TCG_TYPE_I32
) {
1064 arg2
= (uint32_t)arg2
;
1067 /* Handle common and trivial cases before handling anything else. */
1071 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
1074 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
1075 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1078 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1081 tcg_out32(s
, NOR
| SAB(arg1
, arg0
, arg1
));
1085 /* Extract the sign bit. */
1086 if (type
== TCG_TYPE_I32
) {
1087 tcg_out_shri32(s
, arg0
, arg1
, 31);
1089 tcg_out_shri64(s
, arg0
, arg1
, 63);
1097 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1098 All other cases below are also at least 3 insns, so speed up the
1099 code generator by not considering them and always using ISEL. */
1103 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1105 isel
= tcg_to_isel
[cond
];
1107 tcg_out_movi(s
, type
, arg0
, 1);
1109 /* arg0 = (bc ? 0 : 1) */
1110 tab
= TAB(arg0
, 0, arg0
);
1113 /* arg0 = (bc ? 1 : 0) */
1114 tcg_out_movi(s
, type
, TCG_REG_R0
, 0);
1115 tab
= TAB(arg0
, arg0
, TCG_REG_R0
);
1117 tcg_out32(s
, isel
| tab
);
1123 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1124 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
1128 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1129 /* Discard the high bits only once, rather than both inputs. */
1130 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
1131 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1134 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1152 crop
= CRNOR
| BT(7, CR_EQ
) | BA(7, CR_LT
) | BB(7, CR_LT
);
1158 crop
= CRNOR
| BT(7, CR_EQ
) | BA(7, CR_GT
) | BB(7, CR_GT
);
1160 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1164 tcg_out32(s
, MFOCRF
| RT(TCG_REG_R0
) | FXM(7));
1165 tcg_out_rlw(s
, RLWINM
, arg0
, TCG_REG_R0
, sh
, 31, 31);
1173 static void tcg_out_bc(TCGContext
*s
, int bc
, TCGLabel
*l
)
1176 bc
|= reloc_pc14_val(s
->code_ptr
, l
->u
.value_ptr
);
1178 tcg_out_reloc(s
, s
->code_ptr
, R_PPC_REL14
, l
, 0);
1183 static void tcg_out_brcond(TCGContext
*s
, TCGCond cond
,
1184 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
1185 TCGLabel
*l
, TCGType type
)
1187 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1188 tcg_out_bc(s
, tcg_to_bc
[cond
], l
);
1191 static void tcg_out_movcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
1192 TCGArg dest
, TCGArg c1
, TCGArg c2
, TCGArg v1
,
1193 TCGArg v2
, bool const_c2
)
1195 /* If for some reason both inputs are zero, don't produce bad code. */
1196 if (v1
== 0 && v2
== 0) {
1197 tcg_out_movi(s
, type
, dest
, 0);
1201 tcg_out_cmp(s
, cond
, c1
, c2
, const_c2
, 7, type
);
1204 int isel
= tcg_to_isel
[cond
];
1206 /* Swap the V operands if the operation indicates inversion. */
1213 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1215 tcg_out_movi(s
, type
, TCG_REG_R0
, 0);
1217 tcg_out32(s
, isel
| TAB(dest
, v1
, v2
));
1220 cond
= tcg_invert_cond(cond
);
1222 } else if (dest
!= v1
) {
1224 tcg_out_movi(s
, type
, dest
, 0);
1226 tcg_out_mov(s
, type
, dest
, v1
);
1229 /* Branch forward over one insn */
1230 tcg_out32(s
, tcg_to_bc
[cond
] | 8);
1232 tcg_out_movi(s
, type
, dest
, 0);
1234 tcg_out_mov(s
, type
, dest
, v2
);
1239 static void tcg_out_cntxz(TCGContext
*s
, TCGType type
, uint32_t opc
,
1240 TCGArg a0
, TCGArg a1
, TCGArg a2
, bool const_a2
)
1242 if (const_a2
&& a2
== (type
== TCG_TYPE_I32
? 32 : 64)) {
1243 tcg_out32(s
, opc
| RA(a0
) | RS(a1
));
1245 tcg_out_cmp(s
, TCG_COND_EQ
, a1
, 0, 1, 7, type
);
1246 /* Note that the only other valid constant for a2 is 0. */
1248 tcg_out32(s
, opc
| RA(TCG_REG_R0
) | RS(a1
));
1249 tcg_out32(s
, tcg_to_isel
[TCG_COND_EQ
] | TAB(a0
, a2
, TCG_REG_R0
));
1250 } else if (!const_a2
&& a0
== a2
) {
1251 tcg_out32(s
, tcg_to_bc
[TCG_COND_EQ
] | 8);
1252 tcg_out32(s
, opc
| RA(a0
) | RS(a1
));
1254 tcg_out32(s
, opc
| RA(a0
) | RS(a1
));
1255 tcg_out32(s
, tcg_to_bc
[TCG_COND_NE
] | 8);
1257 tcg_out_movi(s
, type
, a0
, 0);
1259 tcg_out_mov(s
, type
, a0
, a2
);
1265 static void tcg_out_cmp2(TCGContext
*s
, const TCGArg
*args
,
1266 const int *const_args
)
1268 static const struct { uint8_t bit1
, bit2
; } bits
[] = {
1269 [TCG_COND_LT
] = { CR_LT
, CR_LT
},
1270 [TCG_COND_LE
] = { CR_LT
, CR_GT
},
1271 [TCG_COND_GT
] = { CR_GT
, CR_GT
},
1272 [TCG_COND_GE
] = { CR_GT
, CR_LT
},
1273 [TCG_COND_LTU
] = { CR_LT
, CR_LT
},
1274 [TCG_COND_LEU
] = { CR_LT
, CR_GT
},
1275 [TCG_COND_GTU
] = { CR_GT
, CR_GT
},
1276 [TCG_COND_GEU
] = { CR_GT
, CR_LT
},
1279 TCGCond cond
= args
[4], cond2
;
1280 TCGArg al
, ah
, bl
, bh
;
1281 int blconst
, bhconst
;
1288 blconst
= const_args
[2];
1289 bhconst
= const_args
[3];
1298 tcg_out_cmp(s
, cond
, al
, bl
, blconst
, 6, TCG_TYPE_I32
);
1299 tcg_out_cmp(s
, cond
, ah
, bh
, bhconst
, 7, TCG_TYPE_I32
);
1300 tcg_out32(s
, op
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, CR_EQ
));
1311 bit1
= bits
[cond
].bit1
;
1312 bit2
= bits
[cond
].bit2
;
1313 op
= (bit1
!= bit2
? CRANDC
: CRAND
);
1314 cond2
= tcg_unsigned_cond(cond
);
1316 tcg_out_cmp(s
, cond
, ah
, bh
, bhconst
, 6, TCG_TYPE_I32
);
1317 tcg_out_cmp(s
, cond2
, al
, bl
, blconst
, 7, TCG_TYPE_I32
);
1318 tcg_out32(s
, op
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, bit2
));
1319 tcg_out32(s
, CROR
| BT(7, CR_EQ
) | BA(6, bit1
) | BB(7, CR_EQ
));
1327 static void tcg_out_setcond2(TCGContext
*s
, const TCGArg
*args
,
1328 const int *const_args
)
1330 tcg_out_cmp2(s
, args
+ 1, const_args
+ 1);
1331 tcg_out32(s
, MFOCRF
| RT(TCG_REG_R0
) | FXM(7));
1332 tcg_out_rlw(s
, RLWINM
, args
[0], TCG_REG_R0
, 31, 31, 31);
1335 static void tcg_out_brcond2 (TCGContext
*s
, const TCGArg
*args
,
1336 const int *const_args
)
1338 tcg_out_cmp2(s
, args
, const_args
);
1339 tcg_out_bc(s
, BC
| BI(7, CR_EQ
) | BO_COND_TRUE
, arg_label(args
[5]));
1342 static void tcg_out_mb(TCGContext
*s
, TCGArg a0
)
1344 uint32_t insn
= HWSYNC
;
1346 if (a0
== TCG_MO_LD_LD
) {
1348 } else if (a0
== TCG_MO_ST_ST
) {
1354 void tb_target_set_jmp_target(uintptr_t tc_ptr
, uintptr_t jmp_addr
,
1357 if (TCG_TARGET_REG_BITS
== 64) {
1358 tcg_insn_unit i1
, i2
;
1359 intptr_t tb_diff
= addr
- tc_ptr
;
1360 intptr_t br_diff
= addr
- (jmp_addr
+ 4);
1363 /* This does not exercise the range of the branch, but we do
1364 still need to be able to load the new value of TCG_REG_TB.
1365 But this does still happen quite often. */
1366 if (tb_diff
== (int16_t)tb_diff
) {
1367 i1
= ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, tb_diff
);
1368 i2
= B
| (br_diff
& 0x3fffffc);
1370 intptr_t lo
= (int16_t)tb_diff
;
1371 intptr_t hi
= (int32_t)(tb_diff
- lo
);
1372 assert(tb_diff
== hi
+ lo
);
1373 i1
= ADDIS
| TAI(TCG_REG_TB
, TCG_REG_TB
, hi
>> 16);
1374 i2
= ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, lo
);
1376 #ifdef HOST_WORDS_BIGENDIAN
1377 pair
= (uint64_t)i1
<< 32 | i2
;
1379 pair
= (uint64_t)i2
<< 32 | i1
;
1382 /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
1383 within atomic_set that would fail to build a ppc32 host. */
1384 atomic_set__nocheck((uint64_t *)jmp_addr
, pair
);
1385 flush_icache_range(jmp_addr
, jmp_addr
+ 8);
1387 intptr_t diff
= addr
- jmp_addr
;
1388 tcg_debug_assert(in_range_b(diff
));
1389 atomic_set((uint32_t *)jmp_addr
, B
| (diff
& 0x3fffffc));
1390 flush_icache_range(jmp_addr
, jmp_addr
+ 4);
1394 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*target
)
1397 /* Look through the descriptor. If the branch is in range, and we
1398 don't have to spend too much effort on building the toc. */
1399 void *tgt
= ((void **)target
)[0];
1400 uintptr_t toc
= ((uintptr_t *)target
)[1];
1401 intptr_t diff
= tcg_pcrel_diff(s
, tgt
);
1403 if (in_range_b(diff
) && toc
== (uint32_t)toc
) {
1404 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP1
, toc
);
1405 tcg_out_b(s
, LK
, tgt
);
1407 /* Fold the low bits of the constant into the addresses below. */
1408 intptr_t arg
= (intptr_t)target
;
1409 int ofs
= (int16_t)arg
;
1411 if (ofs
+ 8 < 0x8000) {
1416 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP1
, arg
);
1417 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_TMP1
, ofs
);
1418 tcg_out32(s
, MTSPR
| RA(TCG_REG_R0
) | CTR
);
1419 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R2
, TCG_REG_TMP1
, ofs
+ SZP
);
1420 tcg_out32(s
, BCCTR
| BO_ALWAYS
| LK
);
1422 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1425 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1426 address, which the callee uses to compute its TOC address. */
1427 /* FIXME: when the branch is in range, we could avoid r12 load if we
1428 knew that the destination uses the same TOC, and what its local
1429 entry point offset is. */
1430 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R12
, (intptr_t)target
);
1432 diff
= tcg_pcrel_diff(s
, target
);
1433 if (in_range_b(diff
)) {
1434 tcg_out_b(s
, LK
, target
);
1436 tcg_out32(s
, MTSPR
| RS(TCG_REG_R12
) | CTR
);
1437 tcg_out32(s
, BCCTR
| BO_ALWAYS
| LK
);
1440 tcg_out_b(s
, LK
, target
);
1444 static const uint32_t qemu_ldx_opc
[16] = {
1451 [MO_BSWAP
| MO_UB
] = LBZX
,
1452 [MO_BSWAP
| MO_UW
] = LHBRX
,
1453 [MO_BSWAP
| MO_UL
] = LWBRX
,
1454 [MO_BSWAP
| MO_Q
] = LDBRX
,
1457 static const uint32_t qemu_stx_opc
[16] = {
1462 [MO_BSWAP
| MO_UB
] = STBX
,
1463 [MO_BSWAP
| MO_UW
] = STHBRX
,
1464 [MO_BSWAP
| MO_UL
] = STWBRX
,
1465 [MO_BSWAP
| MO_Q
] = STDBRX
,
1468 static const uint32_t qemu_exts_opc
[4] = {
1469 EXTSB
, EXTSH
, EXTSW
, 0
1472 #if defined (CONFIG_SOFTMMU)
1473 #include "tcg-ldst.inc.c"
1475 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1476 * int mmu_idx, uintptr_t ra)
1478 static void * const qemu_ld_helpers
[16] = {
1479 [MO_UB
] = helper_ret_ldub_mmu
,
1480 [MO_LEUW
] = helper_le_lduw_mmu
,
1481 [MO_LEUL
] = helper_le_ldul_mmu
,
1482 [MO_LEQ
] = helper_le_ldq_mmu
,
1483 [MO_BEUW
] = helper_be_lduw_mmu
,
1484 [MO_BEUL
] = helper_be_ldul_mmu
,
1485 [MO_BEQ
] = helper_be_ldq_mmu
,
1488 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1489 * uintxx_t val, int mmu_idx, uintptr_t ra)
1491 static void * const qemu_st_helpers
[16] = {
1492 [MO_UB
] = helper_ret_stb_mmu
,
1493 [MO_LEUW
] = helper_le_stw_mmu
,
1494 [MO_LEUL
] = helper_le_stl_mmu
,
1495 [MO_LEQ
] = helper_le_stq_mmu
,
1496 [MO_BEUW
] = helper_be_stw_mmu
,
1497 [MO_BEUL
] = helper_be_stl_mmu
,
1498 [MO_BEQ
] = helper_be_stq_mmu
,
1501 /* We expect to use a 16-bit negative offset from ENV. */
1502 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1503 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1505 /* Perform the TLB load and compare. Places the result of the comparison
1506 in CR7, loads the addend of the TLB into R3, and returns the register
1507 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1509 static TCGReg
tcg_out_tlb_read(TCGContext
*s
, TCGMemOp opc
,
1510 TCGReg addrlo
, TCGReg addrhi
,
1511 int mem_index
, bool is_read
)
1515 ? offsetof(CPUTLBEntry
, addr_read
)
1516 : offsetof(CPUTLBEntry
, addr_write
));
1517 int fast_off
= TLB_MASK_TABLE_OFS(mem_index
);
1518 int mask_off
= fast_off
+ offsetof(CPUTLBDescFast
, mask
);
1519 int table_off
= fast_off
+ offsetof(CPUTLBDescFast
, table
);
1520 unsigned s_bits
= opc
& MO_SIZE
;
1521 unsigned a_bits
= get_alignment_bits(opc
);
1523 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1524 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R3
, TCG_AREG0
, mask_off
);
1525 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R4
, TCG_AREG0
, table_off
);
1527 /* Extract the page index, shifted into place for tlb index. */
1528 if (TCG_TARGET_REG_BITS
== 32) {
1529 tcg_out_shri32(s
, TCG_REG_TMP1
, addrlo
,
1530 TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
1532 tcg_out_shri64(s
, TCG_REG_TMP1
, addrlo
,
1533 TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
1535 tcg_out32(s
, AND
| SAB(TCG_REG_R3
, TCG_REG_R3
, TCG_REG_TMP1
));
1537 /* Load the TLB comparator. */
1538 if (cmp_off
== 0 && TCG_TARGET_REG_BITS
>= TARGET_LONG_BITS
) {
1539 uint32_t lxu
= (TCG_TARGET_REG_BITS
== 32 || TARGET_LONG_BITS
== 32
1541 tcg_out32(s
, lxu
| TAB(TCG_REG_TMP1
, TCG_REG_R3
, TCG_REG_R4
));
1543 tcg_out32(s
, ADD
| TAB(TCG_REG_R3
, TCG_REG_R3
, TCG_REG_R4
));
1544 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1545 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_REG_TMP1
, TCG_REG_R3
, cmp_off
+ 4);
1546 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_REG_R4
, TCG_REG_R3
, cmp_off
);
1548 tcg_out_ld(s
, TCG_TYPE_TL
, TCG_REG_TMP1
, TCG_REG_R3
, cmp_off
);
1552 /* Load the TLB addend for use on the fast path. Do this asap
1553 to minimize any load use delay. */
1554 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R3
, TCG_REG_R3
,
1555 offsetof(CPUTLBEntry
, addend
));
1557 /* Clear the non-page, non-alignment bits from the address */
1558 if (TCG_TARGET_REG_BITS
== 32) {
1559 /* We don't support unaligned accesses on 32-bits.
1560 * Preserve the bottom bits and thus trigger a comparison
1561 * failure on unaligned accesses.
1563 if (a_bits
< s_bits
) {
1566 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, addrlo
, 0,
1567 (32 - a_bits
) & 31, 31 - TARGET_PAGE_BITS
);
1571 /* If the access is unaligned, we need to make sure we fail if we
1572 * cross a page boundary. The trick is to add the access size-1
1573 * to the address before masking the low bits. That will make the
1574 * address overflow to the next page if we cross a page boundary,
1575 * which will then force a mismatch of the TLB compare.
1577 if (a_bits
< s_bits
) {
1578 unsigned a_mask
= (1 << a_bits
) - 1;
1579 unsigned s_mask
= (1 << s_bits
) - 1;
1580 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, t
, s_mask
- a_mask
));
1584 /* Mask the address for the requested alignment. */
1585 if (TARGET_LONG_BITS
== 32) {
1586 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, t
, 0,
1587 (32 - a_bits
) & 31, 31 - TARGET_PAGE_BITS
);
1588 /* Zero-extend the address for use in the final address. */
1589 tcg_out_ext32u(s
, TCG_REG_R4
, addrlo
);
1590 addrlo
= TCG_REG_R4
;
1591 } else if (a_bits
== 0) {
1592 tcg_out_rld(s
, RLDICR
, TCG_REG_R0
, t
, 0, 63 - TARGET_PAGE_BITS
);
1594 tcg_out_rld(s
, RLDICL
, TCG_REG_R0
, t
,
1595 64 - TARGET_PAGE_BITS
, TARGET_PAGE_BITS
- a_bits
);
1596 tcg_out_rld(s
, RLDICL
, TCG_REG_R0
, TCG_REG_R0
, TARGET_PAGE_BITS
, 0);
1600 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1601 tcg_out_cmp(s
, TCG_COND_EQ
, TCG_REG_R0
, TCG_REG_TMP1
,
1602 0, 7, TCG_TYPE_I32
);
1603 tcg_out_cmp(s
, TCG_COND_EQ
, addrhi
, TCG_REG_R4
, 0, 6, TCG_TYPE_I32
);
1604 tcg_out32(s
, CRAND
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, CR_EQ
));
1606 tcg_out_cmp(s
, TCG_COND_EQ
, TCG_REG_R0
, TCG_REG_TMP1
,
1613 /* Record the context of a call to the out of line helper code for the slow
1614 path for a load or store, so that we can later generate the correct
1616 static void add_qemu_ldst_label(TCGContext
*s
, bool is_ld
, TCGMemOpIdx oi
,
1617 TCGReg datalo_reg
, TCGReg datahi_reg
,
1618 TCGReg addrlo_reg
, TCGReg addrhi_reg
,
1619 tcg_insn_unit
*raddr
, tcg_insn_unit
*lptr
)
1621 TCGLabelQemuLdst
*label
= new_ldst_label(s
);
1623 label
->is_ld
= is_ld
;
1625 label
->datalo_reg
= datalo_reg
;
1626 label
->datahi_reg
= datahi_reg
;
1627 label
->addrlo_reg
= addrlo_reg
;
1628 label
->addrhi_reg
= addrhi_reg
;
1629 label
->raddr
= raddr
;
1630 label
->label_ptr
[0] = lptr
;
1633 static bool tcg_out_qemu_ld_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1635 TCGMemOpIdx oi
= lb
->oi
;
1636 TCGMemOp opc
= get_memop(oi
);
1637 TCGReg hi
, lo
, arg
= TCG_REG_R3
;
1639 if (!reloc_pc14(lb
->label_ptr
[0], s
->code_ptr
)) {
1643 tcg_out_mov(s
, TCG_TYPE_PTR
, arg
++, TCG_AREG0
);
1645 lo
= lb
->addrlo_reg
;
1646 hi
= lb
->addrhi_reg
;
1647 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1648 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1651 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1652 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1654 /* If the address needed to be zero-extended, we'll have already
1655 placed it in R4. The only remaining case is 64-bit guest. */
1656 tcg_out_mov(s
, TCG_TYPE_TL
, arg
++, lo
);
1659 tcg_out_movi(s
, TCG_TYPE_I32
, arg
++, oi
);
1660 tcg_out32(s
, MFSPR
| RT(arg
) | LR
);
1662 tcg_out_call(s
, qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1664 lo
= lb
->datalo_reg
;
1665 hi
= lb
->datahi_reg
;
1666 if (TCG_TARGET_REG_BITS
== 32 && (opc
& MO_SIZE
) == MO_64
) {
1667 tcg_out_mov(s
, TCG_TYPE_I32
, lo
, TCG_REG_R4
);
1668 tcg_out_mov(s
, TCG_TYPE_I32
, hi
, TCG_REG_R3
);
1669 } else if (opc
& MO_SIGN
) {
1670 uint32_t insn
= qemu_exts_opc
[opc
& MO_SIZE
];
1671 tcg_out32(s
, insn
| RA(lo
) | RS(TCG_REG_R3
));
1673 tcg_out_mov(s
, TCG_TYPE_REG
, lo
, TCG_REG_R3
);
1676 tcg_out_b(s
, 0, lb
->raddr
);
1680 static bool tcg_out_qemu_st_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1682 TCGMemOpIdx oi
= lb
->oi
;
1683 TCGMemOp opc
= get_memop(oi
);
1684 TCGMemOp s_bits
= opc
& MO_SIZE
;
1685 TCGReg hi
, lo
, arg
= TCG_REG_R3
;
1687 if (!reloc_pc14(lb
->label_ptr
[0], s
->code_ptr
)) {
1691 tcg_out_mov(s
, TCG_TYPE_PTR
, arg
++, TCG_AREG0
);
1693 lo
= lb
->addrlo_reg
;
1694 hi
= lb
->addrhi_reg
;
1695 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1696 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1699 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1700 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1702 /* If the address needed to be zero-extended, we'll have already
1703 placed it in R4. The only remaining case is 64-bit guest. */
1704 tcg_out_mov(s
, TCG_TYPE_TL
, arg
++, lo
);
1707 lo
= lb
->datalo_reg
;
1708 hi
= lb
->datahi_reg
;
1709 if (TCG_TARGET_REG_BITS
== 32) {
1712 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1715 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1718 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1721 tcg_out_rlw(s
, RLWINM
, arg
++, lo
, 0, 32 - (8 << s_bits
), 31);
1725 if (s_bits
== MO_64
) {
1726 tcg_out_mov(s
, TCG_TYPE_I64
, arg
++, lo
);
1728 tcg_out_rld(s
, RLDICL
, arg
++, lo
, 0, 64 - (8 << s_bits
));
1732 tcg_out_movi(s
, TCG_TYPE_I32
, arg
++, oi
);
1733 tcg_out32(s
, MFSPR
| RT(arg
) | LR
);
1735 tcg_out_call(s
, qemu_st_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1737 tcg_out_b(s
, 0, lb
->raddr
);
1740 #endif /* SOFTMMU */
1742 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1744 TCGReg datalo
, datahi
, addrlo
, rbase
;
1745 TCGReg addrhi
__attribute__((unused
));
1747 TCGMemOp opc
, s_bits
;
1748 #ifdef CONFIG_SOFTMMU
1750 tcg_insn_unit
*label_ptr
;
1754 datahi
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1756 addrhi
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1758 opc
= get_memop(oi
);
1759 s_bits
= opc
& MO_SIZE
;
1761 #ifdef CONFIG_SOFTMMU
1762 mem_index
= get_mmuidx(oi
);
1763 addrlo
= tcg_out_tlb_read(s
, opc
, addrlo
, addrhi
, mem_index
, true);
1765 /* Load a pointer into the current opcode w/conditional branch-link. */
1766 label_ptr
= s
->code_ptr
;
1767 tcg_out32(s
, BC
| BI(7, CR_EQ
) | BO_COND_FALSE
| LK
);
1770 #else /* !CONFIG_SOFTMMU */
1771 rbase
= guest_base
? TCG_GUEST_BASE_REG
: 0;
1772 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1773 tcg_out_ext32u(s
, TCG_REG_TMP1
, addrlo
);
1774 addrlo
= TCG_REG_TMP1
;
1778 if (TCG_TARGET_REG_BITS
== 32 && s_bits
== MO_64
) {
1779 if (opc
& MO_BSWAP
) {
1780 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1781 tcg_out32(s
, LWBRX
| TAB(datalo
, rbase
, addrlo
));
1782 tcg_out32(s
, LWBRX
| TAB(datahi
, rbase
, TCG_REG_R0
));
1783 } else if (rbase
!= 0) {
1784 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1785 tcg_out32(s
, LWZX
| TAB(datahi
, rbase
, addrlo
));
1786 tcg_out32(s
, LWZX
| TAB(datalo
, rbase
, TCG_REG_R0
));
1787 } else if (addrlo
== datahi
) {
1788 tcg_out32(s
, LWZ
| TAI(datalo
, addrlo
, 4));
1789 tcg_out32(s
, LWZ
| TAI(datahi
, addrlo
, 0));
1791 tcg_out32(s
, LWZ
| TAI(datahi
, addrlo
, 0));
1792 tcg_out32(s
, LWZ
| TAI(datalo
, addrlo
, 4));
1795 uint32_t insn
= qemu_ldx_opc
[opc
& (MO_BSWAP
| MO_SSIZE
)];
1796 if (!HAVE_ISA_2_06
&& insn
== LDBRX
) {
1797 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1798 tcg_out32(s
, LWBRX
| TAB(datalo
, rbase
, addrlo
));
1799 tcg_out32(s
, LWBRX
| TAB(TCG_REG_R0
, rbase
, TCG_REG_R0
));
1800 tcg_out_rld(s
, RLDIMI
, datalo
, TCG_REG_R0
, 32, 0);
1802 tcg_out32(s
, insn
| TAB(datalo
, rbase
, addrlo
));
1804 insn
= qemu_ldx_opc
[opc
& (MO_SIZE
| MO_BSWAP
)];
1805 tcg_out32(s
, insn
| TAB(datalo
, rbase
, addrlo
));
1806 insn
= qemu_exts_opc
[s_bits
];
1807 tcg_out32(s
, insn
| RA(datalo
) | RS(datalo
));
1811 #ifdef CONFIG_SOFTMMU
1812 add_qemu_ldst_label(s
, true, oi
, datalo
, datahi
, addrlo
, addrhi
,
1813 s
->code_ptr
, label_ptr
);
1817 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1819 TCGReg datalo
, datahi
, addrlo
, rbase
;
1820 TCGReg addrhi
__attribute__((unused
));
1822 TCGMemOp opc
, s_bits
;
1823 #ifdef CONFIG_SOFTMMU
1825 tcg_insn_unit
*label_ptr
;
1829 datahi
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1831 addrhi
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1833 opc
= get_memop(oi
);
1834 s_bits
= opc
& MO_SIZE
;
1836 #ifdef CONFIG_SOFTMMU
1837 mem_index
= get_mmuidx(oi
);
1838 addrlo
= tcg_out_tlb_read(s
, opc
, addrlo
, addrhi
, mem_index
, false);
1840 /* Load a pointer into the current opcode w/conditional branch-link. */
1841 label_ptr
= s
->code_ptr
;
1842 tcg_out32(s
, BC
| BI(7, CR_EQ
) | BO_COND_FALSE
| LK
);
1845 #else /* !CONFIG_SOFTMMU */
1846 rbase
= guest_base
? TCG_GUEST_BASE_REG
: 0;
1847 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1848 tcg_out_ext32u(s
, TCG_REG_TMP1
, addrlo
);
1849 addrlo
= TCG_REG_TMP1
;
1853 if (TCG_TARGET_REG_BITS
== 32 && s_bits
== MO_64
) {
1854 if (opc
& MO_BSWAP
) {
1855 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1856 tcg_out32(s
, STWBRX
| SAB(datalo
, rbase
, addrlo
));
1857 tcg_out32(s
, STWBRX
| SAB(datahi
, rbase
, TCG_REG_R0
));
1858 } else if (rbase
!= 0) {
1859 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1860 tcg_out32(s
, STWX
| SAB(datahi
, rbase
, addrlo
));
1861 tcg_out32(s
, STWX
| SAB(datalo
, rbase
, TCG_REG_R0
));
1863 tcg_out32(s
, STW
| TAI(datahi
, addrlo
, 0));
1864 tcg_out32(s
, STW
| TAI(datalo
, addrlo
, 4));
1867 uint32_t insn
= qemu_stx_opc
[opc
& (MO_BSWAP
| MO_SIZE
)];
1868 if (!HAVE_ISA_2_06
&& insn
== STDBRX
) {
1869 tcg_out32(s
, STWBRX
| SAB(datalo
, rbase
, addrlo
));
1870 tcg_out32(s
, ADDI
| TAI(TCG_REG_TMP1
, addrlo
, 4));
1871 tcg_out_shri64(s
, TCG_REG_R0
, datalo
, 32);
1872 tcg_out32(s
, STWBRX
| SAB(TCG_REG_R0
, rbase
, TCG_REG_TMP1
));
1874 tcg_out32(s
, insn
| SAB(datalo
, rbase
, addrlo
));
1878 #ifdef CONFIG_SOFTMMU
1879 add_qemu_ldst_label(s
, false, oi
, datalo
, datahi
, addrlo
, addrhi
,
1880 s
->code_ptr
, label_ptr
);
1884 static void tcg_out_nop_fill(tcg_insn_unit
*p
, int count
)
1887 for (i
= 0; i
< count
; ++i
) {
1892 /* Parameters for function call generation, used in tcg.c. */
1893 #define TCG_TARGET_STACK_ALIGN 16
1894 #define TCG_TARGET_EXTEND_ARGS 1
1897 # define LINK_AREA_SIZE (6 * SZR)
1898 # define LR_OFFSET (1 * SZR)
1899 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1900 #elif defined(TCG_TARGET_CALL_DARWIN)
1901 # define LINK_AREA_SIZE (6 * SZR)
1902 # define LR_OFFSET (2 * SZR)
1903 #elif TCG_TARGET_REG_BITS == 64
1904 # if defined(_CALL_ELF) && _CALL_ELF == 2
1905 # define LINK_AREA_SIZE (4 * SZR)
1906 # define LR_OFFSET (1 * SZR)
1908 #else /* TCG_TARGET_REG_BITS == 32 */
1909 # if defined(_CALL_SYSV)
1910 # define LINK_AREA_SIZE (2 * SZR)
1911 # define LR_OFFSET (1 * SZR)
1915 # error "Unhandled abi"
1917 #ifndef TCG_TARGET_CALL_STACK_OFFSET
1918 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1921 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1922 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1924 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1925 + TCG_STATIC_CALL_ARGS_SIZE \
1926 + CPU_TEMP_BUF_SIZE \
1928 + TCG_TARGET_STACK_ALIGN - 1) \
1929 & -TCG_TARGET_STACK_ALIGN)
1931 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1933 static void tcg_target_qemu_prologue(TCGContext
*s
)
1938 void **desc
= (void **)s
->code_ptr
;
1939 desc
[0] = desc
+ 2; /* entry point */
1940 desc
[1] = 0; /* environment pointer */
1941 s
->code_ptr
= (void *)(desc
+ 2); /* skip over descriptor */
1944 tcg_set_frame(s
, TCG_REG_CALL_STACK
, REG_SAVE_BOT
- CPU_TEMP_BUF_SIZE
,
1948 tcg_out32(s
, MFSPR
| RT(TCG_REG_R0
) | LR
);
1949 tcg_out32(s
, (SZR
== 8 ? STDU
: STWU
)
1950 | SAI(TCG_REG_R1
, TCG_REG_R1
, -FRAME_SIZE
));
1952 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
) {
1953 tcg_out_st(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
1954 TCG_REG_R1
, REG_SAVE_BOT
+ i
* SZR
);
1956 tcg_out_st(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_R1
, FRAME_SIZE
+LR_OFFSET
);
1958 #ifndef CONFIG_SOFTMMU
1960 tcg_out_movi_int(s
, TCG_TYPE_PTR
, TCG_GUEST_BASE_REG
, guest_base
, true);
1961 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
1965 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
1966 tcg_out32(s
, MTSPR
| RS(tcg_target_call_iarg_regs
[1]) | CTR
);
1968 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_REG_TB
, tcg_target_call_iarg_regs
[1]);
1970 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1973 s
->code_gen_epilogue
= tb_ret_addr
= s
->code_ptr
;
1975 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_R1
, FRAME_SIZE
+LR_OFFSET
);
1976 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
) {
1977 tcg_out_ld(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
1978 TCG_REG_R1
, REG_SAVE_BOT
+ i
* SZR
);
1980 tcg_out32(s
, MTSPR
| RS(TCG_REG_R0
) | LR
);
1981 tcg_out32(s
, ADDI
| TAI(TCG_REG_R1
, TCG_REG_R1
, FRAME_SIZE
));
1982 tcg_out32(s
, BCLR
| BO_ALWAYS
);
1985 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
1986 const int *const_args
)
1992 case INDEX_op_exit_tb
:
1993 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R3
, args
[0]);
1994 tcg_out_b(s
, 0, tb_ret_addr
);
1996 case INDEX_op_goto_tb
:
1997 if (s
->tb_jmp_insn_offset
) {
1999 if (TCG_TARGET_REG_BITS
== 64) {
2000 /* Ensure the next insns are 8-byte aligned. */
2001 if ((uintptr_t)s
->code_ptr
& 7) {
2004 s
->tb_jmp_insn_offset
[args
[0]] = tcg_current_code_size(s
);
2005 tcg_out32(s
, ADDIS
| TAI(TCG_REG_TB
, TCG_REG_TB
, 0));
2006 tcg_out32(s
, ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, 0));
2008 s
->tb_jmp_insn_offset
[args
[0]] = tcg_current_code_size(s
);
2010 s
->tb_jmp_reset_offset
[args
[0]] = tcg_current_code_size(s
);
2014 /* Indirect jump. */
2015 tcg_debug_assert(s
->tb_jmp_insn_offset
== NULL
);
2016 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_TB
, 0,
2017 (intptr_t)(s
->tb_jmp_insn_offset
+ args
[0]));
2019 tcg_out32(s
, MTSPR
| RS(TCG_REG_TB
) | CTR
);
2020 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
2021 set_jmp_reset_offset(s
, args
[0]);
2023 /* For the unlinked case, need to reset TCG_REG_TB. */
2024 c
= -tcg_current_code_size(s
);
2025 assert(c
== (int16_t)c
);
2026 tcg_out32(s
, ADDI
| TAI(TCG_REG_TB
, TCG_REG_TB
, c
));
2029 case INDEX_op_goto_ptr
:
2030 tcg_out32(s
, MTSPR
| RS(args
[0]) | CTR
);
2032 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_REG_TB
, args
[0]);
2034 tcg_out32(s
, ADDI
| TAI(TCG_REG_R3
, 0, 0));
2035 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
2039 TCGLabel
*l
= arg_label(args
[0]);
2043 insn
|= reloc_pc24_val(s
->code_ptr
, l
->u
.value_ptr
);
2045 tcg_out_reloc(s
, s
->code_ptr
, R_PPC_REL24
, l
, 0);
2050 case INDEX_op_ld8u_i32
:
2051 case INDEX_op_ld8u_i64
:
2052 tcg_out_mem_long(s
, LBZ
, LBZX
, args
[0], args
[1], args
[2]);
2054 case INDEX_op_ld8s_i32
:
2055 case INDEX_op_ld8s_i64
:
2056 tcg_out_mem_long(s
, LBZ
, LBZX
, args
[0], args
[1], args
[2]);
2057 tcg_out32(s
, EXTSB
| RS(args
[0]) | RA(args
[0]));
2059 case INDEX_op_ld16u_i32
:
2060 case INDEX_op_ld16u_i64
:
2061 tcg_out_mem_long(s
, LHZ
, LHZX
, args
[0], args
[1], args
[2]);
2063 case INDEX_op_ld16s_i32
:
2064 case INDEX_op_ld16s_i64
:
2065 tcg_out_mem_long(s
, LHA
, LHAX
, args
[0], args
[1], args
[2]);
2067 case INDEX_op_ld_i32
:
2068 case INDEX_op_ld32u_i64
:
2069 tcg_out_mem_long(s
, LWZ
, LWZX
, args
[0], args
[1], args
[2]);
2071 case INDEX_op_ld32s_i64
:
2072 tcg_out_mem_long(s
, LWA
, LWAX
, args
[0], args
[1], args
[2]);
2074 case INDEX_op_ld_i64
:
2075 tcg_out_mem_long(s
, LD
, LDX
, args
[0], args
[1], args
[2]);
2077 case INDEX_op_st8_i32
:
2078 case INDEX_op_st8_i64
:
2079 tcg_out_mem_long(s
, STB
, STBX
, args
[0], args
[1], args
[2]);
2081 case INDEX_op_st16_i32
:
2082 case INDEX_op_st16_i64
:
2083 tcg_out_mem_long(s
, STH
, STHX
, args
[0], args
[1], args
[2]);
2085 case INDEX_op_st_i32
:
2086 case INDEX_op_st32_i64
:
2087 tcg_out_mem_long(s
, STW
, STWX
, args
[0], args
[1], args
[2]);
2089 case INDEX_op_st_i64
:
2090 tcg_out_mem_long(s
, STD
, STDX
, args
[0], args
[1], args
[2]);
2093 case INDEX_op_add_i32
:
2094 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2095 if (const_args
[2]) {
2097 tcg_out_mem_long(s
, ADDI
, ADD
, a0
, a1
, (int32_t)a2
);
2099 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
2102 case INDEX_op_sub_i32
:
2103 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2104 if (const_args
[1]) {
2105 if (const_args
[2]) {
2106 tcg_out_movi(s
, TCG_TYPE_I32
, a0
, a1
- a2
);
2108 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
2110 } else if (const_args
[2]) {
2114 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
2118 case INDEX_op_and_i32
:
2119 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2120 if (const_args
[2]) {
2121 tcg_out_andi32(s
, a0
, a1
, a2
);
2123 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
2126 case INDEX_op_and_i64
:
2127 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2128 if (const_args
[2]) {
2129 tcg_out_andi64(s
, a0
, a1
, a2
);
2131 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
2134 case INDEX_op_or_i64
:
2135 case INDEX_op_or_i32
:
2136 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2137 if (const_args
[2]) {
2138 tcg_out_ori32(s
, a0
, a1
, a2
);
2140 tcg_out32(s
, OR
| SAB(a1
, a0
, a2
));
2143 case INDEX_op_xor_i64
:
2144 case INDEX_op_xor_i32
:
2145 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2146 if (const_args
[2]) {
2147 tcg_out_xori32(s
, a0
, a1
, a2
);
2149 tcg_out32(s
, XOR
| SAB(a1
, a0
, a2
));
2152 case INDEX_op_andc_i32
:
2153 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2154 if (const_args
[2]) {
2155 tcg_out_andi32(s
, a0
, a1
, ~a2
);
2157 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
2160 case INDEX_op_andc_i64
:
2161 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2162 if (const_args
[2]) {
2163 tcg_out_andi64(s
, a0
, a1
, ~a2
);
2165 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
2168 case INDEX_op_orc_i32
:
2169 if (const_args
[2]) {
2170 tcg_out_ori32(s
, args
[0], args
[1], ~args
[2]);
2174 case INDEX_op_orc_i64
:
2175 tcg_out32(s
, ORC
| SAB(args
[1], args
[0], args
[2]));
2177 case INDEX_op_eqv_i32
:
2178 if (const_args
[2]) {
2179 tcg_out_xori32(s
, args
[0], args
[1], ~args
[2]);
2183 case INDEX_op_eqv_i64
:
2184 tcg_out32(s
, EQV
| SAB(args
[1], args
[0], args
[2]));
2186 case INDEX_op_nand_i32
:
2187 case INDEX_op_nand_i64
:
2188 tcg_out32(s
, NAND
| SAB(args
[1], args
[0], args
[2]));
2190 case INDEX_op_nor_i32
:
2191 case INDEX_op_nor_i64
:
2192 tcg_out32(s
, NOR
| SAB(args
[1], args
[0], args
[2]));
2195 case INDEX_op_clz_i32
:
2196 tcg_out_cntxz(s
, TCG_TYPE_I32
, CNTLZW
, args
[0], args
[1],
2197 args
[2], const_args
[2]);
2199 case INDEX_op_ctz_i32
:
2200 tcg_out_cntxz(s
, TCG_TYPE_I32
, CNTTZW
, args
[0], args
[1],
2201 args
[2], const_args
[2]);
2203 case INDEX_op_ctpop_i32
:
2204 tcg_out32(s
, CNTPOPW
| SAB(args
[1], args
[0], 0));
2207 case INDEX_op_clz_i64
:
2208 tcg_out_cntxz(s
, TCG_TYPE_I64
, CNTLZD
, args
[0], args
[1],
2209 args
[2], const_args
[2]);
2211 case INDEX_op_ctz_i64
:
2212 tcg_out_cntxz(s
, TCG_TYPE_I64
, CNTTZD
, args
[0], args
[1],
2213 args
[2], const_args
[2]);
2215 case INDEX_op_ctpop_i64
:
2216 tcg_out32(s
, CNTPOPD
| SAB(args
[1], args
[0], 0));
2219 case INDEX_op_mul_i32
:
2220 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2221 if (const_args
[2]) {
2222 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
2224 tcg_out32(s
, MULLW
| TAB(a0
, a1
, a2
));
2228 case INDEX_op_div_i32
:
2229 tcg_out32(s
, DIVW
| TAB(args
[0], args
[1], args
[2]));
2232 case INDEX_op_divu_i32
:
2233 tcg_out32(s
, DIVWU
| TAB(args
[0], args
[1], args
[2]));
2236 case INDEX_op_shl_i32
:
2237 if (const_args
[2]) {
2238 tcg_out_shli32(s
, args
[0], args
[1], args
[2]);
2240 tcg_out32(s
, SLW
| SAB(args
[1], args
[0], args
[2]));
2243 case INDEX_op_shr_i32
:
2244 if (const_args
[2]) {
2245 tcg_out_shri32(s
, args
[0], args
[1], args
[2]);
2247 tcg_out32(s
, SRW
| SAB(args
[1], args
[0], args
[2]));
2250 case INDEX_op_sar_i32
:
2251 if (const_args
[2]) {
2252 tcg_out32(s
, SRAWI
| RS(args
[1]) | RA(args
[0]) | SH(args
[2]));
2254 tcg_out32(s
, SRAW
| SAB(args
[1], args
[0], args
[2]));
2257 case INDEX_op_rotl_i32
:
2258 if (const_args
[2]) {
2259 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], args
[2], 0, 31);
2261 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], args
[2])
2265 case INDEX_op_rotr_i32
:
2266 if (const_args
[2]) {
2267 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], 32 - args
[2], 0, 31);
2269 tcg_out32(s
, SUBFIC
| TAI(TCG_REG_R0
, args
[2], 32));
2270 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], TCG_REG_R0
)
2275 case INDEX_op_brcond_i32
:
2276 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
2277 arg_label(args
[3]), TCG_TYPE_I32
);
2279 case INDEX_op_brcond_i64
:
2280 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
2281 arg_label(args
[3]), TCG_TYPE_I64
);
2283 case INDEX_op_brcond2_i32
:
2284 tcg_out_brcond2(s
, args
, const_args
);
2287 case INDEX_op_neg_i32
:
2288 case INDEX_op_neg_i64
:
2289 tcg_out32(s
, NEG
| RT(args
[0]) | RA(args
[1]));
2292 case INDEX_op_not_i32
:
2293 case INDEX_op_not_i64
:
2294 tcg_out32(s
, NOR
| SAB(args
[1], args
[0], args
[1]));
2297 case INDEX_op_add_i64
:
2298 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2299 if (const_args
[2]) {
2301 tcg_out_mem_long(s
, ADDI
, ADD
, a0
, a1
, a2
);
2303 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
2306 case INDEX_op_sub_i64
:
2307 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2308 if (const_args
[1]) {
2309 if (const_args
[2]) {
2310 tcg_out_movi(s
, TCG_TYPE_I64
, a0
, a1
- a2
);
2312 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
2314 } else if (const_args
[2]) {
2318 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
2322 case INDEX_op_shl_i64
:
2323 if (const_args
[2]) {
2324 tcg_out_shli64(s
, args
[0], args
[1], args
[2]);
2326 tcg_out32(s
, SLD
| SAB(args
[1], args
[0], args
[2]));
2329 case INDEX_op_shr_i64
:
2330 if (const_args
[2]) {
2331 tcg_out_shri64(s
, args
[0], args
[1], args
[2]);
2333 tcg_out32(s
, SRD
| SAB(args
[1], args
[0], args
[2]));
2336 case INDEX_op_sar_i64
:
2337 if (const_args
[2]) {
2338 int sh
= SH(args
[2] & 0x1f) | (((args
[2] >> 5) & 1) << 1);
2339 tcg_out32(s
, SRADI
| RA(args
[0]) | RS(args
[1]) | sh
);
2341 tcg_out32(s
, SRAD
| SAB(args
[1], args
[0], args
[2]));
2344 case INDEX_op_rotl_i64
:
2345 if (const_args
[2]) {
2346 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], args
[2], 0);
2348 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], args
[2]) | MB64(0));
2351 case INDEX_op_rotr_i64
:
2352 if (const_args
[2]) {
2353 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], 64 - args
[2], 0);
2355 tcg_out32(s
, SUBFIC
| TAI(TCG_REG_R0
, args
[2], 64));
2356 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], TCG_REG_R0
) | MB64(0));
2360 case INDEX_op_mul_i64
:
2361 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2362 if (const_args
[2]) {
2363 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
2365 tcg_out32(s
, MULLD
| TAB(a0
, a1
, a2
));
2368 case INDEX_op_div_i64
:
2369 tcg_out32(s
, DIVD
| TAB(args
[0], args
[1], args
[2]));
2371 case INDEX_op_divu_i64
:
2372 tcg_out32(s
, DIVDU
| TAB(args
[0], args
[1], args
[2]));
2375 case INDEX_op_qemu_ld_i32
:
2376 tcg_out_qemu_ld(s
, args
, false);
2378 case INDEX_op_qemu_ld_i64
:
2379 tcg_out_qemu_ld(s
, args
, true);
2381 case INDEX_op_qemu_st_i32
:
2382 tcg_out_qemu_st(s
, args
, false);
2384 case INDEX_op_qemu_st_i64
:
2385 tcg_out_qemu_st(s
, args
, true);
2388 case INDEX_op_ext8s_i32
:
2389 case INDEX_op_ext8s_i64
:
2392 case INDEX_op_ext16s_i32
:
2393 case INDEX_op_ext16s_i64
:
2396 case INDEX_op_ext_i32_i64
:
2397 case INDEX_op_ext32s_i64
:
2401 tcg_out32(s
, c
| RS(args
[1]) | RA(args
[0]));
2403 case INDEX_op_extu_i32_i64
:
2404 tcg_out_ext32u(s
, args
[0], args
[1]);
2407 case INDEX_op_setcond_i32
:
2408 tcg_out_setcond(s
, TCG_TYPE_I32
, args
[3], args
[0], args
[1], args
[2],
2411 case INDEX_op_setcond_i64
:
2412 tcg_out_setcond(s
, TCG_TYPE_I64
, args
[3], args
[0], args
[1], args
[2],
2415 case INDEX_op_setcond2_i32
:
2416 tcg_out_setcond2(s
, args
, const_args
);
2419 case INDEX_op_bswap16_i32
:
2420 case INDEX_op_bswap16_i64
:
2421 a0
= args
[0], a1
= args
[1];
2424 /* a0 = (a1 r<< 24) & 0xff # 000c */
2425 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
2426 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2427 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 8, 16, 23);
2429 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2430 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, a1
, 8, 16, 23);
2431 /* a0 = (a1 r<< 24) & 0xff # 000c */
2432 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
2433 /* a0 = a0 | r0 # 00dc */
2434 tcg_out32(s
, OR
| SAB(TCG_REG_R0
, a0
, a0
));
2438 case INDEX_op_bswap32_i32
:
2439 case INDEX_op_bswap32_i64
:
2440 /* Stolen from gcc's builtin_bswap32 */
2442 a0
= args
[0] == a1
? TCG_REG_R0
: args
[0];
2444 /* a1 = args[1] # abcd */
2445 /* a0 = rotate_left (a1, 8) # bcda */
2446 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
2447 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2448 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
2449 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2450 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
2452 if (a0
== TCG_REG_R0
) {
2453 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2457 case INDEX_op_bswap64_i64
:
2458 a0
= args
[0], a1
= args
[1], a2
= TCG_REG_R0
;
2464 /* a1 = # abcd efgh */
2465 /* a0 = rl32(a1, 8) # 0000 fghe */
2466 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
2467 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2468 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
2469 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2470 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
2472 /* a0 = rl64(a0, 32) # hgfe 0000 */
2473 /* a2 = rl64(a1, 32) # efgh abcd */
2474 tcg_out_rld(s
, RLDICL
, a0
, a0
, 32, 0);
2475 tcg_out_rld(s
, RLDICL
, a2
, a1
, 32, 0);
2477 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2478 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 8, 0, 31);
2479 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2480 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 0, 7);
2481 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2482 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 16, 23);
2485 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2489 case INDEX_op_deposit_i32
:
2490 if (const_args
[2]) {
2491 uint32_t mask
= ((2u << (args
[4] - 1)) - 1) << args
[3];
2492 tcg_out_andi32(s
, args
[0], args
[0], ~mask
);
2494 tcg_out_rlw(s
, RLWIMI
, args
[0], args
[2], args
[3],
2495 32 - args
[3] - args
[4], 31 - args
[3]);
2498 case INDEX_op_deposit_i64
:
2499 if (const_args
[2]) {
2500 uint64_t mask
= ((2ull << (args
[4] - 1)) - 1) << args
[3];
2501 tcg_out_andi64(s
, args
[0], args
[0], ~mask
);
2503 tcg_out_rld(s
, RLDIMI
, args
[0], args
[2], args
[3],
2504 64 - args
[3] - args
[4]);
2508 case INDEX_op_extract_i32
:
2509 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1],
2510 32 - args
[2], 32 - args
[3], 31);
2512 case INDEX_op_extract_i64
:
2513 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], 64 - args
[2], 64 - args
[3]);
2516 case INDEX_op_movcond_i32
:
2517 tcg_out_movcond(s
, TCG_TYPE_I32
, args
[5], args
[0], args
[1], args
[2],
2518 args
[3], args
[4], const_args
[2]);
2520 case INDEX_op_movcond_i64
:
2521 tcg_out_movcond(s
, TCG_TYPE_I64
, args
[5], args
[0], args
[1], args
[2],
2522 args
[3], args
[4], const_args
[2]);
2525 #if TCG_TARGET_REG_BITS == 64
2526 case INDEX_op_add2_i64
:
2528 case INDEX_op_add2_i32
:
2530 /* Note that the CA bit is defined based on the word size of the
2531 environment. So in 64-bit mode it's always carry-out of bit 63.
2532 The fallback code using deposit works just as well for 32-bit. */
2533 a0
= args
[0], a1
= args
[1];
2534 if (a0
== args
[3] || (!const_args
[5] && a0
== args
[5])) {
2537 if (const_args
[4]) {
2538 tcg_out32(s
, ADDIC
| TAI(a0
, args
[2], args
[4]));
2540 tcg_out32(s
, ADDC
| TAB(a0
, args
[2], args
[4]));
2542 if (const_args
[5]) {
2543 tcg_out32(s
, (args
[5] ? ADDME
: ADDZE
) | RT(a1
) | RA(args
[3]));
2545 tcg_out32(s
, ADDE
| TAB(a1
, args
[3], args
[5]));
2547 if (a0
!= args
[0]) {
2548 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2552 #if TCG_TARGET_REG_BITS == 64
2553 case INDEX_op_sub2_i64
:
2555 case INDEX_op_sub2_i32
:
2557 a0
= args
[0], a1
= args
[1];
2558 if (a0
== args
[5] || (!const_args
[3] && a0
== args
[3])) {
2561 if (const_args
[2]) {
2562 tcg_out32(s
, SUBFIC
| TAI(a0
, args
[4], args
[2]));
2564 tcg_out32(s
, SUBFC
| TAB(a0
, args
[4], args
[2]));
2566 if (const_args
[3]) {
2567 tcg_out32(s
, (args
[3] ? SUBFME
: SUBFZE
) | RT(a1
) | RA(args
[5]));
2569 tcg_out32(s
, SUBFE
| TAB(a1
, args
[5], args
[3]));
2571 if (a0
!= args
[0]) {
2572 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2576 case INDEX_op_muluh_i32
:
2577 tcg_out32(s
, MULHWU
| TAB(args
[0], args
[1], args
[2]));
2579 case INDEX_op_mulsh_i32
:
2580 tcg_out32(s
, MULHW
| TAB(args
[0], args
[1], args
[2]));
2582 case INDEX_op_muluh_i64
:
2583 tcg_out32(s
, MULHDU
| TAB(args
[0], args
[1], args
[2]));
2585 case INDEX_op_mulsh_i64
:
2586 tcg_out32(s
, MULHD
| TAB(args
[0], args
[1], args
[2]));
2590 tcg_out_mb(s
, args
[0]);
2593 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
2594 case INDEX_op_mov_i64
:
2595 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
2596 case INDEX_op_movi_i64
:
2597 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
2603 static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op
)
2605 static const TCGTargetOpDef r
= { .args_ct_str
= { "r" } };
2606 static const TCGTargetOpDef r_r
= { .args_ct_str
= { "r", "r" } };
2607 static const TCGTargetOpDef r_L
= { .args_ct_str
= { "r", "L" } };
2608 static const TCGTargetOpDef S_S
= { .args_ct_str
= { "S", "S" } };
2609 static const TCGTargetOpDef r_ri
= { .args_ct_str
= { "r", "ri" } };
2610 static const TCGTargetOpDef r_r_r
= { .args_ct_str
= { "r", "r", "r" } };
2611 static const TCGTargetOpDef r_L_L
= { .args_ct_str
= { "r", "L", "L" } };
2612 static const TCGTargetOpDef L_L_L
= { .args_ct_str
= { "L", "L", "L" } };
2613 static const TCGTargetOpDef S_S_S
= { .args_ct_str
= { "S", "S", "S" } };
2614 static const TCGTargetOpDef r_r_ri
= { .args_ct_str
= { "r", "r", "ri" } };
2615 static const TCGTargetOpDef r_r_rI
= { .args_ct_str
= { "r", "r", "rI" } };
2616 static const TCGTargetOpDef r_r_rT
= { .args_ct_str
= { "r", "r", "rT" } };
2617 static const TCGTargetOpDef r_r_rU
= { .args_ct_str
= { "r", "r", "rU" } };
2618 static const TCGTargetOpDef r_rI_ri
2619 = { .args_ct_str
= { "r", "rI", "ri" } };
2620 static const TCGTargetOpDef r_rI_rT
2621 = { .args_ct_str
= { "r", "rI", "rT" } };
2622 static const TCGTargetOpDef r_r_rZW
2623 = { .args_ct_str
= { "r", "r", "rZW" } };
2624 static const TCGTargetOpDef L_L_L_L
2625 = { .args_ct_str
= { "L", "L", "L", "L" } };
2626 static const TCGTargetOpDef S_S_S_S
2627 = { .args_ct_str
= { "S", "S", "S", "S" } };
2628 static const TCGTargetOpDef movc
2629 = { .args_ct_str
= { "r", "r", "ri", "rZ", "rZ" } };
2630 static const TCGTargetOpDef dep
2631 = { .args_ct_str
= { "r", "0", "rZ" } };
2632 static const TCGTargetOpDef br2
2633 = { .args_ct_str
= { "r", "r", "ri", "ri" } };
2634 static const TCGTargetOpDef setc2
2635 = { .args_ct_str
= { "r", "r", "r", "ri", "ri" } };
2636 static const TCGTargetOpDef add2
2637 = { .args_ct_str
= { "r", "r", "r", "r", "rI", "rZM" } };
2638 static const TCGTargetOpDef sub2
2639 = { .args_ct_str
= { "r", "r", "rI", "rZM", "r", "r" } };
2642 case INDEX_op_goto_ptr
:
2645 case INDEX_op_ld8u_i32
:
2646 case INDEX_op_ld8s_i32
:
2647 case INDEX_op_ld16u_i32
:
2648 case INDEX_op_ld16s_i32
:
2649 case INDEX_op_ld_i32
:
2650 case INDEX_op_st8_i32
:
2651 case INDEX_op_st16_i32
:
2652 case INDEX_op_st_i32
:
2653 case INDEX_op_ctpop_i32
:
2654 case INDEX_op_neg_i32
:
2655 case INDEX_op_not_i32
:
2656 case INDEX_op_ext8s_i32
:
2657 case INDEX_op_ext16s_i32
:
2658 case INDEX_op_bswap16_i32
:
2659 case INDEX_op_bswap32_i32
:
2660 case INDEX_op_extract_i32
:
2661 case INDEX_op_ld8u_i64
:
2662 case INDEX_op_ld8s_i64
:
2663 case INDEX_op_ld16u_i64
:
2664 case INDEX_op_ld16s_i64
:
2665 case INDEX_op_ld32u_i64
:
2666 case INDEX_op_ld32s_i64
:
2667 case INDEX_op_ld_i64
:
2668 case INDEX_op_st8_i64
:
2669 case INDEX_op_st16_i64
:
2670 case INDEX_op_st32_i64
:
2671 case INDEX_op_st_i64
:
2672 case INDEX_op_ctpop_i64
:
2673 case INDEX_op_neg_i64
:
2674 case INDEX_op_not_i64
:
2675 case INDEX_op_ext8s_i64
:
2676 case INDEX_op_ext16s_i64
:
2677 case INDEX_op_ext32s_i64
:
2678 case INDEX_op_ext_i32_i64
:
2679 case INDEX_op_extu_i32_i64
:
2680 case INDEX_op_bswap16_i64
:
2681 case INDEX_op_bswap32_i64
:
2682 case INDEX_op_bswap64_i64
:
2683 case INDEX_op_extract_i64
:
2686 case INDEX_op_add_i32
:
2687 case INDEX_op_and_i32
:
2688 case INDEX_op_or_i32
:
2689 case INDEX_op_xor_i32
:
2690 case INDEX_op_andc_i32
:
2691 case INDEX_op_orc_i32
:
2692 case INDEX_op_eqv_i32
:
2693 case INDEX_op_shl_i32
:
2694 case INDEX_op_shr_i32
:
2695 case INDEX_op_sar_i32
:
2696 case INDEX_op_rotl_i32
:
2697 case INDEX_op_rotr_i32
:
2698 case INDEX_op_setcond_i32
:
2699 case INDEX_op_and_i64
:
2700 case INDEX_op_andc_i64
:
2701 case INDEX_op_shl_i64
:
2702 case INDEX_op_shr_i64
:
2703 case INDEX_op_sar_i64
:
2704 case INDEX_op_rotl_i64
:
2705 case INDEX_op_rotr_i64
:
2706 case INDEX_op_setcond_i64
:
2708 case INDEX_op_mul_i32
:
2709 case INDEX_op_mul_i64
:
2711 case INDEX_op_div_i32
:
2712 case INDEX_op_divu_i32
:
2713 case INDEX_op_nand_i32
:
2714 case INDEX_op_nor_i32
:
2715 case INDEX_op_muluh_i32
:
2716 case INDEX_op_mulsh_i32
:
2717 case INDEX_op_orc_i64
:
2718 case INDEX_op_eqv_i64
:
2719 case INDEX_op_nand_i64
:
2720 case INDEX_op_nor_i64
:
2721 case INDEX_op_div_i64
:
2722 case INDEX_op_divu_i64
:
2723 case INDEX_op_mulsh_i64
:
2724 case INDEX_op_muluh_i64
:
2726 case INDEX_op_sub_i32
:
2728 case INDEX_op_add_i64
:
2730 case INDEX_op_or_i64
:
2731 case INDEX_op_xor_i64
:
2733 case INDEX_op_sub_i64
:
2735 case INDEX_op_clz_i32
:
2736 case INDEX_op_ctz_i32
:
2737 case INDEX_op_clz_i64
:
2738 case INDEX_op_ctz_i64
:
2741 case INDEX_op_brcond_i32
:
2742 case INDEX_op_brcond_i64
:
2745 case INDEX_op_movcond_i32
:
2746 case INDEX_op_movcond_i64
:
2748 case INDEX_op_deposit_i32
:
2749 case INDEX_op_deposit_i64
:
2751 case INDEX_op_brcond2_i32
:
2753 case INDEX_op_setcond2_i32
:
2755 case INDEX_op_add2_i64
:
2756 case INDEX_op_add2_i32
:
2758 case INDEX_op_sub2_i64
:
2759 case INDEX_op_sub2_i32
:
2762 case INDEX_op_qemu_ld_i32
:
2763 return (TCG_TARGET_REG_BITS
== 64 || TARGET_LONG_BITS
== 32
2765 case INDEX_op_qemu_st_i32
:
2766 return (TCG_TARGET_REG_BITS
== 64 || TARGET_LONG_BITS
== 32
2768 case INDEX_op_qemu_ld_i64
:
2769 return (TCG_TARGET_REG_BITS
== 64 ? &r_L
2770 : TARGET_LONG_BITS
== 32 ? &L_L_L
: &L_L_L_L
);
2771 case INDEX_op_qemu_st_i64
:
2772 return (TCG_TARGET_REG_BITS
== 64 ? &S_S
2773 : TARGET_LONG_BITS
== 32 ? &S_S_S
: &S_S_S_S
);
2780 static void tcg_target_init(TCGContext
*s
)
2782 unsigned long hwcap
= qemu_getauxval(AT_HWCAP
);
2783 unsigned long hwcap2
= qemu_getauxval(AT_HWCAP2
);
2785 if (hwcap
& PPC_FEATURE_ARCH_2_06
) {
2786 have_isa_2_06
= true;
2788 #ifdef PPC_FEATURE2_ARCH_3_00
2789 if (hwcap2
& PPC_FEATURE2_ARCH_3_00
) {
2790 have_isa_3_00
= true;
2794 tcg_target_available_regs
[TCG_TYPE_I32
] = 0xffffffff;
2795 tcg_target_available_regs
[TCG_TYPE_I64
] = 0xffffffff;
2797 tcg_target_call_clobber_regs
= 0;
2798 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R0
);
2799 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R2
);
2800 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R3
);
2801 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R4
);
2802 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R5
);
2803 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R6
);
2804 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R7
);
2805 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R8
);
2806 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R9
);
2807 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R10
);
2808 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R11
);
2809 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R12
);
2811 s
->reserved_regs
= 0;
2812 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
); /* tcg temp */
2813 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
); /* stack pointer */
2814 #if defined(_CALL_SYSV)
2815 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
); /* toc pointer */
2817 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
2818 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R13
); /* thread pointer */
2820 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TMP1
); /* mem temp */
2822 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TB
); /* tb->tc_ptr */
2829 DebugFrameFDEHeader fde
;
2830 uint8_t fde_def_cfa
[4];
2831 uint8_t fde_reg_ofs
[ARRAY_SIZE(tcg_target_callee_save_regs
) * 2 + 3];
2834 /* We're expecting a 2 byte uleb128 encoded value. */
2835 QEMU_BUILD_BUG_ON(FRAME_SIZE
>= (1 << 14));
2837 #if TCG_TARGET_REG_BITS == 64
2838 # define ELF_HOST_MACHINE EM_PPC64
2840 # define ELF_HOST_MACHINE EM_PPC
2843 static DebugFrame debug_frame
= {
2844 .cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2847 .cie
.code_align
= 1,
2848 .cie
.data_align
= (-SZR
& 0x7f), /* sleb128 -SZR */
2849 .cie
.return_column
= 65,
2851 /* Total FDE size does not include the "len" member. */
2852 .fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, fde
.cie_offset
),
2855 12, TCG_REG_R1
, /* DW_CFA_def_cfa r1, ... */
2856 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2860 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2861 0x11, 65, (LR_OFFSET
/ -SZR
) & 0x7f,
2865 void tcg_register_jit(void *buf
, size_t buf_size
)
2867 uint8_t *p
= &debug_frame
.fde_reg_ofs
[3];
2870 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
, p
+= 2) {
2871 p
[0] = 0x80 + tcg_target_callee_save_regs
[i
];
2872 p
[1] = (FRAME_SIZE
- (REG_SAVE_BOT
+ i
* SZR
)) / SZR
;
2875 debug_frame
.fde
.func_start
= (uintptr_t)buf
;
2876 debug_frame
.fde
.func_len
= buf_size
;
2878 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));
2880 #endif /* __ELF__ */
2882 void flush_icache_range(uintptr_t start
, uintptr_t stop
)
2884 uintptr_t p
, start1
, stop1
;
2885 size_t dsize
= qemu_dcache_linesize
;
2886 size_t isize
= qemu_icache_linesize
;
2888 start1
= start
& ~(dsize
- 1);
2889 stop1
= (stop
+ dsize
- 1) & ~(dsize
- 1);
2890 for (p
= start1
; p
< stop1
; p
+= dsize
) {
2891 asm volatile ("dcbst 0,%0" : : "r"(p
) : "memory");
2893 asm volatile ("sync" : : : "memory");
2895 start
&= start
& ~(isize
- 1);
2896 stop1
= (stop
+ isize
- 1) & ~(isize
- 1);
2897 for (p
= start1
; p
< stop1
; p
+= isize
) {
2898 asm volatile ("icbi 0,%0" : : "r"(p
) : "memory");
2900 asm volatile ("sync" : : : "memory");
2901 asm volatile ("isync" : : : "memory");