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block: avoid creating too large iovecs in multiwrite_merge
[qemu/ar7.git] / target-mips / translate_init.c
blobb79ed568047bc57610f1a67873358860ba5497e1
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1 << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1 << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1 << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 /* Define a implementation number of 1.
49 Define a major version 1, minor version 0. */
50 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
51
52 /* MMU types, the first four entries have the same layout as the
53 CP0C0_MT field. */
54 enum mips_mmu_types {
55 MMU_TYPE_NONE,
56 MMU_TYPE_R4000,
57 MMU_TYPE_RESERVED,
58 MMU_TYPE_FMT,
59 MMU_TYPE_R3000,
60 MMU_TYPE_R6000,
61 MMU_TYPE_R8000
62 };
63
64 struct mips_def_t {
65 const char *name;
66 int32_t CP0_PRid;
67 int32_t CP0_Config0;
68 int32_t CP0_Config1;
69 int32_t CP0_Config2;
70 int32_t CP0_Config3;
71 int32_t CP0_Config6;
72 int32_t CP0_Config7;
73 target_ulong CP0_LLAddr_rw_bitmask;
74 int CP0_LLAddr_shift;
75 int32_t SYNCI_Step;
76 int32_t CCRes;
77 int32_t CP0_Status_rw_bitmask;
78 int32_t CP0_TCStatus_rw_bitmask;
79 int32_t CP0_SRSCtl;
80 int32_t CP1_fcr0;
81 int32_t SEGBITS;
82 int32_t PABITS;
83 int32_t CP0_SRSConf0_rw_bitmask;
84 int32_t CP0_SRSConf0;
85 int32_t CP0_SRSConf1_rw_bitmask;
86 int32_t CP0_SRSConf1;
87 int32_t CP0_SRSConf2_rw_bitmask;
88 int32_t CP0_SRSConf2;
89 int32_t CP0_SRSConf3_rw_bitmask;
90 int32_t CP0_SRSConf3;
91 int32_t CP0_SRSConf4_rw_bitmask;
92 int32_t CP0_SRSConf4;
93 int insn_flags;
94 enum mips_mmu_types mmu_type;
95 };
96
97 /*****************************************************************************/
98 /* MIPS CPU definitions */
99 static const mips_def_t mips_defs[] =
100 {
101 {
102 .name = "4Kc",
103 .CP0_PRid = 0x00018000,
104 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
105 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
106 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
107 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
108 (0 << CP0C1_CA),
109 .CP0_Config2 = MIPS_CONFIG2,
110 .CP0_Config3 = MIPS_CONFIG3,
111 .CP0_LLAddr_rw_bitmask = 0,
112 .CP0_LLAddr_shift = 4,
113 .SYNCI_Step = 32,
114 .CCRes = 2,
115 .CP0_Status_rw_bitmask = 0x1278FF17,
116 .SEGBITS = 32,
117 .PABITS = 32,
118 .insn_flags = CPU_MIPS32,
119 .mmu_type = MMU_TYPE_R4000,
120 },
121 {
122 .name = "4Km",
123 .CP0_PRid = 0x00018300,
124 /* Config1 implemented, fixed mapping MMU,
125 no virtual icache, uncached coherency. */
126 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
127 .CP0_Config1 = MIPS_CONFIG1 |
128 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
129 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
130 (1 << CP0C1_CA),
131 .CP0_Config2 = MIPS_CONFIG2,
132 .CP0_Config3 = MIPS_CONFIG3,
133 .CP0_LLAddr_rw_bitmask = 0,
134 .CP0_LLAddr_shift = 4,
135 .SYNCI_Step = 32,
136 .CCRes = 2,
137 .CP0_Status_rw_bitmask = 0x1258FF17,
138 .SEGBITS = 32,
139 .PABITS = 32,
140 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
141 .mmu_type = MMU_TYPE_FMT,
142 },
143 {
144 .name = "4KEcR1",
145 .CP0_PRid = 0x00018400,
146 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
147 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
148 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
149 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
150 (0 << CP0C1_CA),
151 .CP0_Config2 = MIPS_CONFIG2,
152 .CP0_Config3 = MIPS_CONFIG3,
153 .CP0_LLAddr_rw_bitmask = 0,
154 .CP0_LLAddr_shift = 4,
155 .SYNCI_Step = 32,
156 .CCRes = 2,
157 .CP0_Status_rw_bitmask = 0x1278FF17,
158 .SEGBITS = 32,
159 .PABITS = 32,
160 .insn_flags = CPU_MIPS32,
161 .mmu_type = MMU_TYPE_R4000,
162 },
163 {
164 .name = "4KEmR1",
165 .CP0_PRid = 0x00018500,
166 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
167 .CP0_Config1 = MIPS_CONFIG1 |
168 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
169 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
170 (1 << CP0C1_CA),
171 .CP0_Config2 = MIPS_CONFIG2,
172 .CP0_Config3 = MIPS_CONFIG3,
173 .CP0_LLAddr_rw_bitmask = 0,
174 .CP0_LLAddr_shift = 4,
175 .SYNCI_Step = 32,
176 .CCRes = 2,
177 .CP0_Status_rw_bitmask = 0x1258FF17,
178 .SEGBITS = 32,
179 .PABITS = 32,
180 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
181 .mmu_type = MMU_TYPE_FMT,
182 },
183 {
184 .name = "4KEc",
185 .CP0_PRid = 0x00019000,
186 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
187 (MMU_TYPE_R4000 << CP0C0_MT),
188 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
189 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
190 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
191 (0 << CP0C1_CA),
192 .CP0_Config2 = MIPS_CONFIG2,
193 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
194 .CP0_LLAddr_rw_bitmask = 0,
195 .CP0_LLAddr_shift = 4,
196 .SYNCI_Step = 32,
197 .CCRes = 2,
198 .CP0_Status_rw_bitmask = 0x1278FF17,
199 .SEGBITS = 32,
200 .PABITS = 32,
201 .insn_flags = CPU_MIPS32R2,
202 .mmu_type = MMU_TYPE_R4000,
203 },
204 {
205 .name = "4KEm",
206 .CP0_PRid = 0x00019100,
207 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
208 (MMU_TYPE_FMT << CP0C0_MT),
209 .CP0_Config1 = MIPS_CONFIG1 |
210 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
211 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
212 (1 << CP0C1_CA),
213 .CP0_Config2 = MIPS_CONFIG2,
214 .CP0_Config3 = MIPS_CONFIG3,
215 .CP0_LLAddr_rw_bitmask = 0,
216 .CP0_LLAddr_shift = 4,
217 .SYNCI_Step = 32,
218 .CCRes = 2,
219 .CP0_Status_rw_bitmask = 0x1258FF17,
220 .SEGBITS = 32,
221 .PABITS = 32,
222 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
223 .mmu_type = MMU_TYPE_FMT,
224 },
225 {
226 .name = "24Kc",
227 .CP0_PRid = 0x00019300,
228 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
229 (MMU_TYPE_R4000 << CP0C0_MT),
230 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
231 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
232 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
233 (1 << CP0C1_CA),
234 .CP0_Config2 = MIPS_CONFIG2,
235 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
236 .CP0_LLAddr_rw_bitmask = 0,
237 .CP0_LLAddr_shift = 4,
238 .SYNCI_Step = 32,
239 .CCRes = 2,
240 /* No DSP implemented. */
241 .CP0_Status_rw_bitmask = 0x1278FF1F,
242 .SEGBITS = 32,
243 .PABITS = 32,
244 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
245 .mmu_type = MMU_TYPE_R4000,
246 },
247 {
248 .name = "24Kf",
249 .CP0_PRid = 0x00019300,
250 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
251 (MMU_TYPE_R4000 << CP0C0_MT),
252 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
253 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
254 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
255 (1 << CP0C1_CA),
256 .CP0_Config2 = MIPS_CONFIG2,
257 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
258 .CP0_LLAddr_rw_bitmask = 0,
259 .CP0_LLAddr_shift = 4,
260 .SYNCI_Step = 32,
261 .CCRes = 2,
262 /* No DSP implemented. */
263 .CP0_Status_rw_bitmask = 0x3678FF1F,
264 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
265 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
266 .SEGBITS = 32,
267 .PABITS = 32,
268 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
269 .mmu_type = MMU_TYPE_R4000,
270 },
271 {
272 .name = "34Kf",
273 .CP0_PRid = 0x00019500,
274 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
275 (MMU_TYPE_R4000 << CP0C0_MT),
276 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
277 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
278 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
279 (1 << CP0C1_CA),
280 .CP0_Config2 = MIPS_CONFIG2,
281 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
282 .CP0_LLAddr_rw_bitmask = 0,
283 .CP0_LLAddr_shift = 0,
284 .SYNCI_Step = 32,
285 .CCRes = 2,
286 /* No DSP implemented. */
287 .CP0_Status_rw_bitmask = 0x3678FF1F,
288 /* No DSP implemented. */
289 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
290 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
291 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
292 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
293 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
294 (0xff << CP0TCSt_TASID),
295 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
296 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
297 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
298 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
299 .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
300 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
301 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
302 .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
303 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
304 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
305 .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
306 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
307 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
308 .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
309 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
310 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
311 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
312 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
313 .SEGBITS = 32,
314 .PABITS = 32,
315 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
316 .mmu_type = MMU_TYPE_R4000,
317 },
318 #if defined(TARGET_MIPS64)
319 {
320 .name = "R4000",
321 .CP0_PRid = 0x00000400,
322 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
323 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
324 /* Note: Config1 is only used internally, the R4000 has only Config0. */
325 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
326 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
327 .CP0_LLAddr_shift = 4,
328 .SYNCI_Step = 16,
329 .CCRes = 2,
330 .CP0_Status_rw_bitmask = 0x3678FFFF,
331 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
332 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
333 .SEGBITS = 40,
334 .PABITS = 36,
335 .insn_flags = CPU_MIPS3,
336 .mmu_type = MMU_TYPE_R4000,
337 },
338 {
339 .name = "VR5432",
340 .CP0_PRid = 0x00005400,
341 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
342 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
343 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
344 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
345 .CP0_LLAddr_shift = 4,
346 .SYNCI_Step = 16,
347 .CCRes = 2,
348 .CP0_Status_rw_bitmask = 0x3678FFFF,
349 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
350 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
351 .SEGBITS = 40,
352 .PABITS = 32,
353 .insn_flags = CPU_VR54XX,
354 .mmu_type = MMU_TYPE_R4000,
355 },
356 {
357 .name = "5Kc",
358 .CP0_PRid = 0x00018100,
359 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
360 (MMU_TYPE_R4000 << CP0C0_MT),
361 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
362 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
363 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
364 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
365 .CP0_Config2 = MIPS_CONFIG2,
366 .CP0_Config3 = MIPS_CONFIG3,
367 .CP0_LLAddr_rw_bitmask = 0,
368 .CP0_LLAddr_shift = 4,
369 .SYNCI_Step = 32,
370 .CCRes = 2,
371 .CP0_Status_rw_bitmask = 0x32F8FFFF,
372 .SEGBITS = 42,
373 .PABITS = 36,
374 .insn_flags = CPU_MIPS64,
375 .mmu_type = MMU_TYPE_R4000,
376 },
377 {
378 .name = "5Kf",
379 .CP0_PRid = 0x00018100,
380 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
381 (MMU_TYPE_R4000 << CP0C0_MT),
382 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
383 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
384 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
385 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
386 .CP0_Config2 = MIPS_CONFIG2,
387 .CP0_Config3 = MIPS_CONFIG3,
388 .CP0_LLAddr_rw_bitmask = 0,
389 .CP0_LLAddr_shift = 4,
390 .SYNCI_Step = 32,
391 .CCRes = 2,
392 .CP0_Status_rw_bitmask = 0x36F8FFFF,
393 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
394 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
395 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
396 .SEGBITS = 42,
397 .PABITS = 36,
398 .insn_flags = CPU_MIPS64,
399 .mmu_type = MMU_TYPE_R4000,
400 },
401 {
402 .name = "20Kc",
403 /* We emulate a later version of the 20Kc, earlier ones had a broken
404 WAIT instruction. */
405 .CP0_PRid = 0x000182a0,
406 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
407 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
408 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
409 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
410 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
411 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
412 .CP0_Config2 = MIPS_CONFIG2,
413 .CP0_Config3 = MIPS_CONFIG3,
414 .CP0_LLAddr_rw_bitmask = 0,
415 .CP0_LLAddr_shift = 0,
416 .SYNCI_Step = 32,
417 .CCRes = 1,
418 .CP0_Status_rw_bitmask = 0x36FBFFFF,
419 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
420 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
421 (1 << FCR0_D) | (1 << FCR0_S) |
422 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
423 .SEGBITS = 40,
424 .PABITS = 36,
425 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
426 .mmu_type = MMU_TYPE_R4000,
427 },
428 {
429 /* A generic CPU providing MIPS64 Release 2 features.
430 FIXME: Eventually this should be replaced by a real CPU model. */
431 .name = "MIPS64R2-generic",
432 .CP0_PRid = 0x00010000,
433 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
434 (MMU_TYPE_R4000 << CP0C0_MT),
435 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
436 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
437 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
438 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
439 .CP0_Config2 = MIPS_CONFIG2,
440 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
441 .CP0_LLAddr_rw_bitmask = 0,
442 .CP0_LLAddr_shift = 0,
443 .SYNCI_Step = 32,
444 .CCRes = 2,
445 .CP0_Status_rw_bitmask = 0x36FBFFFF,
446 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
447 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
448 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
449 .SEGBITS = 42,
450 /* The architectural limit is 59, but we have hardcoded 36 bit
451 in some places...
452 .PABITS = 59, */ /* the architectural limit */
453 .PABITS = 36,
454 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
455 .mmu_type = MMU_TYPE_R4000,
456 },
457 #endif
458 };
459
460 static const mips_def_t *cpu_mips_find_by_name (const char *name)
461 {
462 int i;
463
464 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
465 if (strcasecmp(name, mips_defs[i].name) == 0) {
466 return &mips_defs[i];
467 }
468 }
469 return NULL;
470 }
471
472 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
473 {
474 int i;
475
476 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
477 (*cpu_fprintf)(f, "MIPS '%s'\n",
478 mips_defs[i].name);
479 }
480 }
481
482 #ifndef CONFIG_USER_ONLY
483 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
484 {
485 env->tlb->nb_tlb = 1;
486 env->tlb->map_address = &no_mmu_map_address;
487 }
488
489 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
490 {
491 env->tlb->nb_tlb = 1;
492 env->tlb->map_address = &fixed_mmu_map_address;
493 }
494
495 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
496 {
497 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
498 env->tlb->map_address = &r4k_map_address;
499 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
500 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
501 env->tlb->helper_tlbp = r4k_helper_tlbp;
502 env->tlb->helper_tlbr = r4k_helper_tlbr;
503 }
504
505 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
506 {
507 env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
508
509 switch (def->mmu_type) {
510 case MMU_TYPE_NONE:
511 no_mmu_init(env, def);
512 break;
513 case MMU_TYPE_R4000:
514 r4k_mmu_init(env, def);
515 break;
516 case MMU_TYPE_FMT:
517 fixed_mmu_init(env, def);
518 break;
519 case MMU_TYPE_R3000:
520 case MMU_TYPE_R6000:
521 case MMU_TYPE_R8000:
522 default:
523 cpu_abort(env, "MMU type not supported\n");
524 }
525 }
526 #endif /* CONFIG_USER_ONLY */
527
528 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
529 {
530 int i;
531
532 for (i = 0; i < MIPS_FPU_MAX; i++)
533 env->fpus[i].fcr0 = def->CP1_fcr0;
534
535 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
536 }
537
538 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
539 {
540 env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
541
542 /* MVPConf1 implemented, TLB sharable, no gating storage support,
543 programmable cache partitioning implemented, number of allocatable
544 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
545 implemented, 5 TCs implemented. */
546 env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
547 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
548 // TODO: actually do 2 VPEs.
549 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
550 // (0x04 << CP0MVPC0_PTC);
551 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
552 (0x04 << CP0MVPC0_PTC);
553 #if !defined(CONFIG_USER_ONLY)
554 /* Usermode has no TLB support */
555 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
556 #endif
557
558 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
559 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
560 env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
561 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
562 (0x1 << CP0MVPC1_PCP1);
563 }
AR7 emulation for QEMU