target/xtensa/overlay_tool.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \
  29               a1, a2, a3, a4, a5, a6) { \
  30     .targno = (no), \
  31     .flags = (fl), \
  32     .type = (typ), \
  33     .group = (grp), \
  34     .size = (sz), \
  35 },
  36 #define XTREG_END { .targno = -1 },
  37
  38 #ifndef XCHAL_HAVE_DEPBITS
  39 #define XCHAL_HAVE_DEPBITS 0
  40 #endif
  41
  42 #ifndef XCHAL_HAVE_DIV32
  43 #define XCHAL_HAVE_DIV32 0
  44 #endif
  45
  46 #ifndef XCHAL_UNALIGNED_LOAD_HW
  47 #define XCHAL_UNALIGNED_LOAD_HW 0
  48 #endif
  49
  50 #ifndef XCHAL_HAVE_VECBASE
  51 #define XCHAL_HAVE_VECBASE 0
  52 #define XCHAL_VECBASE_RESET_VADDR 0
  53 #endif
  54
  55 #ifndef XCHAL_RESET_VECTOR0_VADDR
  56 #define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
  57 #endif
  58
  59 #ifndef XCHAL_RESET_VECTOR1_VADDR
  60 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
  61 #endif
  62
  63 #ifndef XCHAL_HW_MIN_VERSION
  64 #define XCHAL_HW_MIN_VERSION 0
  65 #endif
  66
  67 #ifndef XCHAL_LOOP_BUFFER_SIZE
  68 #define XCHAL_LOOP_BUFFER_SIZE 0
  69 #endif
  70
  71 #ifndef XCHAL_HAVE_EXTERN_REGS
  72 #define XCHAL_HAVE_EXTERN_REGS 0
  73 #endif
  74
  75 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
  76
  77 #define XTENSA_OPTIONS ( \
  78     XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
  79     XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
  80     XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
  81     XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
  82     XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
  83     XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
  84     XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
  85     XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
  86     XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
  87     XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
  88     XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
  89     XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
  90     XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
  91     XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
  92     XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
  93     XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
  94     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
  95     XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
  96         XTENSA_OPTION_ATOMCTL) | \
  97     XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
  98     /* Interrupts and exceptions */ \
  99     XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
 100     XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
 101     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
 102         XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
 103     XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
 104     XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
 105         XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
 106     XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
 107     /* Local memory, TODO */ \
 108     XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
 109     XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
 110             XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
 111     XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \
 112     XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
 113             XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
 114     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
 115     /* Memory protection and translation */ \
 116     XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
 117             XTENSA_OPTION_REGION_PROTECTION) | \
 118     XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
 119             XTENSA_OPTION_REGION_TRANSLATION) | \
 120     XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
 121     XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
 122     /* Other, TODO */ \
 123     XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
 124     XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
 125     XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
 126     XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
 127     XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \
 128     XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))
 129
 130 #ifndef XCHAL_WINDOW_OF4_VECOFS
 131 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 132 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 133 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 134 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 135 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 136 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 137 #endif
 138
 139 #if XCHAL_HAVE_WINDOWED
 140 #define WINDOW_VECTORS \
 141    [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
 142        XCHAL_WINDOW_VECTORS_VADDR, \
 143    [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
 144        XCHAL_WINDOW_VECTORS_VADDR, \
 145    [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
 146        XCHAL_WINDOW_VECTORS_VADDR, \
 147    [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
 148        XCHAL_WINDOW_VECTORS_VADDR, \
 149    [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
 150        XCHAL_WINDOW_VECTORS_VADDR, \
 151    [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
 152        XCHAL_WINDOW_VECTORS_VADDR,
 153 #else
 154 #define WINDOW_VECTORS
 155 #endif
 156
 157 #define EXCEPTION_VECTORS { \
 158         [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
 159         [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
 160         WINDOW_VECTORS \
 161         [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
 162         [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
 163         [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
 164         [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
 165     }
 166
 167 #define INTERRUPT_VECTORS { \
 168         0, \
 169         0, \
 170         XCHAL_INTLEVEL2_VECTOR_VADDR, \
 171         XCHAL_INTLEVEL3_VECTOR_VADDR, \
 172         XCHAL_INTLEVEL4_VECTOR_VADDR, \
 173         XCHAL_INTLEVEL5_VECTOR_VADDR, \
 174         XCHAL_INTLEVEL6_VECTOR_VADDR, \
 175         XCHAL_INTLEVEL7_VECTOR_VADDR, \
 176     }
 177
 178 #define LEVEL_MASKS { \
 179         [1] = XCHAL_INTLEVEL1_MASK, \
 180         [2] = XCHAL_INTLEVEL2_MASK, \
 181         [3] = XCHAL_INTLEVEL3_MASK, \
 182         [4] = XCHAL_INTLEVEL4_MASK, \
 183         [5] = XCHAL_INTLEVEL5_MASK, \
 184         [6] = XCHAL_INTLEVEL6_MASK, \
 185         [7] = XCHAL_INTLEVEL7_MASK, \
 186     }
 187
 188 #define INTTYPE_MASKS { \
 189         [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
 190         [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
 191         [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
 192     }
 193
 194 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
 195 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
 196 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
 197 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
 198 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
 199 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
 200 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
 201 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
 202 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
 203
 204
 205 #define INTERRUPT(i) { \
 206         .level = XCHAL_INT ## i ## _LEVEL, \
 207         .inttype = XCHAL_INT ## i ## _TYPE, \
 208     }
 209
 210 #define INTERRUPTS { \
 211         [0] = INTERRUPT(0), \
 212         [1] = INTERRUPT(1), \
 213         [2] = INTERRUPT(2), \
 214         [3] = INTERRUPT(3), \
 215         [4] = INTERRUPT(4), \
 216         [5] = INTERRUPT(5), \
 217         [6] = INTERRUPT(6), \
 218         [7] = INTERRUPT(7), \
 219         [8] = INTERRUPT(8), \
 220         [9] = INTERRUPT(9), \
 221         [10] = INTERRUPT(10), \
 222         [11] = INTERRUPT(11), \
 223         [12] = INTERRUPT(12), \
 224         [13] = INTERRUPT(13), \
 225         [14] = INTERRUPT(14), \
 226         [15] = INTERRUPT(15), \
 227         [16] = INTERRUPT(16), \
 228         [17] = INTERRUPT(17), \
 229         [18] = INTERRUPT(18), \
 230         [19] = INTERRUPT(19), \
 231         [20] = INTERRUPT(20), \
 232         [21] = INTERRUPT(21), \
 233         [22] = INTERRUPT(22), \
 234         [23] = INTERRUPT(23), \
 235         [24] = INTERRUPT(24), \
 236         [25] = INTERRUPT(25), \
 237         [26] = INTERRUPT(26), \
 238         [27] = INTERRUPT(27), \
 239         [28] = INTERRUPT(28), \
 240         [29] = INTERRUPT(29), \
 241         [30] = INTERRUPT(30), \
 242         [31] = INTERRUPT(31), \
 243     }
 244
 245 #define TIMERINTS { \
 246         [0] = XCHAL_TIMER0_INTERRUPT, \
 247         [1] = XCHAL_TIMER1_INTERRUPT, \
 248         [2] = XCHAL_TIMER2_INTERRUPT, \
 249     }
 250
 251 #define EXTINTS { \
 252         [0] = XCHAL_EXTINT0_NUM, \
 253         [1] = XCHAL_EXTINT1_NUM, \
 254         [2] = XCHAL_EXTINT2_NUM, \
 255         [3] = XCHAL_EXTINT3_NUM, \
 256         [4] = XCHAL_EXTINT4_NUM, \
 257         [5] = XCHAL_EXTINT5_NUM, \
 258         [6] = XCHAL_EXTINT6_NUM, \
 259         [7] = XCHAL_EXTINT7_NUM, \
 260         [8] = XCHAL_EXTINT8_NUM, \
 261         [9] = XCHAL_EXTINT9_NUM, \
 262         [10] = XCHAL_EXTINT10_NUM, \
 263         [11] = XCHAL_EXTINT11_NUM, \
 264         [12] = XCHAL_EXTINT12_NUM, \
 265         [13] = XCHAL_EXTINT13_NUM, \
 266         [14] = XCHAL_EXTINT14_NUM, \
 267         [15] = XCHAL_EXTINT15_NUM, \
 268         [16] = XCHAL_EXTINT16_NUM, \
 269         [17] = XCHAL_EXTINT17_NUM, \
 270         [18] = XCHAL_EXTINT18_NUM, \
 271         [19] = XCHAL_EXTINT19_NUM, \
 272         [20] = XCHAL_EXTINT20_NUM, \
 273         [21] = XCHAL_EXTINT21_NUM, \
 274         [22] = XCHAL_EXTINT22_NUM, \
 275         [23] = XCHAL_EXTINT23_NUM, \
 276         [24] = XCHAL_EXTINT24_NUM, \
 277         [25] = XCHAL_EXTINT25_NUM, \
 278         [26] = XCHAL_EXTINT26_NUM, \
 279         [27] = XCHAL_EXTINT27_NUM, \
 280         [28] = XCHAL_EXTINT28_NUM, \
 281         [29] = XCHAL_EXTINT29_NUM, \
 282         [30] = XCHAL_EXTINT30_NUM, \
 283         [31] = XCHAL_EXTINT31_NUM, \
 284     }
 285
 286 #define EXCEPTIONS_SECTION \
 287     .excm_level = XCHAL_EXCM_LEVEL, \
 288     .vecbase = XCHAL_VECBASE_RESET_VADDR, \
 289     .exception_vector = EXCEPTION_VECTORS
 290
 291 #define INTERRUPTS_SECTION \
 292     .ninterrupt = XCHAL_NUM_INTERRUPTS, \
 293     .nlevel = XCHAL_NUM_INTLEVELS, \
 294     .interrupt_vector = INTERRUPT_VECTORS, \
 295     .level_mask = LEVEL_MASKS, \
 296     .inttype_mask = INTTYPE_MASKS, \
 297     .interrupt = INTERRUPTS, \
 298     .nccompare = XCHAL_NUM_TIMERS, \
 299     .timerint = TIMERINTS, \
 300     .nextint = XCHAL_NUM_EXTINTERRUPTS, \
 301     .extint = EXTINTS
 302
 303 #if XCHAL_HAVE_PTP_MMU
 304
 305 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
 306         .nways = ways, \
 307         .way_size = { \
 308             (refill_way_size), (refill_way_size), \
 309             (refill_way_size), (refill_way_size), \
 310             4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
 311         }, \
 312         .varway56 = (way56), \
 313         .nrefillentries = (refill_way_size) * 4, \
 314     }
 315
 316 #define ITLB(varway56) \
 317     TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
 318
 319 #define DTLB(varway56) \
 320     TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
 321
 322 #define TLB_SECTION \
 323     .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
 324     .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
 325
 326 #ifndef XCHAL_SYSROM0_PADDR
 327 #define XCHAL_SYSROM0_PADDR 0xfe000000
 328 #define XCHAL_SYSROM0_SIZE  0x02000000
 329 #endif
 330
 331 #ifndef XCHAL_SYSRAM0_PADDR
 332 #define XCHAL_SYSRAM0_PADDR 0x00000000
 333 #define XCHAL_SYSRAM0_SIZE  0x08000000
 334 #endif
 335
 336 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
 337
 338 #define TLB_TEMPLATE { \
 339         .nways = 1, \
 340         .way_size = { \
 341             8, \
 342         } \
 343     }
 344
 345 #define TLB_SECTION \
 346     .itlb = TLB_TEMPLATE, \
 347     .dtlb = TLB_TEMPLATE
 348
 349 #ifndef XCHAL_SYSROM0_PADDR
 350 #define XCHAL_SYSROM0_PADDR 0x50000000
 351 #define XCHAL_SYSROM0_SIZE  0x04000000
 352 #endif
 353
 354 #ifndef XCHAL_SYSRAM0_PADDR
 355 #define XCHAL_SYSRAM0_PADDR 0x60000000
 356 #define XCHAL_SYSRAM0_SIZE  0x04000000
 357 #endif
 358
 359 #else
 360
 361 #ifndef XCHAL_SYSROM0_PADDR
 362 #define XCHAL_SYSROM0_PADDR 0x50000000
 363 #define XCHAL_SYSROM0_SIZE  0x04000000
 364 #endif
 365
 366 #ifndef XCHAL_SYSRAM0_PADDR
 367 #define XCHAL_SYSRAM0_PADDR 0x60000000
 368 #define XCHAL_SYSRAM0_SIZE  0x04000000
 369 #endif
 370
 371 #endif
 372
 373 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
 374 #define REGISTER_CORE(core) \
 375     static void __attribute__((constructor)) register_core(void) \
 376     { \
 377         static XtensaConfigList node = { \
 378             .config = &core, \
 379         }; \
 380         xtensa_finalize_config(&core); \
 381         xtensa_register_core(&node); \
 382     }
 383 #else
 384 #define REGISTER_CORE(core)
 385 #endif
 386
 387 #define DEBUG_SECTION \
 388     .debug_level = XCHAL_DEBUGLEVEL, \
 389     .nibreak = XCHAL_NUM_IBREAK, \
 390     .ndbreak = XCHAL_NUM_DBREAK
 391
 392 #define CACHE_SECTION \
 393     .icache_ways = XCHAL_ICACHE_WAYS, \
 394     .dcache_ways = XCHAL_DCACHE_WAYS, \
 395     .memctl_mask = \
 396         (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
 397         (XCHAL_DCACHE_SIZE ? \
 398          MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \
 399         MEMCTL_ISNP | MEMCTL_DSNP | \
 400         (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
 401
 402 #define MEM_LOCATION(name, n) \
 403     { \
 404         .addr = XCHAL_ ## name ## n ## _PADDR, \
 405         .size = XCHAL_ ## name ## n ## _SIZE, \
 406     }
 407
 408 #define MEM_SECTIONS(name) \
 409     MEM_LOCATION(name, 0), \
 410     MEM_LOCATION(name, 1), \
 411     MEM_LOCATION(name, 2), \
 412     MEM_LOCATION(name, 3)
 413
 414 #define MEM_SECTION(name) \
 415     .num = XCHAL_NUM_ ## name, \
 416     .location = { \
 417         MEM_SECTIONS(name) \
 418     }
 419
 420 #define SYSMEM_SECTION(name) \
 421     .num = 1, \
 422     .location = { \
 423         { \
 424             .addr = XCHAL_ ## name ## 0_PADDR, \
 425             .size = XCHAL_ ## name ## 0_SIZE, \
 426         } \
 427     }
 428
 429 #define LOCAL_MEMORIES_SECTION \
 430     .instrom = { \
 431         MEM_SECTION(INSTROM) \
 432     }, \
 433     .instram = { \
 434         MEM_SECTION(INSTRAM) \
 435     }, \
 436     .datarom = { \
 437         MEM_SECTION(DATAROM) \
 438     }, \
 439     .dataram = { \
 440         MEM_SECTION(DATARAM) \
 441     }, \
 442     .sysrom = { \
 443         SYSMEM_SECTION(SYSROM) \
 444     }, \
 445     .sysram = { \
 446         SYSMEM_SECTION(SYSRAM) \
 447     }
 448
 449 #define CONFIG_SECTION \
 450     .configid = { \
 451         XCHAL_HW_CONFIGID0, \
 452         XCHAL_HW_CONFIGID1, \
 453     }
 454
 455 #define DEFAULT_SECTIONS \
 456     .options = XTENSA_OPTIONS, \
 457     .nareg = XCHAL_NUM_AREGS, \
 458     .ndepc = (XCHAL_XEA_VERSION >= 2), \
 459     .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
 460     .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
 461     EXCEPTIONS_SECTION, \
 462     INTERRUPTS_SECTION, \
 463     TLB_SECTION, \
 464     DEBUG_SECTION, \
 465     CACHE_SECTION, \
 466     LOCAL_MEMORIES_SECTION, \
 467     CONFIG_SECTION
 468
 469
 470 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
 471 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
 472 #endif
 473 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
 474 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
 475 #endif
 476 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
 477 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
 478 #endif
 479 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
 480 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
 481 #endif
 482 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
 483 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
 484 #endif
 485 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
 486 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
 487 #endif
 488
 489
 490 #if XCHAL_NUM_INTERRUPTS <= 0
 491 #define XCHAL_INT0_LEVEL 0
 492 #define XCHAL_INT0_TYPE 0
 493 #endif
 494 #if XCHAL_NUM_INTERRUPTS <= 1
 495 #define XCHAL_INT1_LEVEL 0
 496 #define XCHAL_INT1_TYPE 0
 497 #endif
 498 #if XCHAL_NUM_INTERRUPTS <= 2
 499 #define XCHAL_INT2_LEVEL 0
 500 #define XCHAL_INT2_TYPE 0
 501 #endif
 502 #if XCHAL_NUM_INTERRUPTS <= 3
 503 #define XCHAL_INT3_LEVEL 0
 504 #define XCHAL_INT3_TYPE 0
 505 #endif
 506 #if XCHAL_NUM_INTERRUPTS <= 4
 507 #define XCHAL_INT4_LEVEL 0
 508 #define XCHAL_INT4_TYPE 0
 509 #endif
 510 #if XCHAL_NUM_INTERRUPTS <= 5
 511 #define XCHAL_INT5_LEVEL 0
 512 #define XCHAL_INT5_TYPE 0
 513 #endif
 514 #if XCHAL_NUM_INTERRUPTS <= 6
 515 #define XCHAL_INT6_LEVEL 0
 516 #define XCHAL_INT6_TYPE 0
 517 #endif
 518 #if XCHAL_NUM_INTERRUPTS <= 7
 519 #define XCHAL_INT7_LEVEL 0
 520 #define XCHAL_INT7_TYPE 0
 521 #endif
 522 #if XCHAL_NUM_INTERRUPTS <= 8
 523 #define XCHAL_INT8_LEVEL 0
 524 #define XCHAL_INT8_TYPE 0
 525 #endif
 526 #if XCHAL_NUM_INTERRUPTS <= 9
 527 #define XCHAL_INT9_LEVEL 0
 528 #define XCHAL_INT9_TYPE 0
 529 #endif
 530 #if XCHAL_NUM_INTERRUPTS <= 10
 531 #define XCHAL_INT10_LEVEL 0
 532 #define XCHAL_INT10_TYPE 0
 533 #endif
 534 #if XCHAL_NUM_INTERRUPTS <= 11
 535 #define XCHAL_INT11_LEVEL 0
 536 #define XCHAL_INT11_TYPE 0
 537 #endif
 538 #if XCHAL_NUM_INTERRUPTS <= 12
 539 #define XCHAL_INT12_LEVEL 0
 540 #define XCHAL_INT12_TYPE 0
 541 #endif
 542 #if XCHAL_NUM_INTERRUPTS <= 13
 543 #define XCHAL_INT13_LEVEL 0
 544 #define XCHAL_INT13_TYPE 0
 545 #endif
 546 #if XCHAL_NUM_INTERRUPTS <= 14
 547 #define XCHAL_INT14_LEVEL 0
 548 #define XCHAL_INT14_TYPE 0
 549 #endif
 550 #if XCHAL_NUM_INTERRUPTS <= 15
 551 #define XCHAL_INT15_LEVEL 0
 552 #define XCHAL_INT15_TYPE 0
 553 #endif
 554 #if XCHAL_NUM_INTERRUPTS <= 16
 555 #define XCHAL_INT16_LEVEL 0
 556 #define XCHAL_INT16_TYPE 0
 557 #endif
 558 #if XCHAL_NUM_INTERRUPTS <= 17
 559 #define XCHAL_INT17_LEVEL 0
 560 #define XCHAL_INT17_TYPE 0
 561 #endif
 562 #if XCHAL_NUM_INTERRUPTS <= 18
 563 #define XCHAL_INT18_LEVEL 0
 564 #define XCHAL_INT18_TYPE 0
 565 #endif
 566 #if XCHAL_NUM_INTERRUPTS <= 19
 567 #define XCHAL_INT19_LEVEL 0
 568 #define XCHAL_INT19_TYPE 0
 569 #endif
 570 #if XCHAL_NUM_INTERRUPTS <= 20
 571 #define XCHAL_INT20_LEVEL 0
 572 #define XCHAL_INT20_TYPE 0
 573 #endif
 574 #if XCHAL_NUM_INTERRUPTS <= 21
 575 #define XCHAL_INT21_LEVEL 0
 576 #define XCHAL_INT21_TYPE 0
 577 #endif
 578 #if XCHAL_NUM_INTERRUPTS <= 22
 579 #define XCHAL_INT22_LEVEL 0
 580 #define XCHAL_INT22_TYPE 0
 581 #endif
 582 #if XCHAL_NUM_INTERRUPTS <= 23
 583 #define XCHAL_INT23_LEVEL 0
 584 #define XCHAL_INT23_TYPE 0
 585 #endif
 586 #if XCHAL_NUM_INTERRUPTS <= 24
 587 #define XCHAL_INT24_LEVEL 0
 588 #define XCHAL_INT24_TYPE 0
 589 #endif
 590 #if XCHAL_NUM_INTERRUPTS <= 25
 591 #define XCHAL_INT25_LEVEL 0
 592 #define XCHAL_INT25_TYPE 0
 593 #endif
 594 #if XCHAL_NUM_INTERRUPTS <= 26
 595 #define XCHAL_INT26_LEVEL 0
 596 #define XCHAL_INT26_TYPE 0
 597 #endif
 598 #if XCHAL_NUM_INTERRUPTS <= 27
 599 #define XCHAL_INT27_LEVEL 0
 600 #define XCHAL_INT27_TYPE 0
 601 #endif
 602 #if XCHAL_NUM_INTERRUPTS <= 28
 603 #define XCHAL_INT28_LEVEL 0
 604 #define XCHAL_INT28_TYPE 0
 605 #endif
 606 #if XCHAL_NUM_INTERRUPTS <= 29
 607 #define XCHAL_INT29_LEVEL 0
 608 #define XCHAL_INT29_TYPE 0
 609 #endif
 610 #if XCHAL_NUM_INTERRUPTS <= 30
 611 #define XCHAL_INT30_LEVEL 0
 612 #define XCHAL_INT30_TYPE 0
 613 #endif
 614 #if XCHAL_NUM_INTERRUPTS <= 31
 615 #define XCHAL_INT31_LEVEL 0
 616 #define XCHAL_INT31_TYPE 0
 617 #endif
 618
 619
 620 #if XCHAL_NUM_EXTINTERRUPTS <= 0
 621 #define XCHAL_EXTINT0_NUM 0
 622 #endif
 623 #if XCHAL_NUM_EXTINTERRUPTS <= 1
 624 #define XCHAL_EXTINT1_NUM 0
 625 #endif
 626 #if XCHAL_NUM_EXTINTERRUPTS <= 2
 627 #define XCHAL_EXTINT2_NUM 0
 628 #endif
 629 #if XCHAL_NUM_EXTINTERRUPTS <= 3
 630 #define XCHAL_EXTINT3_NUM 0
 631 #endif
 632 #if XCHAL_NUM_EXTINTERRUPTS <= 4
 633 #define XCHAL_EXTINT4_NUM 0
 634 #endif
 635 #if XCHAL_NUM_EXTINTERRUPTS <= 5
 636 #define XCHAL_EXTINT5_NUM 0
 637 #endif
 638 #if XCHAL_NUM_EXTINTERRUPTS <= 6
 639 #define XCHAL_EXTINT6_NUM 0
 640 #endif
 641 #if XCHAL_NUM_EXTINTERRUPTS <= 7
 642 #define XCHAL_EXTINT7_NUM 0
 643 #endif
 644 #if XCHAL_NUM_EXTINTERRUPTS <= 8
 645 #define XCHAL_EXTINT8_NUM 0
 646 #endif
 647 #if XCHAL_NUM_EXTINTERRUPTS <= 9
 648 #define XCHAL_EXTINT9_NUM 0
 649 #endif
 650 #if XCHAL_NUM_EXTINTERRUPTS <= 10
 651 #define XCHAL_EXTINT10_NUM 0
 652 #endif
 653 #if XCHAL_NUM_EXTINTERRUPTS <= 11
 654 #define XCHAL_EXTINT11_NUM 0
 655 #endif
 656 #if XCHAL_NUM_EXTINTERRUPTS <= 12
 657 #define XCHAL_EXTINT12_NUM 0
 658 #endif
 659 #if XCHAL_NUM_EXTINTERRUPTS <= 13
 660 #define XCHAL_EXTINT13_NUM 0
 661 #endif
 662 #if XCHAL_NUM_EXTINTERRUPTS <= 14
 663 #define XCHAL_EXTINT14_NUM 0
 664 #endif
 665 #if XCHAL_NUM_EXTINTERRUPTS <= 15
 666 #define XCHAL_EXTINT15_NUM 0
 667 #endif
 668 #if XCHAL_NUM_EXTINTERRUPTS <= 16
 669 #define XCHAL_EXTINT16_NUM 0
 670 #endif
 671 #if XCHAL_NUM_EXTINTERRUPTS <= 17
 672 #define XCHAL_EXTINT17_NUM 0
 673 #endif
 674 #if XCHAL_NUM_EXTINTERRUPTS <= 18
 675 #define XCHAL_EXTINT18_NUM 0
 676 #endif
 677 #if XCHAL_NUM_EXTINTERRUPTS <= 19
 678 #define XCHAL_EXTINT19_NUM 0
 679 #endif
 680 #if XCHAL_NUM_EXTINTERRUPTS <= 20
 681 #define XCHAL_EXTINT20_NUM 0
 682 #endif
 683 #if XCHAL_NUM_EXTINTERRUPTS <= 21
 684 #define XCHAL_EXTINT21_NUM 0
 685 #endif
 686 #if XCHAL_NUM_EXTINTERRUPTS <= 22
 687 #define XCHAL_EXTINT22_NUM 0
 688 #endif
 689 #if XCHAL_NUM_EXTINTERRUPTS <= 23
 690 #define XCHAL_EXTINT23_NUM 0
 691 #endif
 692 #if XCHAL_NUM_EXTINTERRUPTS <= 24
 693 #define XCHAL_EXTINT24_NUM 0
 694 #endif
 695 #if XCHAL_NUM_EXTINTERRUPTS <= 25
 696 #define XCHAL_EXTINT25_NUM 0
 697 #endif
 698 #if XCHAL_NUM_EXTINTERRUPTS <= 26
 699 #define XCHAL_EXTINT26_NUM 0
 700 #endif
 701 #if XCHAL_NUM_EXTINTERRUPTS <= 27
 702 #define XCHAL_EXTINT27_NUM 0
 703 #endif
 704 #if XCHAL_NUM_EXTINTERRUPTS <= 28
 705 #define XCHAL_EXTINT28_NUM 0
 706 #endif
 707 #if XCHAL_NUM_EXTINTERRUPTS <= 29
 708 #define XCHAL_EXTINT29_NUM 0
 709 #endif
 710 #if XCHAL_NUM_EXTINTERRUPTS <= 30
 711 #define XCHAL_EXTINT30_NUM 0
 712 #endif
 713 #if XCHAL_NUM_EXTINTERRUPTS <= 31
 714 #define XCHAL_EXTINT31_NUM 0
 715 #endif
 716
 717
 718 #define XTHAL_TIMER_UNCONFIGURED 0
 719
 720 #if XCHAL_NUM_INSTROM < 1
 721 #define XCHAL_INSTROM0_PADDR 0
 722 #define XCHAL_INSTROM0_SIZE 0
 723 #endif
 724 #if XCHAL_NUM_INSTROM < 2
 725 #define XCHAL_INSTROM1_PADDR 0
 726 #define XCHAL_INSTROM1_SIZE 0
 727 #endif
 728 #if XCHAL_NUM_INSTROM < 3
 729 #define XCHAL_INSTROM2_PADDR 0
 730 #define XCHAL_INSTROM2_SIZE 0
 731 #endif
 732 #if XCHAL_NUM_INSTROM < 4
 733 #define XCHAL_INSTROM3_PADDR 0
 734 #define XCHAL_INSTROM3_SIZE 0
 735 #endif
 736 #if XCHAL_NUM_INSTROM > MAX_NMEMORY
 737 #error XCHAL_NUM_INSTROM > MAX_NMEMORY
 738 #endif
 739
 740 #if XCHAL_NUM_INSTRAM < 1
 741 #define XCHAL_INSTRAM0_PADDR 0
 742 #define XCHAL_INSTRAM0_SIZE 0
 743 #endif
 744 #if XCHAL_NUM_INSTRAM < 2
 745 #define XCHAL_INSTRAM1_PADDR 0
 746 #define XCHAL_INSTRAM1_SIZE 0
 747 #endif
 748 #if XCHAL_NUM_INSTRAM < 3
 749 #define XCHAL_INSTRAM2_PADDR 0
 750 #define XCHAL_INSTRAM2_SIZE 0
 751 #endif
 752 #if XCHAL_NUM_INSTRAM < 4
 753 #define XCHAL_INSTRAM3_PADDR 0
 754 #define XCHAL_INSTRAM3_SIZE 0
 755 #endif
 756 #if XCHAL_NUM_INSTRAM > MAX_NMEMORY
 757 #error XCHAL_NUM_INSTRAM > MAX_NMEMORY
 758 #endif
 759
 760 #if XCHAL_NUM_DATAROM < 1
 761 #define XCHAL_DATAROM0_PADDR 0
 762 #define XCHAL_DATAROM0_SIZE 0
 763 #endif
 764 #if XCHAL_NUM_DATAROM < 2
 765 #define XCHAL_DATAROM1_PADDR 0
 766 #define XCHAL_DATAROM1_SIZE 0
 767 #endif
 768 #if XCHAL_NUM_DATAROM < 3
 769 #define XCHAL_DATAROM2_PADDR 0
 770 #define XCHAL_DATAROM2_SIZE 0
 771 #endif
 772 #if XCHAL_NUM_DATAROM < 4
 773 #define XCHAL_DATAROM3_PADDR 0
 774 #define XCHAL_DATAROM3_SIZE 0
 775 #endif
 776 #if XCHAL_NUM_DATAROM > MAX_NMEMORY
 777 #error XCHAL_NUM_DATAROM > MAX_NMEMORY
 778 #endif
 779
 780 #if XCHAL_NUM_DATARAM < 1
 781 #define XCHAL_DATARAM0_PADDR 0
 782 #define XCHAL_DATARAM0_SIZE 0
 783 #endif
 784 #if XCHAL_NUM_DATARAM < 2
 785 #define XCHAL_DATARAM1_PADDR 0
 786 #define XCHAL_DATARAM1_SIZE 0
 787 #endif
 788 #if XCHAL_NUM_DATARAM < 3
 789 #define XCHAL_DATARAM2_PADDR 0
 790 #define XCHAL_DATARAM2_SIZE 0
 791 #endif
 792 #if XCHAL_NUM_DATARAM < 4
 793 #define XCHAL_DATARAM3_PADDR 0
 794 #define XCHAL_DATARAM3_SIZE 0
 795 #endif
 796 #if XCHAL_NUM_DATARAM > MAX_NMEMORY
 797 #error XCHAL_NUM_DATARAM > MAX_NMEMORY
 798 #endif