hw/isa/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "hw/isa/vt82c686.h"
  15 #include "hw/pci/pci.h"
  16 #include "hw/qdev-properties.h"
  17 #include "hw/isa/isa.h"
  18 #include "hw/isa/superio.h"
  19 #include "migration/vmstate.h"
  20 #include "hw/isa/apm.h"
  21 #include "hw/acpi/acpi.h"
  22 #include "hw/i2c/pm_smbus.h"
  23 #include "qapi/error.h"
  24 #include "qemu/module.h"
  25 #include "qemu/range.h"
  26 #include "qemu/timer.h"
  27 #include "exec/address-spaces.h"
  28 #include "trace.h"
  29
  30 #define TYPE_VIA_PM "via-pm"
  31 OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM)
  32
  33 struct ViaPMState {
  34     PCIDevice dev;
  35     MemoryRegion io;
  36     ACPIREGS ar;
  37     APMState apm;
  38     PMSMBus smb;
  39 };
  40
  41 static void pm_io_space_update(ViaPMState *s)
  42 {
  43     uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL;
  44
  45     memory_region_transaction_begin();
  46     memory_region_set_address(&s->io, pmbase);
  47     memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7));
  48     memory_region_transaction_commit();
  49 }
  50
  51 static void smb_io_space_update(ViaPMState *s)
  52 {
  53     uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL;
  54
  55     memory_region_transaction_begin();
  56     memory_region_set_address(&s->smb.io, smbase);
  57     memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0));
  58     memory_region_transaction_commit();
  59 }
  60
  61 static int vmstate_acpi_post_load(void *opaque, int version_id)
  62 {
  63     ViaPMState *s = opaque;
  64
  65     pm_io_space_update(s);
  66     smb_io_space_update(s);
  67     return 0;
  68 }
  69
  70 static const VMStateDescription vmstate_acpi = {
  71     .name = "vt82c686b_pm",
  72     .version_id = 1,
  73     .minimum_version_id = 1,
  74     .post_load = vmstate_acpi_post_load,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_PCI_DEVICE(dev, ViaPMState),
  77         VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState),
  78         VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState),
  79         VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState),
  80         VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState),
  81         VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState),
  82         VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState),
  83         VMSTATE_END_OF_LIST()
  84     }
  85 };
  86
  87 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
  88 {
  89     ViaPMState *s = VIA_PM(d);
  90
  91     trace_via_pm_write(addr, val, len);
  92     pci_default_write_config(d, addr, val, len);
  93     if (ranges_overlap(addr, len, 0x48, 4)) {
  94         uint32_t v = pci_get_long(s->dev.config + 0x48);
  95         pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1);
  96     }
  97     if (range_covers_byte(addr, len, 0x41)) {
  98         pm_io_space_update(s);
  99     }
 100     if (ranges_overlap(addr, len, 0x90, 4)) {
 101         uint32_t v = pci_get_long(s->dev.config + 0x90);
 102         pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1);
 103     }
 104     if (range_covers_byte(addr, len, 0xd2)) {
 105         s->dev.config[0xd2] &= 0xf;
 106         smb_io_space_update(s);
 107     }
 108 }
 109
 110 static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size)
 111 {
 112     trace_via_pm_io_write(addr, data, size);
 113 }
 114
 115 static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size)
 116 {
 117     trace_via_pm_io_read(addr, 0, size);
 118     return 0;
 119 }
 120
 121 static const MemoryRegionOps pm_io_ops = {
 122     .read = pm_io_read,
 123     .write = pm_io_write,
 124     .endianness = DEVICE_NATIVE_ENDIAN,
 125     .impl = {
 126         .min_access_size = 1,
 127         .max_access_size = 1,
 128     },
 129 };
 130
 131 static void pm_update_sci(ViaPMState *s)
 132 {
 133     int sci_level, pmsts;
 134
 135     pmsts = acpi_pm1_evt_get_sts(&s->ar);
 136     sci_level = (((pmsts & s->ar.pm1.evt.en) &
 137                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 138                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 139                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 140                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 141     pci_set_irq(&s->dev, sci_level);
 142     /* schedule a timer interruption if needed */
 143     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 144                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 145 }
 146
 147 static void pm_tmr_timer(ACPIREGS *ar)
 148 {
 149     ViaPMState *s = container_of(ar, ViaPMState, ar);
 150     pm_update_sci(s);
 151 }
 152
 153 static void via_pm_reset(DeviceState *d)
 154 {
 155     ViaPMState *s = VIA_PM(d);
 156
 157     memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0,
 158            PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE);
 159     /* Power Management IO base */
 160     pci_set_long(s->dev.config + 0x48, 1);
 161     /* SMBus IO base */
 162     pci_set_long(s->dev.config + 0x90, 1);
 163
 164     pm_io_space_update(s);
 165     smb_io_space_update(s);
 166 }
 167
 168 static void via_pm_realize(PCIDevice *dev, Error **errp)
 169 {
 170     ViaPMState *s = VIA_PM(dev);
 171
 172     pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK |
 173                  PCI_STATUS_DEVSEL_MEDIUM);
 174
 175     pm_smbus_init(DEVICE(s), &s->smb, false);
 176     memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io);
 177     memory_region_set_enabled(&s->smb.io, false);
 178
 179     apm_init(dev, &s->apm, NULL, s);
 180
 181     memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128);
 182     memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io);
 183     memory_region_set_enabled(&s->io, false);
 184
 185     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 186     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 187     acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
 188 }
 189
 190 typedef struct via_pm_init_info {
 191     uint16_t device_id;
 192 } ViaPMInitInfo;
 193
 194 static void via_pm_class_init(ObjectClass *klass, void *data)
 195 {
 196     DeviceClass *dc = DEVICE_CLASS(klass);
 197     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 198     ViaPMInitInfo *info = data;
 199
 200     k->realize = via_pm_realize;
 201     k->config_write = pm_write_config;
 202     k->vendor_id = PCI_VENDOR_ID_VIA;
 203     k->device_id = info->device_id;
 204     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 205     k->revision = 0x40;
 206     dc->reset = via_pm_reset;
 207     /* Reason: part of VIA south bridge, does not exist stand alone */
 208     dc->user_creatable = false;
 209     dc->vmsd = &vmstate_acpi;
 210 }
 211
 212 static const TypeInfo via_pm_info = {
 213     .name          = TYPE_VIA_PM,
 214     .parent        = TYPE_PCI_DEVICE,
 215     .instance_size = sizeof(ViaPMState),
 216     .abstract      = true,
 217     .interfaces = (InterfaceInfo[]) {
 218         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 219         { },
 220     },
 221 };
 222
 223 static const ViaPMInitInfo vt82c686b_pm_init_info = {
 224     .device_id = PCI_DEVICE_ID_VIA_82C686B_PM,
 225 };
 226
 227 static const TypeInfo vt82c686b_pm_info = {
 228     .name          = TYPE_VT82C686B_PM,
 229     .parent        = TYPE_VIA_PM,
 230     .class_init    = via_pm_class_init,
 231     .class_data    = (void *)&vt82c686b_pm_init_info,
 232 };
 233
 234 static const ViaPMInitInfo vt8231_pm_init_info = {
 235     .device_id = PCI_DEVICE_ID_VIA_8231_PM,
 236 };
 237
 238 static const TypeInfo vt8231_pm_info = {
 239     .name          = TYPE_VT8231_PM,
 240     .parent        = TYPE_VIA_PM,
 241     .class_init    = via_pm_class_init,
 242     .class_data    = (void *)&vt8231_pm_init_info,
 243 };
 244
 245
 246 typedef struct SuperIOConfig {
 247     uint8_t regs[0x100];
 248     uint8_t index;
 249     MemoryRegion io;
 250 } SuperIOConfig;
 251
 252 static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
 253                               unsigned size)
 254 {
 255     SuperIOConfig *sc = opaque;
 256
 257     if (addr == 0x3f0) { /* config index register */
 258         sc->index = data & 0xff;
 259     } else {
 260         bool can_write = true;
 261         /* 0x3f1, config data register */
 262         trace_via_superio_write(sc->index, data & 0xff);
 263         switch (sc->index) {
 264         case 0x00 ... 0xdf:
 265         case 0xe4:
 266         case 0xe5:
 267         case 0xe9 ... 0xed:
 268         case 0xf3:
 269         case 0xf5:
 270         case 0xf7:
 271         case 0xf9 ... 0xfb:
 272         case 0xfd ... 0xff:
 273             can_write = false;
 274             break;
 275         /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
 276         default:
 277             break;
 278
 279         }
 280         if (can_write) {
 281             sc->regs[sc->index] = data & 0xff;
 282         }
 283     }
 284 }
 285
 286 static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
 287 {
 288     SuperIOConfig *sc = opaque;
 289     uint8_t val = sc->regs[sc->index];
 290
 291     trace_via_superio_read(sc->index, val);
 292     return val;
 293 }
 294
 295 static const MemoryRegionOps superio_cfg_ops = {
 296     .read = superio_cfg_read,
 297     .write = superio_cfg_write,
 298     .endianness = DEVICE_NATIVE_ENDIAN,
 299     .impl = {
 300         .min_access_size = 1,
 301         .max_access_size = 1,
 302     },
 303 };
 304
 305
 306 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
 307
 308 struct VT82C686BISAState {
 309     PCIDevice dev;
 310     SuperIOConfig superio_cfg;
 311 };
 312
 313 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
 314                                    uint32_t val, int len)
 315 {
 316     VT82C686BISAState *s = VT82C686B_ISA(d);
 317
 318     trace_via_isa_write(addr, val, len);
 319     pci_default_write_config(d, addr, val, len);
 320     if (addr == 0x85) {
 321         /* BIT(1): enable or disable superio config io ports */
 322         memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
 323     }
 324 }
 325
 326 static const VMStateDescription vmstate_via = {
 327     .name = "vt82c686b",
 328     .version_id = 1,
 329     .minimum_version_id = 1,
 330     .fields = (VMStateField[]) {
 331         VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
 332         VMSTATE_END_OF_LIST()
 333     }
 334 };
 335
 336 static void vt82c686b_isa_reset(DeviceState *dev)
 337 {
 338     VT82C686BISAState *s = VT82C686B_ISA(dev);
 339     uint8_t *pci_conf = s->dev.config;
 340
 341     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 342     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 343                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 344     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 345
 346     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 347     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 348     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 349     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 350     pci_conf[0x59] = 0x04;
 351     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 352     pci_conf[0x5f] = 0x04;
 353     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 354
 355     s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
 356     s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
 357     s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
 358     s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
 359     s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
 360     s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
 361 }
 362
 363 static void vt82c686b_realize(PCIDevice *d, Error **errp)
 364 {
 365     VT82C686BISAState *s = VT82C686B_ISA(d);
 366     uint8_t *pci_conf;
 367     ISABus *isa_bus;
 368     uint8_t *wmask;
 369     int i;
 370
 371     isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
 372                           pci_address_space_io(d), errp);
 373     if (!isa_bus) {
 374         return;
 375     }
 376
 377     pci_conf = d->config;
 378     pci_config_set_prog_interface(pci_conf, 0x0);
 379
 380     wmask = d->wmask;
 381     for (i = 0x00; i < 0xff; i++) {
 382         if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
 383             wmask[i] = 0x00;
 384         }
 385     }
 386
 387     memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
 388                           &s->superio_cfg, "superio_cfg", 2);
 389     memory_region_set_enabled(&s->superio_cfg.io, false);
 390     /*
 391      * The floppy also uses 0x3f0 and 0x3f1.
 392      * But we do not emulate a floppy, so just set it here.
 393      */
 394     memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
 395                                 &s->superio_cfg.io);
 396 }
 397
 398 static void via_class_init(ObjectClass *klass, void *data)
 399 {
 400     DeviceClass *dc = DEVICE_CLASS(klass);
 401     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 402
 403     k->realize = vt82c686b_realize;
 404     k->config_write = vt82c686b_write_config;
 405     k->vendor_id = PCI_VENDOR_ID_VIA;
 406     k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
 407     k->class_id = PCI_CLASS_BRIDGE_ISA;
 408     k->revision = 0x40;
 409     dc->reset = vt82c686b_isa_reset;
 410     dc->desc = "ISA bridge";
 411     dc->vmsd = &vmstate_via;
 412     /*
 413      * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
 414      * e.g. by mips_fuloong2e_init()
 415      */
 416     dc->user_creatable = false;
 417 }
 418
 419 static const TypeInfo via_info = {
 420     .name          = TYPE_VT82C686B_ISA,
 421     .parent        = TYPE_PCI_DEVICE,
 422     .instance_size = sizeof(VT82C686BISAState),
 423     .class_init    = via_class_init,
 424     .interfaces = (InterfaceInfo[]) {
 425         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 426         { },
 427     },
 428 };
 429
 430
 431 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
 432 {
 433     ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
 434
 435     sc->serial.count = 2;
 436     sc->parallel.count = 1;
 437     sc->ide.count = 0;
 438     sc->floppy.count = 1;
 439 }
 440
 441 static const TypeInfo via_superio_info = {
 442     .name          = TYPE_VT82C686B_SUPERIO,
 443     .parent        = TYPE_ISA_SUPERIO,
 444     .instance_size = sizeof(ISASuperIODevice),
 445     .class_size    = sizeof(ISASuperIOClass),
 446     .class_init    = vt82c686b_superio_class_init,
 447 };
 448
 449
 450 static void vt82c686b_register_types(void)
 451 {
 452     type_register_static(&via_pm_info);
 453     type_register_static(&vt82c686b_pm_info);
 454     type_register_static(&vt8231_pm_info);
 455     type_register_static(&via_info);
 456     type_register_static(&via_superio_info);
 457 }
 458
 459 type_init(vt82c686b_register_types)