2 * PowerPC implementation of KVM hooks
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
17 #include "qemu/osdep.h"
19 #include <sys/ioctl.h>
22 #include <linux/kvm.h>
24 #include "qemu-common.h"
25 #include "qapi/error.h"
26 #include "qemu/error-report.h"
28 #include "cpu-models.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/hw_accel.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/device_tree.h"
35 #include "mmu-hash64.h"
37 #include "hw/sysbus.h"
38 #include "hw/ppc/spapr.h"
39 #include "hw/ppc/spapr_cpu_core.h"
40 #include "hw/ppc/ppc.h"
41 #include "sysemu/watchdog.h"
43 #include "exec/gdbstub.h"
44 #include "exec/memattrs.h"
45 #include "exec/ram_addr.h"
46 #include "sysemu/hostmem.h"
47 #include "qemu/cutils.h"
48 #include "qemu/mmap-alloc.h"
50 #include "sysemu/kvm_int.h"
52 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
54 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
58 static int cap_interrupt_unset
;
59 static int cap_interrupt_level
;
60 static int cap_segstate
;
61 static int cap_booke_sregs
;
62 static int cap_ppc_smt
;
63 static int cap_ppc_smt_possible
;
64 static int cap_spapr_tce
;
65 static int cap_spapr_tce_64
;
66 static int cap_spapr_multitce
;
67 static int cap_spapr_vfio
;
69 static int cap_one_reg
;
71 static int cap_ppc_watchdog
;
73 static int cap_htab_fd
;
74 static int cap_fixup_hcalls
;
75 static int cap_htm
; /* Hardware transactional memory support */
76 static int cap_mmu_radix
;
77 static int cap_mmu_hash_v3
;
79 static int cap_resize_hpt
;
80 static int cap_ppc_pvr_compat
;
81 static int cap_ppc_safe_cache
;
82 static int cap_ppc_safe_bounds_check
;
83 static int cap_ppc_safe_indirect_branch
;
84 static int cap_ppc_count_cache_flush_assist
;
85 static int cap_ppc_nested_kvm_hv
;
86 static int cap_large_decr
;
88 static uint32_t debug_inst_opcode
;
91 * XXX We have a race condition where we actually have a level triggered
92 * interrupt, but the infrastructure can't expose that yet, so the guest
93 * takes but ignores it, goes to sleep and never gets notified that there's
94 * still an interrupt pending.
96 * As a quick workaround, let's just wake up again 20 ms after we injected
97 * an interrupt. That way we can assure that we're always reinjecting
98 * interrupts in case the guest swallowed them.
100 static QEMUTimer
*idle_timer
;
102 static void kvm_kick_cpu(void *opaque
)
104 PowerPCCPU
*cpu
= opaque
;
106 qemu_cpu_kick(CPU(cpu
));
110 * Check whether we are running with KVM-PR (instead of KVM-HV). This
111 * should only be used for fallback tests - generally we should use
112 * explicit capabilities for the features we want, rather than
113 * assuming what is/isn't available depending on the KVM variant.
115 static bool kvmppc_is_pr(KVMState
*ks
)
117 /* Assume KVM-PR if the GET_PVINFO capability is available */
118 return kvm_vm_check_extension(ks
, KVM_CAP_PPC_GET_PVINFO
) != 0;
121 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
);
122 static void kvmppc_get_cpu_characteristics(KVMState
*s
);
123 static int kvmppc_get_dec_bits(void);
125 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
127 cap_interrupt_unset
= kvm_check_extension(s
, KVM_CAP_PPC_UNSET_IRQ
);
128 cap_interrupt_level
= kvm_check_extension(s
, KVM_CAP_PPC_IRQ_LEVEL
);
129 cap_segstate
= kvm_check_extension(s
, KVM_CAP_PPC_SEGSTATE
);
130 cap_booke_sregs
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_SREGS
);
131 cap_ppc_smt_possible
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT_POSSIBLE
);
132 cap_spapr_tce
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE
);
133 cap_spapr_tce_64
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE_64
);
134 cap_spapr_multitce
= kvm_check_extension(s
, KVM_CAP_SPAPR_MULTITCE
);
135 cap_spapr_vfio
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_TCE_VFIO
);
136 cap_one_reg
= kvm_check_extension(s
, KVM_CAP_ONE_REG
);
137 cap_hior
= kvm_check_extension(s
, KVM_CAP_PPC_HIOR
);
138 cap_epr
= kvm_check_extension(s
, KVM_CAP_PPC_EPR
);
139 cap_ppc_watchdog
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_WATCHDOG
);
141 * Note: we don't set cap_papr here, because this capability is
142 * only activated after this by kvmppc_set_papr()
144 cap_htab_fd
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTAB_FD
);
145 cap_fixup_hcalls
= kvm_check_extension(s
, KVM_CAP_PPC_FIXUP_HCALL
);
146 cap_ppc_smt
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT
);
147 cap_htm
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTM
);
148 cap_mmu_radix
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
);
149 cap_mmu_hash_v3
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_HASH_V3
);
150 cap_xive
= kvm_vm_check_extension(s
, KVM_CAP_PPC_IRQ_XIVE
);
151 cap_resize_hpt
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_RESIZE_HPT
);
152 kvmppc_get_cpu_characteristics(s
);
153 cap_ppc_nested_kvm_hv
= kvm_vm_check_extension(s
, KVM_CAP_PPC_NESTED_HV
);
154 cap_large_decr
= kvmppc_get_dec_bits();
156 * Note: setting it to false because there is not such capability
157 * in KVM at this moment.
159 * TODO: call kvm_vm_check_extension() with the right capability
160 * after the kernel starts implementing it.
162 cap_ppc_pvr_compat
= false;
164 if (!cap_interrupt_level
) {
165 fprintf(stderr
, "KVM: Couldn't find level irq capability. Expect the "
166 "VM to stall at times!\n");
169 kvm_ppc_register_host_cpu_type(ms
);
174 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
179 static int kvm_arch_sync_sregs(PowerPCCPU
*cpu
)
181 CPUPPCState
*cenv
= &cpu
->env
;
182 CPUState
*cs
= CPU(cpu
);
183 struct kvm_sregs sregs
;
186 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
188 * What we're really trying to say is "if we're on BookE, we
189 * use the native PVR for now". This is the only sane way to
190 * check it though, so we potentially confuse users that they
191 * can run BookE guests on BookS. Let's hope nobody dares
197 fprintf(stderr
, "kvm error: missing PVR setting capability\n");
202 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_SREGS
, &sregs
);
207 sregs
.pvr
= cenv
->spr
[SPR_PVR
];
208 return kvm_vcpu_ioctl(cs
, KVM_SET_SREGS
, &sregs
);
211 /* Set up a shared TLB array with KVM */
212 static int kvm_booke206_tlb_init(PowerPCCPU
*cpu
)
214 CPUPPCState
*env
= &cpu
->env
;
215 CPUState
*cs
= CPU(cpu
);
216 struct kvm_book3e_206_tlb_params params
= {};
217 struct kvm_config_tlb cfg
= {};
218 unsigned int entries
= 0;
221 if (!kvm_enabled() ||
222 !kvm_check_extension(cs
->kvm_state
, KVM_CAP_SW_TLB
)) {
226 assert(ARRAY_SIZE(params
.tlb_sizes
) == BOOKE206_MAX_TLBN
);
228 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
229 params
.tlb_sizes
[i
] = booke206_tlb_size(env
, i
);
230 params
.tlb_ways
[i
] = booke206_tlb_ways(env
, i
);
231 entries
+= params
.tlb_sizes
[i
];
234 assert(entries
== env
->nb_tlb
);
235 assert(sizeof(struct kvm_book3e_206_tlb_entry
) == sizeof(ppcmas_tlb_t
));
237 env
->tlb_dirty
= true;
239 cfg
.array
= (uintptr_t)env
->tlb
.tlbm
;
240 cfg
.array_len
= sizeof(ppcmas_tlb_t
) * entries
;
241 cfg
.params
= (uintptr_t)¶ms
;
242 cfg
.mmu_type
= KVM_MMU_FSL_BOOKE_NOHV
;
244 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_SW_TLB
, 0, (uintptr_t)&cfg
);
246 fprintf(stderr
, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
247 __func__
, strerror(-ret
));
251 env
->kvm_sw_tlb
= true;
256 #if defined(TARGET_PPC64)
257 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info
*info
, Error
**errp
)
261 assert(kvm_state
!= NULL
);
263 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_GET_SMMU_INFO
)) {
264 error_setg(errp
, "KVM doesn't expose the MMU features it supports");
265 error_append_hint(errp
, "Consider switching to a newer KVM\n");
269 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_SMMU_INFO
, info
);
274 error_setg_errno(errp
, -ret
,
275 "KVM failed to provide the MMU features it supports");
278 struct ppc_radix_page_info
*kvm_get_radix_page_info(void)
280 KVMState
*s
= KVM_STATE(current_machine
->accelerator
);
281 struct ppc_radix_page_info
*radix_page_info
;
282 struct kvm_ppc_rmmu_info rmmu_info
;
285 if (!kvm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
)) {
288 if (kvm_vm_ioctl(s
, KVM_PPC_GET_RMMU_INFO
, &rmmu_info
)) {
291 radix_page_info
= g_malloc0(sizeof(*radix_page_info
));
292 radix_page_info
->count
= 0;
293 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
294 if (rmmu_info
.ap_encodings
[i
]) {
295 radix_page_info
->entries
[i
] = rmmu_info
.ap_encodings
[i
];
296 radix_page_info
->count
++;
299 return radix_page_info
;
302 target_ulong
kvmppc_configure_v3_mmu(PowerPCCPU
*cpu
,
303 bool radix
, bool gtse
,
306 CPUState
*cs
= CPU(cpu
);
309 struct kvm_ppc_mmuv3_cfg cfg
= {
310 .process_table
= proc_tbl
,
314 flags
|= KVM_PPC_MMUV3_RADIX
;
317 flags
|= KVM_PPC_MMUV3_GTSE
;
320 ret
= kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_CONFIGURE_V3_MMU
, &cfg
);
327 return H_NOT_AVAILABLE
;
333 bool kvmppc_hpt_needs_host_contiguous_pages(void)
335 static struct kvm_ppc_smmu_info smmu_info
;
337 if (!kvm_enabled()) {
341 kvm_get_smmu_info(&smmu_info
, &error_fatal
);
342 return !!(smmu_info
.flags
& KVM_PPC_PAGE_SIZES_REAL
);
345 void kvm_check_mmu(PowerPCCPU
*cpu
, Error
**errp
)
347 struct kvm_ppc_smmu_info smmu_info
;
349 Error
*local_err
= NULL
;
351 /* For now, we only have anything to check on hash64 MMUs */
352 if (!cpu
->hash64_opts
|| !kvm_enabled()) {
356 kvm_get_smmu_info(&smmu_info
, &local_err
);
358 error_propagate(errp
, local_err
);
362 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)
363 && !(smmu_info
.flags
& KVM_PPC_1T_SEGMENTS
)) {
365 "KVM does not support 1TiB segments which guest expects");
369 if (smmu_info
.slb_size
< cpu
->hash64_opts
->slb_size
) {
370 error_setg(errp
, "KVM only supports %u SLB entries, but guest needs %u",
371 smmu_info
.slb_size
, cpu
->hash64_opts
->slb_size
);
376 * Verify that every pagesize supported by the cpu model is
377 * supported by KVM with the same encodings
379 for (iq
= 0; iq
< ARRAY_SIZE(cpu
->hash64_opts
->sps
); iq
++) {
380 PPCHash64SegmentPageSizes
*qsps
= &cpu
->hash64_opts
->sps
[iq
];
381 struct kvm_ppc_one_seg_page_size
*ksps
;
383 for (ik
= 0; ik
< ARRAY_SIZE(smmu_info
.sps
); ik
++) {
384 if (qsps
->page_shift
== smmu_info
.sps
[ik
].page_shift
) {
388 if (ik
>= ARRAY_SIZE(smmu_info
.sps
)) {
389 error_setg(errp
, "KVM doesn't support for base page shift %u",
394 ksps
= &smmu_info
.sps
[ik
];
395 if (ksps
->slb_enc
!= qsps
->slb_enc
) {
397 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
398 ksps
->slb_enc
, ksps
->page_shift
, qsps
->slb_enc
);
402 for (jq
= 0; jq
< ARRAY_SIZE(qsps
->enc
); jq
++) {
403 for (jk
= 0; jk
< ARRAY_SIZE(ksps
->enc
); jk
++) {
404 if (qsps
->enc
[jq
].page_shift
== ksps
->enc
[jk
].page_shift
) {
409 if (jk
>= ARRAY_SIZE(ksps
->enc
)) {
410 error_setg(errp
, "KVM doesn't support page shift %u/%u",
411 qsps
->enc
[jq
].page_shift
, qsps
->page_shift
);
414 if (qsps
->enc
[jq
].pte_enc
!= ksps
->enc
[jk
].pte_enc
) {
416 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
417 ksps
->enc
[jk
].pte_enc
, qsps
->enc
[jq
].page_shift
,
418 qsps
->page_shift
, qsps
->enc
[jq
].pte_enc
);
424 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
426 * Mostly what guest pagesizes we can use are related to the
427 * host pages used to map guest RAM, which is handled in the
428 * platform code. Cache-Inhibited largepages (64k) however are
429 * used for I/O, so if they're mapped to the host at all it
430 * will be a normal mapping, not a special hugepage one used
433 if (getpagesize() < 0x10000) {
435 "KVM can't supply 64kiB CI pages, which guest expects");
439 #endif /* !defined (TARGET_PPC64) */
441 unsigned long kvm_arch_vcpu_id(CPUState
*cpu
)
443 return POWERPC_CPU(cpu
)->vcpu_id
;
447 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
448 * only 1 watchpoint, so array size of 4 is sufficient for now.
450 #define MAX_HW_BKPTS 4
452 static struct HWBreakpoint
{
455 } hw_debug_points
[MAX_HW_BKPTS
];
457 static CPUWatchpoint hw_watchpoint
;
459 /* Default there is no breakpoint and watchpoint supported */
460 static int max_hw_breakpoint
;
461 static int max_hw_watchpoint
;
462 static int nb_hw_breakpoint
;
463 static int nb_hw_watchpoint
;
465 static void kvmppc_hw_debug_points_init(CPUPPCState
*cenv
)
467 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
468 max_hw_breakpoint
= 2;
469 max_hw_watchpoint
= 2;
472 if ((max_hw_breakpoint
+ max_hw_watchpoint
) > MAX_HW_BKPTS
) {
473 fprintf(stderr
, "Error initializing h/w breakpoints\n");
478 int kvm_arch_init_vcpu(CPUState
*cs
)
480 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
481 CPUPPCState
*cenv
= &cpu
->env
;
484 /* Synchronize sregs with kvm */
485 ret
= kvm_arch_sync_sregs(cpu
);
487 if (ret
== -EINVAL
) {
488 error_report("Register sync failed... If you're using kvm-hv.ko,"
489 " only \"-cpu host\" is possible");
494 idle_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, kvm_kick_cpu
, cpu
);
496 switch (cenv
->mmu_model
) {
497 case POWERPC_MMU_BOOKE206
:
498 /* This target supports access to KVM's guest TLB */
499 ret
= kvm_booke206_tlb_init(cpu
);
501 case POWERPC_MMU_2_07
:
502 if (!cap_htm
&& !kvmppc_is_pr(cs
->kvm_state
)) {
504 * KVM-HV has transactional memory on POWER8 also without
505 * the KVM_CAP_PPC_HTM extension, so enable it here
506 * instead as long as it's availble to userspace on the
509 if (qemu_getauxval(AT_HWCAP2
) & PPC_FEATURE2_HAS_HTM
) {
518 kvm_get_one_reg(cs
, KVM_REG_PPC_DEBUG_INST
, &debug_inst_opcode
);
519 kvmppc_hw_debug_points_init(cenv
);
524 int kvm_arch_destroy_vcpu(CPUState
*cs
)
529 static void kvm_sw_tlb_put(PowerPCCPU
*cpu
)
531 CPUPPCState
*env
= &cpu
->env
;
532 CPUState
*cs
= CPU(cpu
);
533 struct kvm_dirty_tlb dirty_tlb
;
534 unsigned char *bitmap
;
537 if (!env
->kvm_sw_tlb
) {
541 bitmap
= g_malloc((env
->nb_tlb
+ 7) / 8);
542 memset(bitmap
, 0xFF, (env
->nb_tlb
+ 7) / 8);
544 dirty_tlb
.bitmap
= (uintptr_t)bitmap
;
545 dirty_tlb
.num_dirty
= env
->nb_tlb
;
547 ret
= kvm_vcpu_ioctl(cs
, KVM_DIRTY_TLB
, &dirty_tlb
);
549 fprintf(stderr
, "%s: KVM_DIRTY_TLB: %s\n",
550 __func__
, strerror(-ret
));
556 static void kvm_get_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
558 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
559 CPUPPCState
*env
= &cpu
->env
;
564 struct kvm_one_reg reg
= {
566 .addr
= (uintptr_t) &val
,
570 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
572 trace_kvm_failed_spr_get(spr
, strerror(errno
));
574 switch (id
& KVM_REG_SIZE_MASK
) {
575 case KVM_REG_SIZE_U32
:
576 env
->spr
[spr
] = val
.u32
;
579 case KVM_REG_SIZE_U64
:
580 env
->spr
[spr
] = val
.u64
;
584 /* Don't handle this size yet */
590 static void kvm_put_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
592 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
593 CPUPPCState
*env
= &cpu
->env
;
598 struct kvm_one_reg reg
= {
600 .addr
= (uintptr_t) &val
,
604 switch (id
& KVM_REG_SIZE_MASK
) {
605 case KVM_REG_SIZE_U32
:
606 val
.u32
= env
->spr
[spr
];
609 case KVM_REG_SIZE_U64
:
610 val
.u64
= env
->spr
[spr
];
614 /* Don't handle this size yet */
618 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
620 trace_kvm_failed_spr_set(spr
, strerror(errno
));
624 static int kvm_put_fp(CPUState
*cs
)
626 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
627 CPUPPCState
*env
= &cpu
->env
;
628 struct kvm_one_reg reg
;
632 if (env
->insns_flags
& PPC_FLOAT
) {
633 uint64_t fpscr
= env
->fpscr
;
634 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
636 reg
.id
= KVM_REG_PPC_FPSCR
;
637 reg
.addr
= (uintptr_t)&fpscr
;
638 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
640 trace_kvm_failed_fpscr_set(strerror(errno
));
644 for (i
= 0; i
< 32; i
++) {
646 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
647 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
649 #ifdef HOST_WORDS_BIGENDIAN
650 vsr
[0] = float64_val(*fpr
);
654 vsr
[1] = float64_val(*fpr
);
656 reg
.addr
= (uintptr_t) &vsr
;
657 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
659 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
661 trace_kvm_failed_fp_set(vsx
? "VSR" : "FPR", i
,
668 if (env
->insns_flags
& PPC_ALTIVEC
) {
669 reg
.id
= KVM_REG_PPC_VSCR
;
670 reg
.addr
= (uintptr_t)&env
->vscr
;
671 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
673 trace_kvm_failed_vscr_set(strerror(errno
));
677 for (i
= 0; i
< 32; i
++) {
678 reg
.id
= KVM_REG_PPC_VR(i
);
679 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
680 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
682 trace_kvm_failed_vr_set(i
, strerror(errno
));
691 static int kvm_get_fp(CPUState
*cs
)
693 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
694 CPUPPCState
*env
= &cpu
->env
;
695 struct kvm_one_reg reg
;
699 if (env
->insns_flags
& PPC_FLOAT
) {
701 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
703 reg
.id
= KVM_REG_PPC_FPSCR
;
704 reg
.addr
= (uintptr_t)&fpscr
;
705 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
707 trace_kvm_failed_fpscr_get(strerror(errno
));
713 for (i
= 0; i
< 32; i
++) {
715 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
716 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
718 reg
.addr
= (uintptr_t) &vsr
;
719 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
721 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
723 trace_kvm_failed_fp_get(vsx
? "VSR" : "FPR", i
,
727 #ifdef HOST_WORDS_BIGENDIAN
742 if (env
->insns_flags
& PPC_ALTIVEC
) {
743 reg
.id
= KVM_REG_PPC_VSCR
;
744 reg
.addr
= (uintptr_t)&env
->vscr
;
745 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
747 trace_kvm_failed_vscr_get(strerror(errno
));
751 for (i
= 0; i
< 32; i
++) {
752 reg
.id
= KVM_REG_PPC_VR(i
);
753 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
754 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
756 trace_kvm_failed_vr_get(i
, strerror(errno
));
765 #if defined(TARGET_PPC64)
766 static int kvm_get_vpa(CPUState
*cs
)
768 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
769 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
770 struct kvm_one_reg reg
;
773 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
774 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
775 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
777 trace_kvm_failed_vpa_addr_get(strerror(errno
));
781 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
782 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
783 reg
.id
= KVM_REG_PPC_VPA_SLB
;
784 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
785 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
787 trace_kvm_failed_slb_get(strerror(errno
));
791 assert((uintptr_t)&spapr_cpu
->dtl_size
792 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
793 reg
.id
= KVM_REG_PPC_VPA_DTL
;
794 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
795 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
797 trace_kvm_failed_dtl_get(strerror(errno
));
804 static int kvm_put_vpa(CPUState
*cs
)
806 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
807 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
808 struct kvm_one_reg reg
;
812 * SLB shadow or DTL can't be registered unless a master VPA is
813 * registered. That means when restoring state, if a VPA *is*
814 * registered, we need to set that up first. If not, we need to
815 * deregister the others before deregistering the master VPA
817 assert(spapr_cpu
->vpa_addr
818 || !(spapr_cpu
->slb_shadow_addr
|| spapr_cpu
->dtl_addr
));
820 if (spapr_cpu
->vpa_addr
) {
821 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
822 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
823 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
825 trace_kvm_failed_vpa_addr_set(strerror(errno
));
830 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
831 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
832 reg
.id
= KVM_REG_PPC_VPA_SLB
;
833 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
834 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
836 trace_kvm_failed_slb_set(strerror(errno
));
840 assert((uintptr_t)&spapr_cpu
->dtl_size
841 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
842 reg
.id
= KVM_REG_PPC_VPA_DTL
;
843 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
844 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
846 trace_kvm_failed_dtl_set(strerror(errno
));
850 if (!spapr_cpu
->vpa_addr
) {
851 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
852 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
853 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
855 trace_kvm_failed_null_vpa_addr_set(strerror(errno
));
862 #endif /* TARGET_PPC64 */
864 int kvmppc_put_books_sregs(PowerPCCPU
*cpu
)
866 CPUPPCState
*env
= &cpu
->env
;
867 struct kvm_sregs sregs
;
870 sregs
.pvr
= env
->spr
[SPR_PVR
];
873 PPCVirtualHypervisorClass
*vhc
=
874 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
875 sregs
.u
.s
.sdr1
= vhc
->encode_hpt_for_kvm_pr(cpu
->vhyp
);
877 sregs
.u
.s
.sdr1
= env
->spr
[SPR_SDR1
];
882 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
883 sregs
.u
.s
.ppc64
.slb
[i
].slbe
= env
->slb
[i
].esid
;
884 if (env
->slb
[i
].esid
& SLB_ESID_V
) {
885 sregs
.u
.s
.ppc64
.slb
[i
].slbe
|= i
;
887 sregs
.u
.s
.ppc64
.slb
[i
].slbv
= env
->slb
[i
].vsid
;
892 for (i
= 0; i
< 16; i
++) {
893 sregs
.u
.s
.ppc32
.sr
[i
] = env
->sr
[i
];
897 for (i
= 0; i
< 8; i
++) {
898 /* Beware. We have to swap upper and lower bits here */
899 sregs
.u
.s
.ppc32
.dbat
[i
] = ((uint64_t)env
->DBAT
[0][i
] << 32)
901 sregs
.u
.s
.ppc32
.ibat
[i
] = ((uint64_t)env
->IBAT
[0][i
] << 32)
905 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
908 int kvm_arch_put_registers(CPUState
*cs
, int level
)
910 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
911 CPUPPCState
*env
= &cpu
->env
;
912 struct kvm_regs regs
;
916 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
923 regs
.xer
= cpu_read_xer(env
);
927 regs
.srr0
= env
->spr
[SPR_SRR0
];
928 regs
.srr1
= env
->spr
[SPR_SRR1
];
930 regs
.sprg0
= env
->spr
[SPR_SPRG0
];
931 regs
.sprg1
= env
->spr
[SPR_SPRG1
];
932 regs
.sprg2
= env
->spr
[SPR_SPRG2
];
933 regs
.sprg3
= env
->spr
[SPR_SPRG3
];
934 regs
.sprg4
= env
->spr
[SPR_SPRG4
];
935 regs
.sprg5
= env
->spr
[SPR_SPRG5
];
936 regs
.sprg6
= env
->spr
[SPR_SPRG6
];
937 regs
.sprg7
= env
->spr
[SPR_SPRG7
];
939 regs
.pid
= env
->spr
[SPR_BOOKE_PID
];
941 for (i
= 0; i
< 32; i
++) {
942 regs
.gpr
[i
] = env
->gpr
[i
];
946 for (i
= 0; i
< 8; i
++) {
947 regs
.cr
|= (env
->crf
[i
] & 15) << (4 * (7 - i
));
950 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
957 if (env
->tlb_dirty
) {
959 env
->tlb_dirty
= false;
962 if (cap_segstate
&& (level
>= KVM_PUT_RESET_STATE
)) {
963 ret
= kvmppc_put_books_sregs(cpu
);
969 if (cap_hior
&& (level
>= KVM_PUT_RESET_STATE
)) {
970 kvm_put_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
977 * We deliberately ignore errors here, for kernels which have
978 * the ONE_REG calls, but don't support the specific
979 * registers, there's a reasonable chance things will still
980 * work, at least until we try to migrate.
982 for (i
= 0; i
< 1024; i
++) {
983 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
986 kvm_put_one_spr(cs
, id
, i
);
992 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
993 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
995 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
996 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
998 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
999 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
1000 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
1001 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
1002 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
1003 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
1004 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
1005 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
1006 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
1007 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
1011 if (kvm_put_vpa(cs
) < 0) {
1012 trace_kvm_failed_put_vpa();
1016 kvm_set_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
1017 #endif /* TARGET_PPC64 */
1023 static void kvm_sync_excp(CPUPPCState
*env
, int vector
, int ivor
)
1025 env
->excp_vectors
[vector
] = env
->spr
[ivor
] + env
->spr
[SPR_BOOKE_IVPR
];
1028 static int kvmppc_get_booke_sregs(PowerPCCPU
*cpu
)
1030 CPUPPCState
*env
= &cpu
->env
;
1031 struct kvm_sregs sregs
;
1034 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1039 if (sregs
.u
.e
.features
& KVM_SREGS_E_BASE
) {
1040 env
->spr
[SPR_BOOKE_CSRR0
] = sregs
.u
.e
.csrr0
;
1041 env
->spr
[SPR_BOOKE_CSRR1
] = sregs
.u
.e
.csrr1
;
1042 env
->spr
[SPR_BOOKE_ESR
] = sregs
.u
.e
.esr
;
1043 env
->spr
[SPR_BOOKE_DEAR
] = sregs
.u
.e
.dear
;
1044 env
->spr
[SPR_BOOKE_MCSR
] = sregs
.u
.e
.mcsr
;
1045 env
->spr
[SPR_BOOKE_TSR
] = sregs
.u
.e
.tsr
;
1046 env
->spr
[SPR_BOOKE_TCR
] = sregs
.u
.e
.tcr
;
1047 env
->spr
[SPR_DECR
] = sregs
.u
.e
.dec
;
1048 env
->spr
[SPR_TBL
] = sregs
.u
.e
.tb
& 0xffffffff;
1049 env
->spr
[SPR_TBU
] = sregs
.u
.e
.tb
>> 32;
1050 env
->spr
[SPR_VRSAVE
] = sregs
.u
.e
.vrsave
;
1053 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206
) {
1054 env
->spr
[SPR_BOOKE_PIR
] = sregs
.u
.e
.pir
;
1055 env
->spr
[SPR_BOOKE_MCSRR0
] = sregs
.u
.e
.mcsrr0
;
1056 env
->spr
[SPR_BOOKE_MCSRR1
] = sregs
.u
.e
.mcsrr1
;
1057 env
->spr
[SPR_BOOKE_DECAR
] = sregs
.u
.e
.decar
;
1058 env
->spr
[SPR_BOOKE_IVPR
] = sregs
.u
.e
.ivpr
;
1061 if (sregs
.u
.e
.features
& KVM_SREGS_E_64
) {
1062 env
->spr
[SPR_BOOKE_EPCR
] = sregs
.u
.e
.epcr
;
1065 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPRG8
) {
1066 env
->spr
[SPR_BOOKE_SPRG8
] = sregs
.u
.e
.sprg8
;
1069 if (sregs
.u
.e
.features
& KVM_SREGS_E_IVOR
) {
1070 env
->spr
[SPR_BOOKE_IVOR0
] = sregs
.u
.e
.ivor_low
[0];
1071 kvm_sync_excp(env
, POWERPC_EXCP_CRITICAL
, SPR_BOOKE_IVOR0
);
1072 env
->spr
[SPR_BOOKE_IVOR1
] = sregs
.u
.e
.ivor_low
[1];
1073 kvm_sync_excp(env
, POWERPC_EXCP_MCHECK
, SPR_BOOKE_IVOR1
);
1074 env
->spr
[SPR_BOOKE_IVOR2
] = sregs
.u
.e
.ivor_low
[2];
1075 kvm_sync_excp(env
, POWERPC_EXCP_DSI
, SPR_BOOKE_IVOR2
);
1076 env
->spr
[SPR_BOOKE_IVOR3
] = sregs
.u
.e
.ivor_low
[3];
1077 kvm_sync_excp(env
, POWERPC_EXCP_ISI
, SPR_BOOKE_IVOR3
);
1078 env
->spr
[SPR_BOOKE_IVOR4
] = sregs
.u
.e
.ivor_low
[4];
1079 kvm_sync_excp(env
, POWERPC_EXCP_EXTERNAL
, SPR_BOOKE_IVOR4
);
1080 env
->spr
[SPR_BOOKE_IVOR5
] = sregs
.u
.e
.ivor_low
[5];
1081 kvm_sync_excp(env
, POWERPC_EXCP_ALIGN
, SPR_BOOKE_IVOR5
);
1082 env
->spr
[SPR_BOOKE_IVOR6
] = sregs
.u
.e
.ivor_low
[6];
1083 kvm_sync_excp(env
, POWERPC_EXCP_PROGRAM
, SPR_BOOKE_IVOR6
);
1084 env
->spr
[SPR_BOOKE_IVOR7
] = sregs
.u
.e
.ivor_low
[7];
1085 kvm_sync_excp(env
, POWERPC_EXCP_FPU
, SPR_BOOKE_IVOR7
);
1086 env
->spr
[SPR_BOOKE_IVOR8
] = sregs
.u
.e
.ivor_low
[8];
1087 kvm_sync_excp(env
, POWERPC_EXCP_SYSCALL
, SPR_BOOKE_IVOR8
);
1088 env
->spr
[SPR_BOOKE_IVOR9
] = sregs
.u
.e
.ivor_low
[9];
1089 kvm_sync_excp(env
, POWERPC_EXCP_APU
, SPR_BOOKE_IVOR9
);
1090 env
->spr
[SPR_BOOKE_IVOR10
] = sregs
.u
.e
.ivor_low
[10];
1091 kvm_sync_excp(env
, POWERPC_EXCP_DECR
, SPR_BOOKE_IVOR10
);
1092 env
->spr
[SPR_BOOKE_IVOR11
] = sregs
.u
.e
.ivor_low
[11];
1093 kvm_sync_excp(env
, POWERPC_EXCP_FIT
, SPR_BOOKE_IVOR11
);
1094 env
->spr
[SPR_BOOKE_IVOR12
] = sregs
.u
.e
.ivor_low
[12];
1095 kvm_sync_excp(env
, POWERPC_EXCP_WDT
, SPR_BOOKE_IVOR12
);
1096 env
->spr
[SPR_BOOKE_IVOR13
] = sregs
.u
.e
.ivor_low
[13];
1097 kvm_sync_excp(env
, POWERPC_EXCP_DTLB
, SPR_BOOKE_IVOR13
);
1098 env
->spr
[SPR_BOOKE_IVOR14
] = sregs
.u
.e
.ivor_low
[14];
1099 kvm_sync_excp(env
, POWERPC_EXCP_ITLB
, SPR_BOOKE_IVOR14
);
1100 env
->spr
[SPR_BOOKE_IVOR15
] = sregs
.u
.e
.ivor_low
[15];
1101 kvm_sync_excp(env
, POWERPC_EXCP_DEBUG
, SPR_BOOKE_IVOR15
);
1103 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPE
) {
1104 env
->spr
[SPR_BOOKE_IVOR32
] = sregs
.u
.e
.ivor_high
[0];
1105 kvm_sync_excp(env
, POWERPC_EXCP_SPEU
, SPR_BOOKE_IVOR32
);
1106 env
->spr
[SPR_BOOKE_IVOR33
] = sregs
.u
.e
.ivor_high
[1];
1107 kvm_sync_excp(env
, POWERPC_EXCP_EFPDI
, SPR_BOOKE_IVOR33
);
1108 env
->spr
[SPR_BOOKE_IVOR34
] = sregs
.u
.e
.ivor_high
[2];
1109 kvm_sync_excp(env
, POWERPC_EXCP_EFPRI
, SPR_BOOKE_IVOR34
);
1112 if (sregs
.u
.e
.features
& KVM_SREGS_E_PM
) {
1113 env
->spr
[SPR_BOOKE_IVOR35
] = sregs
.u
.e
.ivor_high
[3];
1114 kvm_sync_excp(env
, POWERPC_EXCP_EPERFM
, SPR_BOOKE_IVOR35
);
1117 if (sregs
.u
.e
.features
& KVM_SREGS_E_PC
) {
1118 env
->spr
[SPR_BOOKE_IVOR36
] = sregs
.u
.e
.ivor_high
[4];
1119 kvm_sync_excp(env
, POWERPC_EXCP_DOORI
, SPR_BOOKE_IVOR36
);
1120 env
->spr
[SPR_BOOKE_IVOR37
] = sregs
.u
.e
.ivor_high
[5];
1121 kvm_sync_excp(env
, POWERPC_EXCP_DOORCI
, SPR_BOOKE_IVOR37
);
1125 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206_MMU
) {
1126 env
->spr
[SPR_BOOKE_MAS0
] = sregs
.u
.e
.mas0
;
1127 env
->spr
[SPR_BOOKE_MAS1
] = sregs
.u
.e
.mas1
;
1128 env
->spr
[SPR_BOOKE_MAS2
] = sregs
.u
.e
.mas2
;
1129 env
->spr
[SPR_BOOKE_MAS3
] = sregs
.u
.e
.mas7_3
& 0xffffffff;
1130 env
->spr
[SPR_BOOKE_MAS4
] = sregs
.u
.e
.mas4
;
1131 env
->spr
[SPR_BOOKE_MAS6
] = sregs
.u
.e
.mas6
;
1132 env
->spr
[SPR_BOOKE_MAS7
] = sregs
.u
.e
.mas7_3
>> 32;
1133 env
->spr
[SPR_MMUCFG
] = sregs
.u
.e
.mmucfg
;
1134 env
->spr
[SPR_BOOKE_TLB0CFG
] = sregs
.u
.e
.tlbcfg
[0];
1135 env
->spr
[SPR_BOOKE_TLB1CFG
] = sregs
.u
.e
.tlbcfg
[1];
1138 if (sregs
.u
.e
.features
& KVM_SREGS_EXP
) {
1139 env
->spr
[SPR_BOOKE_EPR
] = sregs
.u
.e
.epr
;
1142 if (sregs
.u
.e
.features
& KVM_SREGS_E_PD
) {
1143 env
->spr
[SPR_BOOKE_EPLC
] = sregs
.u
.e
.eplc
;
1144 env
->spr
[SPR_BOOKE_EPSC
] = sregs
.u
.e
.epsc
;
1147 if (sregs
.u
.e
.impl_id
== KVM_SREGS_E_IMPL_FSL
) {
1148 env
->spr
[SPR_E500_SVR
] = sregs
.u
.e
.impl
.fsl
.svr
;
1149 env
->spr
[SPR_Exxx_MCAR
] = sregs
.u
.e
.impl
.fsl
.mcar
;
1150 env
->spr
[SPR_HID0
] = sregs
.u
.e
.impl
.fsl
.hid0
;
1152 if (sregs
.u
.e
.impl
.fsl
.features
& KVM_SREGS_E_FSL_PIDn
) {
1153 env
->spr
[SPR_BOOKE_PID1
] = sregs
.u
.e
.impl
.fsl
.pid1
;
1154 env
->spr
[SPR_BOOKE_PID2
] = sregs
.u
.e
.impl
.fsl
.pid2
;
1161 static int kvmppc_get_books_sregs(PowerPCCPU
*cpu
)
1163 CPUPPCState
*env
= &cpu
->env
;
1164 struct kvm_sregs sregs
;
1168 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1174 ppc_store_sdr1(env
, sregs
.u
.s
.sdr1
);
1180 * The packed SLB array we get from KVM_GET_SREGS only contains
1181 * information about valid entries. So we flush our internal copy
1182 * to get rid of stale ones, then put all valid SLB entries back
1185 memset(env
->slb
, 0, sizeof(env
->slb
));
1186 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
1187 target_ulong rb
= sregs
.u
.s
.ppc64
.slb
[i
].slbe
;
1188 target_ulong rs
= sregs
.u
.s
.ppc64
.slb
[i
].slbv
;
1190 * Only restore valid entries
1192 if (rb
& SLB_ESID_V
) {
1193 ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
);
1199 for (i
= 0; i
< 16; i
++) {
1200 env
->sr
[i
] = sregs
.u
.s
.ppc32
.sr
[i
];
1204 for (i
= 0; i
< 8; i
++) {
1205 env
->DBAT
[0][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] & 0xffffffff;
1206 env
->DBAT
[1][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] >> 32;
1207 env
->IBAT
[0][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] & 0xffffffff;
1208 env
->IBAT
[1][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] >> 32;
1214 int kvm_arch_get_registers(CPUState
*cs
)
1216 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1217 CPUPPCState
*env
= &cpu
->env
;
1218 struct kvm_regs regs
;
1222 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
1228 for (i
= 7; i
>= 0; i
--) {
1229 env
->crf
[i
] = cr
& 15;
1233 env
->ctr
= regs
.ctr
;
1235 cpu_write_xer(env
, regs
.xer
);
1236 env
->msr
= regs
.msr
;
1239 env
->spr
[SPR_SRR0
] = regs
.srr0
;
1240 env
->spr
[SPR_SRR1
] = regs
.srr1
;
1242 env
->spr
[SPR_SPRG0
] = regs
.sprg0
;
1243 env
->spr
[SPR_SPRG1
] = regs
.sprg1
;
1244 env
->spr
[SPR_SPRG2
] = regs
.sprg2
;
1245 env
->spr
[SPR_SPRG3
] = regs
.sprg3
;
1246 env
->spr
[SPR_SPRG4
] = regs
.sprg4
;
1247 env
->spr
[SPR_SPRG5
] = regs
.sprg5
;
1248 env
->spr
[SPR_SPRG6
] = regs
.sprg6
;
1249 env
->spr
[SPR_SPRG7
] = regs
.sprg7
;
1251 env
->spr
[SPR_BOOKE_PID
] = regs
.pid
;
1253 for (i
= 0; i
< 32; i
++) {
1254 env
->gpr
[i
] = regs
.gpr
[i
];
1259 if (cap_booke_sregs
) {
1260 ret
= kvmppc_get_booke_sregs(cpu
);
1267 ret
= kvmppc_get_books_sregs(cpu
);
1274 kvm_get_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
1281 * We deliberately ignore errors here, for kernels which have
1282 * the ONE_REG calls, but don't support the specific
1283 * registers, there's a reasonable chance things will still
1284 * work, at least until we try to migrate.
1286 for (i
= 0; i
< 1024; i
++) {
1287 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
1290 kvm_get_one_spr(cs
, id
, i
);
1296 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
1297 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
1299 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
1300 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
1302 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
1303 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
1304 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
1305 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
1306 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
1307 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
1308 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
1309 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
1310 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
1311 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
1315 if (kvm_get_vpa(cs
) < 0) {
1316 trace_kvm_failed_get_vpa();
1320 kvm_get_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
1327 int kvmppc_set_interrupt(PowerPCCPU
*cpu
, int irq
, int level
)
1329 unsigned virq
= level
? KVM_INTERRUPT_SET_LEVEL
: KVM_INTERRUPT_UNSET
;
1331 if (irq
!= PPC_INTERRUPT_EXT
) {
1335 if (!kvm_enabled() || !cap_interrupt_unset
|| !cap_interrupt_level
) {
1339 kvm_vcpu_ioctl(CPU(cpu
), KVM_INTERRUPT
, &virq
);
1344 #if defined(TARGET_PPC64)
1345 #define PPC_INPUT_INT PPC970_INPUT_INT
1347 #define PPC_INPUT_INT PPC6xx_INPUT_INT
1350 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
1352 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1353 CPUPPCState
*env
= &cpu
->env
;
1357 qemu_mutex_lock_iothread();
1360 * PowerPC QEMU tracks the various core input pins (interrupt,
1361 * critical interrupt, reset, etc) in PPC-specific
1362 * env->irq_input_state.
1364 if (!cap_interrupt_level
&&
1365 run
->ready_for_interrupt_injection
&&
1366 (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1367 (env
->irq_input_state
& (1 << PPC_INPUT_INT
)))
1370 * For now KVM disregards the 'irq' argument. However, in the
1371 * future KVM could cache it in-kernel to avoid a heavyweight
1372 * exit when reading the UIC.
1374 irq
= KVM_INTERRUPT_SET
;
1376 trace_kvm_injected_interrupt(irq
);
1377 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &irq
);
1379 printf("cpu %d fail inject %x\n", cs
->cpu_index
, irq
);
1382 /* Always wake up soon in case the interrupt was level based */
1383 timer_mod(idle_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1384 (NANOSECONDS_PER_SECOND
/ 50));
1388 * We don't know if there are more interrupts pending after
1389 * this. However, the guest will return to userspace in the course
1390 * of handling this one anyways, so we will get a chance to
1394 qemu_mutex_unlock_iothread();
1397 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
1399 return MEMTXATTRS_UNSPECIFIED
;
1402 int kvm_arch_process_async_events(CPUState
*cs
)
1407 static int kvmppc_handle_halt(PowerPCCPU
*cpu
)
1409 CPUState
*cs
= CPU(cpu
);
1410 CPUPPCState
*env
= &cpu
->env
;
1412 if (!(cs
->interrupt_request
& CPU_INTERRUPT_HARD
) && (msr_ee
)) {
1414 cs
->exception_index
= EXCP_HLT
;
1420 /* map dcr access to existing qemu dcr emulation */
1421 static int kvmppc_handle_dcr_read(CPUPPCState
*env
,
1422 uint32_t dcrn
, uint32_t *data
)
1424 if (ppc_dcr_read(env
->dcr_env
, dcrn
, data
) < 0) {
1425 fprintf(stderr
, "Read to unhandled DCR (0x%x)\n", dcrn
);
1431 static int kvmppc_handle_dcr_write(CPUPPCState
*env
,
1432 uint32_t dcrn
, uint32_t data
)
1434 if (ppc_dcr_write(env
->dcr_env
, dcrn
, data
) < 0) {
1435 fprintf(stderr
, "Write to unhandled DCR (0x%x)\n", dcrn
);
1441 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1443 /* Mixed endian case is not handled */
1444 uint32_t sc
= debug_inst_opcode
;
1446 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1448 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 1)) {
1455 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1459 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 0) ||
1460 sc
!= debug_inst_opcode
||
1461 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1469 static int find_hw_breakpoint(target_ulong addr
, int type
)
1473 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1474 <= ARRAY_SIZE(hw_debug_points
));
1476 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1477 if (hw_debug_points
[n
].addr
== addr
&&
1478 hw_debug_points
[n
].type
== type
) {
1486 static int find_hw_watchpoint(target_ulong addr
, int *flag
)
1490 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_ACCESS
);
1492 *flag
= BP_MEM_ACCESS
;
1496 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_WRITE
);
1498 *flag
= BP_MEM_WRITE
;
1502 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_READ
);
1504 *flag
= BP_MEM_READ
;
1511 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1512 target_ulong len
, int type
)
1514 if ((nb_hw_breakpoint
+ nb_hw_watchpoint
) >= ARRAY_SIZE(hw_debug_points
)) {
1518 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].addr
= addr
;
1519 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].type
= type
;
1522 case GDB_BREAKPOINT_HW
:
1523 if (nb_hw_breakpoint
>= max_hw_breakpoint
) {
1527 if (find_hw_breakpoint(addr
, type
) >= 0) {
1534 case GDB_WATCHPOINT_WRITE
:
1535 case GDB_WATCHPOINT_READ
:
1536 case GDB_WATCHPOINT_ACCESS
:
1537 if (nb_hw_watchpoint
>= max_hw_watchpoint
) {
1541 if (find_hw_breakpoint(addr
, type
) >= 0) {
1555 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1556 target_ulong len
, int type
)
1560 n
= find_hw_breakpoint(addr
, type
);
1566 case GDB_BREAKPOINT_HW
:
1570 case GDB_WATCHPOINT_WRITE
:
1571 case GDB_WATCHPOINT_READ
:
1572 case GDB_WATCHPOINT_ACCESS
:
1579 hw_debug_points
[n
] = hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
];
1584 void kvm_arch_remove_all_hw_breakpoints(void)
1586 nb_hw_breakpoint
= nb_hw_watchpoint
= 0;
1589 void kvm_arch_update_guest_debug(CPUState
*cs
, struct kvm_guest_debug
*dbg
)
1593 /* Software Breakpoint updates */
1594 if (kvm_sw_breakpoints_active(cs
)) {
1595 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1598 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1599 <= ARRAY_SIZE(hw_debug_points
));
1600 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
) <= ARRAY_SIZE(dbg
->arch
.bp
));
1602 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1603 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1604 memset(dbg
->arch
.bp
, 0, sizeof(dbg
->arch
.bp
));
1605 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1606 switch (hw_debug_points
[n
].type
) {
1607 case GDB_BREAKPOINT_HW
:
1608 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_BREAKPOINT
;
1610 case GDB_WATCHPOINT_WRITE
:
1611 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
;
1613 case GDB_WATCHPOINT_READ
:
1614 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_READ
;
1616 case GDB_WATCHPOINT_ACCESS
:
1617 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
|
1618 KVMPPC_DEBUG_WATCH_READ
;
1621 cpu_abort(cs
, "Unsupported breakpoint type\n");
1623 dbg
->arch
.bp
[n
].addr
= hw_debug_points
[n
].addr
;
1628 static int kvm_handle_hw_breakpoint(CPUState
*cs
,
1629 struct kvm_debug_exit_arch
*arch_info
)
1635 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1636 if (arch_info
->status
& KVMPPC_DEBUG_BREAKPOINT
) {
1637 n
= find_hw_breakpoint(arch_info
->address
, GDB_BREAKPOINT_HW
);
1641 } else if (arch_info
->status
& (KVMPPC_DEBUG_WATCH_READ
|
1642 KVMPPC_DEBUG_WATCH_WRITE
)) {
1643 n
= find_hw_watchpoint(arch_info
->address
, &flag
);
1646 cs
->watchpoint_hit
= &hw_watchpoint
;
1647 hw_watchpoint
.vaddr
= hw_debug_points
[n
].addr
;
1648 hw_watchpoint
.flags
= flag
;
1655 static int kvm_handle_singlestep(void)
1660 static int kvm_handle_sw_breakpoint(void)
1665 static int kvm_handle_debug(PowerPCCPU
*cpu
, struct kvm_run
*run
)
1667 CPUState
*cs
= CPU(cpu
);
1668 CPUPPCState
*env
= &cpu
->env
;
1669 struct kvm_debug_exit_arch
*arch_info
= &run
->debug
.arch
;
1671 if (cs
->singlestep_enabled
) {
1672 return kvm_handle_singlestep();
1675 if (arch_info
->status
) {
1676 return kvm_handle_hw_breakpoint(cs
, arch_info
);
1679 if (kvm_find_sw_breakpoint(cs
, arch_info
->address
)) {
1680 return kvm_handle_sw_breakpoint();
1684 * QEMU is not able to handle debug exception, so inject
1685 * program exception to guest;
1686 * Yes program exception NOT debug exception !!
1687 * When QEMU is using debug resources then debug exception must
1688 * be always set. To achieve this we set MSR_DE and also set
1689 * MSRP_DEP so guest cannot change MSR_DE.
1690 * When emulating debug resource for guest we want guest
1691 * to control MSR_DE (enable/disable debug interrupt on need).
1692 * Supporting both configurations are NOT possible.
1693 * So the result is that we cannot share debug resources
1694 * between QEMU and Guest on BOOKE architecture.
1695 * In the current design QEMU gets the priority over guest,
1696 * this means that if QEMU is using debug resources then guest
1698 * For software breakpoint QEMU uses a privileged instruction;
1699 * So there cannot be any reason that we are here for guest
1700 * set debug exception, only possibility is guest executed a
1701 * privileged / illegal instruction and that's why we are
1702 * injecting a program interrupt.
1704 cpu_synchronize_state(cs
);
1706 * env->nip is PC, so increment this by 4 to use
1707 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1710 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
1711 env
->error_code
= POWERPC_EXCP_INVAL
;
1712 ppc_cpu_do_interrupt(cs
);
1717 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
1719 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1720 CPUPPCState
*env
= &cpu
->env
;
1723 qemu_mutex_lock_iothread();
1725 switch (run
->exit_reason
) {
1727 if (run
->dcr
.is_write
) {
1728 trace_kvm_handle_dcr_write();
1729 ret
= kvmppc_handle_dcr_write(env
, run
->dcr
.dcrn
, run
->dcr
.data
);
1731 trace_kvm_handle_dcr_read();
1732 ret
= kvmppc_handle_dcr_read(env
, run
->dcr
.dcrn
, &run
->dcr
.data
);
1736 trace_kvm_handle_halt();
1737 ret
= kvmppc_handle_halt(cpu
);
1739 #if defined(TARGET_PPC64)
1740 case KVM_EXIT_PAPR_HCALL
:
1741 trace_kvm_handle_papr_hcall();
1742 run
->papr_hcall
.ret
= spapr_hypercall(cpu
,
1744 run
->papr_hcall
.args
);
1749 trace_kvm_handle_epr();
1750 run
->epr
.epr
= ldl_phys(cs
->as
, env
->mpic_iack
);
1753 case KVM_EXIT_WATCHDOG
:
1754 trace_kvm_handle_watchdog_expiry();
1755 watchdog_perform_action();
1759 case KVM_EXIT_DEBUG
:
1760 trace_kvm_handle_debug_exception();
1761 if (kvm_handle_debug(cpu
, run
)) {
1765 /* re-enter, this exception was guest-internal */
1770 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
1775 qemu_mutex_unlock_iothread();
1779 int kvmppc_or_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1781 CPUState
*cs
= CPU(cpu
);
1782 uint32_t bits
= tsr_bits
;
1783 struct kvm_one_reg reg
= {
1784 .id
= KVM_REG_PPC_OR_TSR
,
1785 .addr
= (uintptr_t) &bits
,
1788 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1791 int kvmppc_clear_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1794 CPUState
*cs
= CPU(cpu
);
1795 uint32_t bits
= tsr_bits
;
1796 struct kvm_one_reg reg
= {
1797 .id
= KVM_REG_PPC_CLEAR_TSR
,
1798 .addr
= (uintptr_t) &bits
,
1801 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1804 int kvmppc_set_tcr(PowerPCCPU
*cpu
)
1806 CPUState
*cs
= CPU(cpu
);
1807 CPUPPCState
*env
= &cpu
->env
;
1808 uint32_t tcr
= env
->spr
[SPR_BOOKE_TCR
];
1810 struct kvm_one_reg reg
= {
1811 .id
= KVM_REG_PPC_TCR
,
1812 .addr
= (uintptr_t) &tcr
,
1815 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1818 int kvmppc_booke_watchdog_enable(PowerPCCPU
*cpu
)
1820 CPUState
*cs
= CPU(cpu
);
1823 if (!kvm_enabled()) {
1827 if (!cap_ppc_watchdog
) {
1828 printf("warning: KVM does not support watchdog");
1832 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_BOOKE_WATCHDOG
, 0);
1834 fprintf(stderr
, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1835 __func__
, strerror(-ret
));
1842 static int read_cpuinfo(const char *field
, char *value
, int len
)
1846 int field_len
= strlen(field
);
1849 f
= fopen("/proc/cpuinfo", "r");
1855 if (!fgets(line
, sizeof(line
), f
)) {
1858 if (!strncmp(line
, field
, field_len
)) {
1859 pstrcpy(value
, len
, line
);
1870 uint32_t kvmppc_get_tbfreq(void)
1874 uint32_t retval
= NANOSECONDS_PER_SECOND
;
1876 if (read_cpuinfo("timebase", line
, sizeof(line
))) {
1880 ns
= strchr(line
, ':');
1890 bool kvmppc_get_host_serial(char **value
)
1892 return g_file_get_contents("/proc/device-tree/system-id", value
, NULL
,
1896 bool kvmppc_get_host_model(char **value
)
1898 return g_file_get_contents("/proc/device-tree/model", value
, NULL
, NULL
);
1901 /* Try to find a device tree node for a CPU with clock-frequency property */
1902 static int kvmppc_find_cpu_dt(char *buf
, int buf_len
)
1904 struct dirent
*dirp
;
1907 dp
= opendir(PROC_DEVTREE_CPU
);
1909 printf("Can't open directory " PROC_DEVTREE_CPU
"\n");
1914 while ((dirp
= readdir(dp
)) != NULL
) {
1916 snprintf(buf
, buf_len
, "%s%s/clock-frequency", PROC_DEVTREE_CPU
,
1918 f
= fopen(buf
, "r");
1920 snprintf(buf
, buf_len
, "%s%s", PROC_DEVTREE_CPU
, dirp
->d_name
);
1927 if (buf
[0] == '\0') {
1928 printf("Unknown host!\n");
1935 static uint64_t kvmppc_read_int_dt(const char *filename
)
1944 f
= fopen(filename
, "rb");
1949 len
= fread(&u
, 1, sizeof(u
), f
);
1953 /* property is a 32-bit quantity */
1954 return be32_to_cpu(u
.v32
);
1956 return be64_to_cpu(u
.v64
);
1963 * Read a CPU node property from the host device tree that's a single
1964 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1965 * (can't find or open the property, or doesn't understand the format)
1967 static uint64_t kvmppc_read_int_cpu_dt(const char *propname
)
1969 char buf
[PATH_MAX
], *tmp
;
1972 if (kvmppc_find_cpu_dt(buf
, sizeof(buf
))) {
1976 tmp
= g_strdup_printf("%s/%s", buf
, propname
);
1977 val
= kvmppc_read_int_dt(tmp
);
1983 uint64_t kvmppc_get_clockfreq(void)
1985 return kvmppc_read_int_cpu_dt("clock-frequency");
1988 static int kvmppc_get_dec_bits(void)
1990 int nr_bits
= kvmppc_read_int_cpu_dt("ibm,dec-bits");
1998 static int kvmppc_get_pvinfo(CPUPPCState
*env
, struct kvm_ppc_pvinfo
*pvinfo
)
2000 CPUState
*cs
= env_cpu(env
);
2002 if (kvm_vm_check_extension(cs
->kvm_state
, KVM_CAP_PPC_GET_PVINFO
) &&
2003 !kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_GET_PVINFO
, pvinfo
)) {
2010 int kvmppc_get_hasidle(CPUPPCState
*env
)
2012 struct kvm_ppc_pvinfo pvinfo
;
2014 if (!kvmppc_get_pvinfo(env
, &pvinfo
) &&
2015 (pvinfo
.flags
& KVM_PPC_PVINFO_FLAGS_EV_IDLE
)) {
2022 int kvmppc_get_hypercall(CPUPPCState
*env
, uint8_t *buf
, int buf_len
)
2024 uint32_t *hc
= (uint32_t *)buf
;
2025 struct kvm_ppc_pvinfo pvinfo
;
2027 if (!kvmppc_get_pvinfo(env
, &pvinfo
)) {
2028 memcpy(buf
, pvinfo
.hcall
, buf_len
);
2033 * Fallback to always fail hypercalls regardless of endianness:
2035 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2037 * b .+8 (becomes nop in wrong endian)
2038 * bswap32(li r3, -1)
2041 hc
[0] = cpu_to_be32(0x08000048);
2042 hc
[1] = cpu_to_be32(0x3860ffff);
2043 hc
[2] = cpu_to_be32(0x48000008);
2044 hc
[3] = cpu_to_be32(bswap32(0x3860ffff));
2049 static inline int kvmppc_enable_hcall(KVMState
*s
, target_ulong hcall
)
2051 return kvm_vm_enable_cap(s
, KVM_CAP_PPC_ENABLE_HCALL
, 0, hcall
, 1);
2054 void kvmppc_enable_logical_ci_hcalls(void)
2057 * FIXME: it would be nice if we could detect the cases where
2058 * we're using a device which requires the in kernel
2059 * implementation of these hcalls, but the kernel lacks them and
2060 * produce a warning.
2062 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_LOAD
);
2063 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_STORE
);
2066 void kvmppc_enable_set_mode_hcall(void)
2068 kvmppc_enable_hcall(kvm_state
, H_SET_MODE
);
2071 void kvmppc_enable_clear_ref_mod_hcalls(void)
2073 kvmppc_enable_hcall(kvm_state
, H_CLEAR_REF
);
2074 kvmppc_enable_hcall(kvm_state
, H_CLEAR_MOD
);
2077 void kvmppc_enable_h_page_init(void)
2079 kvmppc_enable_hcall(kvm_state
, H_PAGE_INIT
);
2082 void kvmppc_set_papr(PowerPCCPU
*cpu
)
2084 CPUState
*cs
= CPU(cpu
);
2087 if (!kvm_enabled()) {
2091 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_PAPR
, 0);
2093 error_report("This vCPU type or KVM version does not support PAPR");
2098 * Update the capability flag so we sync the right information
2104 int kvmppc_set_compat(PowerPCCPU
*cpu
, uint32_t compat_pvr
)
2106 return kvm_set_one_reg(CPU(cpu
), KVM_REG_PPC_ARCH_COMPAT
, &compat_pvr
);
2109 void kvmppc_set_mpic_proxy(PowerPCCPU
*cpu
, int mpic_proxy
)
2111 CPUState
*cs
= CPU(cpu
);
2114 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_EPR
, 0, mpic_proxy
);
2115 if (ret
&& mpic_proxy
) {
2116 error_report("This KVM version does not support EPR");
2121 int kvmppc_smt_threads(void)
2123 return cap_ppc_smt
? cap_ppc_smt
: 1;
2126 int kvmppc_set_smt_threads(int smt
)
2130 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_SMT
, 0, smt
, 0);
2137 void kvmppc_hint_smt_possible(Error
**errp
)
2143 assert(kvm_enabled());
2144 if (cap_ppc_smt_possible
) {
2145 g
= g_string_new("Available VSMT modes:");
2146 for (i
= 63; i
>= 0; i
--) {
2147 if ((1UL << i
) & cap_ppc_smt_possible
) {
2148 g_string_append_printf(g
, " %lu", (1UL << i
));
2151 s
= g_string_free(g
, false);
2152 error_append_hint(errp
, "%s.\n", s
);
2155 error_append_hint(errp
,
2156 "This KVM seems to be too old to support VSMT.\n");
2162 uint64_t kvmppc_rma_size(uint64_t current_size
, unsigned int hash_shift
)
2164 struct kvm_ppc_smmu_info info
;
2165 long rampagesize
, best_page_shift
;
2169 * Find the largest hardware supported page size that's less than
2170 * or equal to the (logical) backing page size of guest RAM
2172 kvm_get_smmu_info(&info
, &error_fatal
);
2173 rampagesize
= qemu_minrampagesize();
2174 best_page_shift
= 0;
2176 for (i
= 0; i
< KVM_PPC_PAGE_SIZES_MAX_SZ
; i
++) {
2177 struct kvm_ppc_one_seg_page_size
*sps
= &info
.sps
[i
];
2179 if (!sps
->page_shift
) {
2183 if ((sps
->page_shift
> best_page_shift
)
2184 && ((1UL << sps
->page_shift
) <= rampagesize
)) {
2185 best_page_shift
= sps
->page_shift
;
2189 return MIN(current_size
,
2190 1ULL << (best_page_shift
+ hash_shift
- 7));
2194 bool kvmppc_spapr_use_multitce(void)
2196 return cap_spapr_multitce
;
2199 int kvmppc_spapr_enable_inkernel_multitce(void)
2203 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2204 H_PUT_TCE_INDIRECT
, 1);
2206 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2213 void *kvmppc_create_spapr_tce(uint32_t liobn
, uint32_t page_shift
,
2214 uint64_t bus_offset
, uint32_t nb_table
,
2215 int *pfd
, bool need_vfio
)
2222 * Must set fd to -1 so we don't try to munmap when called for
2223 * destroying the table, which the upper layers -will- do
2226 if (!cap_spapr_tce
|| (need_vfio
&& !cap_spapr_vfio
)) {
2230 if (cap_spapr_tce_64
) {
2231 struct kvm_create_spapr_tce_64 args
= {
2233 .page_shift
= page_shift
,
2234 .offset
= bus_offset
>> page_shift
,
2238 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE_64
, &args
);
2241 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2245 } else if (cap_spapr_tce
) {
2246 uint64_t window_size
= (uint64_t) nb_table
<< page_shift
;
2247 struct kvm_create_spapr_tce args
= {
2249 .window_size
= window_size
,
2251 if ((window_size
!= args
.window_size
) || bus_offset
) {
2254 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE
, &args
);
2256 fprintf(stderr
, "KVM: Failed to create TCE table for liobn 0x%x\n",
2264 len
= nb_table
* sizeof(uint64_t);
2265 /* FIXME: round this up to page size */
2267 table
= mmap(NULL
, len
, PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, 0);
2268 if (table
== MAP_FAILED
) {
2269 fprintf(stderr
, "KVM: Failed to map TCE table for liobn 0x%x\n",
2279 int kvmppc_remove_spapr_tce(void *table
, int fd
, uint32_t nb_table
)
2287 len
= nb_table
* sizeof(uint64_t);
2288 if ((munmap(table
, len
) < 0) ||
2290 fprintf(stderr
, "KVM: Unexpected error removing TCE table: %s",
2292 /* Leak the table */
2298 int kvmppc_reset_htab(int shift_hint
)
2300 uint32_t shift
= shift_hint
;
2302 if (!kvm_enabled()) {
2303 /* Full emulation, tell caller to allocate htab itself */
2306 if (kvm_vm_check_extension(kvm_state
, KVM_CAP_PPC_ALLOC_HTAB
)) {
2308 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_ALLOCATE_HTAB
, &shift
);
2309 if (ret
== -ENOTTY
) {
2311 * At least some versions of PR KVM advertise the
2312 * capability, but don't implement the ioctl(). Oops.
2313 * Return 0 so that we allocate the htab in qemu, as is
2317 } else if (ret
< 0) {
2324 * We have a kernel that predates the htab reset calls. For PR
2325 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2326 * this era, it has allocated a 16MB fixed size hash table
2329 if (kvmppc_is_pr(kvm_state
)) {
2330 /* PR - tell caller to allocate htab */
2333 /* HV - assume 16MB kernel allocated htab */
2338 static inline uint32_t mfpvr(void)
2347 static void alter_insns(uint64_t *word
, uint64_t flags
, bool on
)
2356 static void kvmppc_host_cpu_class_init(ObjectClass
*oc
, void *data
)
2358 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2359 uint32_t dcache_size
= kvmppc_read_int_cpu_dt("d-cache-size");
2360 uint32_t icache_size
= kvmppc_read_int_cpu_dt("i-cache-size");
2362 /* Now fix up the class with information we can query from the host */
2365 alter_insns(&pcc
->insns_flags
, PPC_ALTIVEC
,
2366 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_ALTIVEC
);
2367 alter_insns(&pcc
->insns_flags2
, PPC2_VSX
,
2368 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_VSX
);
2369 alter_insns(&pcc
->insns_flags2
, PPC2_DFP
,
2370 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_DFP
);
2372 if (dcache_size
!= -1) {
2373 pcc
->l1_dcache_size
= dcache_size
;
2376 if (icache_size
!= -1) {
2377 pcc
->l1_icache_size
= icache_size
;
2380 #if defined(TARGET_PPC64)
2381 pcc
->radix_page_info
= kvm_get_radix_page_info();
2383 if ((pcc
->pvr
& 0xffffff00) == CPU_POWERPC_POWER9_DD1
) {
2385 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2386 * compliant. More importantly, advertising ISA 3.00
2387 * architected mode may prevent guests from activating
2388 * necessary DD1 workarounds.
2390 pcc
->pcr_supported
&= ~(PCR_COMPAT_3_00
| PCR_COMPAT_2_07
2391 | PCR_COMPAT_2_06
| PCR_COMPAT_2_05
);
2393 #endif /* defined(TARGET_PPC64) */
2396 bool kvmppc_has_cap_epr(void)
2401 bool kvmppc_has_cap_fixup_hcalls(void)
2403 return cap_fixup_hcalls
;
2406 bool kvmppc_has_cap_htm(void)
2411 bool kvmppc_has_cap_mmu_radix(void)
2413 return cap_mmu_radix
;
2416 bool kvmppc_has_cap_mmu_hash_v3(void)
2418 return cap_mmu_hash_v3
;
2421 static bool kvmppc_power8_host(void)
2426 uint32_t base_pvr
= CPU_POWERPC_POWER_SERVER_MASK
& mfpvr();
2427 ret
= (base_pvr
== CPU_POWERPC_POWER8E_BASE
) ||
2428 (base_pvr
== CPU_POWERPC_POWER8NVL_BASE
) ||
2429 (base_pvr
== CPU_POWERPC_POWER8_BASE
);
2431 #endif /* TARGET_PPC64 */
2435 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c
)
2437 bool l1d_thread_priv_req
= !kvmppc_power8_host();
2439 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_L1D_FLUSH_PR
) {
2441 } else if ((!l1d_thread_priv_req
||
2442 c
.character
& c
.character_mask
& H_CPU_CHAR_L1D_THREAD_PRIV
) &&
2443 (c
.character
& c
.character_mask
2444 & (H_CPU_CHAR_L1D_FLUSH_ORI30
| H_CPU_CHAR_L1D_FLUSH_TRIG2
))) {
2451 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c
)
2453 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_BNDS_CHK_SPEC_BAR
) {
2455 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_SPEC_BAR_ORI31
) {
2462 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c
)
2464 if ((~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) &&
2465 (~c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) &&
2466 (~c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
)) {
2467 return SPAPR_CAP_FIXED_NA
;
2468 } else if (c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) {
2469 return SPAPR_CAP_WORKAROUND
;
2470 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) {
2471 return SPAPR_CAP_FIXED_CCD
;
2472 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
) {
2473 return SPAPR_CAP_FIXED_IBS
;
2479 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c
)
2481 if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTR_FLUSH_ASSIST
) {
2487 bool kvmppc_has_cap_xive(void)
2492 static void kvmppc_get_cpu_characteristics(KVMState
*s
)
2494 struct kvm_ppc_cpu_char c
;
2498 cap_ppc_safe_cache
= 0;
2499 cap_ppc_safe_bounds_check
= 0;
2500 cap_ppc_safe_indirect_branch
= 0;
2502 ret
= kvm_vm_check_extension(s
, KVM_CAP_PPC_GET_CPU_CHAR
);
2506 ret
= kvm_vm_ioctl(s
, KVM_PPC_GET_CPU_CHAR
, &c
);
2511 cap_ppc_safe_cache
= parse_cap_ppc_safe_cache(c
);
2512 cap_ppc_safe_bounds_check
= parse_cap_ppc_safe_bounds_check(c
);
2513 cap_ppc_safe_indirect_branch
= parse_cap_ppc_safe_indirect_branch(c
);
2514 cap_ppc_count_cache_flush_assist
=
2515 parse_cap_ppc_count_cache_flush_assist(c
);
2518 int kvmppc_get_cap_safe_cache(void)
2520 return cap_ppc_safe_cache
;
2523 int kvmppc_get_cap_safe_bounds_check(void)
2525 return cap_ppc_safe_bounds_check
;
2528 int kvmppc_get_cap_safe_indirect_branch(void)
2530 return cap_ppc_safe_indirect_branch
;
2533 int kvmppc_get_cap_count_cache_flush_assist(void)
2535 return cap_ppc_count_cache_flush_assist
;
2538 bool kvmppc_has_cap_nested_kvm_hv(void)
2540 return !!cap_ppc_nested_kvm_hv
;
2543 int kvmppc_set_cap_nested_kvm_hv(int enable
)
2545 return kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_NESTED_HV
, 0, enable
);
2548 bool kvmppc_has_cap_spapr_vfio(void)
2550 return cap_spapr_vfio
;
2553 int kvmppc_get_cap_large_decr(void)
2555 return cap_large_decr
;
2558 int kvmppc_enable_cap_large_decr(PowerPCCPU
*cpu
, int enable
)
2560 CPUState
*cs
= CPU(cpu
);
2563 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2564 /* Do we need to modify the LPCR? */
2565 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2571 kvm_set_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2572 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2574 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2582 PowerPCCPUClass
*kvm_ppc_get_host_cpu_class(void)
2584 uint32_t host_pvr
= mfpvr();
2585 PowerPCCPUClass
*pvr_pcc
;
2587 pvr_pcc
= ppc_cpu_class_by_pvr(host_pvr
);
2588 if (pvr_pcc
== NULL
) {
2589 pvr_pcc
= ppc_cpu_class_by_pvr_mask(host_pvr
);
2595 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
)
2597 TypeInfo type_info
= {
2598 .name
= TYPE_HOST_POWERPC_CPU
,
2599 .class_init
= kvmppc_host_cpu_class_init
,
2601 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2602 PowerPCCPUClass
*pvr_pcc
;
2607 pvr_pcc
= kvm_ppc_get_host_cpu_class();
2608 if (pvr_pcc
== NULL
) {
2611 type_info
.parent
= object_class_get_name(OBJECT_CLASS(pvr_pcc
));
2612 type_register(&type_info
);
2613 if (object_dynamic_cast(OBJECT(ms
), TYPE_SPAPR_MACHINE
)) {
2614 /* override TCG default cpu type with 'host' cpu model */
2615 mc
->default_cpu_type
= TYPE_HOST_POWERPC_CPU
;
2618 oc
= object_class_by_name(type_info
.name
);
2622 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2623 * we want "POWER8" to be a "family" alias that points to the current
2624 * host CPU type, too)
2626 dc
= DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc
));
2627 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
2628 if (strcasecmp(ppc_cpu_aliases
[i
].alias
, dc
->desc
) == 0) {
2631 ppc_cpu_aliases
[i
].model
= g_strdup(object_class_get_name(oc
));
2632 suffix
= strstr(ppc_cpu_aliases
[i
].model
, POWERPC_CPU_TYPE_SUFFIX
);
2643 int kvmppc_define_rtas_kernel_token(uint32_t token
, const char *function
)
2645 struct kvm_rtas_token_args args
= {
2649 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_RTAS
)) {
2653 strncpy(args
.name
, function
, sizeof(args
.name
) - 1);
2655 return kvm_vm_ioctl(kvm_state
, KVM_PPC_RTAS_DEFINE_TOKEN
, &args
);
2658 int kvmppc_get_htab_fd(bool write
, uint64_t index
, Error
**errp
)
2660 struct kvm_get_htab_fd s
= {
2661 .flags
= write
? KVM_GET_HTAB_WRITE
: 0,
2662 .start_index
= index
,
2667 error_setg(errp
, "KVM version doesn't support %s the HPT",
2668 write
? "writing" : "reading");
2672 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_HTAB_FD
, &s
);
2674 error_setg(errp
, "Unable to open fd for %s HPT %s KVM: %s",
2675 write
? "writing" : "reading", write
? "to" : "from",
2683 int kvmppc_save_htab(QEMUFile
*f
, int fd
, size_t bufsize
, int64_t max_ns
)
2685 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2686 uint8_t buf
[bufsize
];
2690 rc
= read(fd
, buf
, bufsize
);
2692 fprintf(stderr
, "Error reading data from KVM HTAB fd: %s\n",
2696 uint8_t *buffer
= buf
;
2699 struct kvm_get_htab_header
*head
=
2700 (struct kvm_get_htab_header
*) buffer
;
2701 size_t chunksize
= sizeof(*head
) +
2702 HASH_PTE_SIZE_64
* head
->n_valid
;
2704 qemu_put_be32(f
, head
->index
);
2705 qemu_put_be16(f
, head
->n_valid
);
2706 qemu_put_be16(f
, head
->n_invalid
);
2707 qemu_put_buffer(f
, (void *)(head
+ 1),
2708 HASH_PTE_SIZE_64
* head
->n_valid
);
2710 buffer
+= chunksize
;
2716 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) < max_ns
)));
2718 return (rc
== 0) ? 1 : 0;
2721 int kvmppc_load_htab_chunk(QEMUFile
*f
, int fd
, uint32_t index
,
2722 uint16_t n_valid
, uint16_t n_invalid
)
2724 struct kvm_get_htab_header
*buf
;
2725 size_t chunksize
= sizeof(*buf
) + n_valid
* HASH_PTE_SIZE_64
;
2728 buf
= alloca(chunksize
);
2730 buf
->n_valid
= n_valid
;
2731 buf
->n_invalid
= n_invalid
;
2733 qemu_get_buffer(f
, (void *)(buf
+ 1), HASH_PTE_SIZE_64
* n_valid
);
2735 rc
= write(fd
, buf
, chunksize
);
2737 fprintf(stderr
, "Error writing KVM hash table: %s\n",
2741 if (rc
!= chunksize
) {
2742 /* We should never get a short write on a single chunk */
2743 fprintf(stderr
, "Short write, restoring KVM hash table\n");
2749 bool kvm_arch_stop_on_emulation_error(CPUState
*cpu
)
2754 void kvm_arch_init_irq_routing(KVMState
*s
)
2758 void kvmppc_read_hptes(ppc_hash_pte64_t
*hptes
, hwaddr ptex
, int n
)
2763 fd
= kvmppc_get_htab_fd(false, ptex
, &error_abort
);
2767 struct kvm_get_htab_header
*hdr
;
2768 int m
= n
< HPTES_PER_GROUP
? n
: HPTES_PER_GROUP
;
2769 char buf
[sizeof(*hdr
) + m
* HASH_PTE_SIZE_64
];
2771 rc
= read(fd
, buf
, sizeof(buf
));
2773 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2776 hdr
= (struct kvm_get_htab_header
*)buf
;
2777 while ((i
< n
) && ((char *)hdr
< (buf
+ rc
))) {
2778 int invalid
= hdr
->n_invalid
, valid
= hdr
->n_valid
;
2780 if (hdr
->index
!= (ptex
+ i
)) {
2781 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2782 " != (%"HWADDR_PRIu
" + %d", hdr
->index
, ptex
, i
);
2785 if (n
- i
< valid
) {
2788 memcpy(hptes
+ i
, hdr
+ 1, HASH_PTE_SIZE_64
* valid
);
2791 if ((n
- i
) < invalid
) {
2794 memset(hptes
+ i
, 0, invalid
* HASH_PTE_SIZE_64
);
2797 hdr
= (struct kvm_get_htab_header
*)
2798 ((char *)(hdr
+ 1) + HASH_PTE_SIZE_64
* hdr
->n_valid
);
2805 void kvmppc_write_hpte(hwaddr ptex
, uint64_t pte0
, uint64_t pte1
)
2809 struct kvm_get_htab_header hdr
;
2814 fd
= kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort
);
2816 buf
.hdr
.n_valid
= 1;
2817 buf
.hdr
.n_invalid
= 0;
2818 buf
.hdr
.index
= ptex
;
2819 buf
.pte0
= cpu_to_be64(pte0
);
2820 buf
.pte1
= cpu_to_be64(pte1
);
2822 rc
= write(fd
, &buf
, sizeof(buf
));
2823 if (rc
!= sizeof(buf
)) {
2824 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2829 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
2830 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
2835 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
2836 int vector
, PCIDevice
*dev
)
2841 int kvm_arch_release_virq_post(int virq
)
2846 int kvm_arch_msi_data_to_gsi(uint32_t data
)
2848 return data
& 0xffff;
2851 int kvmppc_enable_hwrng(void)
2853 if (!kvm_enabled() || !kvm_check_extension(kvm_state
, KVM_CAP_PPC_HWRNG
)) {
2857 return kvmppc_enable_hcall(kvm_state
, H_RANDOM
);
2860 void kvmppc_check_papr_resize_hpt(Error
**errp
)
2862 if (!kvm_enabled()) {
2863 return; /* No KVM, we're good */
2866 if (cap_resize_hpt
) {
2867 return; /* Kernel has explicit support, we're good */
2870 /* Otherwise fallback on looking for PR KVM */
2871 if (kvmppc_is_pr(kvm_state
)) {
2876 "Hash page table resizing not available with this KVM version");
2879 int kvmppc_resize_hpt_prepare(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2881 CPUState
*cs
= CPU(cpu
);
2882 struct kvm_ppc_resize_hpt rhpt
= {
2887 if (!cap_resize_hpt
) {
2891 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_PREPARE
, &rhpt
);
2894 int kvmppc_resize_hpt_commit(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2896 CPUState
*cs
= CPU(cpu
);
2897 struct kvm_ppc_resize_hpt rhpt
= {
2902 if (!cap_resize_hpt
) {
2906 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_COMMIT
, &rhpt
);
2910 * This is a helper function to detect a post migration scenario
2911 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2912 * the guest kernel can't handle a PVR value other than the actual host
2913 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2915 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2916 * (so, we're HV), return true. The workaround itself is done in
2919 * The order here is important: we'll only check for KVM PR as a
2920 * fallback if the guest kernel can't handle the situation itself.
2921 * We need to avoid as much as possible querying the running KVM type
2924 bool kvmppc_pvr_workaround_required(PowerPCCPU
*cpu
)
2926 CPUState
*cs
= CPU(cpu
);
2928 if (!kvm_enabled()) {
2932 if (cap_ppc_pvr_compat
) {
2936 return !kvmppc_is_pr(cs
->kvm_state
);
2939 void kvmppc_set_reg_ppc_online(PowerPCCPU
*cpu
, unsigned int online
)
2941 CPUState
*cs
= CPU(cpu
);
2943 if (kvm_enabled()) {
2944 kvm_set_one_reg(cs
, KVM_REG_PPC_ONLINE
, &online
);
2948 void kvmppc_set_reg_tb_offset(PowerPCCPU
*cpu
, int64_t tb_offset
)
2950 CPUState
*cs
= CPU(cpu
);
2952 if (kvm_enabled()) {
2953 kvm_set_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &tb_offset
);