2 * QEMU model of the LatticeMico32 timer block.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://www.latticesemi.com/documents/mico32timer.pdf
24 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
28 #include "qemu/timer.h"
29 #include "hw/ptimer.h"
30 #include "qemu/error-report.h"
31 #include "qemu/main-loop.h"
32 #include "qemu/module.h"
34 #define DEFAULT_FREQUENCY (50*1000000)
56 #define TYPE_LM32_TIMER "lm32-timer"
57 #define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER)
59 struct LM32TimerState
{
60 SysBusDevice parent_obj
;
72 typedef struct LM32TimerState LM32TimerState
;
74 static void timer_update_irq(LM32TimerState
*s
)
76 int state
= (s
->regs
[R_SR
] & SR_TO
) && (s
->regs
[R_CR
] & CR_ITO
);
78 trace_lm32_timer_irq_state(state
);
79 qemu_set_irq(s
->irq
, state
);
82 static uint64_t timer_read(void *opaque
, hwaddr addr
, unsigned size
)
84 LM32TimerState
*s
= opaque
;
95 r
= (uint32_t)ptimer_get_count(s
->ptimer
);
98 error_report("lm32_timer: read access to unknown register 0x"
99 TARGET_FMT_plx
, addr
<< 2);
103 trace_lm32_timer_memory_read(addr
<< 2, r
);
107 static void timer_write(void *opaque
, hwaddr addr
,
108 uint64_t value
, unsigned size
)
110 LM32TimerState
*s
= opaque
;
112 trace_lm32_timer_memory_write(addr
, value
);
117 s
->regs
[R_SR
] &= ~SR_TO
;
120 s
->regs
[R_CR
] = value
;
121 if (s
->regs
[R_CR
] & CR_START
) {
122 ptimer_run(s
->ptimer
, 1);
124 if (s
->regs
[R_CR
] & CR_STOP
) {
125 ptimer_stop(s
->ptimer
);
129 s
->regs
[R_PERIOD
] = value
;
130 ptimer_set_count(s
->ptimer
, value
);
133 error_report("lm32_timer: write access to read only register 0x"
134 TARGET_FMT_plx
, addr
<< 2);
137 error_report("lm32_timer: write access to unknown register 0x"
138 TARGET_FMT_plx
, addr
<< 2);
144 static const MemoryRegionOps timer_ops
= {
146 .write
= timer_write
,
147 .endianness
= DEVICE_NATIVE_ENDIAN
,
149 .min_access_size
= 4,
150 .max_access_size
= 4,
154 static void timer_hit(void *opaque
)
156 LM32TimerState
*s
= opaque
;
158 trace_lm32_timer_hit();
160 s
->regs
[R_SR
] |= SR_TO
;
162 if (s
->regs
[R_CR
] & CR_CONT
) {
163 ptimer_set_count(s
->ptimer
, s
->regs
[R_PERIOD
]);
164 ptimer_run(s
->ptimer
, 1);
169 static void timer_reset(DeviceState
*d
)
171 LM32TimerState
*s
= LM32_TIMER(d
);
174 for (i
= 0; i
< R_MAX
; i
++) {
177 ptimer_stop(s
->ptimer
);
180 static void lm32_timer_init(Object
*obj
)
182 LM32TimerState
*s
= LM32_TIMER(obj
);
183 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
185 sysbus_init_irq(dev
, &s
->irq
);
187 s
->bh
= qemu_bh_new(timer_hit
, s
);
188 s
->ptimer
= ptimer_init(s
->bh
, PTIMER_POLICY_DEFAULT
);
190 memory_region_init_io(&s
->iomem
, obj
, &timer_ops
, s
,
192 sysbus_init_mmio(dev
, &s
->iomem
);
195 static void lm32_timer_realize(DeviceState
*dev
, Error
**errp
)
197 LM32TimerState
*s
= LM32_TIMER(dev
);
199 ptimer_set_freq(s
->ptimer
, s
->freq_hz
);
202 static const VMStateDescription vmstate_lm32_timer
= {
203 .name
= "lm32-timer",
205 .minimum_version_id
= 1,
206 .fields
= (VMStateField
[]) {
207 VMSTATE_PTIMER(ptimer
, LM32TimerState
),
208 VMSTATE_UINT32(freq_hz
, LM32TimerState
),
209 VMSTATE_UINT32_ARRAY(regs
, LM32TimerState
, R_MAX
),
210 VMSTATE_END_OF_LIST()
214 static Property lm32_timer_properties
[] = {
215 DEFINE_PROP_UINT32("frequency", LM32TimerState
, freq_hz
, DEFAULT_FREQUENCY
),
216 DEFINE_PROP_END_OF_LIST(),
219 static void lm32_timer_class_init(ObjectClass
*klass
, void *data
)
221 DeviceClass
*dc
= DEVICE_CLASS(klass
);
223 dc
->realize
= lm32_timer_realize
;
224 dc
->reset
= timer_reset
;
225 dc
->vmsd
= &vmstate_lm32_timer
;
226 dc
->props
= lm32_timer_properties
;
229 static const TypeInfo lm32_timer_info
= {
230 .name
= TYPE_LM32_TIMER
,
231 .parent
= TYPE_SYS_BUS_DEVICE
,
232 .instance_size
= sizeof(LM32TimerState
),
233 .instance_init
= lm32_timer_init
,
234 .class_init
= lm32_timer_class_init
,
237 static void lm32_timer_register_types(void)
239 type_register_static(&lm32_timer_info
);
242 type_init(lm32_timer_register_types
)