2 * Samsung exynos4210 Real Time Clock
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * Ogurtsov Oleg <o.ogurtsov@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 * CLKSEL Bit[1] not used
25 * CLKOUTEN Bit[9] not used
28 #include "qemu/osdep.h"
29 #include "qemu-common.h"
31 #include "qemu/module.h"
32 #include "hw/sysbus.h"
33 #include "qemu/timer.h"
35 #include "hw/ptimer.h"
38 #include "sysemu/sysemu.h"
40 #include "hw/arm/exynos4210.h"
45 #define DPRINTF(fmt, ...) \
46 do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
47 ## __VA_ARGS__); } while (0)
49 #define DPRINTF(fmt, ...) do {} while (0)
52 #define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100
60 #define ALMHOUR 0x005C
63 #define ALMYEAR 0x0068
66 #define BCDHOUR 0x0078
68 #define BCDDAYWEEK 0x0080
70 #define BCDYEAR 0x0088
71 #define CURTICNT 0x0090
73 #define TICK_TIMER_ENABLE 0x0100
74 #define TICNT_THRESHOLD 2
77 #define RTC_ENABLE 0x0001
79 #define INTP_TICK_ENABLE 0x0001
80 #define INTP_ALM_ENABLE 0x0002
82 #define ALARM_INT_ENABLE 0x0040
84 #define RTC_BASE_FREQ 32768
86 #define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
87 #define EXYNOS4210_RTC(obj) \
88 OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)
90 typedef struct Exynos4210RTCState
{
91 SysBusDevice parent_obj
;
102 uint32_t reg_almhour
;
105 uint32_t reg_almyear
;
106 uint32_t reg_curticcnt
;
108 ptimer_state
*ptimer
; /* tick timer */
109 ptimer_state
*ptimer_1Hz
; /* clock timer */
112 qemu_irq tick_irq
; /* Time Tick Generator irq */
113 qemu_irq alm_irq
; /* alarm irq */
115 struct tm current_tm
; /* current time */
116 } Exynos4210RTCState
;
118 #define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)
121 static const VMStateDescription vmstate_exynos4210_rtc_state
= {
122 .name
= "exynos4210.rtc",
124 .minimum_version_id
= 1,
125 .fields
= (VMStateField
[]) {
126 VMSTATE_UINT32(reg_intp
, Exynos4210RTCState
),
127 VMSTATE_UINT32(reg_rtccon
, Exynos4210RTCState
),
128 VMSTATE_UINT32(reg_ticcnt
, Exynos4210RTCState
),
129 VMSTATE_UINT32(reg_rtcalm
, Exynos4210RTCState
),
130 VMSTATE_UINT32(reg_almsec
, Exynos4210RTCState
),
131 VMSTATE_UINT32(reg_almmin
, Exynos4210RTCState
),
132 VMSTATE_UINT32(reg_almhour
, Exynos4210RTCState
),
133 VMSTATE_UINT32(reg_almday
, Exynos4210RTCState
),
134 VMSTATE_UINT32(reg_almmon
, Exynos4210RTCState
),
135 VMSTATE_UINT32(reg_almyear
, Exynos4210RTCState
),
136 VMSTATE_UINT32(reg_curticcnt
, Exynos4210RTCState
),
137 VMSTATE_PTIMER(ptimer
, Exynos4210RTCState
),
138 VMSTATE_PTIMER(ptimer_1Hz
, Exynos4210RTCState
),
139 VMSTATE_UINT32(freq
, Exynos4210RTCState
),
140 VMSTATE_INT32(current_tm
.tm_sec
, Exynos4210RTCState
),
141 VMSTATE_INT32(current_tm
.tm_min
, Exynos4210RTCState
),
142 VMSTATE_INT32(current_tm
.tm_hour
, Exynos4210RTCState
),
143 VMSTATE_INT32(current_tm
.tm_wday
, Exynos4210RTCState
),
144 VMSTATE_INT32(current_tm
.tm_mday
, Exynos4210RTCState
),
145 VMSTATE_INT32(current_tm
.tm_mon
, Exynos4210RTCState
),
146 VMSTATE_INT32(current_tm
.tm_year
, Exynos4210RTCState
),
147 VMSTATE_END_OF_LIST()
151 #define BCD3DIGITS(x) \
152 ((uint32_t)to_bcd((uint8_t)(x % 100)) + \
153 ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))
155 static void check_alarm_raise(Exynos4210RTCState
*s
)
157 unsigned int alarm_raise
= 0;
158 struct tm stm
= s
->current_tm
;
160 if ((s
->reg_rtcalm
& 0x01) &&
161 (to_bcd((uint8_t)stm
.tm_sec
) == (uint8_t)s
->reg_almsec
)) {
164 if ((s
->reg_rtcalm
& 0x02) &&
165 (to_bcd((uint8_t)stm
.tm_min
) == (uint8_t)s
->reg_almmin
)) {
168 if ((s
->reg_rtcalm
& 0x04) &&
169 (to_bcd((uint8_t)stm
.tm_hour
) == (uint8_t)s
->reg_almhour
)) {
172 if ((s
->reg_rtcalm
& 0x08) &&
173 (to_bcd((uint8_t)stm
.tm_mday
) == (uint8_t)s
->reg_almday
)) {
176 if ((s
->reg_rtcalm
& 0x10) &&
177 (to_bcd((uint8_t)stm
.tm_mon
) == (uint8_t)s
->reg_almmon
)) {
180 if ((s
->reg_rtcalm
& 0x20) &&
181 (BCD3DIGITS(stm
.tm_year
) == s
->reg_almyear
)) {
186 DPRINTF("ALARM IRQ\n");
188 s
->reg_intp
|= INTP_ALM_ENABLE
;
189 qemu_irq_raise(s
->alm_irq
);
194 * RTC update frequency
196 * reg_value - current RTCCON register or his new value
198 static void exynos4210_rtc_update_freq(Exynos4210RTCState
*s
,
204 /* set frequncy for time generator */
205 s
->freq
= RTC_BASE_FREQ
/ (1 << TICCKSEL(reg_value
));
207 if (freq
!= s
->freq
) {
208 ptimer_set_freq(s
->ptimer
, s
->freq
);
209 DPRINTF("freq=%dHz\n", s
->freq
);
213 /* month is between 0 and 11. */
214 static int get_days_in_month(int month
, int year
)
216 static const int days_tab
[12] = {
217 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
220 if ((unsigned)month
>= 12) {
225 if ((year
% 4) == 0 && ((year
% 100) != 0 || (year
% 400) == 0)) {
232 /* update 'tm' to the next second */
233 static void rtc_next_second(struct tm
*tm
)
238 if ((unsigned)tm
->tm_sec
>= 60) {
241 if ((unsigned)tm
->tm_min
>= 60) {
244 if ((unsigned)tm
->tm_hour
>= 24) {
248 if ((unsigned)tm
->tm_wday
>= 7) {
251 days_in_month
= get_days_in_month(tm
->tm_mon
,
254 if (tm
->tm_mday
< 1) {
256 } else if (tm
->tm_mday
> days_in_month
) {
259 if (tm
->tm_mon
>= 12) {
272 static void exynos4210_rtc_tick(void *opaque
)
274 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
276 DPRINTF("TICK IRQ\n");
278 s
->reg_intp
|= INTP_TICK_ENABLE
;
280 qemu_irq_raise(s
->tick_irq
);
283 ptimer_set_count(s
->ptimer
, s
->reg_ticcnt
);
284 ptimer_run(s
->ptimer
, 1);
290 static void exynos4210_rtc_1Hz_tick(void *opaque
)
292 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
294 rtc_next_second(&s
->current_tm
);
295 /* DPRINTF("1Hz tick\n"); */
298 if (s
->reg_rtcalm
& ALARM_INT_ENABLE
) {
299 check_alarm_raise(s
);
302 ptimer_set_count(s
->ptimer_1Hz
, RTC_BASE_FREQ
);
303 ptimer_run(s
->ptimer_1Hz
, 1);
309 static uint64_t exynos4210_rtc_read(void *opaque
, hwaddr offset
,
313 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
320 value
= s
->reg_rtccon
;
323 value
= s
->reg_ticcnt
;
326 value
= s
->reg_rtcalm
;
329 value
= s
->reg_almsec
;
332 value
= s
->reg_almmin
;
335 value
= s
->reg_almhour
;
338 value
= s
->reg_almday
;
341 value
= s
->reg_almmon
;
344 value
= s
->reg_almyear
;
348 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_sec
);
351 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_min
);
354 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_hour
);
357 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_wday
);
360 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_mday
);
363 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_mon
+ 1);
366 value
= BCD3DIGITS(s
->current_tm
.tm_year
);
370 s
->reg_curticcnt
= ptimer_get_count(s
->ptimer
);
371 value
= s
->reg_curticcnt
;
375 qemu_log_mask(LOG_GUEST_ERROR
,
376 "exynos4210.rtc: bad read offset " TARGET_FMT_plx
,
386 static void exynos4210_rtc_write(void *opaque
, hwaddr offset
,
387 uint64_t value
, unsigned size
)
389 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
393 if (value
& INTP_ALM_ENABLE
) {
394 qemu_irq_lower(s
->alm_irq
);
395 s
->reg_intp
&= (~INTP_ALM_ENABLE
);
397 if (value
& INTP_TICK_ENABLE
) {
398 qemu_irq_lower(s
->tick_irq
);
399 s
->reg_intp
&= (~INTP_TICK_ENABLE
);
403 if (value
& RTC_ENABLE
) {
404 exynos4210_rtc_update_freq(s
, value
);
406 if ((value
& RTC_ENABLE
) > (s
->reg_rtccon
& RTC_ENABLE
)) {
408 ptimer_set_count(s
->ptimer_1Hz
, RTC_BASE_FREQ
);
409 ptimer_run(s
->ptimer_1Hz
, 1);
410 DPRINTF("run clock timer\n");
412 if ((value
& RTC_ENABLE
) < (s
->reg_rtccon
& RTC_ENABLE
)) {
414 ptimer_stop(s
->ptimer
);
416 ptimer_stop(s
->ptimer_1Hz
);
417 DPRINTF("stop all timers\n");
419 if (value
& RTC_ENABLE
) {
420 if ((value
& TICK_TIMER_ENABLE
) >
421 (s
->reg_rtccon
& TICK_TIMER_ENABLE
) &&
423 ptimer_set_count(s
->ptimer
, s
->reg_ticcnt
);
424 ptimer_run(s
->ptimer
, 1);
425 DPRINTF("run tick timer\n");
427 if ((value
& TICK_TIMER_ENABLE
) <
428 (s
->reg_rtccon
& TICK_TIMER_ENABLE
)) {
429 ptimer_stop(s
->ptimer
);
432 s
->reg_rtccon
= value
;
435 if (value
> TICNT_THRESHOLD
) {
436 s
->reg_ticcnt
= value
;
438 qemu_log_mask(LOG_GUEST_ERROR
,
439 "exynos4210.rtc: bad TICNT value %u",
445 s
->reg_rtcalm
= value
;
448 s
->reg_almsec
= (value
& 0x7f);
451 s
->reg_almmin
= (value
& 0x7f);
454 s
->reg_almhour
= (value
& 0x3f);
457 s
->reg_almday
= (value
& 0x3f);
460 s
->reg_almmon
= (value
& 0x1f);
463 s
->reg_almyear
= (value
& 0x0fff);
467 if (s
->reg_rtccon
& RTC_ENABLE
) {
468 s
->current_tm
.tm_sec
= (int)from_bcd((uint8_t)value
);
472 if (s
->reg_rtccon
& RTC_ENABLE
) {
473 s
->current_tm
.tm_min
= (int)from_bcd((uint8_t)value
);
477 if (s
->reg_rtccon
& RTC_ENABLE
) {
478 s
->current_tm
.tm_hour
= (int)from_bcd((uint8_t)value
);
482 if (s
->reg_rtccon
& RTC_ENABLE
) {
483 s
->current_tm
.tm_wday
= (int)from_bcd((uint8_t)value
);
487 if (s
->reg_rtccon
& RTC_ENABLE
) {
488 s
->current_tm
.tm_mday
= (int)from_bcd((uint8_t)value
);
492 if (s
->reg_rtccon
& RTC_ENABLE
) {
493 s
->current_tm
.tm_mon
= (int)from_bcd((uint8_t)value
) - 1;
497 if (s
->reg_rtccon
& RTC_ENABLE
) {
499 s
->current_tm
.tm_year
= (int)from_bcd((uint8_t)value
) +
500 (int)from_bcd((uint8_t)((value
>> 8) & 0x0f)) * 100;
505 qemu_log_mask(LOG_GUEST_ERROR
,
506 "exynos4210.rtc: bad write offset " TARGET_FMT_plx
,
514 * Set default values to timer fields and registers
516 static void exynos4210_rtc_reset(DeviceState
*d
)
518 Exynos4210RTCState
*s
= EXYNOS4210_RTC(d
);
520 qemu_get_timedate(&s
->current_tm
, 0);
522 DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
523 s
->current_tm
.tm_year
, s
->current_tm
.tm_mon
, s
->current_tm
.tm_mday
,
524 s
->current_tm
.tm_hour
, s
->current_tm
.tm_min
, s
->current_tm
.tm_sec
);
537 s
->reg_curticcnt
= 0;
539 exynos4210_rtc_update_freq(s
, s
->reg_rtccon
);
540 ptimer_stop(s
->ptimer
);
541 ptimer_stop(s
->ptimer_1Hz
);
544 static const MemoryRegionOps exynos4210_rtc_ops
= {
545 .read
= exynos4210_rtc_read
,
546 .write
= exynos4210_rtc_write
,
547 .endianness
= DEVICE_NATIVE_ENDIAN
,
551 * RTC timer initialization
553 static void exynos4210_rtc_init(Object
*obj
)
555 Exynos4210RTCState
*s
= EXYNOS4210_RTC(obj
);
556 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
559 bh
= qemu_bh_new(exynos4210_rtc_tick
, s
);
560 s
->ptimer
= ptimer_init(bh
, PTIMER_POLICY_DEFAULT
);
561 ptimer_set_freq(s
->ptimer
, RTC_BASE_FREQ
);
562 exynos4210_rtc_update_freq(s
, 0);
564 bh
= qemu_bh_new(exynos4210_rtc_1Hz_tick
, s
);
565 s
->ptimer_1Hz
= ptimer_init(bh
, PTIMER_POLICY_DEFAULT
);
566 ptimer_set_freq(s
->ptimer_1Hz
, RTC_BASE_FREQ
);
568 sysbus_init_irq(dev
, &s
->alm_irq
);
569 sysbus_init_irq(dev
, &s
->tick_irq
);
571 memory_region_init_io(&s
->iomem
, obj
, &exynos4210_rtc_ops
, s
,
572 "exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE
);
573 sysbus_init_mmio(dev
, &s
->iomem
);
576 static void exynos4210_rtc_class_init(ObjectClass
*klass
, void *data
)
578 DeviceClass
*dc
= DEVICE_CLASS(klass
);
580 dc
->reset
= exynos4210_rtc_reset
;
581 dc
->vmsd
= &vmstate_exynos4210_rtc_state
;
584 static const TypeInfo exynos4210_rtc_info
= {
585 .name
= TYPE_EXYNOS4210_RTC
,
586 .parent
= TYPE_SYS_BUS_DEVICE
,
587 .instance_size
= sizeof(Exynos4210RTCState
),
588 .instance_init
= exynos4210_rtc_init
,
589 .class_init
= exynos4210_rtc_class_init
,
592 static void exynos4210_rtc_register_types(void)
594 type_register_static(&exynos4210_rtc_info
);
597 type_init(exynos4210_rtc_register_types
)