2 * QEMU TEWS TPCI200 IndustryPack carrier emulation
4 * Copyright (C) 2012 Igalia, S.L.
5 * Author: Alberto Garcia <berto@igalia.com>
7 * This code is licensed under the GNU GPL v2 or (at your option) any
11 #include "qemu/osdep.h"
12 #include "qemu/units.h"
13 #include "hw/ipack/ipack.h"
14 #include "hw/pci/pci.h"
15 #include "qemu/bitops.h"
16 #include "qemu/module.h"
18 /* #define DEBUG_TPCI */
21 #define DPRINTF(fmt, ...) \
22 do { fprintf(stderr, "TPCI200: " fmt, ## __VA_ARGS__); } while (0)
24 #define DPRINTF(fmt, ...) do { } while (0)
30 #define IP_INT_SPACE 3
31 #define IP_IO_SPACE_ADDR_MASK 0x7F
32 #define IP_ID_SPACE_ADDR_MASK 0x3F
33 #define IP_INT_SPACE_ADDR_MASK 0x3F
35 #define STATUS_INT(IP, INTNO) BIT((IP) * 2 + (INTNO))
36 #define STATUS_TIME(IP) BIT((IP) + 12)
37 #define STATUS_ERR_ANY 0xF00
39 #define CTRL_CLKRATE BIT(0)
40 #define CTRL_RECOVER BIT(1)
41 #define CTRL_TIME_INT BIT(2)
42 #define CTRL_ERR_INT BIT(3)
43 #define CTRL_INT_EDGE(INTNO) BIT(4 + (INTNO))
44 #define CTRL_INT(INTNO) BIT(6 + (INTNO))
46 #define REG_REV_ID 0x00
47 #define REG_IP_A_CTRL 0x02
48 #define REG_IP_B_CTRL 0x04
49 #define REG_IP_C_CTRL 0x06
50 #define REG_IP_D_CTRL 0x08
51 #define REG_RESET 0x0A
52 #define REG_STATUS 0x0C
53 #define IP_N_FROM_REG(REG) ((REG) / 2 - 1)
65 uint8_t ctrl
[N_MODULES
];
70 #define TYPE_TPCI200 "tpci200"
72 #define TPCI200(obj) \
73 OBJECT_CHECK(TPCI200State, (obj), TYPE_TPCI200)
75 static const uint8_t local_config_regs
[] = {
76 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00,
77 0x0E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
78 0x00, 0x08, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x01,
79 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x60, 0x41, 0xD4,
80 0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x01,
81 0x14, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x08, 0x01, 0x02,
82 0x00, 0x04, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02, 0x41,
83 0x00, 0x00, 0x00, 0x00, 0x40, 0x7A, 0x00, 0x52, 0x92, 0x24, 0x02
86 static void adjust_addr(bool big_endian
, hwaddr
*addr
, unsigned size
)
88 /* During 8 bit access in big endian mode,
89 odd and even addresses are swapped */
90 if (big_endian
&& size
== 1) {
95 static uint64_t adjust_value(bool big_endian
, uint64_t *val
, unsigned size
)
97 /* Local spaces only support 8/16 bit access,
98 * so there's no need to care for sizes > 2 */
99 if (big_endian
&& size
== 2) {
100 *val
= bswap16(*val
);
105 static void tpci200_set_irq(void *opaque
, int intno
, int level
)
107 IPackDevice
*ip
= opaque
;
108 IPackBus
*bus
= IPACK_BUS(qdev_get_parent_bus(DEVICE(ip
)));
109 PCIDevice
*pcidev
= PCI_DEVICE(BUS(bus
)->parent
);
110 TPCI200State
*dev
= TPCI200(pcidev
);
111 unsigned ip_n
= ip
->slot
;
112 uint16_t prev_status
= dev
->status
;
114 assert(ip
->slot
>= 0 && ip
->slot
< N_MODULES
);
116 /* The requested interrupt must be enabled in the IP CONTROL
118 if (!(dev
->ctrl
[ip_n
] & CTRL_INT(intno
))) {
122 /* Update the interrupt status in the IP STATUS register */
124 dev
->status
|= STATUS_INT(ip_n
, intno
);
126 dev
->status
&= ~STATUS_INT(ip_n
, intno
);
129 /* Return if there are no changes */
130 if (dev
->status
== prev_status
) {
134 DPRINTF("IP %u INT%u#: %u\n", ip_n
, intno
, level
);
136 /* Check if the interrupt is edge sensitive */
137 if (dev
->ctrl
[ip_n
] & CTRL_INT_EDGE(intno
)) {
139 pci_set_irq(&dev
->dev
, !dev
->int_set
);
140 pci_set_irq(&dev
->dev
, dev
->int_set
);
144 uint16_t level_status
= dev
->status
;
146 /* Check if there are any level sensitive interrupts set by
147 removing the ones that are edge sensitive from the status
149 for (i
= 0; i
< N_MODULES
; i
++) {
150 for (j
= 0; j
< 2; j
++) {
151 if (dev
->ctrl
[i
] & CTRL_INT_EDGE(j
)) {
152 level_status
&= ~STATUS_INT(i
, j
);
157 if (level_status
&& !dev
->int_set
) {
158 pci_irq_assert(&dev
->dev
);
160 } else if (!level_status
&& dev
->int_set
) {
161 pci_irq_deassert(&dev
->dev
);
167 static uint64_t tpci200_read_cfg(void *opaque
, hwaddr addr
, unsigned size
)
169 TPCI200State
*s
= opaque
;
171 if (addr
< ARRAY_SIZE(local_config_regs
)) {
172 ret
= local_config_regs
[addr
];
174 /* Endianness is stored in the first bit of these registers */
175 if ((addr
== 0x2b && s
->big_endian
[0]) ||
176 (addr
== 0x2f && s
->big_endian
[1]) ||
177 (addr
== 0x33 && s
->big_endian
[2])) {
180 DPRINTF("Read from LCR 0x%x: 0x%x\n", (unsigned) addr
, (unsigned) ret
);
184 static void tpci200_write_cfg(void *opaque
, hwaddr addr
, uint64_t val
,
187 TPCI200State
*s
= opaque
;
188 /* Endianness is stored in the first bit of these registers */
189 if (addr
== 0x2b || addr
== 0x2f || addr
== 0x33) {
190 unsigned las
= (addr
- 0x2b) / 4;
191 s
->big_endian
[las
] = val
& 1;
192 DPRINTF("LAS%u big endian mode: %u\n", las
, (unsigned) val
& 1);
194 DPRINTF("Write to LCR 0x%x: 0x%x\n", (unsigned) addr
, (unsigned) val
);
198 static uint64_t tpci200_read_las0(void *opaque
, hwaddr addr
, unsigned size
)
200 TPCI200State
*s
= opaque
;
206 DPRINTF("Read REVISION ID\n"); /* Current value is 0x00 */
214 unsigned ip_n
= IP_N_FROM_REG(addr
);
216 DPRINTF("Read IP %c CONTROL: 0x%x\n", 'A' + ip_n
, (unsigned) ret
);
221 DPRINTF("Read RESET\n"); /* Not implemented */
226 DPRINTF("Read STATUS: 0x%x\n", (unsigned) ret
);
231 DPRINTF("Unsupported read from LAS0 0x%x\n", (unsigned) addr
);
235 return adjust_value(s
->big_endian
[0], &ret
, size
);
238 static void tpci200_write_las0(void *opaque
, hwaddr addr
, uint64_t val
,
241 TPCI200State
*s
= opaque
;
243 adjust_value(s
->big_endian
[0], &val
, size
);
248 DPRINTF("Write Revision ID: 0x%x\n", (unsigned) val
); /* No effect */
256 unsigned ip_n
= IP_N_FROM_REG(addr
);
258 DPRINTF("Write IP %c CONTROL: 0x%x\n", 'A' + ip_n
, (unsigned) val
);
263 DPRINTF("Write RESET: 0x%x\n", (unsigned) val
); /* Not implemented */
270 for (i
= 0; i
< N_MODULES
; i
++) {
271 IPackDevice
*ip
= ipack_device_find(&s
->bus
, i
);
274 if (val
& STATUS_INT(i
, 0)) {
275 DPRINTF("Clear IP %c INT0# status\n", 'A' + i
);
276 qemu_irq_lower(ip
->irq
[0]);
278 if (val
& STATUS_INT(i
, 1)) {
279 DPRINTF("Clear IP %c INT1# status\n", 'A' + i
);
280 qemu_irq_lower(ip
->irq
[1]);
284 if (val
& STATUS_TIME(i
)) {
285 DPRINTF("Clear IP %c timeout\n", 'A' + i
);
286 s
->status
&= ~STATUS_TIME(i
);
290 if (val
& STATUS_ERR_ANY
) {
291 DPRINTF("Unexpected write to STATUS register: 0x%x\n",
299 DPRINTF("Unsupported write to LAS0 0x%x: 0x%x\n",
300 (unsigned) addr
, (unsigned) val
);
305 static uint64_t tpci200_read_las1(void *opaque
, hwaddr addr
, unsigned size
)
307 TPCI200State
*s
= opaque
;
310 unsigned ip_n
, space
;
313 adjust_addr(s
->big_endian
[1], &addr
, size
);
316 * The address is divided into the IP module number (0-4), the IP
317 * address space (I/O, ID, INT) and the offset within that space.
320 space
= (addr
>> 6) & 3;
321 ip
= ipack_device_find(&s
->bus
, ip_n
);
324 DPRINTF("Read LAS1: IP module %u not installed\n", ip_n
);
326 IPackDeviceClass
*k
= IPACK_DEVICE_GET_CLASS(ip
);
330 offset
= addr
& IP_ID_SPACE_ADDR_MASK
;
332 ret
= k
->id_read(ip
, offset
);
337 offset
= addr
& IP_INT_SPACE_ADDR_MASK
;
339 /* Read address 0 to ACK IP INT0# and address 2 to ACK IP INT1# */
340 if (offset
== 0 || offset
== 2) {
341 unsigned intno
= offset
/ 2;
342 bool int_set
= s
->status
& STATUS_INT(ip_n
, intno
);
343 bool int_edge_sensitive
= s
->ctrl
[ip_n
] & CTRL_INT_EDGE(intno
);
344 if (int_set
&& !int_edge_sensitive
) {
345 qemu_irq_lower(ip
->irq
[intno
]);
350 ret
= k
->int_read(ip
, offset
);
355 offset
= addr
& IP_IO_SPACE_ADDR_MASK
;
357 ret
= k
->io_read(ip
, offset
);
363 return adjust_value(s
->big_endian
[1], &ret
, size
);
366 static void tpci200_write_las1(void *opaque
, hwaddr addr
, uint64_t val
,
369 TPCI200State
*s
= opaque
;
371 unsigned ip_n
, space
;
374 adjust_addr(s
->big_endian
[1], &addr
, size
);
375 adjust_value(s
->big_endian
[1], &val
, size
);
378 * The address is divided into the IP module number, the IP
379 * address space (I/O, ID, INT) and the offset within that space.
382 space
= (addr
>> 6) & 3;
383 ip
= ipack_device_find(&s
->bus
, ip_n
);
386 DPRINTF("Write LAS1: IP module %u not installed\n", ip_n
);
388 IPackDeviceClass
*k
= IPACK_DEVICE_GET_CLASS(ip
);
392 offset
= addr
& IP_ID_SPACE_ADDR_MASK
;
394 k
->id_write(ip
, offset
, val
);
399 offset
= addr
& IP_INT_SPACE_ADDR_MASK
;
401 k
->int_write(ip
, offset
, val
);
406 offset
= addr
& IP_IO_SPACE_ADDR_MASK
;
408 k
->io_write(ip
, offset
, val
);
415 static uint64_t tpci200_read_las2(void *opaque
, hwaddr addr
, unsigned size
)
417 TPCI200State
*s
= opaque
;
423 adjust_addr(s
->big_endian
[2], &addr
, size
);
426 * The address is divided into the IP module number and the offset
427 * within the IP module MEM space.
430 offset
= addr
& 0x7fffff;
431 ip
= ipack_device_find(&s
->bus
, ip_n
);
434 DPRINTF("Read LAS2: IP module %u not installed\n", ip_n
);
436 IPackDeviceClass
*k
= IPACK_DEVICE_GET_CLASS(ip
);
438 ret
= k
->mem_read16(ip
, offset
);
442 return adjust_value(s
->big_endian
[2], &ret
, size
);
445 static void tpci200_write_las2(void *opaque
, hwaddr addr
, uint64_t val
,
448 TPCI200State
*s
= opaque
;
453 adjust_addr(s
->big_endian
[2], &addr
, size
);
454 adjust_value(s
->big_endian
[2], &val
, size
);
457 * The address is divided into the IP module number and the offset
458 * within the IP module MEM space.
461 offset
= addr
& 0x7fffff;
462 ip
= ipack_device_find(&s
->bus
, ip_n
);
465 DPRINTF("Write LAS2: IP module %u not installed\n", ip_n
);
467 IPackDeviceClass
*k
= IPACK_DEVICE_GET_CLASS(ip
);
468 if (k
->mem_write16
) {
469 k
->mem_write16(ip
, offset
, val
);
474 static uint64_t tpci200_read_las3(void *opaque
, hwaddr addr
, unsigned size
)
476 TPCI200State
*s
= opaque
;
480 * The address is divided into the IP module number and the offset
481 * within the IP module MEM space.
483 unsigned ip_n
= addr
>> 22;
484 uint32_t offset
= addr
& 0x3fffff;
486 ip
= ipack_device_find(&s
->bus
, ip_n
);
489 DPRINTF("Read LAS3: IP module %u not installed\n", ip_n
);
491 IPackDeviceClass
*k
= IPACK_DEVICE_GET_CLASS(ip
);
493 ret
= k
->mem_read8(ip
, offset
);
500 static void tpci200_write_las3(void *opaque
, hwaddr addr
, uint64_t val
,
503 TPCI200State
*s
= opaque
;
506 * The address is divided into the IP module number and the offset
507 * within the IP module MEM space.
509 unsigned ip_n
= addr
>> 22;
510 uint32_t offset
= addr
& 0x3fffff;
512 ip
= ipack_device_find(&s
->bus
, ip_n
);
515 DPRINTF("Write LAS3: IP module %u not installed\n", ip_n
);
517 IPackDeviceClass
*k
= IPACK_DEVICE_GET_CLASS(ip
);
519 k
->mem_write8(ip
, offset
, val
);
524 static const MemoryRegionOps tpci200_cfg_ops
= {
525 .read
= tpci200_read_cfg
,
526 .write
= tpci200_write_cfg
,
527 .endianness
= DEVICE_NATIVE_ENDIAN
,
529 .min_access_size
= 1,
533 .min_access_size
= 1,
538 static const MemoryRegionOps tpci200_las0_ops
= {
539 .read
= tpci200_read_las0
,
540 .write
= tpci200_write_las0
,
541 .endianness
= DEVICE_NATIVE_ENDIAN
,
543 .min_access_size
= 2,
548 static const MemoryRegionOps tpci200_las1_ops
= {
549 .read
= tpci200_read_las1
,
550 .write
= tpci200_write_las1
,
551 .endianness
= DEVICE_NATIVE_ENDIAN
,
553 .min_access_size
= 1,
558 static const MemoryRegionOps tpci200_las2_ops
= {
559 .read
= tpci200_read_las2
,
560 .write
= tpci200_write_las2
,
561 .endianness
= DEVICE_NATIVE_ENDIAN
,
563 .min_access_size
= 1,
568 static const MemoryRegionOps tpci200_las3_ops
= {
569 .read
= tpci200_read_las3
,
570 .write
= tpci200_write_las3
,
571 .endianness
= DEVICE_NATIVE_ENDIAN
,
573 .min_access_size
= 1,
578 static void tpci200_realize(PCIDevice
*pci_dev
, Error
**errp
)
580 TPCI200State
*s
= TPCI200(pci_dev
);
581 uint8_t *c
= s
->dev
.config
;
583 pci_set_word(c
+ PCI_COMMAND
, 0x0003);
584 pci_set_word(c
+ PCI_STATUS
, 0x0280);
586 pci_set_byte(c
+ PCI_INTERRUPT_PIN
, 0x01); /* Interrupt pin A */
588 pci_set_byte(c
+ PCI_CAPABILITY_LIST
, 0x40);
589 pci_set_long(c
+ 0x40, 0x48014801);
590 pci_set_long(c
+ 0x48, 0x00024C06);
591 pci_set_long(c
+ 0x4C, 0x00000003);
593 memory_region_init_io(&s
->mmio
, OBJECT(s
), &tpci200_cfg_ops
,
594 s
, "tpci200_mmio", 128);
595 memory_region_init_io(&s
->io
, OBJECT(s
), &tpci200_cfg_ops
,
596 s
, "tpci200_io", 128);
597 memory_region_init_io(&s
->las0
, OBJECT(s
), &tpci200_las0_ops
,
598 s
, "tpci200_las0", 256);
599 memory_region_init_io(&s
->las1
, OBJECT(s
), &tpci200_las1_ops
,
600 s
, "tpci200_las1", 1024);
601 memory_region_init_io(&s
->las2
, OBJECT(s
), &tpci200_las2_ops
,
602 s
, "tpci200_las2", 32 * MiB
);
603 memory_region_init_io(&s
->las3
, OBJECT(s
), &tpci200_las3_ops
,
604 s
, "tpci200_las3", 16 * MiB
);
605 pci_register_bar(&s
->dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mmio
);
606 pci_register_bar(&s
->dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io
);
607 pci_register_bar(&s
->dev
, 2, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->las0
);
608 pci_register_bar(&s
->dev
, 3, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->las1
);
609 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->las2
);
610 pci_register_bar(&s
->dev
, 5, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->las3
);
612 ipack_bus_new_inplace(&s
->bus
, sizeof(s
->bus
), DEVICE(pci_dev
), NULL
,
613 N_MODULES
, tpci200_set_irq
);
616 static const VMStateDescription vmstate_tpci200
= {
619 .minimum_version_id
= 1,
620 .fields
= (VMStateField
[]) {
621 VMSTATE_PCI_DEVICE(dev
, TPCI200State
),
622 VMSTATE_BOOL_ARRAY(big_endian
, TPCI200State
, 3),
623 VMSTATE_UINT8_ARRAY(ctrl
, TPCI200State
, N_MODULES
),
624 VMSTATE_UINT16(status
, TPCI200State
),
625 VMSTATE_UINT8(int_set
, TPCI200State
),
626 VMSTATE_END_OF_LIST()
630 static void tpci200_class_init(ObjectClass
*klass
, void *data
)
632 DeviceClass
*dc
= DEVICE_CLASS(klass
);
633 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
635 k
->realize
= tpci200_realize
;
636 k
->vendor_id
= PCI_VENDOR_ID_TEWS
;
637 k
->device_id
= PCI_DEVICE_ID_TEWS_TPCI200
;
638 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
639 k
->subsystem_vendor_id
= PCI_VENDOR_ID_TEWS
;
640 k
->subsystem_id
= 0x300A;
641 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
642 dc
->desc
= "TEWS TPCI200 IndustryPack carrier";
643 dc
->vmsd
= &vmstate_tpci200
;
646 static const TypeInfo tpci200_info
= {
647 .name
= TYPE_TPCI200
,
648 .parent
= TYPE_PCI_DEVICE
,
649 .instance_size
= sizeof(TPCI200State
),
650 .class_init
= tpci200_class_init
,
651 .interfaces
= (InterfaceInfo
[]) {
652 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
657 static void tpci200_register_types(void)
659 type_register_static(&tpci200_info
);
662 type_init(tpci200_register_types
)