2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Authors: Stafford Horne <shorne@gmail.com>
9 #include "qemu/osdep.h"
11 #include "qemu/module.h"
12 #include "qapi/error.h"
14 #include "hw/sysbus.h"
15 #include "exec/memory.h"
17 #define TYPE_OR1K_OMPIC "or1k-ompic"
18 #define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPIC)
20 #define OMPIC_CTRL_IRQ_ACK (1 << 31)
21 #define OMPIC_CTRL_IRQ_GEN (1 << 30)
22 #define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff)
24 #define OMPIC_REG(addr) (((addr) >> 2) & 0x1)
25 #define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f)
26 #define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f)
28 #define OMPIC_STATUS_IRQ_PENDING (1 << 30)
29 #define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16)
30 #define OMPIC_STATUS_DATA(data) ((data) & 0xffff)
32 #define OMPIC_CONTROL 0
33 #define OMPIC_STATUS 1
35 #define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */
36 #define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */
38 typedef struct OR1KOMPICState OR1KOMPICState
;
39 typedef struct OR1KOMPICCPUState OR1KOMPICCPUState
;
41 struct OR1KOMPICCPUState
{
47 struct OR1KOMPICState
{
48 SysBusDevice parent_obj
;
51 OR1KOMPICCPUState cpus
[OMPIC_MAX_CPUS
];
56 static uint64_t ompic_read(void *opaque
, hwaddr addr
, unsigned size
)
58 OR1KOMPICState
*s
= opaque
;
59 int src_cpu
= OMPIC_SRC_CPU(addr
);
61 /* We can only write to control control, write control + update status */
62 if (OMPIC_REG(addr
) == OMPIC_CONTROL
) {
63 return s
->cpus
[src_cpu
].control
;
65 return s
->cpus
[src_cpu
].status
;
70 static void ompic_write(void *opaque
, hwaddr addr
, uint64_t data
, unsigned size
)
72 OR1KOMPICState
*s
= opaque
;
73 /* We can only write to control control, write control + update status */
74 if (OMPIC_REG(addr
) == OMPIC_CONTROL
) {
75 int src_cpu
= OMPIC_SRC_CPU(addr
);
77 s
->cpus
[src_cpu
].control
= data
;
79 if (data
& OMPIC_CTRL_IRQ_GEN
) {
80 int dst_cpu
= OMPIC_CTRL_DST(data
);
82 s
->cpus
[dst_cpu
].status
= OMPIC_STATUS_IRQ_PENDING
|
83 OMPIC_STATUS_SRC(src_cpu
) |
84 OMPIC_STATUS_DATA(data
);
86 qemu_irq_raise(s
->cpus
[dst_cpu
].irq
);
88 if (data
& OMPIC_CTRL_IRQ_ACK
) {
89 s
->cpus
[src_cpu
].status
&= ~OMPIC_STATUS_IRQ_PENDING
;
90 qemu_irq_lower(s
->cpus
[src_cpu
].irq
);
95 static const MemoryRegionOps ompic_ops
= {
98 .endianness
= DEVICE_NATIVE_ENDIAN
,
100 .max_access_size
= 8,
104 static void or1k_ompic_init(Object
*obj
)
106 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
107 OR1KOMPICState
*s
= OR1K_OMPIC(obj
);
109 memory_region_init_io(&s
->mr
, OBJECT(s
), &ompic_ops
, s
,
110 "or1k-ompic", OMPIC_ADDRSPACE_SZ
);
111 sysbus_init_mmio(sbd
, &s
->mr
);
114 static void or1k_ompic_realize(DeviceState
*dev
, Error
**errp
)
116 OR1KOMPICState
*s
= OR1K_OMPIC(dev
);
117 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
120 if (s
->num_cpus
> OMPIC_MAX_CPUS
) {
121 error_setg(errp
, "Exceeded maximum CPUs %d", s
->num_cpus
);
124 /* Init IRQ sources for all CPUs */
125 for (i
= 0; i
< s
->num_cpus
; i
++) {
126 sysbus_init_irq(sbd
, &s
->cpus
[i
].irq
);
130 static Property or1k_ompic_properties
[] = {
131 DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState
, num_cpus
, 1),
132 DEFINE_PROP_END_OF_LIST(),
135 static const VMStateDescription vmstate_or1k_ompic_cpu
= {
136 .name
= "or1k_ompic_cpu",
138 .minimum_version_id
= 1,
139 .fields
= (VMStateField
[]) {
140 VMSTATE_UINT32(status
, OR1KOMPICCPUState
),
141 VMSTATE_UINT32(control
, OR1KOMPICCPUState
),
142 VMSTATE_END_OF_LIST()
146 static const VMStateDescription vmstate_or1k_ompic
= {
147 .name
= TYPE_OR1K_OMPIC
,
149 .minimum_version_id
= 1,
150 .fields
= (VMStateField
[]) {
151 VMSTATE_STRUCT_ARRAY(cpus
, OR1KOMPICState
, OMPIC_MAX_CPUS
, 1,
152 vmstate_or1k_ompic_cpu
, OR1KOMPICCPUState
),
153 VMSTATE_UINT32(num_cpus
, OR1KOMPICState
),
154 VMSTATE_END_OF_LIST()
158 static void or1k_ompic_class_init(ObjectClass
*klass
, void *data
)
160 DeviceClass
*dc
= DEVICE_CLASS(klass
);
162 dc
->props
= or1k_ompic_properties
;
163 dc
->realize
= or1k_ompic_realize
;
164 dc
->vmsd
= &vmstate_or1k_ompic
;
167 static const TypeInfo or1k_ompic_info
= {
168 .name
= TYPE_OR1K_OMPIC
,
169 .parent
= TYPE_SYS_BUS_DEVICE
,
170 .instance_size
= sizeof(OR1KOMPICState
),
171 .instance_init
= or1k_ompic_init
,
172 .class_init
= or1k_ompic_class_init
,
175 static void or1k_ompic_register_types(void)
177 type_register_static(&or1k_ompic_info
);
180 type_init(or1k_ompic_register_types
)