hw/intc/arm_gicv2m.c

   1 /*
   2  *  GICv2m extension for MSI/MSI-x support with a GICv2-based system
   3  *
   4  * Copyright (C) 2015 Linaro, All rights reserved.
   5  *
   6  * Author: Christoffer Dall <christoffer.dall@linaro.org>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /* This file implements an emulated GICv2m widget as described in the ARM
  23  * Server Base System Architecture (SBSA) specification Version 2.2
  24  * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined
  25  * identification registers and with a single non-secure MSI register frame.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/pci/msi.h"
  32 #include "sysemu/kvm.h"
  33 #include "qemu/log.h"
  34 #include "qemu/module.h"
  35
  36 #define TYPE_ARM_GICV2M "arm-gicv2m"
  37 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M)
  38
  39 #define GICV2M_NUM_SPI_MAX 128
  40
  41 #define V2M_MSI_TYPER           0x008
  42 #define V2M_MSI_SETSPI_NS       0x040
  43 #define V2M_MSI_IIDR            0xFCC
  44 #define V2M_IIDR0               0xFD0
  45 #define V2M_IIDR11              0xFFC
  46
  47 #define PRODUCT_ID_QEMU         0x51 /* ASCII code Q */
  48
  49 typedef struct ARMGICv2mState {
  50     SysBusDevice parent_obj;
  51
  52     MemoryRegion iomem;
  53     qemu_irq spi[GICV2M_NUM_SPI_MAX];
  54
  55     uint32_t base_spi;
  56     uint32_t num_spi;
  57 } ARMGICv2mState;
  58
  59 static void gicv2m_set_irq(void *opaque, int irq)
  60 {
  61     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  62
  63     qemu_irq_pulse(s->spi[irq]);
  64 }
  65
  66 static uint64_t gicv2m_read(void *opaque, hwaddr offset,
  67                             unsigned size)
  68 {
  69     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  70     uint32_t val;
  71
  72     if (size != 4) {
  73         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size);
  74         return 0;
  75     }
  76
  77     switch (offset) {
  78     case V2M_MSI_TYPER:
  79         val = (s->base_spi + 32) << 16;
  80         val |= s->num_spi;
  81         return val;
  82     case V2M_MSI_IIDR:
  83         /* We don't have any valid implementor so we leave that field as zero
  84          * and we return 0 in the arch revision as per the spec.
  85          */
  86         return (PRODUCT_ID_QEMU << 20);
  87     case V2M_IIDR0 ... V2M_IIDR11:
  88         /* We do not implement any optional identification registers and the
  89          * mandatory MSI_PIDR2 register reads as 0x0, so we capture all
  90          * implementation defined registers here.
  91          */
  92         return 0;
  93     default:
  94         qemu_log_mask(LOG_GUEST_ERROR,
  95                       "gicv2m_read: Bad offset %x\n", (int)offset);
  96         return 0;
  97     }
  98 }
  99
 100 static void gicv2m_write(void *opaque, hwaddr offset,
 101                         uint64_t value, unsigned size)
 102 {
 103     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
 104
 105     if (size != 2 && size != 4) {
 106         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size);
 107         return;
 108     }
 109
 110     switch (offset) {
 111     case V2M_MSI_SETSPI_NS: {
 112         int spi;
 113
 114         spi = (value & 0x3ff) - (s->base_spi + 32);
 115         if (spi >= 0 && spi < s->num_spi) {
 116             gicv2m_set_irq(s, spi);
 117         }
 118         return;
 119     }
 120     default:
 121         qemu_log_mask(LOG_GUEST_ERROR,
 122                       "gicv2m_write: Bad offset %x\n", (int)offset);
 123     }
 124 }
 125
 126 static const MemoryRegionOps gicv2m_ops = {
 127     .read = gicv2m_read,
 128     .write = gicv2m_write,
 129     .endianness = DEVICE_LITTLE_ENDIAN,
 130 };
 131
 132 static void gicv2m_realize(DeviceState *dev, Error **errp)
 133 {
 134     ARMGICv2mState *s = ARM_GICV2M(dev);
 135     int i;
 136
 137     if (s->num_spi > GICV2M_NUM_SPI_MAX) {
 138         error_setg(errp,
 139                    "requested %u SPIs exceeds GICv2m frame maximum %d",
 140                    s->num_spi, GICV2M_NUM_SPI_MAX);
 141         return;
 142     }
 143
 144     if (s->base_spi + 32 > 1020 - s->num_spi) {
 145         error_setg(errp,
 146                    "requested base SPI %u+%u exceeds max. number 1020",
 147                    s->base_spi + 32, s->num_spi);
 148         return;
 149     }
 150
 151     for (i = 0; i < s->num_spi; i++) {
 152         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]);
 153     }
 154
 155     msi_nonbroken = true;
 156     kvm_gsi_direct_mapping = true;
 157     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 158 }
 159
 160 static void gicv2m_init(Object *obj)
 161 {
 162     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 163     ARMGICv2mState *s = ARM_GICV2M(obj);
 164
 165     memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s,
 166                           "gicv2m", 0x1000);
 167     sysbus_init_mmio(sbd, &s->iomem);
 168 }
 169
 170 static Property gicv2m_properties[] = {
 171     DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),
 172     DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64),
 173     DEFINE_PROP_END_OF_LIST(),
 174 };
 175
 176 static void gicv2m_class_init(ObjectClass *klass, void *data)
 177 {
 178     DeviceClass *dc = DEVICE_CLASS(klass);
 179
 180     dc->props = gicv2m_properties;
 181     dc->realize = gicv2m_realize;
 182 }
 183
 184 static const TypeInfo gicv2m_info = {
 185     .name          = TYPE_ARM_GICV2M,
 186     .parent        = TYPE_SYS_BUS_DEVICE,
 187     .instance_size = sizeof(ARMGICv2mState),
 188     .instance_init = gicv2m_init,
 189     .class_init    = gicv2m_class_init,
 190 };
 191
 192 static void gicv2m_register_types(void)
 193 {
 194     type_register_static(&gicv2m_info);
 195 }
 196
 197 type_init(gicv2m_register_types)