hw/cpu/a15mpcore.c

   1 /*
   2  * Cortex-A15MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2012 Linaro Limited.
   5  * Written by Peter Maydell.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/module.h"
  24 #include "hw/cpu/a15mpcore.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_arm.h"
  27
  28 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  29 {
  30     A15MPPrivState *s = (A15MPPrivState *)opaque;
  31
  32     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  33 }
  34
  35 static void a15mp_priv_initfn(Object *obj)
  36 {
  37     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  38     A15MPPrivState *s = A15MPCORE_PRIV(obj);
  39
  40     memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  41     sysbus_init_mmio(sbd, &s->container);
  42
  43     sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
  44                           gic_class_name());
  45     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
  46 }
  47
  48 static void a15mp_priv_realize(DeviceState *dev, Error **errp)
  49 {
  50     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  51     A15MPPrivState *s = A15MPCORE_PRIV(dev);
  52     DeviceState *gicdev;
  53     SysBusDevice *busdev;
  54     int i;
  55     Error *err = NULL;
  56     bool has_el3;
  57     bool has_el2 = false;
  58     Object *cpuobj;
  59
  60     gicdev = DEVICE(&s->gic);
  61     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  62     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  63
  64     if (!kvm_irqchip_in_kernel()) {
  65         /* Make the GIC's TZ support match the CPUs. We assume that
  66          * either all the CPUs have TZ, or none do.
  67          */
  68         cpuobj = OBJECT(qemu_get_cpu(0));
  69         has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  70             object_property_get_bool(cpuobj, "has_el3", &error_abort);
  71         qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  72         /* Similarly for virtualization support */
  73         has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
  74             object_property_get_bool(cpuobj, "has_el2", &error_abort);
  75         qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
  76     }
  77
  78     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  79     if (err != NULL) {
  80         error_propagate(errp, err);
  81         return;
  82     }
  83     busdev = SYS_BUS_DEVICE(&s->gic);
  84
  85     /* Pass through outbound IRQ lines from the GIC */
  86     sysbus_pass_irq(sbd, busdev);
  87
  88     /* Pass through inbound GPIO lines to the GIC */
  89     qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
  90
  91     /* Wire the outputs from each CPU's generic timer to the
  92      * appropriate GIC PPI inputs
  93      */
  94     for (i = 0; i < s->num_cpu; i++) {
  95         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  96         int ppibase = s->num_irq - 32 + i * 32;
  97         int irq;
  98         /* Mapping from the output timer irq lines from the CPU to the
  99          * GIC PPI inputs used on the A15:
 100          */
 101         const int timer_irq[] = {
 102             [GTIMER_PHYS] = 30,
 103             [GTIMER_VIRT] = 27,
 104             [GTIMER_HYP]  = 26,
 105             [GTIMER_SEC]  = 29,
 106         };
 107         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 108             qdev_connect_gpio_out(cpudev, irq,
 109                                   qdev_get_gpio_in(gicdev,
 110                                                    ppibase + timer_irq[irq]));
 111         }
 112         if (has_el2) {
 113             /* Connect the GIC maintenance interrupt to PPI ID 25 */
 114             sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
 115                                qdev_get_gpio_in(gicdev, ppibase + 25));
 116         }
 117     }
 118
 119     /* Memory map (addresses are offsets from PERIPHBASE):
 120      *  0x0000-0x0fff -- reserved
 121      *  0x1000-0x1fff -- GIC Distributor
 122      *  0x2000-0x3fff -- GIC CPU interface
 123      *  0x4000-0x4fff -- GIC virtual interface control for this CPU
 124      *  0x5000-0x51ff -- GIC virtual interface control for CPU 0
 125      *  0x5200-0x53ff -- GIC virtual interface control for CPU 1
 126      *  0x5400-0x55ff -- GIC virtual interface control for CPU 2
 127      *  0x5600-0x57ff -- GIC virtual interface control for CPU 3
 128      *  0x6000-0x7fff -- GIC virtual CPU interface
 129      */
 130     memory_region_add_subregion(&s->container, 0x1000,
 131                                 sysbus_mmio_get_region(busdev, 0));
 132     memory_region_add_subregion(&s->container, 0x2000,
 133                                 sysbus_mmio_get_region(busdev, 1));
 134     if (has_el2) {
 135         memory_region_add_subregion(&s->container, 0x4000,
 136                                     sysbus_mmio_get_region(busdev, 2));
 137         memory_region_add_subregion(&s->container, 0x6000,
 138                                     sysbus_mmio_get_region(busdev, 3));
 139         for (i = 0; i < s->num_cpu; i++) {
 140             hwaddr base = 0x5000 + i * 0x200;
 141             MemoryRegion *mr = sysbus_mmio_get_region(busdev,
 142                                                       4 + s->num_cpu + i);
 143             memory_region_add_subregion(&s->container, base, mr);
 144         }
 145     }
 146 }
 147
 148 static Property a15mp_priv_properties[] = {
 149     DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 150     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 151      * IRQ lines (with another 32 internal). We default to 128+32, which
 152      * is the number provided by the Cortex-A15MP test chip in the
 153      * Versatile Express A15 development board.
 154      * Other boards may differ and should set this property appropriately.
 155      */
 156     DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 157     DEFINE_PROP_END_OF_LIST(),
 158 };
 159
 160 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 161 {
 162     DeviceClass *dc = DEVICE_CLASS(klass);
 163
 164     dc->realize = a15mp_priv_realize;
 165     dc->props = a15mp_priv_properties;
 166     /* We currently have no savable state */
 167 }
 168
 169 static const TypeInfo a15mp_priv_info = {
 170     .name  = TYPE_A15MPCORE_PRIV,
 171     .parent = TYPE_SYS_BUS_DEVICE,
 172     .instance_size  = sizeof(A15MPPrivState),
 173     .instance_init = a15mp_priv_initfn,
 174     .class_init = a15mp_priv_class_init,
 175 };
 176
 177 static void a15mp_register_types(void)
 178 {
 179     type_register_static(&a15mp_priv_info);
 180 }
 181
 182 type_init(a15mp_register_types)