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s390x/virtio: use qemu_check_nic_model()
[qemu/ar7.git] / target-cris / translate.c
blob24299314d0924d361d17886d9f1c29df34562f40
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "cpu.h"
27 #include "disas/disas.h"
28 #include "tcg-op.h"
29 #include "exec/helper-proto.h"
30 #include "mmu.h"
31 #include "exec/cpu_ldst.h"
32 #include "crisv32-decode.h"
33
34 #include "exec/helper-gen.h"
35
36 #include "trace-tcg.h"
37
38
39 #define DISAS_CRIS 0
40 #if DISAS_CRIS
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
42 #else
43 # define LOG_DIS(...) do { } while (0)
44 #endif
45
46 #define D(x)
47 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
48 #define BUG_ON(x) ({if (x) BUG();})
49
50 #define DISAS_SWI 5
51
52 /* Used by the decoder. */
53 #define EXTRACT_FIELD(src, start, end) \
54 (((src) >> start) & ((1 << (end - start + 1)) - 1))
55
56 #define CC_MASK_NZ 0xc
57 #define CC_MASK_NZV 0xe
58 #define CC_MASK_NZVC 0xf
59 #define CC_MASK_RNZV 0x10e
60
61 static TCGv_ptr cpu_env;
62 static TCGv cpu_R[16];
63 static TCGv cpu_PR[16];
64 static TCGv cc_x;
65 static TCGv cc_src;
66 static TCGv cc_dest;
67 static TCGv cc_result;
68 static TCGv cc_op;
69 static TCGv cc_size;
70 static TCGv cc_mask;
71
72 static TCGv env_btaken;
73 static TCGv env_btarget;
74 static TCGv env_pc;
75
76 #include "exec/gen-icount.h"
77
78 /* This is the state at translation time. */
79 typedef struct DisasContext {
80 CRISCPU *cpu;
81 target_ulong pc, ppc;
82
83 /* Decoder. */
84 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
85 uint32_t ir;
86 uint32_t opcode;
87 unsigned int op1;
88 unsigned int op2;
89 unsigned int zsize, zzsize;
90 unsigned int mode;
91 unsigned int postinc;
92
93 unsigned int size;
94 unsigned int src;
95 unsigned int dst;
96 unsigned int cond;
97
98 int update_cc;
99 int cc_op;
100 int cc_size;
101 uint32_t cc_mask;
102
103 int cc_size_uptodate; /* -1 invalid or last written value. */
104
105 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
106 int flags_uptodate; /* Whether or not $ccs is up-to-date. */
107 int flagx_known; /* Whether or not flags_x has the x flag known at
108 translation time. */
109 int flags_x;
110
111 int clear_x; /* Clear x after this insn? */
112 int clear_prefix; /* Clear prefix after this insn? */
113 int clear_locked_irq; /* Clear the irq lockout. */
114 int cpustate_changed;
115 unsigned int tb_flags; /* tb dependent flags. */
116 int is_jmp;
117
118 #define JMP_NOJMP 0
119 #define JMP_DIRECT 1
120 #define JMP_DIRECT_CC 2
121 #define JMP_INDIRECT 3
122 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
123 uint32_t jmp_pc;
124
125 int delayed_branch;
126
127 struct TranslationBlock *tb;
128 int singlestep_enabled;
129 } DisasContext;
130
131 static void gen_BUG(DisasContext *dc, const char *file, int line)
132 {
133 fprintf(stderr, "BUG: pc=%x %s %d\n", dc->pc, file, line);
134 if (qemu_log_separate()) {
135 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
136 }
137 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
138 }
139
140 static const char *regnames[] =
141 {
142 "$r0", "$r1", "$r2", "$r3",
143 "$r4", "$r5", "$r6", "$r7",
144 "$r8", "$r9", "$r10", "$r11",
145 "$r12", "$r13", "$sp", "$acr",
146 };
147 static const char *pregnames[] =
148 {
149 "$bz", "$vr", "$pid", "$srs",
150 "$wz", "$exs", "$eda", "$mof",
151 "$dz", "$ebp", "$erp", "$srp",
152 "$nrp", "$ccs", "$usp", "$spc",
153 };
154
155 /* We need this table to handle preg-moves with implicit width. */
156 static int preg_sizes[] = {
157 1, /* bz. */
158 1, /* vr. */
159 4, /* pid. */
160 1, /* srs. */
161 2, /* wz. */
162 4, 4, 4,
163 4, 4, 4, 4,
164 4, 4, 4, 4,
165 };
166
167 #define t_gen_mov_TN_env(tn, member) \
168 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
169 #define t_gen_mov_env_TN(member, tn) \
170 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
171
172 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
173 {
174 assert(r >= 0 && r <= 15);
175 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
176 tcg_gen_mov_tl(tn, tcg_const_tl(0));
177 } else if (r == PR_VR) {
178 tcg_gen_mov_tl(tn, tcg_const_tl(32));
179 } else {
180 tcg_gen_mov_tl(tn, cpu_PR[r]);
181 }
182 }
183 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
184 {
185 assert(r >= 0 && r <= 15);
186 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
187 return;
188 } else if (r == PR_SRS) {
189 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
190 } else {
191 if (r == PR_PID) {
192 gen_helper_tlb_flush_pid(cpu_env, tn);
193 }
194 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
195 gen_helper_spc_write(cpu_env, tn);
196 } else if (r == PR_CCS) {
197 dc->cpustate_changed = 1;
198 }
199 tcg_gen_mov_tl(cpu_PR[r], tn);
200 }
201 }
202
203 /* Sign extend at translation time. */
204 static int sign_extend(unsigned int val, unsigned int width)
205 {
206 int sval;
207
208 /* LSL. */
209 val <<= 31 - width;
210 sval = val;
211 /* ASR. */
212 sval >>= 31 - width;
213 return sval;
214 }
215
216 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
217 unsigned int size, unsigned int sign)
218 {
219 int r;
220
221 switch (size) {
222 case 4:
223 {
224 r = cpu_ldl_code(env, addr);
225 break;
226 }
227 case 2:
228 {
229 if (sign) {
230 r = cpu_ldsw_code(env, addr);
231 } else {
232 r = cpu_lduw_code(env, addr);
233 }
234 break;
235 }
236 case 1:
237 {
238 if (sign) {
239 r = cpu_ldsb_code(env, addr);
240 } else {
241 r = cpu_ldub_code(env, addr);
242 }
243 break;
244 }
245 default:
246 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
247 break;
248 }
249 return r;
250 }
251
252 static void cris_lock_irq(DisasContext *dc)
253 {
254 dc->clear_locked_irq = 0;
255 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
256 }
257
258 static inline void t_gen_raise_exception(uint32_t index)
259 {
260 TCGv_i32 tmp = tcg_const_i32(index);
261 gen_helper_raise_exception(cpu_env, tmp);
262 tcg_temp_free_i32(tmp);
263 }
264
265 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
266 {
267 TCGv t0, t_31;
268
269 t0 = tcg_temp_new();
270 t_31 = tcg_const_tl(31);
271 tcg_gen_shl_tl(d, a, b);
272
273 tcg_gen_sub_tl(t0, t_31, b);
274 tcg_gen_sar_tl(t0, t0, t_31);
275 tcg_gen_and_tl(t0, t0, d);
276 tcg_gen_xor_tl(d, d, t0);
277 tcg_temp_free(t0);
278 tcg_temp_free(t_31);
279 }
280
281 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
282 {
283 TCGv t0, t_31;
284
285 t0 = tcg_temp_new();
286 t_31 = tcg_temp_new();
287 tcg_gen_shr_tl(d, a, b);
288
289 tcg_gen_movi_tl(t_31, 31);
290 tcg_gen_sub_tl(t0, t_31, b);
291 tcg_gen_sar_tl(t0, t0, t_31);
292 tcg_gen_and_tl(t0, t0, d);
293 tcg_gen_xor_tl(d, d, t0);
294 tcg_temp_free(t0);
295 tcg_temp_free(t_31);
296 }
297
298 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
299 {
300 TCGv t0, t_31;
301
302 t0 = tcg_temp_new();
303 t_31 = tcg_temp_new();
304 tcg_gen_sar_tl(d, a, b);
305
306 tcg_gen_movi_tl(t_31, 31);
307 tcg_gen_sub_tl(t0, t_31, b);
308 tcg_gen_sar_tl(t0, t0, t_31);
309 tcg_gen_or_tl(d, d, t0);
310 tcg_temp_free(t0);
311 tcg_temp_free(t_31);
312 }
313
314 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
315 {
316 TCGv t = tcg_temp_new();
317
318 /*
319 * d <<= 1
320 * if (d >= s)
321 * d -= s;
322 */
323 tcg_gen_shli_tl(d, a, 1);
324 tcg_gen_sub_tl(t, d, b);
325 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
326 tcg_temp_free(t);
327 }
328
329 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
330 {
331 TCGv t;
332
333 /*
334 * d <<= 1
335 * if (n)
336 * d += s;
337 */
338 t = tcg_temp_new();
339 tcg_gen_shli_tl(d, a, 1);
340 tcg_gen_shli_tl(t, ccs, 31 - 3);
341 tcg_gen_sari_tl(t, t, 31);
342 tcg_gen_and_tl(t, t, b);
343 tcg_gen_add_tl(d, d, t);
344 tcg_temp_free(t);
345 }
346
347 /* Extended arithmetics on CRIS. */
348 static inline void t_gen_add_flag(TCGv d, int flag)
349 {
350 TCGv c;
351
352 c = tcg_temp_new();
353 t_gen_mov_TN_preg(c, PR_CCS);
354 /* Propagate carry into d. */
355 tcg_gen_andi_tl(c, c, 1 << flag);
356 if (flag) {
357 tcg_gen_shri_tl(c, c, flag);
358 }
359 tcg_gen_add_tl(d, d, c);
360 tcg_temp_free(c);
361 }
362
363 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
364 {
365 if (dc->flagx_known) {
366 if (dc->flags_x) {
367 TCGv c;
368
369 c = tcg_temp_new();
370 t_gen_mov_TN_preg(c, PR_CCS);
371 /* C flag is already at bit 0. */
372 tcg_gen_andi_tl(c, c, C_FLAG);
373 tcg_gen_add_tl(d, d, c);
374 tcg_temp_free(c);
375 }
376 } else {
377 TCGv x, c;
378
379 x = tcg_temp_new();
380 c = tcg_temp_new();
381 t_gen_mov_TN_preg(x, PR_CCS);
382 tcg_gen_mov_tl(c, x);
383
384 /* Propagate carry into d if X is set. Branch free. */
385 tcg_gen_andi_tl(c, c, C_FLAG);
386 tcg_gen_andi_tl(x, x, X_FLAG);
387 tcg_gen_shri_tl(x, x, 4);
388
389 tcg_gen_and_tl(x, x, c);
390 tcg_gen_add_tl(d, d, x);
391 tcg_temp_free(x);
392 tcg_temp_free(c);
393 }
394 }
395
396 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
397 {
398 if (dc->flagx_known) {
399 if (dc->flags_x) {
400 TCGv c;
401
402 c = tcg_temp_new();
403 t_gen_mov_TN_preg(c, PR_CCS);
404 /* C flag is already at bit 0. */
405 tcg_gen_andi_tl(c, c, C_FLAG);
406 tcg_gen_sub_tl(d, d, c);
407 tcg_temp_free(c);
408 }
409 } else {
410 TCGv x, c;
411
412 x = tcg_temp_new();
413 c = tcg_temp_new();
414 t_gen_mov_TN_preg(x, PR_CCS);
415 tcg_gen_mov_tl(c, x);
416
417 /* Propagate carry into d if X is set. Branch free. */
418 tcg_gen_andi_tl(c, c, C_FLAG);
419 tcg_gen_andi_tl(x, x, X_FLAG);
420 tcg_gen_shri_tl(x, x, 4);
421
422 tcg_gen_and_tl(x, x, c);
423 tcg_gen_sub_tl(d, d, x);
424 tcg_temp_free(x);
425 tcg_temp_free(c);
426 }
427 }
428
429 /* Swap the two bytes within each half word of the s operand.
430 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
431 static inline void t_gen_swapb(TCGv d, TCGv s)
432 {
433 TCGv t, org_s;
434
435 t = tcg_temp_new();
436 org_s = tcg_temp_new();
437
438 /* d and s may refer to the same object. */
439 tcg_gen_mov_tl(org_s, s);
440 tcg_gen_shli_tl(t, org_s, 8);
441 tcg_gen_andi_tl(d, t, 0xff00ff00);
442 tcg_gen_shri_tl(t, org_s, 8);
443 tcg_gen_andi_tl(t, t, 0x00ff00ff);
444 tcg_gen_or_tl(d, d, t);
445 tcg_temp_free(t);
446 tcg_temp_free(org_s);
447 }
448
449 /* Swap the halfwords of the s operand. */
450 static inline void t_gen_swapw(TCGv d, TCGv s)
451 {
452 TCGv t;
453 /* d and s refer the same object. */
454 t = tcg_temp_new();
455 tcg_gen_mov_tl(t, s);
456 tcg_gen_shli_tl(d, t, 16);
457 tcg_gen_shri_tl(t, t, 16);
458 tcg_gen_or_tl(d, d, t);
459 tcg_temp_free(t);
460 }
461
462 /* Reverse the within each byte.
463 T0 = (((T0 << 7) & 0x80808080) |
464 ((T0 << 5) & 0x40404040) |
465 ((T0 << 3) & 0x20202020) |
466 ((T0 << 1) & 0x10101010) |
467 ((T0 >> 1) & 0x08080808) |
468 ((T0 >> 3) & 0x04040404) |
469 ((T0 >> 5) & 0x02020202) |
470 ((T0 >> 7) & 0x01010101));
471 */
472 static inline void t_gen_swapr(TCGv d, TCGv s)
473 {
474 struct {
475 int shift; /* LSL when positive, LSR when negative. */
476 uint32_t mask;
477 } bitrev[] = {
478 {7, 0x80808080},
479 {5, 0x40404040},
480 {3, 0x20202020},
481 {1, 0x10101010},
482 {-1, 0x08080808},
483 {-3, 0x04040404},
484 {-5, 0x02020202},
485 {-7, 0x01010101}
486 };
487 int i;
488 TCGv t, org_s;
489
490 /* d and s refer the same object. */
491 t = tcg_temp_new();
492 org_s = tcg_temp_new();
493 tcg_gen_mov_tl(org_s, s);
494
495 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
496 tcg_gen_andi_tl(d, t, bitrev[0].mask);
497 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
498 if (bitrev[i].shift >= 0) {
499 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
500 } else {
501 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
502 }
503 tcg_gen_andi_tl(t, t, bitrev[i].mask);
504 tcg_gen_or_tl(d, d, t);
505 }
506 tcg_temp_free(t);
507 tcg_temp_free(org_s);
508 }
509
510 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
511 {
512 TCGLabel *l1 = gen_new_label();
513
514 /* Conditional jmp. */
515 tcg_gen_mov_tl(env_pc, pc_false);
516 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
517 tcg_gen_mov_tl(env_pc, pc_true);
518 gen_set_label(l1);
519 }
520
521 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
522 {
523 TranslationBlock *tb;
524 tb = dc->tb;
525 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
526 tcg_gen_goto_tb(n);
527 tcg_gen_movi_tl(env_pc, dest);
528 tcg_gen_exit_tb((uintptr_t)tb + n);
529 } else {
530 tcg_gen_movi_tl(env_pc, dest);
531 tcg_gen_exit_tb(0);
532 }
533 }
534
535 static inline void cris_clear_x_flag(DisasContext *dc)
536 {
537 if (dc->flagx_known && dc->flags_x) {
538 dc->flags_uptodate = 0;
539 }
540
541 dc->flagx_known = 1;
542 dc->flags_x = 0;
543 }
544
545 static void cris_flush_cc_state(DisasContext *dc)
546 {
547 if (dc->cc_size_uptodate != dc->cc_size) {
548 tcg_gen_movi_tl(cc_size, dc->cc_size);
549 dc->cc_size_uptodate = dc->cc_size;
550 }
551 tcg_gen_movi_tl(cc_op, dc->cc_op);
552 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
553 }
554
555 static void cris_evaluate_flags(DisasContext *dc)
556 {
557 if (dc->flags_uptodate) {
558 return;
559 }
560
561 cris_flush_cc_state(dc);
562
563 switch (dc->cc_op) {
564 case CC_OP_MCP:
565 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
566 cpu_PR[PR_CCS], cc_src,
567 cc_dest, cc_result);
568 break;
569 case CC_OP_MULS:
570 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
571 cpu_PR[PR_CCS], cc_result,
572 cpu_PR[PR_MOF]);
573 break;
574 case CC_OP_MULU:
575 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
576 cpu_PR[PR_CCS], cc_result,
577 cpu_PR[PR_MOF]);
578 break;
579 case CC_OP_MOVE:
580 case CC_OP_AND:
581 case CC_OP_OR:
582 case CC_OP_XOR:
583 case CC_OP_ASR:
584 case CC_OP_LSR:
585 case CC_OP_LSL:
586 switch (dc->cc_size) {
587 case 4:
588 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
589 cpu_env, cpu_PR[PR_CCS], cc_result);
590 break;
591 case 2:
592 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
593 cpu_env, cpu_PR[PR_CCS], cc_result);
594 break;
595 default:
596 gen_helper_evaluate_flags(cpu_env);
597 break;
598 }
599 break;
600 case CC_OP_FLAGS:
601 /* live. */
602 break;
603 case CC_OP_SUB:
604 case CC_OP_CMP:
605 if (dc->cc_size == 4) {
606 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
607 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
608 } else {
609 gen_helper_evaluate_flags(cpu_env);
610 }
611
612 break;
613 default:
614 switch (dc->cc_size) {
615 case 4:
616 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
617 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
618 break;
619 default:
620 gen_helper_evaluate_flags(cpu_env);
621 break;
622 }
623 break;
624 }
625
626 if (dc->flagx_known) {
627 if (dc->flags_x) {
628 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
629 } else if (dc->cc_op == CC_OP_FLAGS) {
630 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
631 }
632 }
633 dc->flags_uptodate = 1;
634 }
635
636 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
637 {
638 uint32_t ovl;
639
640 if (!mask) {
641 dc->update_cc = 0;
642 return;
643 }
644
645 /* Check if we need to evaluate the condition codes due to
646 CC overlaying. */
647 ovl = (dc->cc_mask ^ mask) & ~mask;
648 if (ovl) {
649 /* TODO: optimize this case. It trigs all the time. */
650 cris_evaluate_flags(dc);
651 }
652 dc->cc_mask = mask;
653 dc->update_cc = 1;
654 }
655
656 static void cris_update_cc_op(DisasContext *dc, int op, int size)
657 {
658 dc->cc_op = op;
659 dc->cc_size = size;
660 dc->flags_uptodate = 0;
661 }
662
663 static inline void cris_update_cc_x(DisasContext *dc)
664 {
665 /* Save the x flag state at the time of the cc snapshot. */
666 if (dc->flagx_known) {
667 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
668 return;
669 }
670 tcg_gen_movi_tl(cc_x, dc->flags_x);
671 dc->cc_x_uptodate = 2 | dc->flags_x;
672 } else {
673 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
674 dc->cc_x_uptodate = 1;
675 }
676 }
677
678 /* Update cc prior to executing ALU op. Needs source operands untouched. */
679 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
680 TCGv dst, TCGv src, int size)
681 {
682 if (dc->update_cc) {
683 cris_update_cc_op(dc, op, size);
684 tcg_gen_mov_tl(cc_src, src);
685
686 if (op != CC_OP_MOVE
687 && op != CC_OP_AND
688 && op != CC_OP_OR
689 && op != CC_OP_XOR
690 && op != CC_OP_ASR
691 && op != CC_OP_LSR
692 && op != CC_OP_LSL) {
693 tcg_gen_mov_tl(cc_dest, dst);
694 }
695
696 cris_update_cc_x(dc);
697 }
698 }
699
700 /* Update cc after executing ALU op. needs the result. */
701 static inline void cris_update_result(DisasContext *dc, TCGv res)
702 {
703 if (dc->update_cc) {
704 tcg_gen_mov_tl(cc_result, res);
705 }
706 }
707
708 /* Returns one if the write back stage should execute. */
709 static void cris_alu_op_exec(DisasContext *dc, int op,
710 TCGv dst, TCGv a, TCGv b, int size)
711 {
712 /* Emit the ALU insns. */
713 switch (op) {
714 case CC_OP_ADD:
715 tcg_gen_add_tl(dst, a, b);
716 /* Extended arithmetics. */
717 t_gen_addx_carry(dc, dst);
718 break;
719 case CC_OP_ADDC:
720 tcg_gen_add_tl(dst, a, b);
721 t_gen_add_flag(dst, 0); /* C_FLAG. */
722 break;
723 case CC_OP_MCP:
724 tcg_gen_add_tl(dst, a, b);
725 t_gen_add_flag(dst, 8); /* R_FLAG. */
726 break;
727 case CC_OP_SUB:
728 tcg_gen_sub_tl(dst, a, b);
729 /* Extended arithmetics. */
730 t_gen_subx_carry(dc, dst);
731 break;
732 case CC_OP_MOVE:
733 tcg_gen_mov_tl(dst, b);
734 break;
735 case CC_OP_OR:
736 tcg_gen_or_tl(dst, a, b);
737 break;
738 case CC_OP_AND:
739 tcg_gen_and_tl(dst, a, b);
740 break;
741 case CC_OP_XOR:
742 tcg_gen_xor_tl(dst, a, b);
743 break;
744 case CC_OP_LSL:
745 t_gen_lsl(dst, a, b);
746 break;
747 case CC_OP_LSR:
748 t_gen_lsr(dst, a, b);
749 break;
750 case CC_OP_ASR:
751 t_gen_asr(dst, a, b);
752 break;
753 case CC_OP_NEG:
754 tcg_gen_neg_tl(dst, b);
755 /* Extended arithmetics. */
756 t_gen_subx_carry(dc, dst);
757 break;
758 case CC_OP_LZ:
759 gen_helper_lz(dst, b);
760 break;
761 case CC_OP_MULS:
762 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
763 break;
764 case CC_OP_MULU:
765 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
766 break;
767 case CC_OP_DSTEP:
768 t_gen_cris_dstep(dst, a, b);
769 break;
770 case CC_OP_MSTEP:
771 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
772 break;
773 case CC_OP_BOUND:
774 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
775 break;
776 case CC_OP_CMP:
777 tcg_gen_sub_tl(dst, a, b);
778 /* Extended arithmetics. */
779 t_gen_subx_carry(dc, dst);
780 break;
781 default:
782 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
783 BUG();
784 break;
785 }
786
787 if (size == 1) {
788 tcg_gen_andi_tl(dst, dst, 0xff);
789 } else if (size == 2) {
790 tcg_gen_andi_tl(dst, dst, 0xffff);
791 }
792 }
793
794 static void cris_alu(DisasContext *dc, int op,
795 TCGv d, TCGv op_a, TCGv op_b, int size)
796 {
797 TCGv tmp;
798 int writeback;
799
800 writeback = 1;
801
802 if (op == CC_OP_CMP) {
803 tmp = tcg_temp_new();
804 writeback = 0;
805 } else if (size == 4) {
806 tmp = d;
807 writeback = 0;
808 } else {
809 tmp = tcg_temp_new();
810 }
811
812
813 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
814 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
815 cris_update_result(dc, tmp);
816
817 /* Writeback. */
818 if (writeback) {
819 if (size == 1) {
820 tcg_gen_andi_tl(d, d, ~0xff);
821 } else {
822 tcg_gen_andi_tl(d, d, ~0xffff);
823 }
824 tcg_gen_or_tl(d, d, tmp);
825 }
826 if (!TCGV_EQUAL(tmp, d)) {
827 tcg_temp_free(tmp);
828 }
829 }
830
831 static int arith_cc(DisasContext *dc)
832 {
833 if (dc->update_cc) {
834 switch (dc->cc_op) {
835 case CC_OP_ADDC: return 1;
836 case CC_OP_ADD: return 1;
837 case CC_OP_SUB: return 1;
838 case CC_OP_DSTEP: return 1;
839 case CC_OP_LSL: return 1;
840 case CC_OP_LSR: return 1;
841 case CC_OP_ASR: return 1;
842 case CC_OP_CMP: return 1;
843 case CC_OP_NEG: return 1;
844 case CC_OP_OR: return 1;
845 case CC_OP_AND: return 1;
846 case CC_OP_XOR: return 1;
847 case CC_OP_MULU: return 1;
848 case CC_OP_MULS: return 1;
849 default:
850 return 0;
851 }
852 }
853 return 0;
854 }
855
856 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
857 {
858 int arith_opt, move_opt;
859
860 /* TODO: optimize more condition codes. */
861
862 /*
863 * If the flags are live, we've gotta look into the bits of CCS.
864 * Otherwise, if we just did an arithmetic operation we try to
865 * evaluate the condition code faster.
866 *
867 * When this function is done, T0 should be non-zero if the condition
868 * code is true.
869 */
870 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
871 move_opt = (dc->cc_op == CC_OP_MOVE);
872 switch (cond) {
873 case CC_EQ:
874 if ((arith_opt || move_opt)
875 && dc->cc_x_uptodate != (2 | X_FLAG)) {
876 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
877 cc_result, tcg_const_tl(0));
878 } else {
879 cris_evaluate_flags(dc);
880 tcg_gen_andi_tl(cc,
881 cpu_PR[PR_CCS], Z_FLAG);
882 }
883 break;
884 case CC_NE:
885 if ((arith_opt || move_opt)
886 && dc->cc_x_uptodate != (2 | X_FLAG)) {
887 tcg_gen_mov_tl(cc, cc_result);
888 } else {
889 cris_evaluate_flags(dc);
890 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
891 Z_FLAG);
892 tcg_gen_andi_tl(cc, cc, Z_FLAG);
893 }
894 break;
895 case CC_CS:
896 cris_evaluate_flags(dc);
897 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
898 break;
899 case CC_CC:
900 cris_evaluate_flags(dc);
901 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
902 tcg_gen_andi_tl(cc, cc, C_FLAG);
903 break;
904 case CC_VS:
905 cris_evaluate_flags(dc);
906 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
907 break;
908 case CC_VC:
909 cris_evaluate_flags(dc);
910 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
911 V_FLAG);
912 tcg_gen_andi_tl(cc, cc, V_FLAG);
913 break;
914 case CC_PL:
915 if (arith_opt || move_opt) {
916 int bits = 31;
917
918 if (dc->cc_size == 1) {
919 bits = 7;
920 } else if (dc->cc_size == 2) {
921 bits = 15;
922 }
923
924 tcg_gen_shri_tl(cc, cc_result, bits);
925 tcg_gen_xori_tl(cc, cc, 1);
926 } else {
927 cris_evaluate_flags(dc);
928 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
929 N_FLAG);
930 tcg_gen_andi_tl(cc, cc, N_FLAG);
931 }
932 break;
933 case CC_MI:
934 if (arith_opt || move_opt) {
935 int bits = 31;
936
937 if (dc->cc_size == 1) {
938 bits = 7;
939 } else if (dc->cc_size == 2) {
940 bits = 15;
941 }
942
943 tcg_gen_shri_tl(cc, cc_result, bits);
944 tcg_gen_andi_tl(cc, cc, 1);
945 } else {
946 cris_evaluate_flags(dc);
947 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
948 N_FLAG);
949 }
950 break;
951 case CC_LS:
952 cris_evaluate_flags(dc);
953 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
954 C_FLAG | Z_FLAG);
955 break;
956 case CC_HI:
957 cris_evaluate_flags(dc);
958 {
959 TCGv tmp;
960
961 tmp = tcg_temp_new();
962 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
963 C_FLAG | Z_FLAG);
964 /* Overlay the C flag on top of the Z. */
965 tcg_gen_shli_tl(cc, tmp, 2);
966 tcg_gen_and_tl(cc, tmp, cc);
967 tcg_gen_andi_tl(cc, cc, Z_FLAG);
968
969 tcg_temp_free(tmp);
970 }
971 break;
972 case CC_GE:
973 cris_evaluate_flags(dc);
974 /* Overlay the V flag on top of the N. */
975 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
976 tcg_gen_xor_tl(cc,
977 cpu_PR[PR_CCS], cc);
978 tcg_gen_andi_tl(cc, cc, N_FLAG);
979 tcg_gen_xori_tl(cc, cc, N_FLAG);
980 break;
981 case CC_LT:
982 cris_evaluate_flags(dc);
983 /* Overlay the V flag on top of the N. */
984 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
985 tcg_gen_xor_tl(cc,
986 cpu_PR[PR_CCS], cc);
987 tcg_gen_andi_tl(cc, cc, N_FLAG);
988 break;
989 case CC_GT:
990 cris_evaluate_flags(dc);
991 {
992 TCGv n, z;
993
994 n = tcg_temp_new();
995 z = tcg_temp_new();
996
997 /* To avoid a shift we overlay everything on
998 the V flag. */
999 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1000 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1001 /* invert Z. */
1002 tcg_gen_xori_tl(z, z, 2);
1003
1004 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1005 tcg_gen_xori_tl(n, n, 2);
1006 tcg_gen_and_tl(cc, z, n);
1007 tcg_gen_andi_tl(cc, cc, 2);
1008
1009 tcg_temp_free(n);
1010 tcg_temp_free(z);
1011 }
1012 break;
1013 case CC_LE:
1014 cris_evaluate_flags(dc);
1015 {
1016 TCGv n, z;
1017
1018 n = tcg_temp_new();
1019 z = tcg_temp_new();
1020
1021 /* To avoid a shift we overlay everything on
1022 the V flag. */
1023 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1024 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1025
1026 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1027 tcg_gen_or_tl(cc, z, n);
1028 tcg_gen_andi_tl(cc, cc, 2);
1029
1030 tcg_temp_free(n);
1031 tcg_temp_free(z);
1032 }
1033 break;
1034 case CC_P:
1035 cris_evaluate_flags(dc);
1036 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1037 break;
1038 case CC_A:
1039 tcg_gen_movi_tl(cc, 1);
1040 break;
1041 default:
1042 BUG();
1043 break;
1044 };
1045 }
1046
1047 static void cris_store_direct_jmp(DisasContext *dc)
1048 {
1049 /* Store the direct jmp state into the cpu-state. */
1050 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1051 if (dc->jmp == JMP_DIRECT) {
1052 tcg_gen_movi_tl(env_btaken, 1);
1053 }
1054 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1055 dc->jmp = JMP_INDIRECT;
1056 }
1057 }
1058
1059 static void cris_prepare_cc_branch (DisasContext *dc,
1060 int offset, int cond)
1061 {
1062 /* This helps us re-schedule the micro-code to insns in delay-slots
1063 before the actual jump. */
1064 dc->delayed_branch = 2;
1065 dc->jmp = JMP_DIRECT_CC;
1066 dc->jmp_pc = dc->pc + offset;
1067
1068 gen_tst_cc(dc, env_btaken, cond);
1069 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1070 }
1071
1072
1073 /* jumps, when the dest is in a live reg for example. Direct should be set
1074 when the dest addr is constant to allow tb chaining. */
1075 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1076 {
1077 /* This helps us re-schedule the micro-code to insns in delay-slots
1078 before the actual jump. */
1079 dc->delayed_branch = 2;
1080 dc->jmp = type;
1081 if (type == JMP_INDIRECT) {
1082 tcg_gen_movi_tl(env_btaken, 1);
1083 }
1084 }
1085
1086 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1087 {
1088 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1089
1090 /* If we get a fault on a delayslot we must keep the jmp state in
1091 the cpu-state to be able to re-execute the jmp. */
1092 if (dc->delayed_branch == 1) {
1093 cris_store_direct_jmp(dc);
1094 }
1095
1096 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1097 }
1098
1099 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1100 unsigned int size, int sign)
1101 {
1102 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1103
1104 /* If we get a fault on a delayslot we must keep the jmp state in
1105 the cpu-state to be able to re-execute the jmp. */
1106 if (dc->delayed_branch == 1) {
1107 cris_store_direct_jmp(dc);
1108 }
1109
1110 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1111 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1112 }
1113
1114 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1115 unsigned int size)
1116 {
1117 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1118
1119 /* If we get a fault on a delayslot we must keep the jmp state in
1120 the cpu-state to be able to re-execute the jmp. */
1121 if (dc->delayed_branch == 1) {
1122 cris_store_direct_jmp(dc);
1123 }
1124
1125
1126 /* Conditional writes. We only support the kind were X and P are known
1127 at translation time. */
1128 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1129 dc->postinc = 0;
1130 cris_evaluate_flags(dc);
1131 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1132 return;
1133 }
1134
1135 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1136
1137 if (dc->flagx_known && dc->flags_x) {
1138 cris_evaluate_flags(dc);
1139 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1140 }
1141 }
1142
1143 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1144 {
1145 if (size == 1) {
1146 tcg_gen_ext8s_i32(d, s);
1147 } else if (size == 2) {
1148 tcg_gen_ext16s_i32(d, s);
1149 } else if (!TCGV_EQUAL(d, s)) {
1150 tcg_gen_mov_tl(d, s);
1151 }
1152 }
1153
1154 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1155 {
1156 if (size == 1) {
1157 tcg_gen_ext8u_i32(d, s);
1158 } else if (size == 2) {
1159 tcg_gen_ext16u_i32(d, s);
1160 } else if (!TCGV_EQUAL(d, s)) {
1161 tcg_gen_mov_tl(d, s);
1162 }
1163 }
1164
1165 #if DISAS_CRIS
1166 static char memsize_char(int size)
1167 {
1168 switch (size) {
1169 case 1: return 'b'; break;
1170 case 2: return 'w'; break;
1171 case 4: return 'd'; break;
1172 default:
1173 return 'x';
1174 break;
1175 }
1176 }
1177 #endif
1178
1179 static inline unsigned int memsize_z(DisasContext *dc)
1180 {
1181 return dc->zsize + 1;
1182 }
1183
1184 static inline unsigned int memsize_zz(DisasContext *dc)
1185 {
1186 switch (dc->zzsize) {
1187 case 0: return 1;
1188 case 1: return 2;
1189 default:
1190 return 4;
1191 }
1192 }
1193
1194 static inline void do_postinc (DisasContext *dc, int size)
1195 {
1196 if (dc->postinc) {
1197 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1198 }
1199 }
1200
1201 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1202 int size, int s_ext, TCGv dst)
1203 {
1204 if (s_ext) {
1205 t_gen_sext(dst, cpu_R[rs], size);
1206 } else {
1207 t_gen_zext(dst, cpu_R[rs], size);
1208 }
1209 }
1210
1211 /* Prepare T0 and T1 for a register alu operation.
1212 s_ext decides if the operand1 should be sign-extended or zero-extended when
1213 needed. */
1214 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1215 int size, int s_ext, TCGv dst, TCGv src)
1216 {
1217 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1218
1219 if (s_ext) {
1220 t_gen_sext(dst, cpu_R[rd], size);
1221 } else {
1222 t_gen_zext(dst, cpu_R[rd], size);
1223 }
1224 }
1225
1226 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1227 int s_ext, int memsize, TCGv dst)
1228 {
1229 unsigned int rs;
1230 uint32_t imm;
1231 int is_imm;
1232 int insn_len = 2;
1233
1234 rs = dc->op1;
1235 is_imm = rs == 15 && dc->postinc;
1236
1237 /* Load [$rs] onto T1. */
1238 if (is_imm) {
1239 insn_len = 2 + memsize;
1240 if (memsize == 1) {
1241 insn_len++;
1242 }
1243
1244 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1245 tcg_gen_movi_tl(dst, imm);
1246 dc->postinc = 0;
1247 } else {
1248 cris_flush_cc_state(dc);
1249 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1250 if (s_ext) {
1251 t_gen_sext(dst, dst, memsize);
1252 } else {
1253 t_gen_zext(dst, dst, memsize);
1254 }
1255 }
1256 return insn_len;
1257 }
1258
1259 /* Prepare T0 and T1 for a memory + alu operation.
1260 s_ext decides if the operand1 should be sign-extended or zero-extended when
1261 needed. */
1262 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1263 int s_ext, int memsize, TCGv dst, TCGv src)
1264 {
1265 int insn_len;
1266
1267 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1268 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1269 return insn_len;
1270 }
1271
1272 #if DISAS_CRIS
1273 static const char *cc_name(int cc)
1274 {
1275 static const char *cc_names[16] = {
1276 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1277 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1278 };
1279 assert(cc < 16);
1280 return cc_names[cc];
1281 }
1282 #endif
1283
1284 /* Start of insn decoders. */
1285
1286 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1287 {
1288 int32_t offset;
1289 int sign;
1290 uint32_t cond = dc->op2;
1291
1292 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1293 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1294
1295 offset *= 2;
1296 offset |= sign << 8;
1297 offset = sign_extend(offset, 8);
1298
1299 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1300
1301 /* op2 holds the condition-code. */
1302 cris_cc_mask(dc, 0);
1303 cris_prepare_cc_branch(dc, offset, cond);
1304 return 2;
1305 }
1306 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1307 {
1308 int32_t imm;
1309
1310 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1311 imm = sign_extend(dc->op1, 7);
1312
1313 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1314 cris_cc_mask(dc, 0);
1315 /* Fetch register operand, */
1316 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1317
1318 return 2;
1319 }
1320 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1321 {
1322 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1323
1324 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1325
1326 cris_cc_mask(dc, CC_MASK_NZVC);
1327
1328 cris_alu(dc, CC_OP_ADD,
1329 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1330 return 2;
1331 }
1332 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1333 {
1334 uint32_t imm;
1335
1336 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1337 imm = sign_extend(dc->op1, 5);
1338 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1339
1340 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1341 return 2;
1342 }
1343 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1344 {
1345 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1346
1347 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1348
1349 cris_cc_mask(dc, CC_MASK_NZVC);
1350 cris_alu(dc, CC_OP_SUB,
1351 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1352 return 2;
1353 }
1354 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1355 {
1356 uint32_t imm;
1357 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1358 imm = sign_extend(dc->op1, 5);
1359
1360 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1361 cris_cc_mask(dc, CC_MASK_NZVC);
1362
1363 cris_alu(dc, CC_OP_CMP,
1364 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1365 return 2;
1366 }
1367 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1368 {
1369 uint32_t imm;
1370 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1371 imm = sign_extend(dc->op1, 5);
1372
1373 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1374 cris_cc_mask(dc, CC_MASK_NZ);
1375
1376 cris_alu(dc, CC_OP_AND,
1377 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1378 return 2;
1379 }
1380 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1381 {
1382 uint32_t imm;
1383 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1384 imm = sign_extend(dc->op1, 5);
1385 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1386 cris_cc_mask(dc, CC_MASK_NZ);
1387
1388 cris_alu(dc, CC_OP_OR,
1389 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1390 return 2;
1391 }
1392 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1393 {
1394 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1395 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1396
1397 cris_cc_mask(dc, CC_MASK_NZ);
1398 cris_evaluate_flags(dc);
1399 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1400 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1401 cris_alu(dc, CC_OP_MOVE,
1402 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1403 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1404 dc->flags_uptodate = 1;
1405 return 2;
1406 }
1407 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1408 {
1409 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1410 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1411 cris_cc_mask(dc, CC_MASK_NZ);
1412
1413 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1414 cris_alu(dc, CC_OP_MOVE,
1415 cpu_R[dc->op2],
1416 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1417 return 2;
1418 }
1419 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1420 {
1421 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1422 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1423
1424 cris_cc_mask(dc, CC_MASK_NZ);
1425
1426 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1427
1428 cris_alu(dc, CC_OP_MOVE,
1429 cpu_R[dc->op2],
1430 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1431 return 2;
1432 }
1433 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1434 {
1435 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1436 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1437
1438 cris_cc_mask(dc, CC_MASK_NZ);
1439
1440 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1441 cris_alu(dc, CC_OP_MOVE,
1442 cpu_R[dc->op2],
1443 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1444 return 2;
1445 }
1446
1447 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1448 {
1449 int size = memsize_zz(dc);
1450
1451 LOG_DIS("move.%c $r%u, $r%u\n",
1452 memsize_char(size), dc->op1, dc->op2);
1453
1454 cris_cc_mask(dc, CC_MASK_NZ);
1455 if (size == 4) {
1456 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1457 cris_cc_mask(dc, CC_MASK_NZ);
1458 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1459 cris_update_cc_x(dc);
1460 cris_update_result(dc, cpu_R[dc->op2]);
1461 } else {
1462 TCGv t0;
1463
1464 t0 = tcg_temp_new();
1465 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1466 cris_alu(dc, CC_OP_MOVE,
1467 cpu_R[dc->op2],
1468 cpu_R[dc->op2], t0, size);
1469 tcg_temp_free(t0);
1470 }
1471 return 2;
1472 }
1473
1474 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1475 {
1476 int cond = dc->op2;
1477
1478 LOG_DIS("s%s $r%u\n",
1479 cc_name(cond), dc->op1);
1480
1481 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1482 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
1483
1484 cris_cc_mask(dc, 0);
1485 return 2;
1486 }
1487
1488 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1489 {
1490 if (size == 4) {
1491 t[0] = cpu_R[dc->op2];
1492 t[1] = cpu_R[dc->op1];
1493 } else {
1494 t[0] = tcg_temp_new();
1495 t[1] = tcg_temp_new();
1496 }
1497 }
1498
1499 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1500 {
1501 if (size != 4) {
1502 tcg_temp_free(t[0]);
1503 tcg_temp_free(t[1]);
1504 }
1505 }
1506
1507 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1508 {
1509 TCGv t[2];
1510 int size = memsize_zz(dc);
1511
1512 LOG_DIS("and.%c $r%u, $r%u\n",
1513 memsize_char(size), dc->op1, dc->op2);
1514
1515 cris_cc_mask(dc, CC_MASK_NZ);
1516
1517 cris_alu_alloc_temps(dc, size, t);
1518 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1519 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1520 cris_alu_free_temps(dc, size, t);
1521 return 2;
1522 }
1523
1524 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1525 {
1526 TCGv t0;
1527 LOG_DIS("lz $r%u, $r%u\n",
1528 dc->op1, dc->op2);
1529 cris_cc_mask(dc, CC_MASK_NZ);
1530 t0 = tcg_temp_new();
1531 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1532 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1533 tcg_temp_free(t0);
1534 return 2;
1535 }
1536
1537 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1538 {
1539 TCGv t[2];
1540 int size = memsize_zz(dc);
1541
1542 LOG_DIS("lsl.%c $r%u, $r%u\n",
1543 memsize_char(size), dc->op1, dc->op2);
1544
1545 cris_cc_mask(dc, CC_MASK_NZ);
1546 cris_alu_alloc_temps(dc, size, t);
1547 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1548 tcg_gen_andi_tl(t[1], t[1], 63);
1549 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1550 cris_alu_alloc_temps(dc, size, t);
1551 return 2;
1552 }
1553
1554 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1555 {
1556 TCGv t[2];
1557 int size = memsize_zz(dc);
1558
1559 LOG_DIS("lsr.%c $r%u, $r%u\n",
1560 memsize_char(size), dc->op1, dc->op2);
1561
1562 cris_cc_mask(dc, CC_MASK_NZ);
1563 cris_alu_alloc_temps(dc, size, t);
1564 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1565 tcg_gen_andi_tl(t[1], t[1], 63);
1566 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1567 cris_alu_free_temps(dc, size, t);
1568 return 2;
1569 }
1570
1571 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1572 {
1573 TCGv t[2];
1574 int size = memsize_zz(dc);
1575
1576 LOG_DIS("asr.%c $r%u, $r%u\n",
1577 memsize_char(size), dc->op1, dc->op2);
1578
1579 cris_cc_mask(dc, CC_MASK_NZ);
1580 cris_alu_alloc_temps(dc, size, t);
1581 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1582 tcg_gen_andi_tl(t[1], t[1], 63);
1583 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1584 cris_alu_free_temps(dc, size, t);
1585 return 2;
1586 }
1587
1588 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1589 {
1590 TCGv t[2];
1591 int size = memsize_zz(dc);
1592
1593 LOG_DIS("muls.%c $r%u, $r%u\n",
1594 memsize_char(size), dc->op1, dc->op2);
1595 cris_cc_mask(dc, CC_MASK_NZV);
1596 cris_alu_alloc_temps(dc, size, t);
1597 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1598
1599 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1600 cris_alu_free_temps(dc, size, t);
1601 return 2;
1602 }
1603
1604 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1605 {
1606 TCGv t[2];
1607 int size = memsize_zz(dc);
1608
1609 LOG_DIS("mulu.%c $r%u, $r%u\n",
1610 memsize_char(size), dc->op1, dc->op2);
1611 cris_cc_mask(dc, CC_MASK_NZV);
1612 cris_alu_alloc_temps(dc, size, t);
1613 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1614
1615 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1616 cris_alu_alloc_temps(dc, size, t);
1617 return 2;
1618 }
1619
1620
1621 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1622 {
1623 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1624 cris_cc_mask(dc, CC_MASK_NZ);
1625 cris_alu(dc, CC_OP_DSTEP,
1626 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1627 return 2;
1628 }
1629
1630 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1631 {
1632 TCGv t[2];
1633 int size = memsize_zz(dc);
1634 LOG_DIS("xor.%c $r%u, $r%u\n",
1635 memsize_char(size), dc->op1, dc->op2);
1636 BUG_ON(size != 4); /* xor is dword. */
1637 cris_cc_mask(dc, CC_MASK_NZ);
1638 cris_alu_alloc_temps(dc, size, t);
1639 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1640
1641 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1642 cris_alu_free_temps(dc, size, t);
1643 return 2;
1644 }
1645
1646 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1647 {
1648 TCGv l0;
1649 int size = memsize_zz(dc);
1650 LOG_DIS("bound.%c $r%u, $r%u\n",
1651 memsize_char(size), dc->op1, dc->op2);
1652 cris_cc_mask(dc, CC_MASK_NZ);
1653 l0 = tcg_temp_local_new();
1654 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1655 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1656 tcg_temp_free(l0);
1657 return 2;
1658 }
1659
1660 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1661 {
1662 TCGv t[2];
1663 int size = memsize_zz(dc);
1664 LOG_DIS("cmp.%c $r%u, $r%u\n",
1665 memsize_char(size), dc->op1, dc->op2);
1666 cris_cc_mask(dc, CC_MASK_NZVC);
1667 cris_alu_alloc_temps(dc, size, t);
1668 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1669
1670 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1671 cris_alu_free_temps(dc, size, t);
1672 return 2;
1673 }
1674
1675 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1676 {
1677 TCGv t0;
1678
1679 LOG_DIS("abs $r%u, $r%u\n",
1680 dc->op1, dc->op2);
1681 cris_cc_mask(dc, CC_MASK_NZ);
1682
1683 t0 = tcg_temp_new();
1684 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1685 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1686 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1687 tcg_temp_free(t0);
1688
1689 cris_alu(dc, CC_OP_MOVE,
1690 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1691 return 2;
1692 }
1693
1694 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1695 {
1696 TCGv t[2];
1697 int size = memsize_zz(dc);
1698 LOG_DIS("add.%c $r%u, $r%u\n",
1699 memsize_char(size), dc->op1, dc->op2);
1700 cris_cc_mask(dc, CC_MASK_NZVC);
1701 cris_alu_alloc_temps(dc, size, t);
1702 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1703
1704 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1705 cris_alu_free_temps(dc, size, t);
1706 return 2;
1707 }
1708
1709 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1710 {
1711 LOG_DIS("addc $r%u, $r%u\n",
1712 dc->op1, dc->op2);
1713 cris_evaluate_flags(dc);
1714 /* Set for this insn. */
1715 dc->flagx_known = 1;
1716 dc->flags_x = X_FLAG;
1717
1718 cris_cc_mask(dc, CC_MASK_NZVC);
1719 cris_alu(dc, CC_OP_ADDC,
1720 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1721 return 2;
1722 }
1723
1724 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1725 {
1726 LOG_DIS("mcp $p%u, $r%u\n",
1727 dc->op2, dc->op1);
1728 cris_evaluate_flags(dc);
1729 cris_cc_mask(dc, CC_MASK_RNZV);
1730 cris_alu(dc, CC_OP_MCP,
1731 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1732 return 2;
1733 }
1734
1735 #if DISAS_CRIS
1736 static char * swapmode_name(int mode, char *modename) {
1737 int i = 0;
1738 if (mode & 8) {
1739 modename[i++] = 'n';
1740 }
1741 if (mode & 4) {
1742 modename[i++] = 'w';
1743 }
1744 if (mode & 2) {
1745 modename[i++] = 'b';
1746 }
1747 if (mode & 1) {
1748 modename[i++] = 'r';
1749 }
1750 modename[i++] = 0;
1751 return modename;
1752 }
1753 #endif
1754
1755 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1756 {
1757 TCGv t0;
1758 #if DISAS_CRIS
1759 char modename[4];
1760 #endif
1761 LOG_DIS("swap%s $r%u\n",
1762 swapmode_name(dc->op2, modename), dc->op1);
1763
1764 cris_cc_mask(dc, CC_MASK_NZ);
1765 t0 = tcg_temp_new();
1766 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1767 if (dc->op2 & 8) {
1768 tcg_gen_not_tl(t0, t0);
1769 }
1770 if (dc->op2 & 4) {
1771 t_gen_swapw(t0, t0);
1772 }
1773 if (dc->op2 & 2) {
1774 t_gen_swapb(t0, t0);
1775 }
1776 if (dc->op2 & 1) {
1777 t_gen_swapr(t0, t0);
1778 }
1779 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1780 tcg_temp_free(t0);
1781 return 2;
1782 }
1783
1784 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1785 {
1786 TCGv t[2];
1787 int size = memsize_zz(dc);
1788 LOG_DIS("or.%c $r%u, $r%u\n",
1789 memsize_char(size), dc->op1, dc->op2);
1790 cris_cc_mask(dc, CC_MASK_NZ);
1791 cris_alu_alloc_temps(dc, size, t);
1792 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1793 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1794 cris_alu_free_temps(dc, size, t);
1795 return 2;
1796 }
1797
1798 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1799 {
1800 TCGv t0;
1801 LOG_DIS("addi.%c $r%u, $r%u\n",
1802 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1803 cris_cc_mask(dc, 0);
1804 t0 = tcg_temp_new();
1805 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1806 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1807 tcg_temp_free(t0);
1808 return 2;
1809 }
1810
1811 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1812 {
1813 TCGv t0;
1814 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1815 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1816 cris_cc_mask(dc, 0);
1817 t0 = tcg_temp_new();
1818 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1819 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1820 tcg_temp_free(t0);
1821 return 2;
1822 }
1823
1824 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1825 {
1826 TCGv t[2];
1827 int size = memsize_zz(dc);
1828 LOG_DIS("neg.%c $r%u, $r%u\n",
1829 memsize_char(size), dc->op1, dc->op2);
1830 cris_cc_mask(dc, CC_MASK_NZVC);
1831 cris_alu_alloc_temps(dc, size, t);
1832 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1833
1834 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1835 cris_alu_free_temps(dc, size, t);
1836 return 2;
1837 }
1838
1839 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1840 {
1841 LOG_DIS("btst $r%u, $r%u\n",
1842 dc->op1, dc->op2);
1843 cris_cc_mask(dc, CC_MASK_NZ);
1844 cris_evaluate_flags(dc);
1845 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1846 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1847 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1848 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1849 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1850 dc->flags_uptodate = 1;
1851 return 2;
1852 }
1853
1854 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1855 {
1856 TCGv t[2];
1857 int size = memsize_zz(dc);
1858 LOG_DIS("sub.%c $r%u, $r%u\n",
1859 memsize_char(size), dc->op1, dc->op2);
1860 cris_cc_mask(dc, CC_MASK_NZVC);
1861 cris_alu_alloc_temps(dc, size, t);
1862 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1863 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1864 cris_alu_free_temps(dc, size, t);
1865 return 2;
1866 }
1867
1868 /* Zero extension. From size to dword. */
1869 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1870 {
1871 TCGv t0;
1872 int size = memsize_z(dc);
1873 LOG_DIS("movu.%c $r%u, $r%u\n",
1874 memsize_char(size),
1875 dc->op1, dc->op2);
1876
1877 cris_cc_mask(dc, CC_MASK_NZ);
1878 t0 = tcg_temp_new();
1879 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1880 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1881 tcg_temp_free(t0);
1882 return 2;
1883 }
1884
1885 /* Sign extension. From size to dword. */
1886 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1887 {
1888 TCGv t0;
1889 int size = memsize_z(dc);
1890 LOG_DIS("movs.%c $r%u, $r%u\n",
1891 memsize_char(size),
1892 dc->op1, dc->op2);
1893
1894 cris_cc_mask(dc, CC_MASK_NZ);
1895 t0 = tcg_temp_new();
1896 /* Size can only be qi or hi. */
1897 t_gen_sext(t0, cpu_R[dc->op1], size);
1898 cris_alu(dc, CC_OP_MOVE,
1899 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1900 tcg_temp_free(t0);
1901 return 2;
1902 }
1903
1904 /* zero extension. From size to dword. */
1905 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1906 {
1907 TCGv t0;
1908 int size = memsize_z(dc);
1909 LOG_DIS("addu.%c $r%u, $r%u\n",
1910 memsize_char(size),
1911 dc->op1, dc->op2);
1912
1913 cris_cc_mask(dc, CC_MASK_NZVC);
1914 t0 = tcg_temp_new();
1915 /* Size can only be qi or hi. */
1916 t_gen_zext(t0, cpu_R[dc->op1], size);
1917 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1918 tcg_temp_free(t0);
1919 return 2;
1920 }
1921
1922 /* Sign extension. From size to dword. */
1923 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1924 {
1925 TCGv t0;
1926 int size = memsize_z(dc);
1927 LOG_DIS("adds.%c $r%u, $r%u\n",
1928 memsize_char(size),
1929 dc->op1, dc->op2);
1930
1931 cris_cc_mask(dc, CC_MASK_NZVC);
1932 t0 = tcg_temp_new();
1933 /* Size can only be qi or hi. */
1934 t_gen_sext(t0, cpu_R[dc->op1], size);
1935 cris_alu(dc, CC_OP_ADD,
1936 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1937 tcg_temp_free(t0);
1938 return 2;
1939 }
1940
1941 /* Zero extension. From size to dword. */
1942 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1943 {
1944 TCGv t0;
1945 int size = memsize_z(dc);
1946 LOG_DIS("subu.%c $r%u, $r%u\n",
1947 memsize_char(size),
1948 dc->op1, dc->op2);
1949
1950 cris_cc_mask(dc, CC_MASK_NZVC);
1951 t0 = tcg_temp_new();
1952 /* Size can only be qi or hi. */
1953 t_gen_zext(t0, cpu_R[dc->op1], size);
1954 cris_alu(dc, CC_OP_SUB,
1955 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1956 tcg_temp_free(t0);
1957 return 2;
1958 }
1959
1960 /* Sign extension. From size to dword. */
1961 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1962 {
1963 TCGv t0;
1964 int size = memsize_z(dc);
1965 LOG_DIS("subs.%c $r%u, $r%u\n",
1966 memsize_char(size),
1967 dc->op1, dc->op2);
1968
1969 cris_cc_mask(dc, CC_MASK_NZVC);
1970 t0 = tcg_temp_new();
1971 /* Size can only be qi or hi. */
1972 t_gen_sext(t0, cpu_R[dc->op1], size);
1973 cris_alu(dc, CC_OP_SUB,
1974 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1975 tcg_temp_free(t0);
1976 return 2;
1977 }
1978
1979 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
1980 {
1981 uint32_t flags;
1982 int set = (~dc->opcode >> 2) & 1;
1983
1984
1985 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1986 | EXTRACT_FIELD(dc->ir, 0, 3);
1987 if (set && flags == 0) {
1988 LOG_DIS("nop\n");
1989 return 2;
1990 } else if (!set && (flags & 0x20)) {
1991 LOG_DIS("di\n");
1992 } else {
1993 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
1994 }
1995
1996 /* User space is not allowed to touch these. Silently ignore. */
1997 if (dc->tb_flags & U_FLAG) {
1998 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
1999 }
2000
2001 if (flags & X_FLAG) {
2002 dc->flagx_known = 1;
2003 if (set) {
2004 dc->flags_x = X_FLAG;
2005 } else {
2006 dc->flags_x = 0;
2007 }
2008 }
2009
2010 /* Break the TB if any of the SPI flag changes. */
2011 if (flags & (P_FLAG | S_FLAG)) {
2012 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2013 dc->is_jmp = DISAS_UPDATE;
2014 dc->cpustate_changed = 1;
2015 }
2016
2017 /* For the I flag, only act on posedge. */
2018 if ((flags & I_FLAG)) {
2019 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2020 dc->is_jmp = DISAS_UPDATE;
2021 dc->cpustate_changed = 1;
2022 }
2023
2024
2025 /* Simply decode the flags. */
2026 cris_evaluate_flags(dc);
2027 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2028 cris_update_cc_x(dc);
2029 tcg_gen_movi_tl(cc_op, dc->cc_op);
2030
2031 if (set) {
2032 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2033 /* Enter user mode. */
2034 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2035 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2036 dc->cpustate_changed = 1;
2037 }
2038 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2039 } else {
2040 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2041 }
2042
2043 dc->flags_uptodate = 1;
2044 dc->clear_x = 0;
2045 return 2;
2046 }
2047
2048 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2049 {
2050 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2051 cris_cc_mask(dc, 0);
2052 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2053 tcg_const_tl(dc->op1));
2054 return 2;
2055 }
2056 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2057 {
2058 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2059 cris_cc_mask(dc, 0);
2060 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2061 tcg_const_tl(dc->op2));
2062 return 2;
2063 }
2064
2065 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2066 {
2067 TCGv t[2];
2068 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2069 cris_cc_mask(dc, 0);
2070
2071 t[0] = tcg_temp_new();
2072 if (dc->op2 == PR_CCS) {
2073 cris_evaluate_flags(dc);
2074 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2075 if (dc->tb_flags & U_FLAG) {
2076 t[1] = tcg_temp_new();
2077 /* User space is not allowed to touch all flags. */
2078 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2079 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2080 tcg_gen_or_tl(t[0], t[1], t[0]);
2081 tcg_temp_free(t[1]);
2082 }
2083 } else {
2084 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2085 }
2086
2087 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2088 if (dc->op2 == PR_CCS) {
2089 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2090 dc->flags_uptodate = 1;
2091 }
2092 tcg_temp_free(t[0]);
2093 return 2;
2094 }
2095 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2096 {
2097 TCGv t0;
2098 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2099 cris_cc_mask(dc, 0);
2100
2101 if (dc->op2 == PR_CCS) {
2102 cris_evaluate_flags(dc);
2103 }
2104
2105 if (dc->op2 == PR_DZ) {
2106 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2107 } else {
2108 t0 = tcg_temp_new();
2109 t_gen_mov_TN_preg(t0, dc->op2);
2110 cris_alu(dc, CC_OP_MOVE,
2111 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2112 preg_sizes[dc->op2]);
2113 tcg_temp_free(t0);
2114 }
2115 return 2;
2116 }
2117
2118 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2119 {
2120 int memsize = memsize_zz(dc);
2121 int insn_len;
2122 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2123 memsize_char(memsize),
2124 dc->op1, dc->postinc ? "+]" : "]",
2125 dc->op2);
2126
2127 if (memsize == 4) {
2128 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2129 cris_cc_mask(dc, CC_MASK_NZ);
2130 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2131 cris_update_cc_x(dc);
2132 cris_update_result(dc, cpu_R[dc->op2]);
2133 } else {
2134 TCGv t0;
2135
2136 t0 = tcg_temp_new();
2137 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2138 cris_cc_mask(dc, CC_MASK_NZ);
2139 cris_alu(dc, CC_OP_MOVE,
2140 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2141 tcg_temp_free(t0);
2142 }
2143 do_postinc(dc, memsize);
2144 return insn_len;
2145 }
2146
2147 static inline void cris_alu_m_alloc_temps(TCGv *t)
2148 {
2149 t[0] = tcg_temp_new();
2150 t[1] = tcg_temp_new();
2151 }
2152
2153 static inline void cris_alu_m_free_temps(TCGv *t)
2154 {
2155 tcg_temp_free(t[0]);
2156 tcg_temp_free(t[1]);
2157 }
2158
2159 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2160 {
2161 TCGv t[2];
2162 int memsize = memsize_z(dc);
2163 int insn_len;
2164 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2165 memsize_char(memsize),
2166 dc->op1, dc->postinc ? "+]" : "]",
2167 dc->op2);
2168
2169 cris_alu_m_alloc_temps(t);
2170 /* sign extend. */
2171 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2172 cris_cc_mask(dc, CC_MASK_NZ);
2173 cris_alu(dc, CC_OP_MOVE,
2174 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2175 do_postinc(dc, memsize);
2176 cris_alu_m_free_temps(t);
2177 return insn_len;
2178 }
2179
2180 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2181 {
2182 TCGv t[2];
2183 int memsize = memsize_z(dc);
2184 int insn_len;
2185 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2186 memsize_char(memsize),
2187 dc->op1, dc->postinc ? "+]" : "]",
2188 dc->op2);
2189
2190 cris_alu_m_alloc_temps(t);
2191 /* sign extend. */
2192 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2193 cris_cc_mask(dc, CC_MASK_NZVC);
2194 cris_alu(dc, CC_OP_ADD,
2195 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2196 do_postinc(dc, memsize);
2197 cris_alu_m_free_temps(t);
2198 return insn_len;
2199 }
2200
2201 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2202 {
2203 TCGv t[2];
2204 int memsize = memsize_z(dc);
2205 int insn_len;
2206 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2207 memsize_char(memsize),
2208 dc->op1, dc->postinc ? "+]" : "]",
2209 dc->op2);
2210
2211 cris_alu_m_alloc_temps(t);
2212 /* sign extend. */
2213 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2214 cris_cc_mask(dc, CC_MASK_NZVC);
2215 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2216 do_postinc(dc, memsize);
2217 cris_alu_m_free_temps(t);
2218 return insn_len;
2219 }
2220
2221 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2222 {
2223 TCGv t[2];
2224 int memsize = memsize_z(dc);
2225 int insn_len;
2226 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2227 memsize_char(memsize),
2228 dc->op1, dc->postinc ? "+]" : "]",
2229 dc->op2);
2230
2231 cris_alu_m_alloc_temps(t);
2232 /* sign extend. */
2233 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2234 cris_cc_mask(dc, CC_MASK_NZVC);
2235 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2236 do_postinc(dc, memsize);
2237 cris_alu_m_free_temps(t);
2238 return insn_len;
2239 }
2240
2241 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2242 {
2243 TCGv t[2];
2244 int memsize = memsize_z(dc);
2245 int insn_len;
2246 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2247 memsize_char(memsize),
2248 dc->op1, dc->postinc ? "+]" : "]",
2249 dc->op2);
2250
2251 cris_alu_m_alloc_temps(t);
2252 /* sign extend. */
2253 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2254 cris_cc_mask(dc, CC_MASK_NZVC);
2255 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2256 do_postinc(dc, memsize);
2257 cris_alu_m_free_temps(t);
2258 return insn_len;
2259 }
2260
2261 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2262 {
2263 TCGv t[2];
2264 int memsize = memsize_z(dc);
2265 int insn_len;
2266
2267 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2268 memsize_char(memsize),
2269 dc->op1, dc->postinc ? "+]" : "]",
2270 dc->op2);
2271
2272 cris_alu_m_alloc_temps(t);
2273 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2274 cris_cc_mask(dc, CC_MASK_NZ);
2275 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2276 do_postinc(dc, memsize);
2277 cris_alu_m_free_temps(t);
2278 return insn_len;
2279 }
2280
2281 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2282 {
2283 TCGv t[2];
2284 int memsize = memsize_z(dc);
2285 int insn_len;
2286 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2287 memsize_char(memsize),
2288 dc->op1, dc->postinc ? "+]" : "]",
2289 dc->op2);
2290
2291 cris_alu_m_alloc_temps(t);
2292 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2293 cris_cc_mask(dc, CC_MASK_NZVC);
2294 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2295 do_postinc(dc, memsize);
2296 cris_alu_m_free_temps(t);
2297 return insn_len;
2298 }
2299
2300 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2301 {
2302 TCGv t[2];
2303 int memsize = memsize_z(dc);
2304 int insn_len;
2305 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2306 memsize_char(memsize),
2307 dc->op1, dc->postinc ? "+]" : "]",
2308 dc->op2);
2309
2310 cris_alu_m_alloc_temps(t);
2311 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2312 cris_cc_mask(dc, CC_MASK_NZVC);
2313 cris_alu(dc, CC_OP_CMP,
2314 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2315 memsize_zz(dc));
2316 do_postinc(dc, memsize);
2317 cris_alu_m_free_temps(t);
2318 return insn_len;
2319 }
2320
2321 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2322 {
2323 TCGv t[2];
2324 int memsize = memsize_zz(dc);
2325 int insn_len;
2326 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2327 memsize_char(memsize),
2328 dc->op1, dc->postinc ? "+]" : "]",
2329 dc->op2);
2330
2331 cris_alu_m_alloc_temps(t);
2332 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2333 cris_cc_mask(dc, CC_MASK_NZVC);
2334 cris_alu(dc, CC_OP_CMP,
2335 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2336 memsize_zz(dc));
2337 do_postinc(dc, memsize);
2338 cris_alu_m_free_temps(t);
2339 return insn_len;
2340 }
2341
2342 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2343 {
2344 TCGv t[2];
2345 int memsize = memsize_zz(dc);
2346 int insn_len;
2347 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2348 memsize_char(memsize),
2349 dc->op1, dc->postinc ? "+]" : "]",
2350 dc->op2);
2351
2352 cris_evaluate_flags(dc);
2353
2354 cris_alu_m_alloc_temps(t);
2355 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2356 cris_cc_mask(dc, CC_MASK_NZ);
2357 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2358
2359 cris_alu(dc, CC_OP_CMP,
2360 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2361 do_postinc(dc, memsize);
2362 cris_alu_m_free_temps(t);
2363 return insn_len;
2364 }
2365
2366 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2367 {
2368 TCGv t[2];
2369 int memsize = memsize_zz(dc);
2370 int insn_len;
2371 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2372 memsize_char(memsize),
2373 dc->op1, dc->postinc ? "+]" : "]",
2374 dc->op2);
2375
2376 cris_alu_m_alloc_temps(t);
2377 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2378 cris_cc_mask(dc, CC_MASK_NZ);
2379 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2380 do_postinc(dc, memsize);
2381 cris_alu_m_free_temps(t);
2382 return insn_len;
2383 }
2384
2385 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2386 {
2387 TCGv t[2];
2388 int memsize = memsize_zz(dc);
2389 int insn_len;
2390 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2391 memsize_char(memsize),
2392 dc->op1, dc->postinc ? "+]" : "]",
2393 dc->op2);
2394
2395 cris_alu_m_alloc_temps(t);
2396 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2397 cris_cc_mask(dc, CC_MASK_NZVC);
2398 cris_alu(dc, CC_OP_ADD,
2399 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2400 do_postinc(dc, memsize);
2401 cris_alu_m_free_temps(t);
2402 return insn_len;
2403 }
2404
2405 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2406 {
2407 TCGv t[2];
2408 int memsize = memsize_zz(dc);
2409 int insn_len;
2410 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2411 memsize_char(memsize),
2412 dc->op1, dc->postinc ? "+]" : "]",
2413 dc->op2);
2414
2415 cris_alu_m_alloc_temps(t);
2416 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2417 cris_cc_mask(dc, 0);
2418 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2419 do_postinc(dc, memsize);
2420 cris_alu_m_free_temps(t);
2421 return insn_len;
2422 }
2423
2424 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2425 {
2426 TCGv l[2];
2427 int memsize = memsize_zz(dc);
2428 int insn_len;
2429 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2430 memsize_char(memsize),
2431 dc->op1, dc->postinc ? "+]" : "]",
2432 dc->op2);
2433
2434 l[0] = tcg_temp_local_new();
2435 l[1] = tcg_temp_local_new();
2436 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2437 cris_cc_mask(dc, CC_MASK_NZ);
2438 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2439 do_postinc(dc, memsize);
2440 tcg_temp_free(l[0]);
2441 tcg_temp_free(l[1]);
2442 return insn_len;
2443 }
2444
2445 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2446 {
2447 TCGv t[2];
2448 int insn_len = 2;
2449 LOG_DIS("addc [$r%u%s, $r%u\n",
2450 dc->op1, dc->postinc ? "+]" : "]",
2451 dc->op2);
2452
2453 cris_evaluate_flags(dc);
2454
2455 /* Set for this insn. */
2456 dc->flagx_known = 1;
2457 dc->flags_x = X_FLAG;
2458
2459 cris_alu_m_alloc_temps(t);
2460 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2461 cris_cc_mask(dc, CC_MASK_NZVC);
2462 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2463 do_postinc(dc, 4);
2464 cris_alu_m_free_temps(t);
2465 return insn_len;
2466 }
2467
2468 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2469 {
2470 TCGv t[2];
2471 int memsize = memsize_zz(dc);
2472 int insn_len;
2473 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2474 memsize_char(memsize),
2475 dc->op1, dc->postinc ? "+]" : "]",
2476 dc->op2, dc->ir, dc->zzsize);
2477
2478 cris_alu_m_alloc_temps(t);
2479 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2480 cris_cc_mask(dc, CC_MASK_NZVC);
2481 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2482 do_postinc(dc, memsize);
2483 cris_alu_m_free_temps(t);
2484 return insn_len;
2485 }
2486
2487 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2488 {
2489 TCGv t[2];
2490 int memsize = memsize_zz(dc);
2491 int insn_len;
2492 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2493 memsize_char(memsize),
2494 dc->op1, dc->postinc ? "+]" : "]",
2495 dc->op2, dc->pc);
2496
2497 cris_alu_m_alloc_temps(t);
2498 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2499 cris_cc_mask(dc, CC_MASK_NZ);
2500 cris_alu(dc, CC_OP_OR,
2501 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2502 do_postinc(dc, memsize);
2503 cris_alu_m_free_temps(t);
2504 return insn_len;
2505 }
2506
2507 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2508 {
2509 TCGv t[2];
2510 int memsize = memsize_zz(dc);
2511 int insn_len = 2;
2512
2513 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2514 memsize_char(memsize),
2515 dc->op1,
2516 dc->postinc ? "+]" : "]",
2517 dc->op2);
2518
2519 cris_alu_m_alloc_temps(t);
2520 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2521 cris_cc_mask(dc, 0);
2522 if (dc->op2 == PR_CCS) {
2523 cris_evaluate_flags(dc);
2524 if (dc->tb_flags & U_FLAG) {
2525 /* User space is not allowed to touch all flags. */
2526 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2527 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2528 tcg_gen_or_tl(t[1], t[0], t[1]);
2529 }
2530 }
2531
2532 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2533
2534 do_postinc(dc, memsize);
2535 cris_alu_m_free_temps(t);
2536 return insn_len;
2537 }
2538
2539 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2540 {
2541 TCGv t0;
2542 int memsize;
2543
2544 memsize = preg_sizes[dc->op2];
2545
2546 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2547 memsize_char(memsize),
2548 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2549
2550 /* prepare store. Address in T0, value in T1. */
2551 if (dc->op2 == PR_CCS) {
2552 cris_evaluate_flags(dc);
2553 }
2554 t0 = tcg_temp_new();
2555 t_gen_mov_TN_preg(t0, dc->op2);
2556 cris_flush_cc_state(dc);
2557 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2558 tcg_temp_free(t0);
2559
2560 cris_cc_mask(dc, 0);
2561 if (dc->postinc) {
2562 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2563 }
2564 return 2;
2565 }
2566
2567 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2568 {
2569 TCGv_i64 tmp[16];
2570 TCGv tmp32;
2571 TCGv addr;
2572 int i;
2573 int nr = dc->op2 + 1;
2574
2575 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2576 dc->postinc ? "+]" : "]", dc->op2);
2577
2578 addr = tcg_temp_new();
2579 /* There are probably better ways of doing this. */
2580 cris_flush_cc_state(dc);
2581 for (i = 0; i < (nr >> 1); i++) {
2582 tmp[i] = tcg_temp_new_i64();
2583 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2584 gen_load64(dc, tmp[i], addr);
2585 }
2586 if (nr & 1) {
2587 tmp32 = tcg_temp_new_i32();
2588 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2589 gen_load(dc, tmp32, addr, 4, 0);
2590 } else {
2591 TCGV_UNUSED(tmp32);
2592 }
2593 tcg_temp_free(addr);
2594
2595 for (i = 0; i < (nr >> 1); i++) {
2596 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
2597 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2598 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2599 tcg_temp_free_i64(tmp[i]);
2600 }
2601 if (nr & 1) {
2602 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2603 tcg_temp_free(tmp32);
2604 }
2605
2606 /* writeback the updated pointer value. */
2607 if (dc->postinc) {
2608 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2609 }
2610
2611 /* gen_load might want to evaluate the previous insns flags. */
2612 cris_cc_mask(dc, 0);
2613 return 2;
2614 }
2615
2616 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2617 {
2618 TCGv tmp;
2619 TCGv addr;
2620 int i;
2621
2622 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2623 dc->postinc ? "+]" : "]");
2624
2625 cris_flush_cc_state(dc);
2626
2627 tmp = tcg_temp_new();
2628 addr = tcg_temp_new();
2629 tcg_gen_movi_tl(tmp, 4);
2630 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2631 for (i = 0; i <= dc->op2; i++) {
2632 /* Displace addr. */
2633 /* Perform the store. */
2634 gen_store(dc, addr, cpu_R[i], 4);
2635 tcg_gen_add_tl(addr, addr, tmp);
2636 }
2637 if (dc->postinc) {
2638 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2639 }
2640 cris_cc_mask(dc, 0);
2641 tcg_temp_free(tmp);
2642 tcg_temp_free(addr);
2643 return 2;
2644 }
2645
2646 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2647 {
2648 int memsize;
2649
2650 memsize = memsize_zz(dc);
2651
2652 LOG_DIS("move.%c $r%u, [$r%u]\n",
2653 memsize_char(memsize), dc->op2, dc->op1);
2654
2655 /* prepare store. */
2656 cris_flush_cc_state(dc);
2657 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2658
2659 if (dc->postinc) {
2660 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2661 }
2662 cris_cc_mask(dc, 0);
2663 return 2;
2664 }
2665
2666 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2667 {
2668 LOG_DIS("lapcq %x, $r%u\n",
2669 dc->pc + dc->op1*2, dc->op2);
2670 cris_cc_mask(dc, 0);
2671 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2672 return 2;
2673 }
2674
2675 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2676 {
2677 unsigned int rd;
2678 int32_t imm;
2679 int32_t pc;
2680
2681 rd = dc->op2;
2682
2683 cris_cc_mask(dc, 0);
2684 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2685 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2686
2687 pc = dc->pc;
2688 pc += imm;
2689 tcg_gen_movi_tl(cpu_R[rd], pc);
2690 return 6;
2691 }
2692
2693 /* Jump to special reg. */
2694 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2695 {
2696 LOG_DIS("jump $p%u\n", dc->op2);
2697
2698 if (dc->op2 == PR_CCS) {
2699 cris_evaluate_flags(dc);
2700 }
2701 t_gen_mov_TN_preg(env_btarget, dc->op2);
2702 /* rete will often have low bit set to indicate delayslot. */
2703 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2704 cris_cc_mask(dc, 0);
2705 cris_prepare_jmp(dc, JMP_INDIRECT);
2706 return 2;
2707 }
2708
2709 /* Jump and save. */
2710 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2711 {
2712 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2713 cris_cc_mask(dc, 0);
2714 /* Store the return address in Pd. */
2715 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2716 if (dc->op2 > 15) {
2717 abort();
2718 }
2719 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2720
2721 cris_prepare_jmp(dc, JMP_INDIRECT);
2722 return 2;
2723 }
2724
2725 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2726 {
2727 uint32_t imm;
2728
2729 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2730
2731 LOG_DIS("jas 0x%x\n", imm);
2732 cris_cc_mask(dc, 0);
2733 /* Store the return address in Pd. */
2734 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2735
2736 dc->jmp_pc = imm;
2737 cris_prepare_jmp(dc, JMP_DIRECT);
2738 return 6;
2739 }
2740
2741 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2742 {
2743 uint32_t imm;
2744
2745 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2746
2747 LOG_DIS("jasc 0x%x\n", imm);
2748 cris_cc_mask(dc, 0);
2749 /* Store the return address in Pd. */
2750 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2751
2752 dc->jmp_pc = imm;
2753 cris_prepare_jmp(dc, JMP_DIRECT);
2754 return 6;
2755 }
2756
2757 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2758 {
2759 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2760 cris_cc_mask(dc, 0);
2761 /* Store the return address in Pd. */
2762 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2763 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2764 cris_prepare_jmp(dc, JMP_INDIRECT);
2765 return 2;
2766 }
2767
2768 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2769 {
2770 int32_t offset;
2771 uint32_t cond = dc->op2;
2772
2773 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2774
2775 LOG_DIS("b%s %d pc=%x dst=%x\n",
2776 cc_name(cond), offset,
2777 dc->pc, dc->pc + offset);
2778
2779 cris_cc_mask(dc, 0);
2780 /* op2 holds the condition-code. */
2781 cris_prepare_cc_branch(dc, offset, cond);
2782 return 4;
2783 }
2784
2785 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2786 {
2787 int32_t simm;
2788
2789 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2790
2791 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2792 cris_cc_mask(dc, 0);
2793 /* Store the return address in Pd. */
2794 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2795
2796 dc->jmp_pc = dc->pc + simm;
2797 cris_prepare_jmp(dc, JMP_DIRECT);
2798 return 6;
2799 }
2800
2801 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2802 {
2803 int32_t simm;
2804 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2805
2806 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2807 cris_cc_mask(dc, 0);
2808 /* Store the return address in Pd. */
2809 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2810
2811 dc->jmp_pc = dc->pc + simm;
2812 cris_prepare_jmp(dc, JMP_DIRECT);
2813 return 6;
2814 }
2815
2816 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2817 {
2818 cris_cc_mask(dc, 0);
2819
2820 if (dc->op2 == 15) {
2821 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2822 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2823 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2824 t_gen_raise_exception(EXCP_HLT);
2825 return 2;
2826 }
2827
2828 switch (dc->op2 & 7) {
2829 case 2:
2830 /* rfe. */
2831 LOG_DIS("rfe\n");
2832 cris_evaluate_flags(dc);
2833 gen_helper_rfe(cpu_env);
2834 dc->is_jmp = DISAS_UPDATE;
2835 break;
2836 case 5:
2837 /* rfn. */
2838 LOG_DIS("rfn\n");
2839 cris_evaluate_flags(dc);
2840 gen_helper_rfn(cpu_env);
2841 dc->is_jmp = DISAS_UPDATE;
2842 break;
2843 case 6:
2844 LOG_DIS("break %d\n", dc->op1);
2845 cris_evaluate_flags(dc);
2846 /* break. */
2847 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2848
2849 /* Breaks start at 16 in the exception vector. */
2850 t_gen_mov_env_TN(trap_vector,
2851 tcg_const_tl(dc->op1 + 16));
2852 t_gen_raise_exception(EXCP_BREAK);
2853 dc->is_jmp = DISAS_UPDATE;
2854 break;
2855 default:
2856 printf("op2=%x\n", dc->op2);
2857 BUG();
2858 break;
2859
2860 }
2861 return 2;
2862 }
2863
2864 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2865 {
2866 return 2;
2867 }
2868
2869 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2870 {
2871 return 2;
2872 }
2873
2874 static int dec_null(CPUCRISState *env, DisasContext *dc)
2875 {
2876 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2877 dc->pc, dc->opcode, dc->op1, dc->op2);
2878 fflush(NULL);
2879 BUG();
2880 return 2;
2881 }
2882
2883 static struct decoder_info {
2884 struct {
2885 uint32_t bits;
2886 uint32_t mask;
2887 };
2888 int (*dec)(CPUCRISState *env, DisasContext *dc);
2889 } decinfo[] = {
2890 /* Order matters here. */
2891 {DEC_MOVEQ, dec_moveq},
2892 {DEC_BTSTQ, dec_btstq},
2893 {DEC_CMPQ, dec_cmpq},
2894 {DEC_ADDOQ, dec_addoq},
2895 {DEC_ADDQ, dec_addq},
2896 {DEC_SUBQ, dec_subq},
2897 {DEC_ANDQ, dec_andq},
2898 {DEC_ORQ, dec_orq},
2899 {DEC_ASRQ, dec_asrq},
2900 {DEC_LSLQ, dec_lslq},
2901 {DEC_LSRQ, dec_lsrq},
2902 {DEC_BCCQ, dec_bccq},
2903
2904 {DEC_BCC_IM, dec_bcc_im},
2905 {DEC_JAS_IM, dec_jas_im},
2906 {DEC_JAS_R, dec_jas_r},
2907 {DEC_JASC_IM, dec_jasc_im},
2908 {DEC_JASC_R, dec_jasc_r},
2909 {DEC_BAS_IM, dec_bas_im},
2910 {DEC_BASC_IM, dec_basc_im},
2911 {DEC_JUMP_P, dec_jump_p},
2912 {DEC_LAPC_IM, dec_lapc_im},
2913 {DEC_LAPCQ, dec_lapcq},
2914
2915 {DEC_RFE_ETC, dec_rfe_etc},
2916 {DEC_ADDC_MR, dec_addc_mr},
2917
2918 {DEC_MOVE_MP, dec_move_mp},
2919 {DEC_MOVE_PM, dec_move_pm},
2920 {DEC_MOVEM_MR, dec_movem_mr},
2921 {DEC_MOVEM_RM, dec_movem_rm},
2922 {DEC_MOVE_PR, dec_move_pr},
2923 {DEC_SCC_R, dec_scc_r},
2924 {DEC_SETF, dec_setclrf},
2925 {DEC_CLEARF, dec_setclrf},
2926
2927 {DEC_MOVE_SR, dec_move_sr},
2928 {DEC_MOVE_RP, dec_move_rp},
2929 {DEC_SWAP_R, dec_swap_r},
2930 {DEC_ABS_R, dec_abs_r},
2931 {DEC_LZ_R, dec_lz_r},
2932 {DEC_MOVE_RS, dec_move_rs},
2933 {DEC_BTST_R, dec_btst_r},
2934 {DEC_ADDC_R, dec_addc_r},
2935
2936 {DEC_DSTEP_R, dec_dstep_r},
2937 {DEC_XOR_R, dec_xor_r},
2938 {DEC_MCP_R, dec_mcp_r},
2939 {DEC_CMP_R, dec_cmp_r},
2940
2941 {DEC_ADDI_R, dec_addi_r},
2942 {DEC_ADDI_ACR, dec_addi_acr},
2943
2944 {DEC_ADD_R, dec_add_r},
2945 {DEC_SUB_R, dec_sub_r},
2946
2947 {DEC_ADDU_R, dec_addu_r},
2948 {DEC_ADDS_R, dec_adds_r},
2949 {DEC_SUBU_R, dec_subu_r},
2950 {DEC_SUBS_R, dec_subs_r},
2951 {DEC_LSL_R, dec_lsl_r},
2952
2953 {DEC_AND_R, dec_and_r},
2954 {DEC_OR_R, dec_or_r},
2955 {DEC_BOUND_R, dec_bound_r},
2956 {DEC_ASR_R, dec_asr_r},
2957 {DEC_LSR_R, dec_lsr_r},
2958
2959 {DEC_MOVU_R, dec_movu_r},
2960 {DEC_MOVS_R, dec_movs_r},
2961 {DEC_NEG_R, dec_neg_r},
2962 {DEC_MOVE_R, dec_move_r},
2963
2964 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2965 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2966
2967 {DEC_MULS_R, dec_muls_r},
2968 {DEC_MULU_R, dec_mulu_r},
2969
2970 {DEC_ADDU_M, dec_addu_m},
2971 {DEC_ADDS_M, dec_adds_m},
2972 {DEC_SUBU_M, dec_subu_m},
2973 {DEC_SUBS_M, dec_subs_m},
2974
2975 {DEC_CMPU_M, dec_cmpu_m},
2976 {DEC_CMPS_M, dec_cmps_m},
2977 {DEC_MOVU_M, dec_movu_m},
2978 {DEC_MOVS_M, dec_movs_m},
2979
2980 {DEC_CMP_M, dec_cmp_m},
2981 {DEC_ADDO_M, dec_addo_m},
2982 {DEC_BOUND_M, dec_bound_m},
2983 {DEC_ADD_M, dec_add_m},
2984 {DEC_SUB_M, dec_sub_m},
2985 {DEC_AND_M, dec_and_m},
2986 {DEC_OR_M, dec_or_m},
2987 {DEC_MOVE_RM, dec_move_rm},
2988 {DEC_TEST_M, dec_test_m},
2989 {DEC_MOVE_MR, dec_move_mr},
2990
2991 {{0, 0}, dec_null}
2992 };
2993
2994 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
2995 {
2996 int insn_len = 2;
2997 int i;
2998
2999 /* Load a halfword onto the instruction register. */
3000 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3001
3002 /* Now decode it. */
3003 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3004 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3005 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3006 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3007 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3008 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3009
3010 /* Large switch for all insns. */
3011 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3012 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3013 insn_len = decinfo[i].dec(env, dc);
3014 break;
3015 }
3016 }
3017
3018 #if !defined(CONFIG_USER_ONLY)
3019 /* Single-stepping ? */
3020 if (dc->tb_flags & S_FLAG) {
3021 TCGLabel *l1 = gen_new_label();
3022 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3023 /* We treat SPC as a break with an odd trap vector. */
3024 cris_evaluate_flags(dc);
3025 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3026 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3027 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3028 t_gen_raise_exception(EXCP_BREAK);
3029 gen_set_label(l1);
3030 }
3031 #endif
3032 return insn_len;
3033 }
3034
3035 #include "translate_v10.c"
3036
3037 /*
3038 * Delay slots on QEMU/CRIS.
3039 *
3040 * If an exception hits on a delayslot, the core will let ERP (the Exception
3041 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3042 * to give SW a hint that the exception actually hit on the dslot.
3043 *
3044 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3045 * the core and any jmp to an odd addresses will mask off that lsb. It is
3046 * simply there to let sw know there was an exception on a dslot.
3047 *
3048 * When the software returns from an exception, the branch will re-execute.
3049 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3050 * and the branch and delayslot dont share pages.
3051 *
3052 * The TB contaning the branch insn will set up env->btarget and evaluate
3053 * env->btaken. When the translation loop exits we will note that the branch
3054 * sequence is broken and let env->dslot be the size of the branch insn (those
3055 * vary in length).
3056 *
3057 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3058 * set). It will also expect to have env->dslot setup with the size of the
3059 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3060 * will execute the dslot and take the branch, either to btarget or just one
3061 * insn ahead.
3062 *
3063 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3064 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3065 * branch and set lsb). Then env->dslot gets cleared so that the exception
3066 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3067 * masked off and we will reexecute the branch insn.
3068 *
3069 */
3070
3071 /* generate intermediate code for basic block 'tb'. */
3072 void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
3073 {
3074 CRISCPU *cpu = cris_env_get_cpu(env);
3075 CPUState *cs = CPU(cpu);
3076 uint32_t pc_start;
3077 unsigned int insn_len;
3078 struct DisasContext ctx;
3079 struct DisasContext *dc = &ctx;
3080 uint32_t next_page_start;
3081 target_ulong npc;
3082 int num_insns;
3083 int max_insns;
3084
3085 if (env->pregs[PR_VR] == 32) {
3086 dc->decoder = crisv32_decoder;
3087 dc->clear_locked_irq = 0;
3088 } else {
3089 dc->decoder = crisv10_decoder;
3090 dc->clear_locked_irq = 1;
3091 }
3092
3093 /* Odd PC indicates that branch is rexecuting due to exception in the
3094 * delayslot, like in real hw.
3095 */
3096 pc_start = tb->pc & ~1;
3097 dc->cpu = cpu;
3098 dc->tb = tb;
3099
3100 dc->is_jmp = DISAS_NEXT;
3101 dc->ppc = pc_start;
3102 dc->pc = pc_start;
3103 dc->singlestep_enabled = cs->singlestep_enabled;
3104 dc->flags_uptodate = 1;
3105 dc->flagx_known = 1;
3106 dc->flags_x = tb->flags & X_FLAG;
3107 dc->cc_x_uptodate = 0;
3108 dc->cc_mask = 0;
3109 dc->update_cc = 0;
3110 dc->clear_prefix = 0;
3111
3112 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3113 dc->cc_size_uptodate = -1;
3114
3115 /* Decode TB flags. */
3116 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3117 | X_FLAG | PFIX_FLAG);
3118 dc->delayed_branch = !!(tb->flags & 7);
3119 if (dc->delayed_branch) {
3120 dc->jmp = JMP_INDIRECT;
3121 } else {
3122 dc->jmp = JMP_NOJMP;
3123 }
3124
3125 dc->cpustate_changed = 0;
3126
3127 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3128 qemu_log(
3129 "pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3130 "pid=%x usp=%x\n"
3131 "%x.%x.%x.%x\n"
3132 "%x.%x.%x.%x\n"
3133 "%x.%x.%x.%x\n"
3134 "%x.%x.%x.%x\n",
3135 dc->pc, dc->ppc,
3136 (uint64_t)tb->flags,
3137 env->btarget, (unsigned)tb->flags & 7,
3138 env->pregs[PR_CCS],
3139 env->pregs[PR_PID], env->pregs[PR_USP],
3140 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3141 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3142 env->regs[8], env->regs[9],
3143 env->regs[10], env->regs[11],
3144 env->regs[12], env->regs[13],
3145 env->regs[14], env->regs[15]);
3146 qemu_log("--------------\n");
3147 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3148 }
3149
3150 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3151 num_insns = 0;
3152 max_insns = tb->cflags & CF_COUNT_MASK;
3153 if (max_insns == 0) {
3154 max_insns = CF_COUNT_MASK;
3155 }
3156 if (max_insns > TCG_MAX_INSNS) {
3157 max_insns = TCG_MAX_INSNS;
3158 }
3159
3160 gen_tb_start(tb);
3161 do {
3162 tcg_gen_insn_start(dc->delayed_branch == 1
3163 ? dc->ppc | 1 : dc->pc);
3164 num_insns++;
3165
3166 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3167 cris_evaluate_flags(dc);
3168 tcg_gen_movi_tl(env_pc, dc->pc);
3169 t_gen_raise_exception(EXCP_DEBUG);
3170 dc->is_jmp = DISAS_UPDATE;
3171 /* The address covered by the breakpoint must be included in
3172 [tb->pc, tb->pc + tb->size) in order to for it to be
3173 properly cleared -- thus we increment the PC here so that
3174 the logic setting tb->size below does the right thing. */
3175 dc->pc += 2;
3176 break;
3177 }
3178
3179 /* Pretty disas. */
3180 LOG_DIS("%8.8x:\t", dc->pc);
3181
3182 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3183 gen_io_start();
3184 }
3185 dc->clear_x = 1;
3186
3187 insn_len = dc->decoder(env, dc);
3188 dc->ppc = dc->pc;
3189 dc->pc += insn_len;
3190 if (dc->clear_x) {
3191 cris_clear_x_flag(dc);
3192 }
3193
3194 /* Check for delayed branches here. If we do it before
3195 actually generating any host code, the simulator will just
3196 loop doing nothing for on this program location. */
3197 if (dc->delayed_branch) {
3198 dc->delayed_branch--;
3199 if (dc->delayed_branch == 0) {
3200 if (tb->flags & 7) {
3201 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3202 }
3203 if (dc->cpustate_changed || !dc->flagx_known
3204 || (dc->flags_x != (tb->flags & X_FLAG))) {
3205 cris_store_direct_jmp(dc);
3206 }
3207
3208 if (dc->clear_locked_irq) {
3209 dc->clear_locked_irq = 0;
3210 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3211 }
3212
3213 if (dc->jmp == JMP_DIRECT_CC) {
3214 TCGLabel *l1 = gen_new_label();
3215 cris_evaluate_flags(dc);
3216
3217 /* Conditional jmp. */
3218 tcg_gen_brcondi_tl(TCG_COND_EQ,
3219 env_btaken, 0, l1);
3220 gen_goto_tb(dc, 1, dc->jmp_pc);
3221 gen_set_label(l1);
3222 gen_goto_tb(dc, 0, dc->pc);
3223 dc->is_jmp = DISAS_TB_JUMP;
3224 dc->jmp = JMP_NOJMP;
3225 } else if (dc->jmp == JMP_DIRECT) {
3226 cris_evaluate_flags(dc);
3227 gen_goto_tb(dc, 0, dc->jmp_pc);
3228 dc->is_jmp = DISAS_TB_JUMP;
3229 dc->jmp = JMP_NOJMP;
3230 } else {
3231 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3232 dc->is_jmp = DISAS_JUMP;
3233 }
3234 break;
3235 }
3236 }
3237
3238 /* If we are rexecuting a branch due to exceptions on
3239 delay slots dont break. */
3240 if (!(tb->pc & 1) && cs->singlestep_enabled) {
3241 break;
3242 }
3243 } while (!dc->is_jmp && !dc->cpustate_changed
3244 && !tcg_op_buf_full()
3245 && !singlestep
3246 && (dc->pc < next_page_start)
3247 && num_insns < max_insns);
3248
3249 if (dc->clear_locked_irq) {
3250 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3251 }
3252
3253 npc = dc->pc;
3254
3255 if (tb->cflags & CF_LAST_IO)
3256 gen_io_end();
3257 /* Force an update if the per-tb cpu state has changed. */
3258 if (dc->is_jmp == DISAS_NEXT
3259 && (dc->cpustate_changed || !dc->flagx_known
3260 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3261 dc->is_jmp = DISAS_UPDATE;
3262 tcg_gen_movi_tl(env_pc, npc);
3263 }
3264 /* Broken branch+delayslot sequence. */
3265 if (dc->delayed_branch == 1) {
3266 /* Set env->dslot to the size of the branch insn. */
3267 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3268 cris_store_direct_jmp(dc);
3269 }
3270
3271 cris_evaluate_flags(dc);
3272
3273 if (unlikely(cs->singlestep_enabled)) {
3274 if (dc->is_jmp == DISAS_NEXT) {
3275 tcg_gen_movi_tl(env_pc, npc);
3276 }
3277 t_gen_raise_exception(EXCP_DEBUG);
3278 } else {
3279 switch (dc->is_jmp) {
3280 case DISAS_NEXT:
3281 gen_goto_tb(dc, 1, npc);
3282 break;
3283 default:
3284 case DISAS_JUMP:
3285 case DISAS_UPDATE:
3286 /* indicate that the hash table must be used
3287 to find the next TB */
3288 tcg_gen_exit_tb(0);
3289 break;
3290 case DISAS_SWI:
3291 case DISAS_TB_JUMP:
3292 /* nothing more to generate */
3293 break;
3294 }
3295 }
3296 gen_tb_end(tb, num_insns);
3297
3298 tb->size = dc->pc - pc_start;
3299 tb->icount = num_insns;
3300
3301 #ifdef DEBUG_DISAS
3302 #if !DISAS_CRIS
3303 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3304 log_target_disas(cs, pc_start, dc->pc - pc_start,
3305 env->pregs[PR_VR]);
3306 qemu_log("\nisize=%d osize=%d\n",
3307 dc->pc - pc_start, tcg_op_buf_count());
3308 }
3309 #endif
3310 #endif
3311 }
3312
3313 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3314 int flags)
3315 {
3316 CRISCPU *cpu = CRIS_CPU(cs);
3317 CPUCRISState *env = &cpu->env;
3318 int i;
3319 uint32_t srs;
3320
3321 if (!env || !f) {
3322 return;
3323 }
3324
3325 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3326 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3327 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3328 env->cc_op,
3329 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3330
3331
3332 for (i = 0; i < 16; i++) {
3333 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3334 if ((i + 1) % 4 == 0) {
3335 cpu_fprintf(f, "\n");
3336 }
3337 }
3338 cpu_fprintf(f, "\nspecial regs:\n");
3339 for (i = 0; i < 16; i++) {
3340 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3341 if ((i + 1) % 4 == 0) {
3342 cpu_fprintf(f, "\n");
3343 }
3344 }
3345 srs = env->pregs[PR_SRS];
3346 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3347 if (srs < ARRAY_SIZE(env->sregs)) {
3348 for (i = 0; i < 16; i++) {
3349 cpu_fprintf(f, "s%2.2d=%8.8x ",
3350 i, env->sregs[srs][i]);
3351 if ((i + 1) % 4 == 0) {
3352 cpu_fprintf(f, "\n");
3353 }
3354 }
3355 }
3356 cpu_fprintf(f, "\n\n");
3357
3358 }
3359
3360 void cris_initialize_tcg(void)
3361 {
3362 int i;
3363
3364 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3365 cc_x = tcg_global_mem_new(TCG_AREG0,
3366 offsetof(CPUCRISState, cc_x), "cc_x");
3367 cc_src = tcg_global_mem_new(TCG_AREG0,
3368 offsetof(CPUCRISState, cc_src), "cc_src");
3369 cc_dest = tcg_global_mem_new(TCG_AREG0,
3370 offsetof(CPUCRISState, cc_dest),
3371 "cc_dest");
3372 cc_result = tcg_global_mem_new(TCG_AREG0,
3373 offsetof(CPUCRISState, cc_result),
3374 "cc_result");
3375 cc_op = tcg_global_mem_new(TCG_AREG0,
3376 offsetof(CPUCRISState, cc_op), "cc_op");
3377 cc_size = tcg_global_mem_new(TCG_AREG0,
3378 offsetof(CPUCRISState, cc_size),
3379 "cc_size");
3380 cc_mask = tcg_global_mem_new(TCG_AREG0,
3381 offsetof(CPUCRISState, cc_mask),
3382 "cc_mask");
3383
3384 env_pc = tcg_global_mem_new(TCG_AREG0,
3385 offsetof(CPUCRISState, pc),
3386 "pc");
3387 env_btarget = tcg_global_mem_new(TCG_AREG0,
3388 offsetof(CPUCRISState, btarget),
3389 "btarget");
3390 env_btaken = tcg_global_mem_new(TCG_AREG0,
3391 offsetof(CPUCRISState, btaken),
3392 "btaken");
3393 for (i = 0; i < 16; i++) {
3394 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3395 offsetof(CPUCRISState, regs[i]),
3396 regnames[i]);
3397 }
3398 for (i = 0; i < 16; i++) {
3399 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3400 offsetof(CPUCRISState, pregs[i]),
3401 pregnames[i]);
3402 }
3403 }
3404
3405 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
3406 target_ulong *data)
3407 {
3408 env->pc = data[0];
3409 }
AR7 emulation for QEMU