2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 #include "hw/registerfields.h"
30 /* register banks for CPU modes */
40 static inline bool excp_is_internal(int excp
)
42 /* Return true if this exception number represents a QEMU-internal
43 * exception that will not be passed to the guest.
45 return excp
== EXCP_INTERRUPT
48 || excp
== EXCP_HALTED
49 || excp
== EXCP_EXCEPTION_EXIT
50 || excp
== EXCP_KERNEL_TRAP
51 || excp
== EXCP_SEMIHOST
;
54 /* Scale factor for generic timers, ie number of ns per tick.
55 * This gives a 62.5MHz timer.
57 #define GTIMER_SCALE 16
59 /* Bit definitions for the v7M CONTROL register */
60 FIELD(V7M_CONTROL
, NPRIV
, 0, 1)
61 FIELD(V7M_CONTROL
, SPSEL
, 1, 1)
62 FIELD(V7M_CONTROL
, FPCA
, 2, 1)
63 FIELD(V7M_CONTROL
, SFPA
, 3, 1)
65 /* Bit definitions for v7M exception return payload */
66 FIELD(V7M_EXCRET
, ES
, 0, 1)
67 FIELD(V7M_EXCRET
, RES0
, 1, 1)
68 FIELD(V7M_EXCRET
, SPSEL
, 2, 1)
69 FIELD(V7M_EXCRET
, MODE
, 3, 1)
70 FIELD(V7M_EXCRET
, FTYPE
, 4, 1)
71 FIELD(V7M_EXCRET
, DCRS
, 5, 1)
72 FIELD(V7M_EXCRET
, S
, 6, 1)
73 FIELD(V7M_EXCRET
, RES1
, 7, 25) /* including the must-be-1 prefix */
75 /* Minimum value which is a magic number for exception return */
76 #define EXC_RETURN_MIN_MAGIC 0xff000000
77 /* Minimum number which is a magic number for function or exception return
78 * when using v8M security extension
80 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
82 /* We use a few fake FSR values for internal purposes in M profile.
83 * M profile cores don't have A/R format FSRs, but currently our
84 * get_phys_addr() code assumes A/R profile and reports failures via
85 * an A/R format FSR value. We then translate that into the proper
86 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
87 * Mostly the FSR values we use for this are those defined for v7PMSA,
88 * since we share some of that codepath. A few kinds of fault are
89 * only for M profile and have no A/R equivalent, though, so we have
90 * to pick a value from the reserved range (which we never otherwise
91 * generate) to use for these.
92 * These values will never be visible to the guest.
94 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
95 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
98 * raise_exception: Raise the specified exception.
99 * Raise a guest exception with the specified value, syndrome register
100 * and target exception level. This should be called from helper functions,
101 * and never returns because we will longjump back up to the CPU main loop.
103 void QEMU_NORETURN
raise_exception(CPUARMState
*env
, uint32_t excp
,
104 uint32_t syndrome
, uint32_t target_el
);
107 * Similarly, but also use unwinding to restore cpu state.
109 void QEMU_NORETURN
raise_exception_ra(CPUARMState
*env
, uint32_t excp
,
110 uint32_t syndrome
, uint32_t target_el
,
114 * For AArch64, map a given EL to an index in the banked_spsr array.
115 * Note that this mapping and the AArch32 mapping defined in bank_number()
116 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
117 * mandated mapping between each other.
119 static inline unsigned int aarch64_banked_spsr_index(unsigned int el
)
121 static const unsigned int map
[4] = {
122 [1] = BANK_SVC
, /* EL1. */
123 [2] = BANK_HYP
, /* EL2. */
124 [3] = BANK_MON
, /* EL3. */
126 assert(el
>= 1 && el
<= 3);
130 /* Map CPU modes onto saved register banks. */
131 static inline int bank_number(int mode
)
134 case ARM_CPU_MODE_USR
:
135 case ARM_CPU_MODE_SYS
:
137 case ARM_CPU_MODE_SVC
:
139 case ARM_CPU_MODE_ABT
:
141 case ARM_CPU_MODE_UND
:
143 case ARM_CPU_MODE_IRQ
:
145 case ARM_CPU_MODE_FIQ
:
147 case ARM_CPU_MODE_HYP
:
149 case ARM_CPU_MODE_MON
:
152 g_assert_not_reached();
156 * r14_bank_number: Map CPU mode onto register bank for r14
158 * Given an AArch32 CPU mode, return the index into the saved register
159 * banks to use for the R14 (LR) in that mode. This is the same as
160 * bank_number(), except for the special case of Hyp mode, where
161 * R14 is shared with USR and SYS, unlike its R13 and SPSR.
162 * This should be used as the index into env->banked_r14[], and
163 * bank_number() used for the index into env->banked_r13[] and
164 * env->banked_spsr[].
166 static inline int r14_bank_number(int mode
)
168 return (mode
== ARM_CPU_MODE_HYP
) ? BANK_USRSYS
: bank_number(mode
);
171 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
);
172 void arm_translate_init(void);
175 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
176 const struct TranslationBlock
*tb
);
177 #endif /* CONFIG_TCG */
180 enum arm_fprounding
{
189 int arm_rmode_to_sf(int rmode
);
191 static inline void aarch64_save_sp(CPUARMState
*env
, int el
)
193 if (env
->pstate
& PSTATE_SP
) {
194 env
->sp_el
[el
] = env
->xregs
[31];
196 env
->sp_el
[0] = env
->xregs
[31];
200 static inline void aarch64_restore_sp(CPUARMState
*env
, int el
)
202 if (env
->pstate
& PSTATE_SP
) {
203 env
->xregs
[31] = env
->sp_el
[el
];
205 env
->xregs
[31] = env
->sp_el
[0];
209 static inline void update_spsel(CPUARMState
*env
, uint32_t imm
)
211 unsigned int cur_el
= arm_current_el(env
);
212 /* Update PSTATE SPSel bit; this requires us to update the
213 * working stack pointer in xregs[31].
215 if (!((imm
^ env
->pstate
) & PSTATE_SP
)) {
218 aarch64_save_sp(env
, cur_el
);
219 env
->pstate
= deposit32(env
->pstate
, 0, 1, imm
);
221 /* We rely on illegal updates to SPsel from EL0 to get trapped
222 * at translation time.
224 assert(cur_el
>= 1 && cur_el
<= 3);
225 aarch64_restore_sp(env
, cur_el
);
232 * Returns the implementation defined bit-width of physical addresses.
233 * The ARMv8 reference manuals refer to this as PAMax().
235 static inline unsigned int arm_pamax(ARMCPU
*cpu
)
237 static const unsigned int pamax_map
[] = {
245 unsigned int parange
=
246 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
248 /* id_aa64mmfr0 is a read-only register so values outside of the
249 * supported mappings can be considered an implementation error. */
250 assert(parange
< ARRAY_SIZE(pamax_map
));
251 return pamax_map
[parange
];
254 /* Return true if extended addresses are enabled.
255 * This is always the case if our translation regime is 64 bit,
256 * but depends on TTBCR.EAE for 32 bit.
258 static inline bool extended_addresses_enabled(CPUARMState
*env
)
260 TCR
*tcr
= &env
->cp15
.tcr_el
[arm_is_secure(env
) ? 3 : 1];
261 return arm_el_is_aa64(env
, 1) ||
262 (arm_feature(env
, ARM_FEATURE_LPAE
) && (tcr
->raw_tcr
& TTBCR_EAE
));
265 /* Valid Syndrome Register EC field values */
266 enum arm_exception_class
{
267 EC_UNCATEGORIZED
= 0x00,
269 EC_CP15RTTRAP
= 0x03,
270 EC_CP15RRTTRAP
= 0x04,
271 EC_CP14RTTRAP
= 0x05,
272 EC_CP14DTTRAP
= 0x06,
273 EC_ADVSIMDFPACCESSTRAP
= 0x07,
276 EC_CP14RRTTRAP
= 0x0c,
278 EC_ILLEGALSTATE
= 0x0e,
285 EC_SYSTEMREGISTERTRAP
= 0x18,
286 EC_SVEACCESSTRAP
= 0x19,
288 EC_INSNABORT_SAME_EL
= 0x21,
289 EC_PCALIGNMENT
= 0x22,
291 EC_DATAABORT_SAME_EL
= 0x25,
292 EC_SPALIGNMENT
= 0x26,
293 EC_AA32_FPTRAP
= 0x28,
294 EC_AA64_FPTRAP
= 0x2c,
296 EC_BREAKPOINT
= 0x30,
297 EC_BREAKPOINT_SAME_EL
= 0x31,
298 EC_SOFTWARESTEP
= 0x32,
299 EC_SOFTWARESTEP_SAME_EL
= 0x33,
300 EC_WATCHPOINT
= 0x34,
301 EC_WATCHPOINT_SAME_EL
= 0x35,
303 EC_VECTORCATCH
= 0x3a,
307 #define ARM_EL_EC_SHIFT 26
308 #define ARM_EL_IL_SHIFT 25
309 #define ARM_EL_ISV_SHIFT 24
310 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
311 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
313 static inline uint32_t syn_get_ec(uint32_t syn
)
315 return syn
>> ARM_EL_EC_SHIFT
;
318 /* Utility functions for constructing various kinds of syndrome value.
319 * Note that in general we follow the AArch64 syndrome values; in a
320 * few cases the value in HSR for exceptions taken to AArch32 Hyp
321 * mode differs slightly, and we fix this up when populating HSR in
322 * arm_cpu_do_interrupt_aarch32_hyp().
323 * The exception is FP/SIMD access traps -- these report extra information
324 * when taking an exception to AArch32. For those we include the extra coproc
325 * and TA fields, and mask them out when taking the exception to AArch64.
327 static inline uint32_t syn_uncategorized(void)
329 return (EC_UNCATEGORIZED
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
;
332 static inline uint32_t syn_aa64_svc(uint32_t imm16
)
334 return (EC_AA64_SVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
337 static inline uint32_t syn_aa64_hvc(uint32_t imm16
)
339 return (EC_AA64_HVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
342 static inline uint32_t syn_aa64_smc(uint32_t imm16
)
344 return (EC_AA64_SMC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
347 static inline uint32_t syn_aa32_svc(uint32_t imm16
, bool is_16bit
)
349 return (EC_AA32_SVC
<< ARM_EL_EC_SHIFT
) | (imm16
& 0xffff)
350 | (is_16bit
? 0 : ARM_EL_IL
);
353 static inline uint32_t syn_aa32_hvc(uint32_t imm16
)
355 return (EC_AA32_HVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
358 static inline uint32_t syn_aa32_smc(void)
360 return (EC_AA32_SMC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
;
363 static inline uint32_t syn_aa64_bkpt(uint32_t imm16
)
365 return (EC_AA64_BKPT
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
368 static inline uint32_t syn_aa32_bkpt(uint32_t imm16
, bool is_16bit
)
370 return (EC_AA32_BKPT
<< ARM_EL_EC_SHIFT
) | (imm16
& 0xffff)
371 | (is_16bit
? 0 : ARM_EL_IL
);
374 static inline uint32_t syn_aa64_sysregtrap(int op0
, int op1
, int op2
,
375 int crn
, int crm
, int rt
,
378 return (EC_SYSTEMREGISTERTRAP
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
379 | (op0
<< 20) | (op2
<< 17) | (op1
<< 14) | (crn
<< 10) | (rt
<< 5)
380 | (crm
<< 1) | isread
;
383 static inline uint32_t syn_cp14_rt_trap(int cv
, int cond
, int opc1
, int opc2
,
384 int crn
, int crm
, int rt
, int isread
,
387 return (EC_CP14RTTRAP
<< ARM_EL_EC_SHIFT
)
388 | (is_16bit
? 0 : ARM_EL_IL
)
389 | (cv
<< 24) | (cond
<< 20) | (opc2
<< 17) | (opc1
<< 14)
390 | (crn
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
393 static inline uint32_t syn_cp15_rt_trap(int cv
, int cond
, int opc1
, int opc2
,
394 int crn
, int crm
, int rt
, int isread
,
397 return (EC_CP15RTTRAP
<< ARM_EL_EC_SHIFT
)
398 | (is_16bit
? 0 : ARM_EL_IL
)
399 | (cv
<< 24) | (cond
<< 20) | (opc2
<< 17) | (opc1
<< 14)
400 | (crn
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
403 static inline uint32_t syn_cp14_rrt_trap(int cv
, int cond
, int opc1
, int crm
,
404 int rt
, int rt2
, int isread
,
407 return (EC_CP14RRTTRAP
<< ARM_EL_EC_SHIFT
)
408 | (is_16bit
? 0 : ARM_EL_IL
)
409 | (cv
<< 24) | (cond
<< 20) | (opc1
<< 16)
410 | (rt2
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
413 static inline uint32_t syn_cp15_rrt_trap(int cv
, int cond
, int opc1
, int crm
,
414 int rt
, int rt2
, int isread
,
417 return (EC_CP15RRTTRAP
<< ARM_EL_EC_SHIFT
)
418 | (is_16bit
? 0 : ARM_EL_IL
)
419 | (cv
<< 24) | (cond
<< 20) | (opc1
<< 16)
420 | (rt2
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
423 static inline uint32_t syn_fp_access_trap(int cv
, int cond
, bool is_16bit
)
425 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */
426 return (EC_ADVSIMDFPACCESSTRAP
<< ARM_EL_EC_SHIFT
)
427 | (is_16bit
? 0 : ARM_EL_IL
)
428 | (cv
<< 24) | (cond
<< 20) | 0xa;
431 static inline uint32_t syn_simd_access_trap(int cv
, int cond
, bool is_16bit
)
433 /* AArch32 SIMD trap: TA == 1 coproc == 0 */
434 return (EC_ADVSIMDFPACCESSTRAP
<< ARM_EL_EC_SHIFT
)
435 | (is_16bit
? 0 : ARM_EL_IL
)
436 | (cv
<< 24) | (cond
<< 20) | (1 << 5);
439 static inline uint32_t syn_sve_access_trap(void)
441 return EC_SVEACCESSTRAP
<< ARM_EL_EC_SHIFT
;
444 static inline uint32_t syn_pactrap(void)
446 return EC_PACTRAP
<< ARM_EL_EC_SHIFT
;
449 static inline uint32_t syn_btitrap(int btype
)
451 return (EC_BTITRAP
<< ARM_EL_EC_SHIFT
) | btype
;
454 static inline uint32_t syn_insn_abort(int same_el
, int ea
, int s1ptw
, int fsc
)
456 return (EC_INSNABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
457 | ARM_EL_IL
| (ea
<< 9) | (s1ptw
<< 7) | fsc
;
460 static inline uint32_t syn_data_abort_no_iss(int same_el
, int fnv
,
461 int ea
, int cm
, int s1ptw
,
464 return (EC_DATAABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
466 | (fnv
<< 10) | (ea
<< 9) | (cm
<< 8) | (s1ptw
<< 7)
470 static inline uint32_t syn_data_abort_with_iss(int same_el
,
471 int sas
, int sse
, int srt
,
473 int ea
, int cm
, int s1ptw
,
477 return (EC_DATAABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
478 | (is_16bit
? 0 : ARM_EL_IL
)
479 | ARM_EL_ISV
| (sas
<< 22) | (sse
<< 21) | (srt
<< 16)
480 | (sf
<< 15) | (ar
<< 14)
481 | (ea
<< 9) | (cm
<< 8) | (s1ptw
<< 7) | (wnr
<< 6) | fsc
;
484 static inline uint32_t syn_swstep(int same_el
, int isv
, int ex
)
486 return (EC_SOFTWARESTEP
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
487 | ARM_EL_IL
| (isv
<< 24) | (ex
<< 6) | 0x22;
490 static inline uint32_t syn_watchpoint(int same_el
, int cm
, int wnr
)
492 return (EC_WATCHPOINT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
493 | ARM_EL_IL
| (cm
<< 8) | (wnr
<< 6) | 0x22;
496 static inline uint32_t syn_breakpoint(int same_el
)
498 return (EC_BREAKPOINT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
502 static inline uint32_t syn_wfx(int cv
, int cond
, int ti
, bool is_16bit
)
504 return (EC_WFX_TRAP
<< ARM_EL_EC_SHIFT
) |
505 (is_16bit
? 0 : (1 << ARM_EL_IL_SHIFT
)) |
506 (cv
<< 24) | (cond
<< 20) | ti
;
509 /* Update a QEMU watchpoint based on the information the guest has set in the
510 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
512 void hw_watchpoint_update(ARMCPU
*cpu
, int n
);
513 /* Update the QEMU watchpoints for every guest watchpoint. This does a
514 * complete delete-and-reinstate of the QEMU watchpoint list and so is
515 * suitable for use after migration or on reset.
517 void hw_watchpoint_update_all(ARMCPU
*cpu
);
518 /* Update a QEMU breakpoint based on the information the guest has set in the
519 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
521 void hw_breakpoint_update(ARMCPU
*cpu
, int n
);
522 /* Update the QEMU breakpoints for every guest breakpoint. This does a
523 * complete delete-and-reinstate of the QEMU breakpoint list and so is
524 * suitable for use after migration or on reset.
526 void hw_breakpoint_update_all(ARMCPU
*cpu
);
528 /* Callback function for checking if a watchpoint should trigger. */
529 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
);
531 /* Adjust addresses (in BE32 mode) before testing against watchpoint
534 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
);
536 /* Callback function for when a watchpoint or breakpoint triggers. */
537 void arm_debug_excp_handler(CPUState
*cs
);
539 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
540 static inline bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
)
544 static inline void arm_handle_psci_call(ARMCPU
*cpu
)
546 g_assert_not_reached();
549 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
550 bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
);
551 /* Actually handle a PSCI call */
552 void arm_handle_psci_call(ARMCPU
*cpu
);
556 * arm_clear_exclusive: clear the exclusive monitor
558 * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
560 static inline void arm_clear_exclusive(CPUARMState
*env
)
562 env
->exclusive_addr
= -1;
566 * ARMFaultType: type of an ARM MMU fault
567 * This corresponds to the v8A pseudocode's Fault enumeration,
568 * with extensions for QEMU internal conditions.
570 typedef enum ARMFaultType
{
577 ARMFault_Translation
,
578 ARMFault_AddressSize
,
579 ARMFault_SyncExternal
,
580 ARMFault_SyncExternalOnWalk
,
582 ARMFault_SyncParityOnWalk
,
583 ARMFault_AsyncParity
,
584 ARMFault_AsyncExternal
,
586 ARMFault_TLBConflict
,
589 ARMFault_ICacheMaint
,
590 ARMFault_QEMU_NSCExec
, /* v8M: NS executing in S&NSC memory */
591 ARMFault_QEMU_SFault
, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
595 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
596 * @type: Type of fault
597 * @level: Table walk level (for translation, access flag and permission faults)
598 * @domain: Domain of the fault address (for non-LPAE CPUs only)
599 * @s2addr: Address that caused a fault at stage 2
600 * @stage2: True if we faulted at stage 2
601 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
602 * @s1ns: True if we faulted on a non-secure IPA while in secure state
603 * @ea: True if we should set the EA (external abort type) bit in syndrome
605 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo
;
606 struct ARMMMUFaultInfo
{
618 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
619 * Compare pseudocode EncodeSDFSC(), though unlike that function
620 * we set up a whole FSR-format code including domain field and
621 * putting the high bit of the FSC into bit 10.
623 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo
*fi
)
630 case ARMFault_AccessFlag
:
631 fsc
= fi
->level
== 1 ? 0x3 : 0x6;
633 case ARMFault_Alignment
:
636 case ARMFault_Permission
:
637 fsc
= fi
->level
== 1 ? 0xd : 0xf;
639 case ARMFault_Domain
:
640 fsc
= fi
->level
== 1 ? 0x9 : 0xb;
642 case ARMFault_Translation
:
643 fsc
= fi
->level
== 1 ? 0x5 : 0x7;
645 case ARMFault_SyncExternal
:
646 fsc
= 0x8 | (fi
->ea
<< 12);
648 case ARMFault_SyncExternalOnWalk
:
649 fsc
= fi
->level
== 1 ? 0xc : 0xe;
650 fsc
|= (fi
->ea
<< 12);
652 case ARMFault_SyncParity
:
655 case ARMFault_SyncParityOnWalk
:
656 fsc
= fi
->level
== 1 ? 0x40c : 0x40e;
658 case ARMFault_AsyncParity
:
661 case ARMFault_AsyncExternal
:
662 fsc
= 0x406 | (fi
->ea
<< 12);
667 case ARMFault_TLBConflict
:
670 case ARMFault_Lockdown
:
673 case ARMFault_Exclusive
:
676 case ARMFault_ICacheMaint
:
679 case ARMFault_Background
:
682 case ARMFault_QEMU_NSCExec
:
683 fsc
= M_FAKE_FSR_NSC_EXEC
;
685 case ARMFault_QEMU_SFault
:
686 fsc
= M_FAKE_FSR_SFAULT
;
689 /* Other faults can't occur in a context that requires a
690 * short-format status code.
692 g_assert_not_reached();
695 fsc
|= (fi
->domain
<< 4);
700 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
701 * Compare pseudocode EncodeLDFSC(), though unlike that function
702 * we fill in also the LPAE bit 9 of a DFSR format.
704 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo
*fi
)
711 case ARMFault_AddressSize
:
714 case ARMFault_AccessFlag
:
715 fsc
= (fi
->level
& 3) | (0x2 << 2);
717 case ARMFault_Permission
:
718 fsc
= (fi
->level
& 3) | (0x3 << 2);
720 case ARMFault_Translation
:
721 fsc
= (fi
->level
& 3) | (0x1 << 2);
723 case ARMFault_SyncExternal
:
724 fsc
= 0x10 | (fi
->ea
<< 12);
726 case ARMFault_SyncExternalOnWalk
:
727 fsc
= (fi
->level
& 3) | (0x5 << 2) | (fi
->ea
<< 12);
729 case ARMFault_SyncParity
:
732 case ARMFault_SyncParityOnWalk
:
733 fsc
= (fi
->level
& 3) | (0x7 << 2);
735 case ARMFault_AsyncParity
:
738 case ARMFault_AsyncExternal
:
739 fsc
= 0x11 | (fi
->ea
<< 12);
741 case ARMFault_Alignment
:
747 case ARMFault_TLBConflict
:
750 case ARMFault_Lockdown
:
753 case ARMFault_Exclusive
:
757 /* Other faults can't occur in a context that requires a
758 * long-format status code.
760 g_assert_not_reached();
767 static inline bool arm_extabort_type(MemTxResult result
)
769 /* The EA bit in syndromes and fault status registers is an
770 * IMPDEF classification of external aborts. ARM implementations
771 * usually use this to indicate AXI bus Decode error (0) or
772 * Slave error (1); in QEMU we follow that.
774 return result
!= MEMTX_DECODE_ERROR
;
777 bool arm_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
778 MMUAccessType access_type
, int mmu_idx
,
779 bool probe
, uintptr_t retaddr
);
781 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx
)
783 return mmu_idx
& ARM_MMU_IDX_COREIDX_MASK
;
786 static inline ARMMMUIdx
core_to_arm_mmu_idx(CPUARMState
*env
, int mmu_idx
)
788 if (arm_feature(env
, ARM_FEATURE_M
)) {
789 return mmu_idx
| ARM_MMU_IDX_M
;
791 return mmu_idx
| ARM_MMU_IDX_A
;
795 static inline ARMMMUIdx
core_to_aa64_mmu_idx(int mmu_idx
)
797 /* AArch64 is always a-profile. */
798 return mmu_idx
| ARM_MMU_IDX_A
;
801 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
);
804 * Return the MMU index for a v7M CPU with all relevant information
805 * manually specified.
807 ARMMMUIdx
arm_v7m_mmu_idx_all(CPUARMState
*env
,
808 bool secstate
, bool priv
, bool negpri
);
811 * Return the MMU index for a v7M CPU in the specified security and
814 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env
,
815 bool secstate
, bool priv
);
817 /* Return the MMU index for a v7M CPU in the specified security state */
818 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
);
820 /* Return true if the stage 1 translation regime is using LPAE format page
822 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
824 /* Raise a data fault alignment exception for the specified virtual address */
825 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
826 MMUAccessType access_type
,
827 int mmu_idx
, uintptr_t retaddr
);
829 /* arm_cpu_do_transaction_failed: handle a memory system error response
830 * (eg "no device/memory present at address") by raising an external abort
833 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
834 vaddr addr
, unsigned size
,
835 MMUAccessType access_type
,
836 int mmu_idx
, MemTxAttrs attrs
,
837 MemTxResult response
, uintptr_t retaddr
);
839 /* Call any registered EL change hooks */
840 static inline void arm_call_pre_el_change_hook(ARMCPU
*cpu
)
842 ARMELChangeHook
*hook
, *next
;
843 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
844 hook
->hook(cpu
, hook
->opaque
);
847 static inline void arm_call_el_change_hook(ARMCPU
*cpu
)
849 ARMELChangeHook
*hook
, *next
;
850 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
851 hook
->hook(cpu
, hook
->opaque
);
855 /* Return true if this address translation regime has two ranges. */
856 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx
)
859 case ARMMMUIdx_Stage1_E0
:
860 case ARMMMUIdx_Stage1_E1
:
861 case ARMMMUIdx_Stage1_E1_PAN
:
862 case ARMMMUIdx_Stage1_SE0
:
863 case ARMMMUIdx_Stage1_SE1
:
864 case ARMMMUIdx_Stage1_SE1_PAN
:
865 case ARMMMUIdx_E10_0
:
866 case ARMMMUIdx_E10_1
:
867 case ARMMMUIdx_E10_1_PAN
:
868 case ARMMMUIdx_E20_0
:
869 case ARMMMUIdx_E20_2
:
870 case ARMMMUIdx_E20_2_PAN
:
871 case ARMMMUIdx_SE10_0
:
872 case ARMMMUIdx_SE10_1
:
873 case ARMMMUIdx_SE10_1_PAN
:
874 case ARMMMUIdx_SE20_0
:
875 case ARMMMUIdx_SE20_2
:
876 case ARMMMUIdx_SE20_2_PAN
:
883 /* Return true if this address translation regime is secure */
884 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
887 case ARMMMUIdx_E10_0
:
888 case ARMMMUIdx_E10_1
:
889 case ARMMMUIdx_E10_1_PAN
:
890 case ARMMMUIdx_E20_0
:
891 case ARMMMUIdx_E20_2
:
892 case ARMMMUIdx_E20_2_PAN
:
893 case ARMMMUIdx_Stage1_E0
:
894 case ARMMMUIdx_Stage1_E1
:
895 case ARMMMUIdx_Stage1_E1_PAN
:
897 case ARMMMUIdx_Stage2
:
898 case ARMMMUIdx_MPrivNegPri
:
899 case ARMMMUIdx_MUserNegPri
:
900 case ARMMMUIdx_MPriv
:
901 case ARMMMUIdx_MUser
:
904 case ARMMMUIdx_SE10_0
:
905 case ARMMMUIdx_SE10_1
:
906 case ARMMMUIdx_SE10_1_PAN
:
907 case ARMMMUIdx_SE20_0
:
908 case ARMMMUIdx_SE20_2
:
909 case ARMMMUIdx_SE20_2_PAN
:
910 case ARMMMUIdx_Stage1_SE0
:
911 case ARMMMUIdx_Stage1_SE1
:
912 case ARMMMUIdx_Stage1_SE1_PAN
:
914 case ARMMMUIdx_Stage2_S
:
915 case ARMMMUIdx_MSPrivNegPri
:
916 case ARMMMUIdx_MSUserNegPri
:
917 case ARMMMUIdx_MSPriv
:
918 case ARMMMUIdx_MSUser
:
921 g_assert_not_reached();
925 static inline bool regime_is_pan(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
928 case ARMMMUIdx_Stage1_E1_PAN
:
929 case ARMMMUIdx_Stage1_SE1_PAN
:
930 case ARMMMUIdx_E10_1_PAN
:
931 case ARMMMUIdx_E20_2_PAN
:
932 case ARMMMUIdx_SE10_1_PAN
:
933 case ARMMMUIdx_SE20_2_PAN
:
940 /* Return the exception level which controls this address translation regime */
941 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
944 case ARMMMUIdx_SE20_0
:
945 case ARMMMUIdx_SE20_2
:
946 case ARMMMUIdx_SE20_2_PAN
:
947 case ARMMMUIdx_E20_0
:
948 case ARMMMUIdx_E20_2
:
949 case ARMMMUIdx_E20_2_PAN
:
950 case ARMMMUIdx_Stage2
:
951 case ARMMMUIdx_Stage2_S
:
957 case ARMMMUIdx_SE10_0
:
958 case ARMMMUIdx_Stage1_SE0
:
959 return arm_el_is_aa64(env
, 3) ? 1 : 3;
960 case ARMMMUIdx_SE10_1
:
961 case ARMMMUIdx_SE10_1_PAN
:
962 case ARMMMUIdx_Stage1_E0
:
963 case ARMMMUIdx_Stage1_E1
:
964 case ARMMMUIdx_Stage1_E1_PAN
:
965 case ARMMMUIdx_Stage1_SE1
:
966 case ARMMMUIdx_Stage1_SE1_PAN
:
967 case ARMMMUIdx_E10_0
:
968 case ARMMMUIdx_E10_1
:
969 case ARMMMUIdx_E10_1_PAN
:
970 case ARMMMUIdx_MPrivNegPri
:
971 case ARMMMUIdx_MUserNegPri
:
972 case ARMMMUIdx_MPriv
:
973 case ARMMMUIdx_MUser
:
974 case ARMMMUIdx_MSPrivNegPri
:
975 case ARMMMUIdx_MSUserNegPri
:
976 case ARMMMUIdx_MSPriv
:
977 case ARMMMUIdx_MSUser
:
980 g_assert_not_reached();
984 /* Return the TCR controlling this translation regime */
985 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
987 if (mmu_idx
== ARMMMUIdx_Stage2
) {
988 return &env
->cp15
.vtcr_el2
;
990 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
992 * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but
993 * those are not currently used by QEMU, so just return VSTCR_EL2.
995 return &env
->cp15
.vstcr_el2
;
997 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
1000 /* Return the FSR value for a debug exception (watchpoint, hardware
1001 * breakpoint or BKPT insn) targeting the specified exception level.
1003 static inline uint32_t arm_debug_exception_fsr(CPUARMState
*env
)
1005 ARMMMUFaultInfo fi
= { .type
= ARMFault_Debug
};
1006 int target_el
= arm_debug_target_el(env
);
1007 bool using_lpae
= false;
1009 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
)) {
1012 if (arm_feature(env
, ARM_FEATURE_LPAE
) &&
1013 (env
->cp15
.tcr_el
[target_el
].raw_tcr
& TTBCR_EAE
)) {
1019 return arm_fi_to_lfsc(&fi
);
1021 return arm_fi_to_sfsc(&fi
);
1026 * arm_num_brps: Return number of implemented breakpoints.
1027 * Note that the ID register BRPS field is "number of bps - 1",
1028 * and we return the actual number of breakpoints.
1030 static inline int arm_num_brps(ARMCPU
*cpu
)
1032 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1033 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, BRPS
) + 1;
1035 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, BRPS
) + 1;
1040 * arm_num_wrps: Return number of implemented watchpoints.
1041 * Note that the ID register WRPS field is "number of wps - 1",
1042 * and we return the actual number of watchpoints.
1044 static inline int arm_num_wrps(ARMCPU
*cpu
)
1046 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1047 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, WRPS
) + 1;
1049 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, WRPS
) + 1;
1054 * arm_num_ctx_cmps: Return number of implemented context comparators.
1055 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
1056 * and we return the actual number of comparators.
1058 static inline int arm_num_ctx_cmps(ARMCPU
*cpu
)
1060 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1061 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, CTX_CMPS
) + 1;
1063 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, CTX_CMPS
) + 1;
1068 * v7m_using_psp: Return true if using process stack pointer
1069 * Return true if the CPU is currently using the process stack
1070 * pointer, or false if it is using the main stack pointer.
1072 static inline bool v7m_using_psp(CPUARMState
*env
)
1074 /* Handler mode always uses the main stack; for thread mode
1075 * the CONTROL.SPSEL bit determines the answer.
1076 * Note that in v7M it is not possible to be in Handler mode with
1077 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
1079 return !arm_v7m_is_handler_mode(env
) &&
1080 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
1084 * v7m_sp_limit: Return SP limit for current CPU state
1085 * Return the SP limit value for the current CPU security state
1086 * and stack pointer.
1088 static inline uint32_t v7m_sp_limit(CPUARMState
*env
)
1090 if (v7m_using_psp(env
)) {
1091 return env
->v7m
.psplim
[env
->v7m
.secure
];
1093 return env
->v7m
.msplim
[env
->v7m
.secure
];
1099 * Return true if the v7M CPACR permits access to the FPU for the specified
1100 * security state and privilege level.
1102 static inline bool v7m_cpacr_pass(CPUARMState
*env
,
1103 bool is_secure
, bool is_priv
)
1105 switch (extract32(env
->v7m
.cpacr
[is_secure
], 20, 2)) {
1107 case 2: /* UNPREDICTABLE: we treat like 0 */
1114 g_assert_not_reached();
1119 * aarch32_mode_name(): Return name of the AArch32 CPU mode
1120 * @psr: Program Status Register indicating CPU mode
1122 * Returns, for debug logging purposes, a printable representation
1123 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
1124 * the low bits of the specified PSR.
1126 static inline const char *aarch32_mode_name(uint32_t psr
)
1128 static const char cpu_mode_names
[16][4] = {
1129 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
1130 "???", "???", "hyp", "und", "???", "???", "???", "sys"
1133 return cpu_mode_names
[psr
& 0xf];
1137 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request
1139 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following
1140 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit.
1141 * Must be called with the iothread lock held.
1143 void arm_cpu_update_virq(ARMCPU
*cpu
);
1146 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request
1148 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following
1149 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit.
1150 * Must be called with the iothread lock held.
1152 void arm_cpu_update_vfiq(ARMCPU
*cpu
);
1156 * @env: The cpu environment
1157 * @el: The EL to use.
1159 * Return the full ARMMMUIdx for the translation regime for EL.
1161 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
);
1165 * @env: The cpu environment
1167 * Return the full ARMMMUIdx for the current translation regime.
1169 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
);
1172 * arm_stage1_mmu_idx:
1173 * @env: The cpu environment
1175 * Return the ARMMMUIdx for the stage1 traversal for the current regime.
1177 #ifdef CONFIG_USER_ONLY
1178 static inline ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
1180 return ARMMMUIdx_Stage1_E0
;
1183 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
);
1187 * arm_mmu_idx_is_stage1_of_2:
1188 * @mmu_idx: The ARMMMUIdx to test
1190 * Return true if @mmu_idx is a NOTLB mmu_idx that is the
1191 * first stage of a two stage regime.
1193 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx
)
1196 case ARMMMUIdx_Stage1_E0
:
1197 case ARMMMUIdx_Stage1_E1
:
1198 case ARMMMUIdx_Stage1_E1_PAN
:
1199 case ARMMMUIdx_Stage1_SE0
:
1200 case ARMMMUIdx_Stage1_SE1
:
1201 case ARMMMUIdx_Stage1_SE1_PAN
:
1208 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features
,
1209 const ARMISARegisters
*id
)
1211 uint32_t valid
= CPSR_M
| CPSR_AIF
| CPSR_IL
| CPSR_NZCV
;
1213 if ((features
>> ARM_FEATURE_V4T
) & 1) {
1216 if ((features
>> ARM_FEATURE_V5
) & 1) {
1217 valid
|= CPSR_Q
; /* V5TE in reality*/
1219 if ((features
>> ARM_FEATURE_V6
) & 1) {
1220 valid
|= CPSR_E
| CPSR_GE
;
1222 if ((features
>> ARM_FEATURE_THUMB2
) & 1) {
1225 if (isar_feature_aa32_jazelle(id
)) {
1228 if (isar_feature_aa32_pan(id
)) {
1235 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters
*id
)
1239 valid
= PSTATE_M
| PSTATE_DAIF
| PSTATE_IL
| PSTATE_SS
| PSTATE_NZCV
;
1240 if (isar_feature_aa64_bti(id
)) {
1241 valid
|= PSTATE_BTYPE
;
1243 if (isar_feature_aa64_pan(id
)) {
1244 valid
|= PSTATE_PAN
;
1246 if (isar_feature_aa64_uao(id
)) {
1247 valid
|= PSTATE_UAO
;
1249 if (isar_feature_aa64_mte(id
)) {
1250 valid
|= PSTATE_TCO
;
1257 * Parameters of a given virtual address, as extracted from the
1258 * translation control register (TCR) for a given regime.
1260 typedef struct ARMVAParameters
{
1262 unsigned select
: 1;
1270 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
1271 ARMMMUIdx mmu_idx
, bool data
);
1273 static inline int exception_target_el(CPUARMState
*env
)
1275 int target_el
= MAX(1, arm_current_el(env
));
1278 * No such thing as secure EL1 if EL3 is aarch32,
1279 * so update the target EL to EL3 in this case.
1281 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
1288 /* Determine if allocation tags are available. */
1289 static inline bool allocation_tag_access_enabled(CPUARMState
*env
, int el
,
1293 && arm_feature(env
, ARM_FEATURE_EL3
)
1294 && !(env
->cp15
.scr_el3
& SCR_ATA
)) {
1297 if (el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
1298 uint64_t hcr
= arm_hcr_el2_eff(env
);
1299 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
1303 sctlr
&= (el
== 0 ? SCTLR_ATA0
: SCTLR_ATA
);
1307 #ifndef CONFIG_USER_ONLY
1309 /* Security attributes for an address, as returned by v8m_security_lookup. */
1310 typedef struct V8M_SAttributes
{
1311 bool subpage
; /* true if these attrs don't cover the whole TARGET_PAGE */
1320 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
1321 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1322 V8M_SAttributes
*sattrs
);
1324 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
1325 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1326 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
1327 int *prot
, bool *is_subpage
,
1328 ARMMMUFaultInfo
*fi
, uint32_t *mregion
);
1330 /* Cacheability and shareability attributes for a memory access */
1331 typedef struct ARMCacheAttrs
{
1332 unsigned int attrs
:8; /* as in the MAIR register encoding */
1333 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
1336 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
1337 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1338 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
1339 target_ulong
*page_size
,
1340 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
1341 __attribute__((nonnull
));
1343 void arm_log_exception(int idx
);
1345 #endif /* !CONFIG_USER_ONLY */
1348 * The log2 of the words in the tag block, for GMID_EL1.BS.
1349 * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
1351 #define GMID_EL1_BS 6
1353 /* We associate one allocation tag per 16 bytes, the minimum. */
1354 #define LOG2_TAG_GRANULE 4
1355 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
1358 * SVE predicates are 1/8 the size of SVE vectors, and cannot use
1359 * the same simd_desc() encoding due to restrictions on size.
1360 * Use these instead.
1362 FIELD(PREDDESC
, OPRSZ
, 0, 6)
1363 FIELD(PREDDESC
, ESZ
, 6, 2)
1364 FIELD(PREDDESC
, DATA
, 8, 24)
1367 * The SVE simd_data field, for memory ops, contains either
1368 * rd (5 bits) or a shift count (2 bits).
1370 #define SVE_MTEDESC_SHIFT 5
1372 /* Bits within a descriptor passed to the helper_mte_check* functions. */
1373 FIELD(MTEDESC
, MIDX
, 0, 4)
1374 FIELD(MTEDESC
, TBI
, 4, 2)
1375 FIELD(MTEDESC
, TCMA
, 6, 2)
1376 FIELD(MTEDESC
, WRITE
, 8, 1)
1377 FIELD(MTEDESC
, ESIZE
, 9, 5)
1378 FIELD(MTEDESC
, TSIZE
, 14, 10) /* mte_checkN only */
1380 bool mte_probe1(CPUARMState
*env
, uint32_t desc
, uint64_t ptr
);
1381 uint64_t mte_check1(CPUARMState
*env
, uint32_t desc
,
1382 uint64_t ptr
, uintptr_t ra
);
1383 uint64_t mte_checkN(CPUARMState
*env
, uint32_t desc
,
1384 uint64_t ptr
, uintptr_t ra
);
1386 static inline int allocation_tag_from_addr(uint64_t ptr
)
1388 return extract64(ptr
, 56, 4);
1391 static inline uint64_t address_with_allocation_tag(uint64_t ptr
, int rtag
)
1393 return deposit64(ptr
, 56, 4, rtag
);
1396 /* Return true if tbi bits mean that the access is checked. */
1397 static inline bool tbi_check(uint32_t desc
, int bit55
)
1399 return (desc
>> (R_MTEDESC_TBI_SHIFT
+ bit55
)) & 1;
1402 /* Return true if tcma bits mean that the access is unchecked. */
1403 static inline bool tcma_check(uint32_t desc
, int bit55
, int ptr_tag
)
1406 * We had extracted bit55 and ptr_tag for other reasons, so fold
1407 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test.
1409 bool match
= ((ptr_tag
+ bit55
) & 0xf) == 0;
1410 bool tcma
= (desc
>> (R_MTEDESC_TCMA_SHIFT
+ bit55
)) & 1;
1411 return tcma
&& match
;
1415 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
1416 * for the tag to be present in the FAR_ELx register. But for user-only
1417 * mode, we do not have a TLB with which to implement this, so we must
1418 * remove the top byte.
1420 static inline uint64_t useronly_clean_ptr(uint64_t ptr
)
1422 /* TBI is known to be enabled. */
1423 #ifdef CONFIG_USER_ONLY
1424 ptr
= sextract64(ptr
, 0, 56);
1429 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc
, uint64_t ptr
)
1431 #ifdef CONFIG_USER_ONLY
1432 int64_t clean_ptr
= sextract64(ptr
, 0, 56);
1433 if (tbi_check(desc
, clean_ptr
< 0)) {