target/arm/cpu_tcg.c

   1 /*
   2  * QEMU ARM TCG CPUs.
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This code is licensed under the GNU GPL v2 or later.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0-or-later
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "cpu.h"
  13 #ifdef CONFIG_TCG
  14 #include "hw/core/tcg-cpu-ops.h"
  15 #endif /* CONFIG_TCG */
  16 #include "internals.h"
  17
  18 /* CPU models. These are not needed for the AArch64 linux-user build. */
  19 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
  20
  21 #ifdef CONFIG_TCG
  22 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  23 {
  24     CPUClass *cc = CPU_GET_CLASS(cs);
  25     ARMCPU *cpu = ARM_CPU(cs);
  26     CPUARMState *env = &cpu->env;
  27     bool ret = false;
  28
  29     /*
  30      * ARMv7-M interrupt masking works differently than -A or -R.
  31      * There is no FIQ/IRQ distinction. Instead of I and F bits
  32      * masking FIQ and IRQ interrupts, an exception is taken only
  33      * if it is higher priority than the current execution priority
  34      * (which depends on state like BASEPRI, FAULTMASK and the
  35      * currently active exception).
  36      */
  37     if (interrupt_request & CPU_INTERRUPT_HARD
  38         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
  39         cs->exception_index = EXCP_IRQ;
  40         cc->tcg_ops->do_interrupt(cs);
  41         ret = true;
  42     }
  43     return ret;
  44 }
  45 #endif /* CONFIG_TCG */
  46
  47 static void arm926_initfn(Object *obj)
  48 {
  49     ARMCPU *cpu = ARM_CPU(obj);
  50
  51     cpu->dtb_compatible = "arm,arm926";
  52     set_feature(&cpu->env, ARM_FEATURE_V5);
  53     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  54     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
  55     cpu->midr = 0x41069265;
  56     cpu->reset_fpsid = 0x41011090;
  57     cpu->ctr = 0x1dd20d2;
  58     cpu->reset_sctlr = 0x00090078;
  59
  60     /*
  61      * ARMv5 does not have the ID_ISAR registers, but we can still
  62      * set the field to indicate Jazelle support within QEMU.
  63      */
  64     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
  65     /*
  66      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
  67      * support even though ARMv5 doesn't have this register.
  68      */
  69     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
  70     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
  71     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
  72 }
  73
  74 static void arm946_initfn(Object *obj)
  75 {
  76     ARMCPU *cpu = ARM_CPU(obj);
  77
  78     cpu->dtb_compatible = "arm,arm946";
  79     set_feature(&cpu->env, ARM_FEATURE_V5);
  80     set_feature(&cpu->env, ARM_FEATURE_PMSA);
  81     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  82     cpu->midr = 0x41059461;
  83     cpu->ctr = 0x0f004006;
  84     cpu->reset_sctlr = 0x00000078;
  85 }
  86
  87 static void arm1026_initfn(Object *obj)
  88 {
  89     ARMCPU *cpu = ARM_CPU(obj);
  90
  91     cpu->dtb_compatible = "arm,arm1026";
  92     set_feature(&cpu->env, ARM_FEATURE_V5);
  93     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
  94     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  95     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
  96     cpu->midr = 0x4106a262;
  97     cpu->reset_fpsid = 0x410110a0;
  98     cpu->ctr = 0x1dd20d2;
  99     cpu->reset_sctlr = 0x00090078;
 100     cpu->reset_auxcr = 1;
 101
 102     /*
 103      * ARMv5 does not have the ID_ISAR registers, but we can still
 104      * set the field to indicate Jazelle support within QEMU.
 105      */
 106     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 107     /*
 108      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 109      * support even though ARMv5 doesn't have this register.
 110      */
 111     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 112     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 113     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 114
 115     {
 116         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 117         ARMCPRegInfo ifar = {
 118             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 119             .access = PL1_RW,
 120             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 121             .resetvalue = 0
 122         };
 123         define_one_arm_cp_reg(cpu, &ifar);
 124     }
 125 }
 126
 127 static void arm1136_r2_initfn(Object *obj)
 128 {
 129     ARMCPU *cpu = ARM_CPU(obj);
 130     /*
 131      * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 132      * older core than plain "arm1136". In particular this does not
 133      * have the v6K features.
 134      * These ID register values are correct for 1136 but may be wrong
 135      * for 1136_r2 (in particular r0p2 does not actually implement most
 136      * of the ID registers).
 137      */
 138
 139     cpu->dtb_compatible = "arm,arm1136";
 140     set_feature(&cpu->env, ARM_FEATURE_V6);
 141     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 142     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 143     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 144     cpu->midr = 0x4107b362;
 145     cpu->reset_fpsid = 0x410120b4;
 146     cpu->isar.mvfr0 = 0x11111111;
 147     cpu->isar.mvfr1 = 0x00000000;
 148     cpu->ctr = 0x1dd20d2;
 149     cpu->reset_sctlr = 0x00050078;
 150     cpu->isar.id_pfr0 = 0x111;
 151     cpu->isar.id_pfr1 = 0x1;
 152     cpu->isar.id_dfr0 = 0x2;
 153     cpu->id_afr0 = 0x3;
 154     cpu->isar.id_mmfr0 = 0x01130003;
 155     cpu->isar.id_mmfr1 = 0x10030302;
 156     cpu->isar.id_mmfr2 = 0x01222110;
 157     cpu->isar.id_isar0 = 0x00140011;
 158     cpu->isar.id_isar1 = 0x12002111;
 159     cpu->isar.id_isar2 = 0x11231111;
 160     cpu->isar.id_isar3 = 0x01102131;
 161     cpu->isar.id_isar4 = 0x141;
 162     cpu->reset_auxcr = 7;
 163 }
 164
 165 static void arm1136_initfn(Object *obj)
 166 {
 167     ARMCPU *cpu = ARM_CPU(obj);
 168
 169     cpu->dtb_compatible = "arm,arm1136";
 170     set_feature(&cpu->env, ARM_FEATURE_V6K);
 171     set_feature(&cpu->env, ARM_FEATURE_V6);
 172     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 173     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 174     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 175     cpu->midr = 0x4117b363;
 176     cpu->reset_fpsid = 0x410120b4;
 177     cpu->isar.mvfr0 = 0x11111111;
 178     cpu->isar.mvfr1 = 0x00000000;
 179     cpu->ctr = 0x1dd20d2;
 180     cpu->reset_sctlr = 0x00050078;
 181     cpu->isar.id_pfr0 = 0x111;
 182     cpu->isar.id_pfr1 = 0x1;
 183     cpu->isar.id_dfr0 = 0x2;
 184     cpu->id_afr0 = 0x3;
 185     cpu->isar.id_mmfr0 = 0x01130003;
 186     cpu->isar.id_mmfr1 = 0x10030302;
 187     cpu->isar.id_mmfr2 = 0x01222110;
 188     cpu->isar.id_isar0 = 0x00140011;
 189     cpu->isar.id_isar1 = 0x12002111;
 190     cpu->isar.id_isar2 = 0x11231111;
 191     cpu->isar.id_isar3 = 0x01102131;
 192     cpu->isar.id_isar4 = 0x141;
 193     cpu->reset_auxcr = 7;
 194 }
 195
 196 static void arm1176_initfn(Object *obj)
 197 {
 198     ARMCPU *cpu = ARM_CPU(obj);
 199
 200     cpu->dtb_compatible = "arm,arm1176";
 201     set_feature(&cpu->env, ARM_FEATURE_V6K);
 202     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 203     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 204     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 205     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 206     set_feature(&cpu->env, ARM_FEATURE_EL3);
 207     cpu->midr = 0x410fb767;
 208     cpu->reset_fpsid = 0x410120b5;
 209     cpu->isar.mvfr0 = 0x11111111;
 210     cpu->isar.mvfr1 = 0x00000000;
 211     cpu->ctr = 0x1dd20d2;
 212     cpu->reset_sctlr = 0x00050078;
 213     cpu->isar.id_pfr0 = 0x111;
 214     cpu->isar.id_pfr1 = 0x11;
 215     cpu->isar.id_dfr0 = 0x33;
 216     cpu->id_afr0 = 0;
 217     cpu->isar.id_mmfr0 = 0x01130003;
 218     cpu->isar.id_mmfr1 = 0x10030302;
 219     cpu->isar.id_mmfr2 = 0x01222100;
 220     cpu->isar.id_isar0 = 0x0140011;
 221     cpu->isar.id_isar1 = 0x12002111;
 222     cpu->isar.id_isar2 = 0x11231121;
 223     cpu->isar.id_isar3 = 0x01102131;
 224     cpu->isar.id_isar4 = 0x01141;
 225     cpu->reset_auxcr = 7;
 226 }
 227
 228 static void arm11mpcore_initfn(Object *obj)
 229 {
 230     ARMCPU *cpu = ARM_CPU(obj);
 231
 232     cpu->dtb_compatible = "arm,arm11mpcore";
 233     set_feature(&cpu->env, ARM_FEATURE_V6K);
 234     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 235     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 236     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 237     cpu->midr = 0x410fb022;
 238     cpu->reset_fpsid = 0x410120b4;
 239     cpu->isar.mvfr0 = 0x11111111;
 240     cpu->isar.mvfr1 = 0x00000000;
 241     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 242     cpu->isar.id_pfr0 = 0x111;
 243     cpu->isar.id_pfr1 = 0x1;
 244     cpu->isar.id_dfr0 = 0;
 245     cpu->id_afr0 = 0x2;
 246     cpu->isar.id_mmfr0 = 0x01100103;
 247     cpu->isar.id_mmfr1 = 0x10020302;
 248     cpu->isar.id_mmfr2 = 0x01222000;
 249     cpu->isar.id_isar0 = 0x00100011;
 250     cpu->isar.id_isar1 = 0x12002111;
 251     cpu->isar.id_isar2 = 0x11221011;
 252     cpu->isar.id_isar3 = 0x01102131;
 253     cpu->isar.id_isar4 = 0x141;
 254     cpu->reset_auxcr = 1;
 255 }
 256
 257 static void cortex_m0_initfn(Object *obj)
 258 {
 259     ARMCPU *cpu = ARM_CPU(obj);
 260     set_feature(&cpu->env, ARM_FEATURE_V6);
 261     set_feature(&cpu->env, ARM_FEATURE_M);
 262
 263     cpu->midr = 0x410cc200;
 264
 265     /*
 266      * These ID register values are not guest visible, because
 267      * we do not implement the Main Extension. They must be set
 268      * to values corresponding to the Cortex-M0's implemented
 269      * features, because QEMU generally controls its emulation
 270      * by looking at ID register fields. We use the same values as
 271      * for the M3.
 272      */
 273     cpu->isar.id_pfr0 = 0x00000030;
 274     cpu->isar.id_pfr1 = 0x00000200;
 275     cpu->isar.id_dfr0 = 0x00100000;
 276     cpu->id_afr0 = 0x00000000;
 277     cpu->isar.id_mmfr0 = 0x00000030;
 278     cpu->isar.id_mmfr1 = 0x00000000;
 279     cpu->isar.id_mmfr2 = 0x00000000;
 280     cpu->isar.id_mmfr3 = 0x00000000;
 281     cpu->isar.id_isar0 = 0x01141110;
 282     cpu->isar.id_isar1 = 0x02111000;
 283     cpu->isar.id_isar2 = 0x21112231;
 284     cpu->isar.id_isar3 = 0x01111110;
 285     cpu->isar.id_isar4 = 0x01310102;
 286     cpu->isar.id_isar5 = 0x00000000;
 287     cpu->isar.id_isar6 = 0x00000000;
 288 }
 289
 290 static void cortex_m3_initfn(Object *obj)
 291 {
 292     ARMCPU *cpu = ARM_CPU(obj);
 293     set_feature(&cpu->env, ARM_FEATURE_V7);
 294     set_feature(&cpu->env, ARM_FEATURE_M);
 295     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 296     cpu->midr = 0x410fc231;
 297     cpu->pmsav7_dregion = 8;
 298     cpu->isar.id_pfr0 = 0x00000030;
 299     cpu->isar.id_pfr1 = 0x00000200;
 300     cpu->isar.id_dfr0 = 0x00100000;
 301     cpu->id_afr0 = 0x00000000;
 302     cpu->isar.id_mmfr0 = 0x00000030;
 303     cpu->isar.id_mmfr1 = 0x00000000;
 304     cpu->isar.id_mmfr2 = 0x00000000;
 305     cpu->isar.id_mmfr3 = 0x00000000;
 306     cpu->isar.id_isar0 = 0x01141110;
 307     cpu->isar.id_isar1 = 0x02111000;
 308     cpu->isar.id_isar2 = 0x21112231;
 309     cpu->isar.id_isar3 = 0x01111110;
 310     cpu->isar.id_isar4 = 0x01310102;
 311     cpu->isar.id_isar5 = 0x00000000;
 312     cpu->isar.id_isar6 = 0x00000000;
 313 }
 314
 315 static void cortex_m4_initfn(Object *obj)
 316 {
 317     ARMCPU *cpu = ARM_CPU(obj);
 318
 319     set_feature(&cpu->env, ARM_FEATURE_V7);
 320     set_feature(&cpu->env, ARM_FEATURE_M);
 321     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 322     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 323     cpu->midr = 0x410fc240; /* r0p0 */
 324     cpu->pmsav7_dregion = 8;
 325     cpu->isar.mvfr0 = 0x10110021;
 326     cpu->isar.mvfr1 = 0x11000011;
 327     cpu->isar.mvfr2 = 0x00000000;
 328     cpu->isar.id_pfr0 = 0x00000030;
 329     cpu->isar.id_pfr1 = 0x00000200;
 330     cpu->isar.id_dfr0 = 0x00100000;
 331     cpu->id_afr0 = 0x00000000;
 332     cpu->isar.id_mmfr0 = 0x00000030;
 333     cpu->isar.id_mmfr1 = 0x00000000;
 334     cpu->isar.id_mmfr2 = 0x00000000;
 335     cpu->isar.id_mmfr3 = 0x00000000;
 336     cpu->isar.id_isar0 = 0x01141110;
 337     cpu->isar.id_isar1 = 0x02111000;
 338     cpu->isar.id_isar2 = 0x21112231;
 339     cpu->isar.id_isar3 = 0x01111110;
 340     cpu->isar.id_isar4 = 0x01310102;
 341     cpu->isar.id_isar5 = 0x00000000;
 342     cpu->isar.id_isar6 = 0x00000000;
 343 }
 344
 345 static void cortex_m7_initfn(Object *obj)
 346 {
 347     ARMCPU *cpu = ARM_CPU(obj);
 348
 349     set_feature(&cpu->env, ARM_FEATURE_V7);
 350     set_feature(&cpu->env, ARM_FEATURE_M);
 351     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 352     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 353     cpu->midr = 0x411fc272; /* r1p2 */
 354     cpu->pmsav7_dregion = 8;
 355     cpu->isar.mvfr0 = 0x10110221;
 356     cpu->isar.mvfr1 = 0x12000011;
 357     cpu->isar.mvfr2 = 0x00000040;
 358     cpu->isar.id_pfr0 = 0x00000030;
 359     cpu->isar.id_pfr1 = 0x00000200;
 360     cpu->isar.id_dfr0 = 0x00100000;
 361     cpu->id_afr0 = 0x00000000;
 362     cpu->isar.id_mmfr0 = 0x00100030;
 363     cpu->isar.id_mmfr1 = 0x00000000;
 364     cpu->isar.id_mmfr2 = 0x01000000;
 365     cpu->isar.id_mmfr3 = 0x00000000;
 366     cpu->isar.id_isar0 = 0x01101110;
 367     cpu->isar.id_isar1 = 0x02112000;
 368     cpu->isar.id_isar2 = 0x20232231;
 369     cpu->isar.id_isar3 = 0x01111131;
 370     cpu->isar.id_isar4 = 0x01310132;
 371     cpu->isar.id_isar5 = 0x00000000;
 372     cpu->isar.id_isar6 = 0x00000000;
 373 }
 374
 375 static void cortex_m33_initfn(Object *obj)
 376 {
 377     ARMCPU *cpu = ARM_CPU(obj);
 378
 379     set_feature(&cpu->env, ARM_FEATURE_V8);
 380     set_feature(&cpu->env, ARM_FEATURE_M);
 381     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 382     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 383     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 384     cpu->midr = 0x410fd213; /* r0p3 */
 385     cpu->pmsav7_dregion = 16;
 386     cpu->sau_sregion = 8;
 387     cpu->isar.mvfr0 = 0x10110021;
 388     cpu->isar.mvfr1 = 0x11000011;
 389     cpu->isar.mvfr2 = 0x00000040;
 390     cpu->isar.id_pfr0 = 0x00000030;
 391     cpu->isar.id_pfr1 = 0x00000210;
 392     cpu->isar.id_dfr0 = 0x00200000;
 393     cpu->id_afr0 = 0x00000000;
 394     cpu->isar.id_mmfr0 = 0x00101F40;
 395     cpu->isar.id_mmfr1 = 0x00000000;
 396     cpu->isar.id_mmfr2 = 0x01000000;
 397     cpu->isar.id_mmfr3 = 0x00000000;
 398     cpu->isar.id_isar0 = 0x01101110;
 399     cpu->isar.id_isar1 = 0x02212000;
 400     cpu->isar.id_isar2 = 0x20232232;
 401     cpu->isar.id_isar3 = 0x01111131;
 402     cpu->isar.id_isar4 = 0x01310132;
 403     cpu->isar.id_isar5 = 0x00000000;
 404     cpu->isar.id_isar6 = 0x00000000;
 405     cpu->clidr = 0x00000000;
 406     cpu->ctr = 0x8000c000;
 407 }
 408
 409 static void cortex_m55_initfn(Object *obj)
 410 {
 411     ARMCPU *cpu = ARM_CPU(obj);
 412
 413     set_feature(&cpu->env, ARM_FEATURE_V8);
 414     set_feature(&cpu->env, ARM_FEATURE_V8_1M);
 415     set_feature(&cpu->env, ARM_FEATURE_M);
 416     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 417     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 418     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 419     cpu->midr = 0x410fd221; /* r0p1 */
 420     cpu->revidr = 0;
 421     cpu->pmsav7_dregion = 16;
 422     cpu->sau_sregion = 8;
 423     /*
 424      * These are the MVFR* values for the FPU, no MVE configuration;
 425      * we will update them later when we implement MVE
 426      */
 427     cpu->isar.mvfr0 = 0x10110221;
 428     cpu->isar.mvfr1 = 0x12100011;
 429     cpu->isar.mvfr2 = 0x00000040;
 430     cpu->isar.id_pfr0 = 0x20000030;
 431     cpu->isar.id_pfr1 = 0x00000230;
 432     cpu->isar.id_dfr0 = 0x10200000;
 433     cpu->id_afr0 = 0x00000000;
 434     cpu->isar.id_mmfr0 = 0x00111040;
 435     cpu->isar.id_mmfr1 = 0x00000000;
 436     cpu->isar.id_mmfr2 = 0x01000000;
 437     cpu->isar.id_mmfr3 = 0x00000011;
 438     cpu->isar.id_isar0 = 0x01103110;
 439     cpu->isar.id_isar1 = 0x02212000;
 440     cpu->isar.id_isar2 = 0x20232232;
 441     cpu->isar.id_isar3 = 0x01111131;
 442     cpu->isar.id_isar4 = 0x01310132;
 443     cpu->isar.id_isar5 = 0x00000000;
 444     cpu->isar.id_isar6 = 0x00000000;
 445     cpu->clidr = 0x00000000; /* caches not implemented */
 446     cpu->ctr = 0x8303c003;
 447 }
 448
 449 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 450     /* Dummy the TCM region regs for the moment */
 451     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 452       .access = PL1_RW, .type = ARM_CP_CONST },
 453     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 454       .access = PL1_RW, .type = ARM_CP_CONST },
 455     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
 456       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 457     REGINFO_SENTINEL
 458 };
 459
 460 static void cortex_r5_initfn(Object *obj)
 461 {
 462     ARMCPU *cpu = ARM_CPU(obj);
 463
 464     set_feature(&cpu->env, ARM_FEATURE_V7);
 465     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 466     set_feature(&cpu->env, ARM_FEATURE_PMSA);
 467     set_feature(&cpu->env, ARM_FEATURE_PMU);
 468     cpu->midr = 0x411fc153; /* r1p3 */
 469     cpu->isar.id_pfr0 = 0x0131;
 470     cpu->isar.id_pfr1 = 0x001;
 471     cpu->isar.id_dfr0 = 0x010400;
 472     cpu->id_afr0 = 0x0;
 473     cpu->isar.id_mmfr0 = 0x0210030;
 474     cpu->isar.id_mmfr1 = 0x00000000;
 475     cpu->isar.id_mmfr2 = 0x01200000;
 476     cpu->isar.id_mmfr3 = 0x0211;
 477     cpu->isar.id_isar0 = 0x02101111;
 478     cpu->isar.id_isar1 = 0x13112111;
 479     cpu->isar.id_isar2 = 0x21232141;
 480     cpu->isar.id_isar3 = 0x01112131;
 481     cpu->isar.id_isar4 = 0x0010142;
 482     cpu->isar.id_isar5 = 0x0;
 483     cpu->isar.id_isar6 = 0x0;
 484     cpu->mp_is_up = true;
 485     cpu->pmsav7_dregion = 16;
 486     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 487 }
 488
 489 static void cortex_r5f_initfn(Object *obj)
 490 {
 491     ARMCPU *cpu = ARM_CPU(obj);
 492
 493     cortex_r5_initfn(obj);
 494     cpu->isar.mvfr0 = 0x10110221;
 495     cpu->isar.mvfr1 = 0x00000011;
 496 }
 497
 498 static void ti925t_initfn(Object *obj)
 499 {
 500     ARMCPU *cpu = ARM_CPU(obj);
 501     set_feature(&cpu->env, ARM_FEATURE_V4T);
 502     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 503     cpu->midr = ARM_CPUID_TI925T;
 504     cpu->ctr = 0x5109149;
 505     cpu->reset_sctlr = 0x00000070;
 506 }
 507
 508 static void sa1100_initfn(Object *obj)
 509 {
 510     ARMCPU *cpu = ARM_CPU(obj);
 511
 512     cpu->dtb_compatible = "intel,sa1100";
 513     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 514     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 515     cpu->midr = 0x4401A11B;
 516     cpu->reset_sctlr = 0x00000070;
 517 }
 518
 519 static void sa1110_initfn(Object *obj)
 520 {
 521     ARMCPU *cpu = ARM_CPU(obj);
 522     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 523     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 524     cpu->midr = 0x6901B119;
 525     cpu->reset_sctlr = 0x00000070;
 526 }
 527
 528 static void pxa250_initfn(Object *obj)
 529 {
 530     ARMCPU *cpu = ARM_CPU(obj);
 531
 532     cpu->dtb_compatible = "marvell,xscale";
 533     set_feature(&cpu->env, ARM_FEATURE_V5);
 534     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 535     cpu->midr = 0x69052100;
 536     cpu->ctr = 0xd172172;
 537     cpu->reset_sctlr = 0x00000078;
 538 }
 539
 540 static void pxa255_initfn(Object *obj)
 541 {
 542     ARMCPU *cpu = ARM_CPU(obj);
 543
 544     cpu->dtb_compatible = "marvell,xscale";
 545     set_feature(&cpu->env, ARM_FEATURE_V5);
 546     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 547     cpu->midr = 0x69052d00;
 548     cpu->ctr = 0xd172172;
 549     cpu->reset_sctlr = 0x00000078;
 550 }
 551
 552 static void pxa260_initfn(Object *obj)
 553 {
 554     ARMCPU *cpu = ARM_CPU(obj);
 555
 556     cpu->dtb_compatible = "marvell,xscale";
 557     set_feature(&cpu->env, ARM_FEATURE_V5);
 558     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 559     cpu->midr = 0x69052903;
 560     cpu->ctr = 0xd172172;
 561     cpu->reset_sctlr = 0x00000078;
 562 }
 563
 564 static void pxa261_initfn(Object *obj)
 565 {
 566     ARMCPU *cpu = ARM_CPU(obj);
 567
 568     cpu->dtb_compatible = "marvell,xscale";
 569     set_feature(&cpu->env, ARM_FEATURE_V5);
 570     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 571     cpu->midr = 0x69052d05;
 572     cpu->ctr = 0xd172172;
 573     cpu->reset_sctlr = 0x00000078;
 574 }
 575
 576 static void pxa262_initfn(Object *obj)
 577 {
 578     ARMCPU *cpu = ARM_CPU(obj);
 579
 580     cpu->dtb_compatible = "marvell,xscale";
 581     set_feature(&cpu->env, ARM_FEATURE_V5);
 582     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 583     cpu->midr = 0x69052d06;
 584     cpu->ctr = 0xd172172;
 585     cpu->reset_sctlr = 0x00000078;
 586 }
 587
 588 static void pxa270a0_initfn(Object *obj)
 589 {
 590     ARMCPU *cpu = ARM_CPU(obj);
 591
 592     cpu->dtb_compatible = "marvell,xscale";
 593     set_feature(&cpu->env, ARM_FEATURE_V5);
 594     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 595     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 596     cpu->midr = 0x69054110;
 597     cpu->ctr = 0xd172172;
 598     cpu->reset_sctlr = 0x00000078;
 599 }
 600
 601 static void pxa270a1_initfn(Object *obj)
 602 {
 603     ARMCPU *cpu = ARM_CPU(obj);
 604
 605     cpu->dtb_compatible = "marvell,xscale";
 606     set_feature(&cpu->env, ARM_FEATURE_V5);
 607     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 608     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 609     cpu->midr = 0x69054111;
 610     cpu->ctr = 0xd172172;
 611     cpu->reset_sctlr = 0x00000078;
 612 }
 613
 614 static void pxa270b0_initfn(Object *obj)
 615 {
 616     ARMCPU *cpu = ARM_CPU(obj);
 617
 618     cpu->dtb_compatible = "marvell,xscale";
 619     set_feature(&cpu->env, ARM_FEATURE_V5);
 620     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 621     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 622     cpu->midr = 0x69054112;
 623     cpu->ctr = 0xd172172;
 624     cpu->reset_sctlr = 0x00000078;
 625 }
 626
 627 static void pxa270b1_initfn(Object *obj)
 628 {
 629     ARMCPU *cpu = ARM_CPU(obj);
 630
 631     cpu->dtb_compatible = "marvell,xscale";
 632     set_feature(&cpu->env, ARM_FEATURE_V5);
 633     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 634     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 635     cpu->midr = 0x69054113;
 636     cpu->ctr = 0xd172172;
 637     cpu->reset_sctlr = 0x00000078;
 638 }
 639
 640 static void pxa270c0_initfn(Object *obj)
 641 {
 642     ARMCPU *cpu = ARM_CPU(obj);
 643
 644     cpu->dtb_compatible = "marvell,xscale";
 645     set_feature(&cpu->env, ARM_FEATURE_V5);
 646     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 647     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 648     cpu->midr = 0x69054114;
 649     cpu->ctr = 0xd172172;
 650     cpu->reset_sctlr = 0x00000078;
 651 }
 652
 653 static void pxa270c5_initfn(Object *obj)
 654 {
 655     ARMCPU *cpu = ARM_CPU(obj);
 656
 657     cpu->dtb_compatible = "marvell,xscale";
 658     set_feature(&cpu->env, ARM_FEATURE_V5);
 659     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 660     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 661     cpu->midr = 0x69054117;
 662     cpu->ctr = 0xd172172;
 663     cpu->reset_sctlr = 0x00000078;
 664 }
 665
 666 #ifdef CONFIG_TCG
 667 static struct TCGCPUOps arm_v7m_tcg_ops = {
 668     .initialize = arm_translate_init,
 669     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
 670     .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
 671     .tlb_fill = arm_cpu_tlb_fill,
 672     .debug_excp_handler = arm_debug_excp_handler,
 673
 674 #if !defined(CONFIG_USER_ONLY)
 675     .do_interrupt = arm_v7m_cpu_do_interrupt,
 676     .do_transaction_failed = arm_cpu_do_transaction_failed,
 677     .do_unaligned_access = arm_cpu_do_unaligned_access,
 678     .adjust_watchpoint_address = arm_adjust_watchpoint_address,
 679     .debug_check_watchpoint = arm_debug_check_watchpoint,
 680 #endif /* !CONFIG_USER_ONLY */
 681 };
 682 #endif /* CONFIG_TCG */
 683
 684 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 685 {
 686     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 687     CPUClass *cc = CPU_CLASS(oc);
 688
 689     acc->info = data;
 690 #ifdef CONFIG_TCG
 691     cc->tcg_ops = &arm_v7m_tcg_ops;
 692 #endif /* CONFIG_TCG */
 693
 694     cc->gdb_core_xml_file = "arm-m-profile.xml";
 695 }
 696
 697 static const ARMCPUInfo arm_tcg_cpus[] = {
 698     { .name = "arm926",      .initfn = arm926_initfn },
 699     { .name = "arm946",      .initfn = arm946_initfn },
 700     { .name = "arm1026",     .initfn = arm1026_initfn },
 701     /*
 702      * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 703      * older core than plain "arm1136". In particular this does not
 704      * have the v6K features.
 705      */
 706     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 707     { .name = "arm1136",     .initfn = arm1136_initfn },
 708     { .name = "arm1176",     .initfn = arm1176_initfn },
 709     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 710     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
 711                              .class_init = arm_v7m_class_init },
 712     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 713                              .class_init = arm_v7m_class_init },
 714     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
 715                              .class_init = arm_v7m_class_init },
 716     { .name = "cortex-m7",   .initfn = cortex_m7_initfn,
 717                              .class_init = arm_v7m_class_init },
 718     { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
 719                              .class_init = arm_v7m_class_init },
 720     { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
 721                              .class_init = arm_v7m_class_init },
 722     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
 723     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
 724     { .name = "ti925t",      .initfn = ti925t_initfn },
 725     { .name = "sa1100",      .initfn = sa1100_initfn },
 726     { .name = "sa1110",      .initfn = sa1110_initfn },
 727     { .name = "pxa250",      .initfn = pxa250_initfn },
 728     { .name = "pxa255",      .initfn = pxa255_initfn },
 729     { .name = "pxa260",      .initfn = pxa260_initfn },
 730     { .name = "pxa261",      .initfn = pxa261_initfn },
 731     { .name = "pxa262",      .initfn = pxa262_initfn },
 732     /* "pxa270" is an alias for "pxa270-a0" */
 733     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 734     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 735     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 736     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 737     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 738     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 739     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 740 };
 741
 742 static void arm_tcg_cpu_register_types(void)
 743 {
 744     size_t i;
 745
 746     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
 747         arm_cpu_register(&arm_tcg_cpus[i]);
 748     }
 749 }
 750
 751 type_init(arm_tcg_cpu_register_types)
 752
 753 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */