hw/char/xilinx_uartlite.c

   1 /*
   2  * QEMU model of Xilinx uartlite.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/log.h"
  27 #include "hw/irq.h"
  28 #include "hw/qdev-properties.h"
  29 #include "hw/sysbus.h"
  30 #include "qemu/module.h"
  31 #include "chardev/char-fe.h"
  32 #include "qom/object.h"
  33
  34 #define DUART(x)
  35
  36 #define R_RX            0
  37 #define R_TX            1
  38 #define R_STATUS        2
  39 #define R_CTRL          3
  40 #define R_MAX           4
  41
  42 #define STATUS_RXVALID    0x01
  43 #define STATUS_RXFULL     0x02
  44 #define STATUS_TXEMPTY    0x04
  45 #define STATUS_TXFULL     0x08
  46 #define STATUS_IE         0x10
  47 #define STATUS_OVERRUN    0x20
  48 #define STATUS_FRAME      0x40
  49 #define STATUS_PARITY     0x80
  50
  51 #define CONTROL_RST_TX    0x01
  52 #define CONTROL_RST_RX    0x02
  53 #define CONTROL_IE        0x10
  54
  55 #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
  56 OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
  57
  58 struct XilinxUARTLite {
  59     SysBusDevice parent_obj;
  60
  61     MemoryRegion mmio;
  62     CharBackend chr;
  63     qemu_irq irq;
  64
  65     uint8_t rx_fifo[8];
  66     unsigned int rx_fifo_pos;
  67     unsigned int rx_fifo_len;
  68
  69     uint32_t regs[R_MAX];
  70 };
  71
  72 static void uart_update_irq(XilinxUARTLite *s)
  73 {
  74     unsigned int irq;
  75
  76     if (s->rx_fifo_len)
  77         s->regs[R_STATUS] |= STATUS_IE;
  78
  79     irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
  80     qemu_set_irq(s->irq, irq);
  81 }
  82
  83 static void uart_update_status(XilinxUARTLite *s)
  84 {
  85     uint32_t r;
  86
  87     r = s->regs[R_STATUS];
  88     r &= ~7;
  89     r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
  90     r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
  91     r |= (!!s->rx_fifo_len);
  92     s->regs[R_STATUS] = r;
  93 }
  94
  95 static void xilinx_uartlite_reset(DeviceState *dev)
  96 {
  97     uart_update_status(XILINX_UARTLITE(dev));
  98 }
  99
 100 static uint64_t
 101 uart_read(void *opaque, hwaddr addr, unsigned int size)
 102 {
 103     XilinxUARTLite *s = opaque;
 104     uint32_t r = 0;
 105     addr >>= 2;
 106     switch (addr)
 107     {
 108         case R_RX:
 109             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
 110             if (s->rx_fifo_len)
 111                 s->rx_fifo_len--;
 112             uart_update_status(s);
 113             uart_update_irq(s);
 114             qemu_chr_fe_accept_input(&s->chr);
 115             break;
 116
 117         default:
 118             if (addr < ARRAY_SIZE(s->regs))
 119                 r = s->regs[addr];
 120             DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
 121             break;
 122     }
 123     return r;
 124 }
 125
 126 static void
 127 uart_write(void *opaque, hwaddr addr,
 128            uint64_t val64, unsigned int size)
 129 {
 130     XilinxUARTLite *s = opaque;
 131     uint32_t value = val64;
 132     unsigned char ch = value;
 133
 134     addr >>= 2;
 135     switch (addr)
 136     {
 137         case R_STATUS:
 138             qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
 139                           __func__);
 140             break;
 141
 142         case R_CTRL:
 143             if (value & CONTROL_RST_RX) {
 144                 s->rx_fifo_pos = 0;
 145                 s->rx_fifo_len = 0;
 146             }
 147             s->regs[addr] = value;
 148             break;
 149
 150         case R_TX:
 151             /* XXX this blocks entire thread. Rewrite to use
 152              * qemu_chr_fe_write and background I/O callbacks */
 153             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 154             s->regs[addr] = value;
 155
 156             /* hax.  */
 157             s->regs[R_STATUS] |= STATUS_IE;
 158             break;
 159
 160         default:
 161             DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
 162             if (addr < ARRAY_SIZE(s->regs))
 163                 s->regs[addr] = value;
 164             break;
 165     }
 166     uart_update_status(s);
 167     uart_update_irq(s);
 168 }
 169
 170 static const MemoryRegionOps uart_ops = {
 171     .read = uart_read,
 172     .write = uart_write,
 173     .endianness = DEVICE_NATIVE_ENDIAN,
 174     .valid = {
 175         .min_access_size = 1,
 176         .max_access_size = 4
 177     }
 178 };
 179
 180 static Property xilinx_uartlite_properties[] = {
 181     DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
 182     DEFINE_PROP_END_OF_LIST(),
 183 };
 184
 185 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 186 {
 187     XilinxUARTLite *s = opaque;
 188
 189     /* Got a byte.  */
 190     if (s->rx_fifo_len >= 8) {
 191         printf("WARNING: UART dropped char.\n");
 192         return;
 193     }
 194     s->rx_fifo[s->rx_fifo_pos] = *buf;
 195     s->rx_fifo_pos++;
 196     s->rx_fifo_pos &= 0x7;
 197     s->rx_fifo_len++;
 198
 199     uart_update_status(s);
 200     uart_update_irq(s);
 201 }
 202
 203 static int uart_can_rx(void *opaque)
 204 {
 205     XilinxUARTLite *s = opaque;
 206
 207     return s->rx_fifo_len < sizeof(s->rx_fifo);
 208 }
 209
 210 static void uart_event(void *opaque, QEMUChrEvent event)
 211 {
 212
 213 }
 214
 215 static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
 216 {
 217     XilinxUARTLite *s = XILINX_UARTLITE(dev);
 218
 219     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 220                              uart_event, NULL, s, NULL, true);
 221 }
 222
 223 static void xilinx_uartlite_init(Object *obj)
 224 {
 225     XilinxUARTLite *s = XILINX_UARTLITE(obj);
 226
 227     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 228
 229     memory_region_init_io(&s->mmio, obj, &uart_ops, s,
 230                           "xlnx.xps-uartlite", R_MAX * 4);
 231     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 232 }
 233
 234 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
 235 {
 236     DeviceClass *dc = DEVICE_CLASS(klass);
 237
 238     dc->reset = xilinx_uartlite_reset;
 239     dc->realize = xilinx_uartlite_realize;
 240     device_class_set_props(dc, xilinx_uartlite_properties);
 241 }
 242
 243 static const TypeInfo xilinx_uartlite_info = {
 244     .name          = TYPE_XILINX_UARTLITE,
 245     .parent        = TYPE_SYS_BUS_DEVICE,
 246     .instance_size = sizeof(XilinxUARTLite),
 247     .instance_init = xilinx_uartlite_init,
 248     .class_init    = xilinx_uartlite_class_init,
 249 };
 250
 251 static void xilinx_uart_register_types(void)
 252 {
 253     type_register_static(&xilinx_uartlite_info);
 254 }
 255
 256 type_init(xilinx_uart_register_types)