hw/arm/strongarm.c

   1 /*
   2  * StrongARM SA-1100/SA-1110 emulation
   3  *
   4  * Copyright (C) 2011 Dmitry Eremin-Solenikov
   5  *
   6  * Largely based on StrongARM emulation:
   7  * Copyright (c) 2006 Openedhand Ltd.
   8  * Written by Andrzej Zaborowski <balrog@zabor.org>
   9  *
  10  * UART code based on QEMU 16550A UART emulation
  11  * Copyright (c) 2003-2004 Fabrice Bellard
  12  * Copyright (c) 2008 Citrix Systems, Inc.
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License version 2 as
  16  *  published by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License along
  24  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  25  *
  26  *  Contributions after 2012-01-13 are licensed under the terms of the
  27  *  GNU GPL, version 2 or (at your option) any later version.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "cpu.h"
  32 #include "hw/boards.h"
  33 #include "hw/sysbus.h"
  34 #include "strongarm.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/arm/arm.h"
  37 #include "chardev/char-fe.h"
  38 #include "chardev/char-serial.h"
  39 #include "sysemu/sysemu.h"
  40 #include "hw/ssi/ssi.h"
  41 #include "qemu/cutils.h"
  42 #include "qemu/log.h"
  43
  44 //#define DEBUG
  45
  46 /*
  47  TODO
  48  - Implement cp15, c14 ?
  49  - Implement cp15, c15 !!! (idle used in L)
  50  - Implement idle mode handling/DIM
  51  - Implement sleep mode/Wake sources
  52  - Implement reset control
  53  - Implement memory control regs
  54  - PCMCIA handling
  55  - Maybe support MBGNT/MBREQ
  56  - DMA channels
  57  - GPCLK
  58  - IrDA
  59  - MCP
  60  - Enhance UART with modem signals
  61  */
  62
  63 #ifdef DEBUG
  64 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
  65 #else
  66 # define DPRINTF(format, ...) do { } while (0)
  67 #endif
  68
  69 static struct {
  70     hwaddr io_base;
  71     int irq;
  72 } sa_serial[] = {
  73     { 0x80010000, SA_PIC_UART1 },
  74     { 0x80030000, SA_PIC_UART2 },
  75     { 0x80050000, SA_PIC_UART3 },
  76     { 0, 0 }
  77 };
  78
  79 /* Interrupt Controller */
  80
  81 #define TYPE_STRONGARM_PIC "strongarm_pic"
  82 #define STRONGARM_PIC(obj) \
  83     OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
  84
  85 typedef struct StrongARMPICState {
  86     SysBusDevice parent_obj;
  87
  88     MemoryRegion iomem;
  89     qemu_irq    irq;
  90     qemu_irq    fiq;
  91
  92     uint32_t pending;
  93     uint32_t enabled;
  94     uint32_t is_fiq;
  95     uint32_t int_idle;
  96 } StrongARMPICState;
  97
  98 #define ICIP    0x00
  99 #define ICMR    0x04
 100 #define ICLR    0x08
 101 #define ICFP    0x10
 102 #define ICPR    0x20
 103 #define ICCR    0x0c
 104
 105 #define SA_PIC_SRCS     32
 106
 107
 108 static void strongarm_pic_update(void *opaque)
 109 {
 110     StrongARMPICState *s = opaque;
 111
 112     /* FIXME: reflect DIM */
 113     qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);
 114     qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
 115 }
 116
 117 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
 118 {
 119     StrongARMPICState *s = opaque;
 120
 121     if (level) {
 122         s->pending |= 1 << irq;
 123     } else {
 124         s->pending &= ~(1 << irq);
 125     }
 126
 127     strongarm_pic_update(s);
 128 }
 129
 130 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
 131                                        unsigned size)
 132 {
 133     StrongARMPICState *s = opaque;
 134
 135     switch (offset) {
 136     case ICIP:
 137         return s->pending & ~s->is_fiq & s->enabled;
 138     case ICMR:
 139         return s->enabled;
 140     case ICLR:
 141         return s->is_fiq;
 142     case ICCR:
 143         return s->int_idle == 0;
 144     case ICFP:
 145         return s->pending & s->is_fiq & s->enabled;
 146     case ICPR:
 147         return s->pending;
 148     default:
 149         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 150                         __func__, offset);
 151         return 0;
 152     }
 153 }
 154
 155 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
 156                                     uint64_t value, unsigned size)
 157 {
 158     StrongARMPICState *s = opaque;
 159
 160     switch (offset) {
 161     case ICMR:
 162         s->enabled = value;
 163         break;
 164     case ICLR:
 165         s->is_fiq = value;
 166         break;
 167     case ICCR:
 168         s->int_idle = (value & 1) ? 0 : ~0;
 169         break;
 170     default:
 171         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 172                         __func__, offset);
 173         break;
 174     }
 175     strongarm_pic_update(s);
 176 }
 177
 178 static const MemoryRegionOps strongarm_pic_ops = {
 179     .read = strongarm_pic_mem_read,
 180     .write = strongarm_pic_mem_write,
 181     .endianness = DEVICE_NATIVE_ENDIAN,
 182 };
 183
 184 static void strongarm_pic_initfn(Object *obj)
 185 {
 186     DeviceState *dev = DEVICE(obj);
 187     StrongARMPICState *s = STRONGARM_PIC(obj);
 188     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 189
 190     qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
 191     memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s,
 192                           "pic", 0x1000);
 193     sysbus_init_mmio(sbd, &s->iomem);
 194     sysbus_init_irq(sbd, &s->irq);
 195     sysbus_init_irq(sbd, &s->fiq);
 196 }
 197
 198 static int strongarm_pic_post_load(void *opaque, int version_id)
 199 {
 200     strongarm_pic_update(opaque);
 201     return 0;
 202 }
 203
 204 static VMStateDescription vmstate_strongarm_pic_regs = {
 205     .name = "strongarm_pic",
 206     .version_id = 0,
 207     .minimum_version_id = 0,
 208     .post_load = strongarm_pic_post_load,
 209     .fields = (VMStateField[]) {
 210         VMSTATE_UINT32(pending, StrongARMPICState),
 211         VMSTATE_UINT32(enabled, StrongARMPICState),
 212         VMSTATE_UINT32(is_fiq, StrongARMPICState),
 213         VMSTATE_UINT32(int_idle, StrongARMPICState),
 214         VMSTATE_END_OF_LIST(),
 215     },
 216 };
 217
 218 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
 219 {
 220     DeviceClass *dc = DEVICE_CLASS(klass);
 221
 222     dc->desc = "StrongARM PIC";
 223     dc->vmsd = &vmstate_strongarm_pic_regs;
 224 }
 225
 226 static const TypeInfo strongarm_pic_info = {
 227     .name          = TYPE_STRONGARM_PIC,
 228     .parent        = TYPE_SYS_BUS_DEVICE,
 229     .instance_size = sizeof(StrongARMPICState),
 230     .instance_init = strongarm_pic_initfn,
 231     .class_init    = strongarm_pic_class_init,
 232 };
 233
 234 /* Real-Time Clock */
 235 #define RTAR 0x00 /* RTC Alarm register */
 236 #define RCNR 0x04 /* RTC Counter register */
 237 #define RTTR 0x08 /* RTC Timer Trim register */
 238 #define RTSR 0x10 /* RTC Status register */
 239
 240 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
 241 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
 242 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
 243 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
 244
 245 /* 16 LSB of RTTR are clockdiv for internal trim logic,
 246  * trim delete isn't emulated, so
 247  * f = 32 768 / (RTTR_trim + 1) */
 248
 249 #define TYPE_STRONGARM_RTC "strongarm-rtc"
 250 #define STRONGARM_RTC(obj) \
 251     OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
 252
 253 typedef struct StrongARMRTCState {
 254     SysBusDevice parent_obj;
 255
 256     MemoryRegion iomem;
 257     uint32_t rttr;
 258     uint32_t rtsr;
 259     uint32_t rtar;
 260     uint32_t last_rcnr;
 261     int64_t last_hz;
 262     QEMUTimer *rtc_alarm;
 263     QEMUTimer *rtc_hz;
 264     qemu_irq rtc_irq;
 265     qemu_irq rtc_hz_irq;
 266 } StrongARMRTCState;
 267
 268 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
 269 {
 270     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
 271     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
 272 }
 273
 274 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
 275 {
 276     int64_t rt = qemu_clock_get_ms(rtc_clock);
 277     s->last_rcnr += ((rt - s->last_hz) << 15) /
 278             (1000 * ((s->rttr & 0xffff) + 1));
 279     s->last_hz = rt;
 280 }
 281
 282 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
 283 {
 284     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
 285         timer_mod(s->rtc_hz, s->last_hz + 1000);
 286     } else {
 287         timer_del(s->rtc_hz);
 288     }
 289
 290     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
 291         timer_mod(s->rtc_alarm, s->last_hz +
 292                 (((s->rtar - s->last_rcnr) * 1000 *
 293                   ((s->rttr & 0xffff) + 1)) >> 15));
 294     } else {
 295         timer_del(s->rtc_alarm);
 296     }
 297 }
 298
 299 static inline void strongarm_rtc_alarm_tick(void *opaque)
 300 {
 301     StrongARMRTCState *s = opaque;
 302     s->rtsr |= RTSR_AL;
 303     strongarm_rtc_timer_update(s);
 304     strongarm_rtc_int_update(s);
 305 }
 306
 307 static inline void strongarm_rtc_hz_tick(void *opaque)
 308 {
 309     StrongARMRTCState *s = opaque;
 310     s->rtsr |= RTSR_HZ;
 311     strongarm_rtc_timer_update(s);
 312     strongarm_rtc_int_update(s);
 313 }
 314
 315 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
 316                                    unsigned size)
 317 {
 318     StrongARMRTCState *s = opaque;
 319
 320     switch (addr) {
 321     case RTTR:
 322         return s->rttr;
 323     case RTSR:
 324         return s->rtsr;
 325     case RTAR:
 326         return s->rtar;
 327     case RCNR:
 328         return s->last_rcnr +
 329                 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
 330                 (1000 * ((s->rttr & 0xffff) + 1));
 331     default:
 332         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 333         return 0;
 334     }
 335 }
 336
 337 static void strongarm_rtc_write(void *opaque, hwaddr addr,
 338                                 uint64_t value, unsigned size)
 339 {
 340     StrongARMRTCState *s = opaque;
 341     uint32_t old_rtsr;
 342
 343     switch (addr) {
 344     case RTTR:
 345         strongarm_rtc_hzupdate(s);
 346         s->rttr = value;
 347         strongarm_rtc_timer_update(s);
 348         break;
 349
 350     case RTSR:
 351         old_rtsr = s->rtsr;
 352         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
 353                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
 354
 355         if (s->rtsr != old_rtsr) {
 356             strongarm_rtc_timer_update(s);
 357         }
 358
 359         strongarm_rtc_int_update(s);
 360         break;
 361
 362     case RTAR:
 363         s->rtar = value;
 364         strongarm_rtc_timer_update(s);
 365         break;
 366
 367     case RCNR:
 368         strongarm_rtc_hzupdate(s);
 369         s->last_rcnr = value;
 370         strongarm_rtc_timer_update(s);
 371         break;
 372
 373     default:
 374         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 375     }
 376 }
 377
 378 static const MemoryRegionOps strongarm_rtc_ops = {
 379     .read = strongarm_rtc_read,
 380     .write = strongarm_rtc_write,
 381     .endianness = DEVICE_NATIVE_ENDIAN,
 382 };
 383
 384 static void strongarm_rtc_init(Object *obj)
 385 {
 386     StrongARMRTCState *s = STRONGARM_RTC(obj);
 387     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 388     struct tm tm;
 389
 390     s->rttr = 0x0;
 391     s->rtsr = 0;
 392
 393     qemu_get_timedate(&tm, 0);
 394
 395     s->last_rcnr = (uint32_t) mktimegm(&tm);
 396     s->last_hz = qemu_clock_get_ms(rtc_clock);
 397
 398     s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
 399     s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
 400
 401     sysbus_init_irq(dev, &s->rtc_irq);
 402     sysbus_init_irq(dev, &s->rtc_hz_irq);
 403
 404     memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s,
 405                           "rtc", 0x10000);
 406     sysbus_init_mmio(dev, &s->iomem);
 407 }
 408
 409 static void strongarm_rtc_pre_save(void *opaque)
 410 {
 411     StrongARMRTCState *s = opaque;
 412
 413     strongarm_rtc_hzupdate(s);
 414 }
 415
 416 static int strongarm_rtc_post_load(void *opaque, int version_id)
 417 {
 418     StrongARMRTCState *s = opaque;
 419
 420     strongarm_rtc_timer_update(s);
 421     strongarm_rtc_int_update(s);
 422
 423     return 0;
 424 }
 425
 426 static const VMStateDescription vmstate_strongarm_rtc_regs = {
 427     .name = "strongarm-rtc",
 428     .version_id = 0,
 429     .minimum_version_id = 0,
 430     .pre_save = strongarm_rtc_pre_save,
 431     .post_load = strongarm_rtc_post_load,
 432     .fields = (VMStateField[]) {
 433         VMSTATE_UINT32(rttr, StrongARMRTCState),
 434         VMSTATE_UINT32(rtsr, StrongARMRTCState),
 435         VMSTATE_UINT32(rtar, StrongARMRTCState),
 436         VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
 437         VMSTATE_INT64(last_hz, StrongARMRTCState),
 438         VMSTATE_END_OF_LIST(),
 439     },
 440 };
 441
 442 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
 443 {
 444     DeviceClass *dc = DEVICE_CLASS(klass);
 445
 446     dc->desc = "StrongARM RTC Controller";
 447     dc->vmsd = &vmstate_strongarm_rtc_regs;
 448 }
 449
 450 static const TypeInfo strongarm_rtc_sysbus_info = {
 451     .name          = TYPE_STRONGARM_RTC,
 452     .parent        = TYPE_SYS_BUS_DEVICE,
 453     .instance_size = sizeof(StrongARMRTCState),
 454     .instance_init = strongarm_rtc_init,
 455     .class_init    = strongarm_rtc_sysbus_class_init,
 456 };
 457
 458 /* GPIO */
 459 #define GPLR 0x00
 460 #define GPDR 0x04
 461 #define GPSR 0x08
 462 #define GPCR 0x0c
 463 #define GRER 0x10
 464 #define GFER 0x14
 465 #define GEDR 0x18
 466 #define GAFR 0x1c
 467
 468 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
 469 #define STRONGARM_GPIO(obj) \
 470     OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
 471
 472 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
 473 struct StrongARMGPIOInfo {
 474     SysBusDevice busdev;
 475     MemoryRegion iomem;
 476     qemu_irq handler[28];
 477     qemu_irq irqs[11];
 478     qemu_irq irqX;
 479
 480     uint32_t ilevel;
 481     uint32_t olevel;
 482     uint32_t dir;
 483     uint32_t rising;
 484     uint32_t falling;
 485     uint32_t status;
 486     uint32_t gafr;
 487
 488     uint32_t prev_level;
 489 };
 490
 491
 492 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
 493 {
 494     int i;
 495     for (i = 0; i < 11; i++) {
 496         qemu_set_irq(s->irqs[i], s->status & (1 << i));
 497     }
 498
 499     qemu_set_irq(s->irqX, (s->status & ~0x7ff));
 500 }
 501
 502 static void strongarm_gpio_set(void *opaque, int line, int level)
 503 {
 504     StrongARMGPIOInfo *s = opaque;
 505     uint32_t mask;
 506
 507     mask = 1 << line;
 508
 509     if (level) {
 510         s->status |= s->rising & mask &
 511                 ~s->ilevel & ~s->dir;
 512         s->ilevel |= mask;
 513     } else {
 514         s->status |= s->falling & mask &
 515                 s->ilevel & ~s->dir;
 516         s->ilevel &= ~mask;
 517     }
 518
 519     if (s->status & mask) {
 520         strongarm_gpio_irq_update(s);
 521     }
 522 }
 523
 524 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
 525 {
 526     uint32_t level, diff;
 527     int bit;
 528
 529     level = s->olevel & s->dir;
 530
 531     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 532         bit = ctz32(diff);
 533         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 534     }
 535
 536     s->prev_level = level;
 537 }
 538
 539 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
 540                                     unsigned size)
 541 {
 542     StrongARMGPIOInfo *s = opaque;
 543
 544     switch (offset) {
 545     case GPDR:        /* GPIO Pin-Direction registers */
 546         return s->dir;
 547
 548     case GPSR:        /* GPIO Pin-Output Set registers */
 549         qemu_log_mask(LOG_GUEST_ERROR,
 550                       "strongarm GPIO: read from write only register GPSR\n");
 551         return 0;
 552
 553     case GPCR:        /* GPIO Pin-Output Clear registers */
 554         qemu_log_mask(LOG_GUEST_ERROR,
 555                       "strongarm GPIO: read from write only register GPCR\n");
 556         return 0;
 557
 558     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 559         return s->rising;
 560
 561     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 562         return s->falling;
 563
 564     case GAFR:        /* GPIO Alternate Function registers */
 565         return s->gafr;
 566
 567     case GPLR:        /* GPIO Pin-Level registers */
 568         return (s->olevel & s->dir) |
 569                (s->ilevel & ~s->dir);
 570
 571     case GEDR:        /* GPIO Edge Detect Status registers */
 572         return s->status;
 573
 574     default:
 575         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 576     }
 577
 578     return 0;
 579 }
 580
 581 static void strongarm_gpio_write(void *opaque, hwaddr offset,
 582                                  uint64_t value, unsigned size)
 583 {
 584     StrongARMGPIOInfo *s = opaque;
 585
 586     switch (offset) {
 587     case GPDR:        /* GPIO Pin-Direction registers */
 588         s->dir = value;
 589         strongarm_gpio_handler_update(s);
 590         break;
 591
 592     case GPSR:        /* GPIO Pin-Output Set registers */
 593         s->olevel |= value;
 594         strongarm_gpio_handler_update(s);
 595         break;
 596
 597     case GPCR:        /* GPIO Pin-Output Clear registers */
 598         s->olevel &= ~value;
 599         strongarm_gpio_handler_update(s);
 600         break;
 601
 602     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 603         s->rising = value;
 604         break;
 605
 606     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 607         s->falling = value;
 608         break;
 609
 610     case GAFR:        /* GPIO Alternate Function registers */
 611         s->gafr = value;
 612         break;
 613
 614     case GEDR:        /* GPIO Edge Detect Status registers */
 615         s->status &= ~value;
 616         strongarm_gpio_irq_update(s);
 617         break;
 618
 619     default:
 620         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 621     }
 622 }
 623
 624 static const MemoryRegionOps strongarm_gpio_ops = {
 625     .read = strongarm_gpio_read,
 626     .write = strongarm_gpio_write,
 627     .endianness = DEVICE_NATIVE_ENDIAN,
 628 };
 629
 630 static DeviceState *strongarm_gpio_init(hwaddr base,
 631                 DeviceState *pic)
 632 {
 633     DeviceState *dev;
 634     int i;
 635
 636     dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
 637     qdev_init_nofail(dev);
 638
 639     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 640     for (i = 0; i < 12; i++)
 641         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 642                     qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
 643
 644     return dev;
 645 }
 646
 647 static void strongarm_gpio_initfn(Object *obj)
 648 {
 649     DeviceState *dev = DEVICE(obj);
 650     StrongARMGPIOInfo *s = STRONGARM_GPIO(obj);
 651     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 652     int i;
 653
 654     qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
 655     qdev_init_gpio_out(dev, s->handler, 28);
 656
 657     memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s,
 658                           "gpio", 0x1000);
 659
 660     sysbus_init_mmio(sbd, &s->iomem);
 661     for (i = 0; i < 11; i++) {
 662         sysbus_init_irq(sbd, &s->irqs[i]);
 663     }
 664     sysbus_init_irq(sbd, &s->irqX);
 665 }
 666
 667 static const VMStateDescription vmstate_strongarm_gpio_regs = {
 668     .name = "strongarm-gpio",
 669     .version_id = 0,
 670     .minimum_version_id = 0,
 671     .fields = (VMStateField[]) {
 672         VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
 673         VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
 674         VMSTATE_UINT32(dir, StrongARMGPIOInfo),
 675         VMSTATE_UINT32(rising, StrongARMGPIOInfo),
 676         VMSTATE_UINT32(falling, StrongARMGPIOInfo),
 677         VMSTATE_UINT32(status, StrongARMGPIOInfo),
 678         VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
 679         VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
 680         VMSTATE_END_OF_LIST(),
 681     },
 682 };
 683
 684 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
 685 {
 686     DeviceClass *dc = DEVICE_CLASS(klass);
 687
 688     dc->desc = "StrongARM GPIO controller";
 689     dc->vmsd = &vmstate_strongarm_gpio_regs;
 690 }
 691
 692 static const TypeInfo strongarm_gpio_info = {
 693     .name          = TYPE_STRONGARM_GPIO,
 694     .parent        = TYPE_SYS_BUS_DEVICE,
 695     .instance_size = sizeof(StrongARMGPIOInfo),
 696     .instance_init = strongarm_gpio_initfn,
 697     .class_init    = strongarm_gpio_class_init,
 698 };
 699
 700 /* Peripheral Pin Controller */
 701 #define PPDR 0x00
 702 #define PPSR 0x04
 703 #define PPAR 0x08
 704 #define PSDR 0x0c
 705 #define PPFR 0x10
 706
 707 #define TYPE_STRONGARM_PPC "strongarm-ppc"
 708 #define STRONGARM_PPC(obj) \
 709     OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
 710
 711 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
 712 struct StrongARMPPCInfo {
 713     SysBusDevice parent_obj;
 714
 715     MemoryRegion iomem;
 716     qemu_irq handler[28];
 717
 718     uint32_t ilevel;
 719     uint32_t olevel;
 720     uint32_t dir;
 721     uint32_t ppar;
 722     uint32_t psdr;
 723     uint32_t ppfr;
 724
 725     uint32_t prev_level;
 726 };
 727
 728 static void strongarm_ppc_set(void *opaque, int line, int level)
 729 {
 730     StrongARMPPCInfo *s = opaque;
 731
 732     if (level) {
 733         s->ilevel |= 1 << line;
 734     } else {
 735         s->ilevel &= ~(1 << line);
 736     }
 737 }
 738
 739 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
 740 {
 741     uint32_t level, diff;
 742     int bit;
 743
 744     level = s->olevel & s->dir;
 745
 746     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 747         bit = ctz32(diff);
 748         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 749     }
 750
 751     s->prev_level = level;
 752 }
 753
 754 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
 755                                    unsigned size)
 756 {
 757     StrongARMPPCInfo *s = opaque;
 758
 759     switch (offset) {
 760     case PPDR:        /* PPC Pin Direction registers */
 761         return s->dir | ~0x3fffff;
 762
 763     case PPSR:        /* PPC Pin State registers */
 764         return (s->olevel & s->dir) |
 765                (s->ilevel & ~s->dir) |
 766                ~0x3fffff;
 767
 768     case PPAR:
 769         return s->ppar | ~0x41000;
 770
 771     case PSDR:
 772         return s->psdr;
 773
 774     case PPFR:
 775         return s->ppfr | ~0x7f001;
 776
 777     default:
 778         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 779     }
 780
 781     return 0;
 782 }
 783
 784 static void strongarm_ppc_write(void *opaque, hwaddr offset,
 785                                 uint64_t value, unsigned size)
 786 {
 787     StrongARMPPCInfo *s = opaque;
 788
 789     switch (offset) {
 790     case PPDR:        /* PPC Pin Direction registers */
 791         s->dir = value & 0x3fffff;
 792         strongarm_ppc_handler_update(s);
 793         break;
 794
 795     case PPSR:        /* PPC Pin State registers */
 796         s->olevel = value & s->dir & 0x3fffff;
 797         strongarm_ppc_handler_update(s);
 798         break;
 799
 800     case PPAR:
 801         s->ppar = value & 0x41000;
 802         break;
 803
 804     case PSDR:
 805         s->psdr = value & 0x3fffff;
 806         break;
 807
 808     case PPFR:
 809         s->ppfr = value & 0x7f001;
 810         break;
 811
 812     default:
 813         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 814     }
 815 }
 816
 817 static const MemoryRegionOps strongarm_ppc_ops = {
 818     .read = strongarm_ppc_read,
 819     .write = strongarm_ppc_write,
 820     .endianness = DEVICE_NATIVE_ENDIAN,
 821 };
 822
 823 static void strongarm_ppc_init(Object *obj)
 824 {
 825     DeviceState *dev = DEVICE(obj);
 826     StrongARMPPCInfo *s = STRONGARM_PPC(obj);
 827     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 828
 829     qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
 830     qdev_init_gpio_out(dev, s->handler, 22);
 831
 832     memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s,
 833                           "ppc", 0x1000);
 834
 835     sysbus_init_mmio(sbd, &s->iomem);
 836 }
 837
 838 static const VMStateDescription vmstate_strongarm_ppc_regs = {
 839     .name = "strongarm-ppc",
 840     .version_id = 0,
 841     .minimum_version_id = 0,
 842     .fields = (VMStateField[]) {
 843         VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
 844         VMSTATE_UINT32(olevel, StrongARMPPCInfo),
 845         VMSTATE_UINT32(dir, StrongARMPPCInfo),
 846         VMSTATE_UINT32(ppar, StrongARMPPCInfo),
 847         VMSTATE_UINT32(psdr, StrongARMPPCInfo),
 848         VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
 849         VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
 850         VMSTATE_END_OF_LIST(),
 851     },
 852 };
 853
 854 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
 855 {
 856     DeviceClass *dc = DEVICE_CLASS(klass);
 857
 858     dc->desc = "StrongARM PPC controller";
 859     dc->vmsd = &vmstate_strongarm_ppc_regs;
 860 }
 861
 862 static const TypeInfo strongarm_ppc_info = {
 863     .name          = TYPE_STRONGARM_PPC,
 864     .parent        = TYPE_SYS_BUS_DEVICE,
 865     .instance_size = sizeof(StrongARMPPCInfo),
 866     .instance_init = strongarm_ppc_init,
 867     .class_init    = strongarm_ppc_class_init,
 868 };
 869
 870 /* UART Ports */
 871 #define UTCR0 0x00
 872 #define UTCR1 0x04
 873 #define UTCR2 0x08
 874 #define UTCR3 0x0c
 875 #define UTDR  0x14
 876 #define UTSR0 0x1c
 877 #define UTSR1 0x20
 878
 879 #define UTCR0_PE  (1 << 0) /* Parity enable */
 880 #define UTCR0_OES (1 << 1) /* Even parity */
 881 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
 882 #define UTCR0_DSS (1 << 3) /* 8-bit data */
 883
 884 #define UTCR3_RXE (1 << 0) /* Rx enable */
 885 #define UTCR3_TXE (1 << 1) /* Tx enable */
 886 #define UTCR3_BRK (1 << 2) /* Force Break */
 887 #define UTCR3_RIE (1 << 3) /* Rx int enable */
 888 #define UTCR3_TIE (1 << 4) /* Tx int enable */
 889 #define UTCR3_LBM (1 << 5) /* Loopback */
 890
 891 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
 892 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
 893 #define UTSR0_RID (1 << 2) /* Receiver Idle */
 894 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
 895 #define UTSR0_REB (1 << 4) /* Receiver end break */
 896 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
 897
 898 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
 899 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
 900 #define UTSR1_PRE (1 << 3) /* Parity error */
 901 #define UTSR1_FRE (1 << 4) /* Frame error */
 902 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
 903
 904 #define RX_FIFO_PRE (1 << 8)
 905 #define RX_FIFO_FRE (1 << 9)
 906 #define RX_FIFO_ROR (1 << 10)
 907
 908 #define TYPE_STRONGARM_UART "strongarm-uart"
 909 #define STRONGARM_UART(obj) \
 910     OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
 911
 912 typedef struct StrongARMUARTState {
 913     SysBusDevice parent_obj;
 914
 915     MemoryRegion iomem;
 916     CharBackend chr;
 917     qemu_irq irq;
 918
 919     uint8_t utcr0;
 920     uint16_t brd;
 921     uint8_t utcr3;
 922     uint8_t utsr0;
 923     uint8_t utsr1;
 924
 925     uint8_t tx_fifo[8];
 926     uint8_t tx_start;
 927     uint8_t tx_len;
 928     uint16_t rx_fifo[12]; /* value + error flags in high bits */
 929     uint8_t rx_start;
 930     uint8_t rx_len;
 931
 932     uint64_t char_transmit_time; /* time to transmit a char in ticks*/
 933     bool wait_break_end;
 934     QEMUTimer *rx_timeout_timer;
 935     QEMUTimer *tx_timer;
 936 } StrongARMUARTState;
 937
 938 static void strongarm_uart_update_status(StrongARMUARTState *s)
 939 {
 940     uint16_t utsr1 = 0;
 941
 942     if (s->tx_len != 8) {
 943         utsr1 |= UTSR1_TNF;
 944     }
 945
 946     if (s->rx_len != 0) {
 947         uint16_t ent = s->rx_fifo[s->rx_start];
 948
 949         utsr1 |= UTSR1_RNE;
 950         if (ent & RX_FIFO_PRE) {
 951             s->utsr1 |= UTSR1_PRE;
 952         }
 953         if (ent & RX_FIFO_FRE) {
 954             s->utsr1 |= UTSR1_FRE;
 955         }
 956         if (ent & RX_FIFO_ROR) {
 957             s->utsr1 |= UTSR1_ROR;
 958         }
 959     }
 960
 961     s->utsr1 = utsr1;
 962 }
 963
 964 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
 965 {
 966     uint16_t utsr0 = s->utsr0 &
 967             (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
 968     int i;
 969
 970     if ((s->utcr3 & UTCR3_TXE) &&
 971                 (s->utcr3 & UTCR3_TIE) &&
 972                 s->tx_len <= 4) {
 973         utsr0 |= UTSR0_TFS;
 974     }
 975
 976     if ((s->utcr3 & UTCR3_RXE) &&
 977                 (s->utcr3 & UTCR3_RIE) &&
 978                 s->rx_len > 4) {
 979         utsr0 |= UTSR0_RFS;
 980     }
 981
 982     for (i = 0; i < s->rx_len && i < 4; i++)
 983         if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
 984             utsr0 |= UTSR0_EIF;
 985             break;
 986         }
 987
 988     s->utsr0 = utsr0;
 989     qemu_set_irq(s->irq, utsr0);
 990 }
 991
 992 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
 993 {
 994     int speed, parity, data_bits, stop_bits, frame_size;
 995     QEMUSerialSetParams ssp;
 996
 997     /* Start bit. */
 998     frame_size = 1;
 999     if (s->utcr0 & UTCR0_PE) {
1000         /* Parity bit. */
1001         frame_size++;
1002         if (s->utcr0 & UTCR0_OES) {
1003             parity = 'E';
1004         } else {
1005             parity = 'O';
1006         }
1007     } else {
1008             parity = 'N';
1009     }
1010     if (s->utcr0 & UTCR0_SBS) {
1011         stop_bits = 2;
1012     } else {
1013         stop_bits = 1;
1014     }
1015
1016     data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1017     frame_size += data_bits + stop_bits;
1018     speed = 3686400 / 16 / (s->brd + 1);
1019     ssp.speed = speed;
1020     ssp.parity = parity;
1021     ssp.data_bits = data_bits;
1022     ssp.stop_bits = stop_bits;
1023     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
1024     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1025
1026     DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1027             speed, parity, data_bits, stop_bits);
1028 }
1029
1030 static void strongarm_uart_rx_to(void *opaque)
1031 {
1032     StrongARMUARTState *s = opaque;
1033
1034     if (s->rx_len) {
1035         s->utsr0 |= UTSR0_RID;
1036         strongarm_uart_update_int_status(s);
1037     }
1038 }
1039
1040 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1041 {
1042     if ((s->utcr3 & UTCR3_RXE) == 0) {
1043         /* rx disabled */
1044         return;
1045     }
1046
1047     if (s->wait_break_end) {
1048         s->utsr0 |= UTSR0_REB;
1049         s->wait_break_end = false;
1050     }
1051
1052     if (s->rx_len < 12) {
1053         s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1054         s->rx_len++;
1055     } else
1056         s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1057 }
1058
1059 static int strongarm_uart_can_receive(void *opaque)
1060 {
1061     StrongARMUARTState *s = opaque;
1062
1063     if (s->rx_len == 12) {
1064         return 0;
1065     }
1066     /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1067     if (s->rx_len < 8) {
1068         return 8 - s->rx_len;
1069     }
1070     return 1;
1071 }
1072
1073 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1074 {
1075     StrongARMUARTState *s = opaque;
1076     int i;
1077
1078     for (i = 0; i < size; i++) {
1079         strongarm_uart_rx_push(s, buf[i]);
1080     }
1081
1082     /* call the timeout receive callback in 3 char transmit time */
1083     timer_mod(s->rx_timeout_timer,
1084                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1085
1086     strongarm_uart_update_status(s);
1087     strongarm_uart_update_int_status(s);
1088 }
1089
1090 static void strongarm_uart_event(void *opaque, int event)
1091 {
1092     StrongARMUARTState *s = opaque;
1093     if (event == CHR_EVENT_BREAK) {
1094         s->utsr0 |= UTSR0_RBB;
1095         strongarm_uart_rx_push(s, RX_FIFO_FRE);
1096         s->wait_break_end = true;
1097         strongarm_uart_update_status(s);
1098         strongarm_uart_update_int_status(s);
1099     }
1100 }
1101
1102 static void strongarm_uart_tx(void *opaque)
1103 {
1104     StrongARMUARTState *s = opaque;
1105     uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1106
1107     if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1108         strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1109     } else if (qemu_chr_fe_get_driver(&s->chr)) {
1110         /* XXX this blocks entire thread. Rewrite to use
1111          * qemu_chr_fe_write and background I/O callbacks */
1112         qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1);
1113     }
1114
1115     s->tx_start = (s->tx_start + 1) % 8;
1116     s->tx_len--;
1117     if (s->tx_len) {
1118         timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1119     }
1120     strongarm_uart_update_status(s);
1121     strongarm_uart_update_int_status(s);
1122 }
1123
1124 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1125                                     unsigned size)
1126 {
1127     StrongARMUARTState *s = opaque;
1128     uint16_t ret;
1129
1130     switch (addr) {
1131     case UTCR0:
1132         return s->utcr0;
1133
1134     case UTCR1:
1135         return s->brd >> 8;
1136
1137     case UTCR2:
1138         return s->brd & 0xff;
1139
1140     case UTCR3:
1141         return s->utcr3;
1142
1143     case UTDR:
1144         if (s->rx_len != 0) {
1145             ret = s->rx_fifo[s->rx_start];
1146             s->rx_start = (s->rx_start + 1) % 12;
1147             s->rx_len--;
1148             strongarm_uart_update_status(s);
1149             strongarm_uart_update_int_status(s);
1150             return ret;
1151         }
1152         return 0;
1153
1154     case UTSR0:
1155         return s->utsr0;
1156
1157     case UTSR1:
1158         return s->utsr1;
1159
1160     default:
1161         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1162         return 0;
1163     }
1164 }
1165
1166 static void strongarm_uart_write(void *opaque, hwaddr addr,
1167                                  uint64_t value, unsigned size)
1168 {
1169     StrongARMUARTState *s = opaque;
1170
1171     switch (addr) {
1172     case UTCR0:
1173         s->utcr0 = value & 0x7f;
1174         strongarm_uart_update_parameters(s);
1175         break;
1176
1177     case UTCR1:
1178         s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1179         strongarm_uart_update_parameters(s);
1180         break;
1181
1182     case UTCR2:
1183         s->brd = (s->brd & 0xf00) | (value & 0xff);
1184         strongarm_uart_update_parameters(s);
1185         break;
1186
1187     case UTCR3:
1188         s->utcr3 = value & 0x3f;
1189         if ((s->utcr3 & UTCR3_RXE) == 0) {
1190             s->rx_len = 0;
1191         }
1192         if ((s->utcr3 & UTCR3_TXE) == 0) {
1193             s->tx_len = 0;
1194         }
1195         strongarm_uart_update_status(s);
1196         strongarm_uart_update_int_status(s);
1197         break;
1198
1199     case UTDR:
1200         if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1201             s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1202             s->tx_len++;
1203             strongarm_uart_update_status(s);
1204             strongarm_uart_update_int_status(s);
1205             if (s->tx_len == 1) {
1206                 strongarm_uart_tx(s);
1207             }
1208         }
1209         break;
1210
1211     case UTSR0:
1212         s->utsr0 = s->utsr0 & ~(value &
1213                 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1214         strongarm_uart_update_int_status(s);
1215         break;
1216
1217     default:
1218         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1219     }
1220 }
1221
1222 static const MemoryRegionOps strongarm_uart_ops = {
1223     .read = strongarm_uart_read,
1224     .write = strongarm_uart_write,
1225     .endianness = DEVICE_NATIVE_ENDIAN,
1226 };
1227
1228 static void strongarm_uart_init(Object *obj)
1229 {
1230     StrongARMUARTState *s = STRONGARM_UART(obj);
1231     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1232
1233     memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s,
1234                           "uart", 0x10000);
1235     sysbus_init_mmio(dev, &s->iomem);
1236     sysbus_init_irq(dev, &s->irq);
1237
1238     s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
1239     s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1240 }
1241
1242 static void strongarm_uart_realize(DeviceState *dev, Error **errp)
1243 {
1244     StrongARMUARTState *s = STRONGARM_UART(dev);
1245
1246     qemu_chr_fe_set_handlers(&s->chr,
1247                              strongarm_uart_can_receive,
1248                              strongarm_uart_receive,
1249                              strongarm_uart_event,
1250                              s, NULL, true);
1251 }
1252
1253 static void strongarm_uart_reset(DeviceState *dev)
1254 {
1255     StrongARMUARTState *s = STRONGARM_UART(dev);
1256
1257     s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1258     s->brd = 23;    /* 9600 */
1259     /* enable send & recv - this actually violates spec */
1260     s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1261
1262     s->rx_len = s->tx_len = 0;
1263
1264     strongarm_uart_update_parameters(s);
1265     strongarm_uart_update_status(s);
1266     strongarm_uart_update_int_status(s);
1267 }
1268
1269 static int strongarm_uart_post_load(void *opaque, int version_id)
1270 {
1271     StrongARMUARTState *s = opaque;
1272
1273     strongarm_uart_update_parameters(s);
1274     strongarm_uart_update_status(s);
1275     strongarm_uart_update_int_status(s);
1276
1277     /* tx and restart timer */
1278     if (s->tx_len) {
1279         strongarm_uart_tx(s);
1280     }
1281
1282     /* restart rx timeout timer */
1283     if (s->rx_len) {
1284         timer_mod(s->rx_timeout_timer,
1285                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1286     }
1287
1288     return 0;
1289 }
1290
1291 static const VMStateDescription vmstate_strongarm_uart_regs = {
1292     .name = "strongarm-uart",
1293     .version_id = 0,
1294     .minimum_version_id = 0,
1295     .post_load = strongarm_uart_post_load,
1296     .fields = (VMStateField[]) {
1297         VMSTATE_UINT8(utcr0, StrongARMUARTState),
1298         VMSTATE_UINT16(brd, StrongARMUARTState),
1299         VMSTATE_UINT8(utcr3, StrongARMUARTState),
1300         VMSTATE_UINT8(utsr0, StrongARMUARTState),
1301         VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1302         VMSTATE_UINT8(tx_start, StrongARMUARTState),
1303         VMSTATE_UINT8(tx_len, StrongARMUARTState),
1304         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1305         VMSTATE_UINT8(rx_start, StrongARMUARTState),
1306         VMSTATE_UINT8(rx_len, StrongARMUARTState),
1307         VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1308         VMSTATE_END_OF_LIST(),
1309     },
1310 };
1311
1312 static Property strongarm_uart_properties[] = {
1313     DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1314     DEFINE_PROP_END_OF_LIST(),
1315 };
1316
1317 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1318 {
1319     DeviceClass *dc = DEVICE_CLASS(klass);
1320
1321     dc->desc = "StrongARM UART controller";
1322     dc->reset = strongarm_uart_reset;
1323     dc->vmsd = &vmstate_strongarm_uart_regs;
1324     dc->props = strongarm_uart_properties;
1325     dc->realize = strongarm_uart_realize;
1326 }
1327
1328 static const TypeInfo strongarm_uart_info = {
1329     .name          = TYPE_STRONGARM_UART,
1330     .parent        = TYPE_SYS_BUS_DEVICE,
1331     .instance_size = sizeof(StrongARMUARTState),
1332     .instance_init = strongarm_uart_init,
1333     .class_init    = strongarm_uart_class_init,
1334 };
1335
1336 /* Synchronous Serial Ports */
1337
1338 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1339 #define STRONGARM_SSP(obj) \
1340     OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1341
1342 typedef struct StrongARMSSPState {
1343     SysBusDevice parent_obj;
1344
1345     MemoryRegion iomem;
1346     qemu_irq irq;
1347     SSIBus *bus;
1348
1349     uint16_t sscr[2];
1350     uint16_t sssr;
1351
1352     uint16_t rx_fifo[8];
1353     uint8_t rx_level;
1354     uint8_t rx_start;
1355 } StrongARMSSPState;
1356
1357 #define SSCR0 0x60 /* SSP Control register 0 */
1358 #define SSCR1 0x64 /* SSP Control register 1 */
1359 #define SSDR  0x6c /* SSP Data register */
1360 #define SSSR  0x74 /* SSP Status register */
1361
1362 /* Bitfields for above registers */
1363 #define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
1364 #define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
1365 #define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
1366 #define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
1367 #define SSCR0_SSE       (1 << 7)
1368 #define SSCR0_DSS(x)    (((x) & 0xf) + 1)
1369 #define SSCR1_RIE       (1 << 0)
1370 #define SSCR1_TIE       (1 << 1)
1371 #define SSCR1_LBM       (1 << 2)
1372 #define SSSR_TNF        (1 << 2)
1373 #define SSSR_RNE        (1 << 3)
1374 #define SSSR_TFS        (1 << 5)
1375 #define SSSR_RFS        (1 << 6)
1376 #define SSSR_ROR        (1 << 7)
1377 #define SSSR_RW         0x0080
1378
1379 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1380 {
1381     int level = 0;
1382
1383     level |= (s->sssr & SSSR_ROR);
1384     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
1385     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
1386     qemu_set_irq(s->irq, level);
1387 }
1388
1389 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1390 {
1391     s->sssr &= ~SSSR_TFS;
1392     s->sssr &= ~SSSR_TNF;
1393     if (s->sscr[0] & SSCR0_SSE) {
1394         if (s->rx_level >= 4) {
1395             s->sssr |= SSSR_RFS;
1396         } else {
1397             s->sssr &= ~SSSR_RFS;
1398         }
1399         if (s->rx_level) {
1400             s->sssr |= SSSR_RNE;
1401         } else {
1402             s->sssr &= ~SSSR_RNE;
1403         }
1404         /* TX FIFO is never filled, so it is always in underrun
1405            condition if SSP is enabled */
1406         s->sssr |= SSSR_TFS;
1407         s->sssr |= SSSR_TNF;
1408     }
1409
1410     strongarm_ssp_int_update(s);
1411 }
1412
1413 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1414                                    unsigned size)
1415 {
1416     StrongARMSSPState *s = opaque;
1417     uint32_t retval;
1418
1419     switch (addr) {
1420     case SSCR0:
1421         return s->sscr[0];
1422     case SSCR1:
1423         return s->sscr[1];
1424     case SSSR:
1425         return s->sssr;
1426     case SSDR:
1427         if (~s->sscr[0] & SSCR0_SSE) {
1428             return 0xffffffff;
1429         }
1430         if (s->rx_level < 1) {
1431             printf("%s: SSP Rx Underrun\n", __func__);
1432             return 0xffffffff;
1433         }
1434         s->rx_level--;
1435         retval = s->rx_fifo[s->rx_start++];
1436         s->rx_start &= 0x7;
1437         strongarm_ssp_fifo_update(s);
1438         return retval;
1439     default:
1440         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1441         break;
1442     }
1443     return 0;
1444 }
1445
1446 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1447                                 uint64_t value, unsigned size)
1448 {
1449     StrongARMSSPState *s = opaque;
1450
1451     switch (addr) {
1452     case SSCR0:
1453         s->sscr[0] = value & 0xffbf;
1454         if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1455             printf("%s: Wrong data size: %i bits\n", __func__,
1456                    (int)SSCR0_DSS(value));
1457         }
1458         if (!(value & SSCR0_SSE)) {
1459             s->sssr = 0;
1460             s->rx_level = 0;
1461         }
1462         strongarm_ssp_fifo_update(s);
1463         break;
1464
1465     case SSCR1:
1466         s->sscr[1] = value & 0x2f;
1467         if (value & SSCR1_LBM) {
1468             printf("%s: Attempt to use SSP LBM mode\n", __func__);
1469         }
1470         strongarm_ssp_fifo_update(s);
1471         break;
1472
1473     case SSSR:
1474         s->sssr &= ~(value & SSSR_RW);
1475         strongarm_ssp_int_update(s);
1476         break;
1477
1478     case SSDR:
1479         if (SSCR0_UWIRE(s->sscr[0])) {
1480             value &= 0xff;
1481         } else
1482             /* Note how 32bits overflow does no harm here */
1483             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1484
1485         /* Data goes from here to the Tx FIFO and is shifted out from
1486          * there directly to the slave, no need to buffer it.
1487          */
1488         if (s->sscr[0] & SSCR0_SSE) {
1489             uint32_t readval;
1490             if (s->sscr[1] & SSCR1_LBM) {
1491                 readval = value;
1492             } else {
1493                 readval = ssi_transfer(s->bus, value);
1494             }
1495
1496             if (s->rx_level < 0x08) {
1497                 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1498             } else {
1499                 s->sssr |= SSSR_ROR;
1500             }
1501         }
1502         strongarm_ssp_fifo_update(s);
1503         break;
1504
1505     default:
1506         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1507         break;
1508     }
1509 }
1510
1511 static const MemoryRegionOps strongarm_ssp_ops = {
1512     .read = strongarm_ssp_read,
1513     .write = strongarm_ssp_write,
1514     .endianness = DEVICE_NATIVE_ENDIAN,
1515 };
1516
1517 static int strongarm_ssp_post_load(void *opaque, int version_id)
1518 {
1519     StrongARMSSPState *s = opaque;
1520
1521     strongarm_ssp_fifo_update(s);
1522
1523     return 0;
1524 }
1525
1526 static void strongarm_ssp_init(Object *obj)
1527 {
1528     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1529     DeviceState *dev = DEVICE(sbd);
1530     StrongARMSSPState *s = STRONGARM_SSP(dev);
1531
1532     sysbus_init_irq(sbd, &s->irq);
1533
1534     memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s,
1535                           "ssp", 0x1000);
1536     sysbus_init_mmio(sbd, &s->iomem);
1537
1538     s->bus = ssi_create_bus(dev, "ssi");
1539 }
1540
1541 static void strongarm_ssp_reset(DeviceState *dev)
1542 {
1543     StrongARMSSPState *s = STRONGARM_SSP(dev);
1544
1545     s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1546     s->rx_start = 0;
1547     s->rx_level = 0;
1548 }
1549
1550 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1551     .name = "strongarm-ssp",
1552     .version_id = 0,
1553     .minimum_version_id = 0,
1554     .post_load = strongarm_ssp_post_load,
1555     .fields = (VMStateField[]) {
1556         VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1557         VMSTATE_UINT16(sssr, StrongARMSSPState),
1558         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1559         VMSTATE_UINT8(rx_start, StrongARMSSPState),
1560         VMSTATE_UINT8(rx_level, StrongARMSSPState),
1561         VMSTATE_END_OF_LIST(),
1562     },
1563 };
1564
1565 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1566 {
1567     DeviceClass *dc = DEVICE_CLASS(klass);
1568
1569     dc->desc = "StrongARM SSP controller";
1570     dc->reset = strongarm_ssp_reset;
1571     dc->vmsd = &vmstate_strongarm_ssp_regs;
1572 }
1573
1574 static const TypeInfo strongarm_ssp_info = {
1575     .name          = TYPE_STRONGARM_SSP,
1576     .parent        = TYPE_SYS_BUS_DEVICE,
1577     .instance_size = sizeof(StrongARMSSPState),
1578     .instance_init = strongarm_ssp_init,
1579     .class_init    = strongarm_ssp_class_init,
1580 };
1581
1582 /* Main CPU functions */
1583 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1584                             unsigned int sdram_size, const char *rev)
1585 {
1586     StrongARMState *s;
1587     int i;
1588
1589     s = g_new0(StrongARMState, 1);
1590
1591     if (!rev) {
1592         rev = "sa1110-b5";
1593     }
1594
1595     if (strncmp(rev, "sa1110", 6)) {
1596         error_report("Machine requires a SA1110 processor.");
1597         exit(1);
1598     }
1599
1600     s->cpu = cpu_arm_init(rev);
1601
1602     if (!s->cpu) {
1603         error_report("Unable to find CPU definition");
1604         exit(1);
1605     }
1606
1607     memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
1608                                          sdram_size);
1609     memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1610
1611     s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1612                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1613                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1614                     NULL);
1615
1616     sysbus_create_varargs("pxa25x-timer", 0x90000000,
1617                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1618                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1619                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1620                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1621                     NULL);
1622
1623     sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1624                     qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1625
1626     s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1627
1628     s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1629
1630     for (i = 0; sa_serial[i].io_base; i++) {
1631         DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
1632         qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1633         qdev_init_nofail(dev);
1634         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1635                 sa_serial[i].io_base);
1636         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1637                 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1638     }
1639
1640     s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1641                 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1642     s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1643
1644     return s;
1645 }
1646
1647 static void strongarm_register_types(void)
1648 {
1649     type_register_static(&strongarm_pic_info);
1650     type_register_static(&strongarm_rtc_sysbus_info);
1651     type_register_static(&strongarm_gpio_info);
1652     type_register_static(&strongarm_ppc_info);
1653     type_register_static(&strongarm_uart_info);
1654     type_register_static(&strongarm_ssp_info);
1655 }
1656
1657 type_init(strongarm_register_types)