hw/dma/bcm2835_dma.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * This code is licensed under the GNU GPLv2 and later.
   4  */
   5
   6 #include "qemu/osdep.h"
   7 #include "qapi/error.h"
   8 #include "hw/dma/bcm2835_dma.h"
   9 #include "hw/irq.h"
  10 #include "migration/vmstate.h"
  11 #include "qemu/log.h"
  12 #include "qemu/module.h"
  13
  14 /* DMA CS Control and Status bits */
  15 #define BCM2708_DMA_ACTIVE      (1 << 0)
  16 #define BCM2708_DMA_END         (1 << 1) /* GE */
  17 #define BCM2708_DMA_INT         (1 << 2)
  18 #define BCM2708_DMA_ISPAUSED    (1 << 4)  /* Pause requested or not active */
  19 #define BCM2708_DMA_ISHELD      (1 << 5)  /* Is held by DREQ flow control */
  20 #define BCM2708_DMA_ERR         (1 << 8)
  21 #define BCM2708_DMA_ABORT       (1 << 30) /* stop current CB, go to next, WO */
  22 #define BCM2708_DMA_RESET       (1 << 31) /* WO, self clearing */
  23
  24 /* DMA control block "info" field bits */
  25 #define BCM2708_DMA_INT_EN      (1 << 0)
  26 #define BCM2708_DMA_TDMODE      (1 << 1)
  27 #define BCM2708_DMA_WAIT_RESP   (1 << 3)
  28 #define BCM2708_DMA_D_INC       (1 << 4)
  29 #define BCM2708_DMA_D_WIDTH     (1 << 5)
  30 #define BCM2708_DMA_D_DREQ      (1 << 6)
  31 #define BCM2708_DMA_D_IGNORE    (1 << 7)
  32 #define BCM2708_DMA_S_INC       (1 << 8)
  33 #define BCM2708_DMA_S_WIDTH     (1 << 9)
  34 #define BCM2708_DMA_S_DREQ      (1 << 10)
  35 #define BCM2708_DMA_S_IGNORE    (1 << 11)
  36
  37 /* Register offsets */
  38 #define BCM2708_DMA_CS          0x00 /* Control and Status */
  39 #define BCM2708_DMA_ADDR        0x04 /* Control block address */
  40 /* the current control block appears in the following registers - read only */
  41 #define BCM2708_DMA_INFO        0x08
  42 #define BCM2708_DMA_SOURCE_AD   0x0c
  43 #define BCM2708_DMA_DEST_AD     0x10
  44 #define BCM2708_DMA_TXFR_LEN    0x14
  45 #define BCM2708_DMA_STRIDE      0x18
  46 #define BCM2708_DMA_NEXTCB      0x1C
  47 #define BCM2708_DMA_DEBUG       0x20
  48
  49 #define BCM2708_DMA_INT_STATUS  0xfe0 /* Interrupt status of each channel */
  50 #define BCM2708_DMA_ENABLE      0xff0 /* Global enable bits for each channel */
  51
  52 #define BCM2708_DMA_CS_RW_MASK  0x30ff0001 /* All RW bits in DMA_CS */
  53
  54 static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
  55 {
  56     BCM2835DMAChan *ch = &s->chan[c];
  57     uint32_t data, xlen, xlen_td, ylen;
  58     int16_t dst_stride, src_stride;
  59
  60     if (!(s->enable & (1 << c))) {
  61         return;
  62     }
  63
  64     while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
  65         /* CB fetch */
  66         ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad);
  67         ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4);
  68         ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8);
  69         ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12);
  70         ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
  71         ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);
  72
  73         ylen = 1;
  74         if (ch->ti & BCM2708_DMA_TDMODE) {
  75             /* 2D transfer mode */
  76             ylen += (ch->txfr_len >> 16) & 0x3fff;
  77             xlen = ch->txfr_len & 0xffff;
  78             dst_stride = ch->stride >> 16;
  79             src_stride = ch->stride & 0xffff;
  80         } else {
  81             xlen = ch->txfr_len;
  82             dst_stride = 0;
  83             src_stride = 0;
  84         }
  85         xlen_td = xlen;
  86
  87         while (ylen != 0) {
  88             /* Normal transfer mode */
  89             while (xlen != 0) {
  90                 if (ch->ti & BCM2708_DMA_S_IGNORE) {
  91                     /* Ignore reads */
  92                     data = 0;
  93                 } else {
  94                     data = ldl_le_phys(&s->dma_as, ch->source_ad);
  95                 }
  96                 if (ch->ti & BCM2708_DMA_S_INC) {
  97                     ch->source_ad += 4;
  98                 }
  99
 100                 if (ch->ti & BCM2708_DMA_D_IGNORE) {
 101                     /* Ignore writes */
 102                 } else {
 103                     stl_le_phys(&s->dma_as, ch->dest_ad, data);
 104                 }
 105                 if (ch->ti & BCM2708_DMA_D_INC) {
 106                     ch->dest_ad += 4;
 107                 }
 108
 109                 /* update remaining transfer length */
 110                 xlen -= 4;
 111                 if (ch->ti & BCM2708_DMA_TDMODE) {
 112                     ch->txfr_len = (ylen << 16) | xlen;
 113                 } else {
 114                     ch->txfr_len = xlen;
 115                 }
 116             }
 117
 118             if (--ylen != 0) {
 119                 ch->source_ad += src_stride;
 120                 ch->dest_ad += dst_stride;
 121                 xlen = xlen_td;
 122             }
 123         }
 124         ch->cs |= BCM2708_DMA_END;
 125         if (ch->ti & BCM2708_DMA_INT_EN) {
 126             ch->cs |= BCM2708_DMA_INT;
 127             s->int_status |= (1 << c);
 128             qemu_set_irq(ch->irq, 1);
 129         }
 130
 131         /* Process next CB */
 132         ch->conblk_ad = ch->nextconbk;
 133     }
 134
 135     ch->cs &= ~BCM2708_DMA_ACTIVE;
 136     ch->cs |= BCM2708_DMA_ISPAUSED;
 137 }
 138
 139 static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch)
 140 {
 141     ch->cs = 0;
 142     ch->conblk_ad = 0;
 143 }
 144
 145 static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
 146                                  unsigned size, unsigned c)
 147 {
 148     BCM2835DMAChan *ch;
 149     uint32_t res = 0;
 150
 151     assert(size == 4);
 152     assert(c < BCM2835_DMA_NCHANS);
 153
 154     ch = &s->chan[c];
 155
 156     switch (offset) {
 157     case BCM2708_DMA_CS:
 158         res = ch->cs;
 159         break;
 160     case BCM2708_DMA_ADDR:
 161         res = ch->conblk_ad;
 162         break;
 163     case BCM2708_DMA_INFO:
 164         res = ch->ti;
 165         break;
 166     case BCM2708_DMA_SOURCE_AD:
 167         res = ch->source_ad;
 168         break;
 169     case BCM2708_DMA_DEST_AD:
 170         res = ch->dest_ad;
 171         break;
 172     case BCM2708_DMA_TXFR_LEN:
 173         res = ch->txfr_len;
 174         break;
 175     case BCM2708_DMA_STRIDE:
 176         res = ch->stride;
 177         break;
 178     case BCM2708_DMA_NEXTCB:
 179         res = ch->nextconbk;
 180         break;
 181     case BCM2708_DMA_DEBUG:
 182         res = ch->debug;
 183         break;
 184     default:
 185         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
 186                       __func__, offset);
 187         break;
 188     }
 189     return res;
 190 }
 191
 192 static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
 193                               uint64_t value, unsigned size, unsigned c)
 194 {
 195     BCM2835DMAChan *ch;
 196     uint32_t oldcs;
 197
 198     assert(size == 4);
 199     assert(c < BCM2835_DMA_NCHANS);
 200
 201     ch = &s->chan[c];
 202
 203     switch (offset) {
 204     case BCM2708_DMA_CS:
 205         oldcs = ch->cs;
 206         if (value & BCM2708_DMA_RESET) {
 207             bcm2835_dma_chan_reset(ch);
 208         }
 209         if (value & BCM2708_DMA_ABORT) {
 210             /* abort is a no-op, since we always run to completion */
 211         }
 212         if (value & BCM2708_DMA_END) {
 213             ch->cs &= ~BCM2708_DMA_END;
 214         }
 215         if (value & BCM2708_DMA_INT) {
 216             ch->cs &= ~BCM2708_DMA_INT;
 217             s->int_status &= ~(1 << c);
 218             qemu_set_irq(ch->irq, 0);
 219         }
 220         ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
 221         ch->cs |= (value & BCM2708_DMA_CS_RW_MASK);
 222         if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
 223             bcm2835_dma_update(s, c);
 224         }
 225         break;
 226     case BCM2708_DMA_ADDR:
 227         ch->conblk_ad = value;
 228         break;
 229     case BCM2708_DMA_DEBUG:
 230         ch->debug = value;
 231         break;
 232     default:
 233         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
 234                       __func__, offset);
 235         break;
 236     }
 237 }
 238
 239 static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
 240 {
 241     BCM2835DMAState *s = opaque;
 242
 243     if (offset < 0xf00) {
 244         return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
 245     } else {
 246         switch (offset) {
 247         case BCM2708_DMA_INT_STATUS:
 248             return s->int_status;
 249         case BCM2708_DMA_ENABLE:
 250             return s->enable;
 251         default:
 252             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
 253                           __func__, offset);
 254             return 0;
 255         }
 256     }
 257 }
 258
 259 static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
 260 {
 261     return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
 262 }
 263
 264 static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
 265                                unsigned size)
 266 {
 267     BCM2835DMAState *s = opaque;
 268
 269     if (offset < 0xf00) {
 270         bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
 271     } else {
 272         switch (offset) {
 273         case BCM2708_DMA_INT_STATUS:
 274             break;
 275         case BCM2708_DMA_ENABLE:
 276             s->enable = (value & 0xffff);
 277             break;
 278         default:
 279             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
 280                           __func__, offset);
 281         }
 282     }
 283
 284 }
 285
 286 static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
 287                                 unsigned size)
 288 {
 289     bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
 290 }
 291
 292 static const MemoryRegionOps bcm2835_dma0_ops = {
 293     .read = bcm2835_dma0_read,
 294     .write = bcm2835_dma0_write,
 295     .endianness = DEVICE_NATIVE_ENDIAN,
 296     .valid.min_access_size = 4,
 297     .valid.max_access_size = 4,
 298 };
 299
 300 static const MemoryRegionOps bcm2835_dma15_ops = {
 301     .read = bcm2835_dma15_read,
 302     .write = bcm2835_dma15_write,
 303     .endianness = DEVICE_NATIVE_ENDIAN,
 304     .valid.min_access_size = 4,
 305     .valid.max_access_size = 4,
 306 };
 307
 308 static const VMStateDescription vmstate_bcm2835_dma_chan = {
 309     .name = TYPE_BCM2835_DMA "-chan",
 310     .version_id = 1,
 311     .minimum_version_id = 1,
 312     .fields = (VMStateField[]) {
 313         VMSTATE_UINT32(cs, BCM2835DMAChan),
 314         VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
 315         VMSTATE_UINT32(ti, BCM2835DMAChan),
 316         VMSTATE_UINT32(source_ad, BCM2835DMAChan),
 317         VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
 318         VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
 319         VMSTATE_UINT32(stride, BCM2835DMAChan),
 320         VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
 321         VMSTATE_UINT32(debug, BCM2835DMAChan),
 322         VMSTATE_END_OF_LIST()
 323     }
 324 };
 325
 326 static const VMStateDescription vmstate_bcm2835_dma = {
 327     .name = TYPE_BCM2835_DMA,
 328     .version_id = 1,
 329     .minimum_version_id = 1,
 330     .fields = (VMStateField[]) {
 331         VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
 332                              vmstate_bcm2835_dma_chan, BCM2835DMAChan),
 333         VMSTATE_UINT32(int_status, BCM2835DMAState),
 334         VMSTATE_UINT32(enable, BCM2835DMAState),
 335         VMSTATE_END_OF_LIST()
 336     }
 337 };
 338
 339 static void bcm2835_dma_init(Object *obj)
 340 {
 341     BCM2835DMAState *s = BCM2835_DMA(obj);
 342     int n;
 343
 344     /* DMA channels 0-14 occupy a contiguous block of IO memory, along
 345      * with the global enable and interrupt status bits. Channel 15
 346      * has the same register map, but is mapped at a discontiguous
 347      * address in a separate IO block.
 348      */
 349     memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
 350                           TYPE_BCM2835_DMA, 0x1000);
 351     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);
 352
 353     memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
 354                           TYPE_BCM2835_DMA "-chan15", 0x100);
 355     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);
 356
 357     for (n = 0; n < 16; n++) {
 358         sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
 359     }
 360 }
 361
 362 static void bcm2835_dma_reset(DeviceState *dev)
 363 {
 364     BCM2835DMAState *s = BCM2835_DMA(dev);
 365     int n;
 366
 367     s->enable = 0xffff;
 368     s->int_status = 0;
 369     for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
 370         bcm2835_dma_chan_reset(&s->chan[n]);
 371     }
 372 }
 373
 374 static void bcm2835_dma_realize(DeviceState *dev, Error **errp)
 375 {
 376     BCM2835DMAState *s = BCM2835_DMA(dev);
 377     Error *err = NULL;
 378     Object *obj;
 379
 380     obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
 381     if (obj == NULL) {
 382         error_setg(errp, "%s: required dma-mr link not found: %s",
 383                    __func__, error_get_pretty(err));
 384         return;
 385     }
 386
 387     s->dma_mr = MEMORY_REGION(obj);
 388     address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_DMA "-memory");
 389
 390     bcm2835_dma_reset(dev);
 391 }
 392
 393 static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
 394 {
 395     DeviceClass *dc = DEVICE_CLASS(klass);
 396
 397     dc->realize = bcm2835_dma_realize;
 398     dc->reset = bcm2835_dma_reset;
 399     dc->vmsd = &vmstate_bcm2835_dma;
 400 }
 401
 402 static TypeInfo bcm2835_dma_info = {
 403     .name          = TYPE_BCM2835_DMA,
 404     .parent        = TYPE_SYS_BUS_DEVICE,
 405     .instance_size = sizeof(BCM2835DMAState),
 406     .class_init    = bcm2835_dma_class_init,
 407     .instance_init = bcm2835_dma_init,
 408 };
 409
 410 static void bcm2835_dma_register_types(void)
 411 {
 412     type_register_static(&bcm2835_dma_info);
 413 }
 414
 415 type_init(bcm2835_dma_register_types)