hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "hw/qdev.h"
   7 #include "exec/memory.h"
   8 #include "sysemu/dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "hw/isa.h"
  12
  13 #include "hw/pci/pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "hw/pci/pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  80 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  81
  82 #define PCI_VENDOR_ID_REDHAT             0x1b36
  83 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  84 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  85 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  86 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  87 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
  88
  89 #define FMT_PCIBUS                      PRIx64
  90
  91 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  92                                 uint32_t address, uint32_t data, int len);
  93 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  94                                    uint32_t address, int len);
  95 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  96                                 pcibus_t addr, pcibus_t size, int type);
  97 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
  98
  99 typedef struct PCIIORegion {
 100     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 101 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 102     pcibus_t size;
 103     uint8_t type;
 104     MemoryRegion *memory;
 105     MemoryRegion *address_space;
 106 } PCIIORegion;
 107
 108 #define PCI_ROM_SLOT 6
 109 #define PCI_NUM_REGIONS 7
 110
 111 enum {
 112     QEMU_PCI_VGA_MEM,
 113     QEMU_PCI_VGA_IO_LO,
 114     QEMU_PCI_VGA_IO_HI,
 115     QEMU_PCI_VGA_NUM_REGIONS,
 116 };
 117
 118 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 119 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 120 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 121 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 122 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 123 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 124
 125 #include "hw/pci/pci_regs.h"
 126
 127 /* PCI HEADER_TYPE */
 128 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 129
 130 /* Size of the standard PCI config header */
 131 #define PCI_CONFIG_HEADER_SIZE 0x40
 132 /* Size of the standard PCI config space */
 133 #define PCI_CONFIG_SPACE_SIZE 0x100
 134 /* Size of the standart PCIe config space: 4KB */
 135 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 136
 137 #define PCI_NUM_PINS 4 /* A-D */
 138
 139 /* Bits in cap_present field. */
 140 enum {
 141     QEMU_PCI_CAP_MSI = 0x1,
 142     QEMU_PCI_CAP_MSIX = 0x2,
 143     QEMU_PCI_CAP_EXPRESS = 0x4,
 144
 145     /* multifunction capable device */
 146 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 147     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 148
 149     /* command register SERR bit enabled */
 150 #define QEMU_PCI_CAP_SERR_BITNR 4
 151     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 152     /* Standard hot plug controller. */
 153 #define QEMU_PCI_SHPC_BITNR 5
 154     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 155 #define QEMU_PCI_SLOTID_BITNR 6
 156     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 157 };
 158
 159 #define TYPE_PCI_DEVICE "pci-device"
 160 #define PCI_DEVICE(obj) \
 161      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 162 #define PCI_DEVICE_CLASS(klass) \
 163      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 164 #define PCI_DEVICE_GET_CLASS(obj) \
 165      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 166
 167 typedef struct PCIINTxRoute {
 168     enum {
 169         PCI_INTX_ENABLED,
 170         PCI_INTX_INVERTED,
 171         PCI_INTX_DISABLED,
 172     } mode;
 173     int irq;
 174 } PCIINTxRoute;
 175
 176 typedef struct PCIDeviceClass {
 177     DeviceClass parent_class;
 178
 179     int (*init)(PCIDevice *dev);
 180     PCIUnregisterFunc *exit;
 181     PCIConfigReadFunc *config_read;
 182     PCIConfigWriteFunc *config_write;
 183
 184     uint16_t vendor_id;
 185     uint16_t device_id;
 186     uint8_t revision;
 187     uint16_t class_id;
 188     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 189     uint16_t subsystem_id;              /* only for header type = 0 */
 190
 191     /*
 192      * pci-to-pci bridge or normal device.
 193      * This doesn't mean pci host switch.
 194      * When card bus bridge is supported, this would be enhanced.
 195      */
 196     int is_bridge;
 197
 198     /* pcie stuff */
 199     int is_express;   /* is this device pci express? */
 200
 201     /* device isn't hot-pluggable */
 202     int no_hotplug;
 203
 204     /* rom bar */
 205     const char *romfile;
 206 } PCIDeviceClass;
 207
 208 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 209 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 210                                       MSIMessage msg);
 211 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 212 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 213                                       unsigned int vector_start,
 214                                       unsigned int vector_end);
 215
 216 struct PCIDevice {
 217     DeviceState qdev;
 218
 219     /* PCI config space */
 220     uint8_t *config;
 221
 222     /* Used to enable config checks on load. Note that writable bits are
 223      * never checked even if set in cmask. */
 224     uint8_t *cmask;
 225
 226     /* Used to implement R/W bytes */
 227     uint8_t *wmask;
 228
 229     /* Used to implement RW1C(Write 1 to Clear) bytes */
 230     uint8_t *w1cmask;
 231
 232     /* Used to allocate config space for capabilities. */
 233     uint8_t *used;
 234
 235     /* the following fields are read only */
 236     PCIBus *bus;
 237     int32_t devfn;
 238     char name[64];
 239     PCIIORegion io_regions[PCI_NUM_REGIONS];
 240     AddressSpace bus_master_as;
 241     MemoryRegion bus_master_enable_region;
 242     DMAContext *dma;
 243
 244     /* do not access the following fields */
 245     PCIConfigReadFunc *config_read;
 246     PCIConfigWriteFunc *config_write;
 247
 248     /* IRQ objects for the INTA-INTD pins.  */
 249     qemu_irq *irq;
 250
 251     /* Legacy PCI VGA regions */
 252     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 253     bool has_vga;
 254
 255     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 256     uint8_t irq_state;
 257
 258     /* Capability bits */
 259     uint32_t cap_present;
 260
 261     /* Offset of MSI-X capability in config space */
 262     uint8_t msix_cap;
 263
 264     /* MSI-X entries */
 265     int msix_entries_nr;
 266
 267     /* Space to store MSIX table & pending bit array */
 268     uint8_t *msix_table;
 269     uint8_t *msix_pba;
 270     /* MemoryRegion container for msix exclusive BAR setup */
 271     MemoryRegion msix_exclusive_bar;
 272     /* Memory Regions for MSIX table and pending bit entries. */
 273     MemoryRegion msix_table_mmio;
 274     MemoryRegion msix_pba_mmio;
 275     /* Reference-count for entries actually in use by driver. */
 276     unsigned *msix_entry_used;
 277     /* MSIX function mask set or MSIX disabled */
 278     bool msix_function_masked;
 279     /* Version id needed for VMState */
 280     int32_t version_id;
 281
 282     /* Offset of MSI capability in config space */
 283     uint8_t msi_cap;
 284
 285     /* PCI Express */
 286     PCIExpressDevice exp;
 287
 288     /* SHPC */
 289     SHPCDevice *shpc;
 290
 291     /* Location of option rom */
 292     char *romfile;
 293     bool has_rom;
 294     MemoryRegion rom;
 295     uint32_t rom_bar;
 296
 297     /* INTx routing notifier */
 298     PCIINTxRoutingNotifier intx_routing_notifier;
 299
 300     /* MSI-X notifiers */
 301     MSIVectorUseNotifier msix_vector_use_notifier;
 302     MSIVectorReleaseNotifier msix_vector_release_notifier;
 303     MSIVectorPollNotifier msix_vector_poll_notifier;
 304 };
 305
 306 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 307                       uint8_t attr, MemoryRegion *memory);
 308 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 309                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 310 void pci_unregister_vga(PCIDevice *pci_dev);
 311 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 312
 313 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 314                        uint8_t offset, uint8_t size);
 315
 316 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 317
 318 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 319
 320
 321 uint32_t pci_default_read_config(PCIDevice *d,
 322                                  uint32_t address, int len);
 323 void pci_default_write_config(PCIDevice *d,
 324                               uint32_t address, uint32_t val, int len);
 325 void pci_device_save(PCIDevice *s, QEMUFile *f);
 326 int pci_device_load(PCIDevice *s, QEMUFile *f);
 327 MemoryRegion *pci_address_space(PCIDevice *dev);
 328 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 329
 330 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 331 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 332 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 333
 334 typedef enum {
 335     PCI_HOTPLUG_DISABLED,
 336     PCI_HOTPLUG_ENABLED,
 337     PCI_COLDPLUG_ENABLED,
 338 } PCIHotplugState;
 339
 340 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 341                               PCIHotplugState state);
 342 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 343                          const char *name,
 344                          MemoryRegion *address_space_mem,
 345                          MemoryRegion *address_space_io,
 346                          uint8_t devfn_min);
 347 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 348                     MemoryRegion *address_space_mem,
 349                     MemoryRegion *address_space_io,
 350                     uint8_t devfn_min);
 351 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 352                   void *irq_opaque, int nirq);
 353 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 354 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 355 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 356 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 357 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 358                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 359                          void *irq_opaque,
 360                          MemoryRegion *address_space_mem,
 361                          MemoryRegion *address_space_io,
 362                          uint8_t devfn_min, int nirq);
 363 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 364 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 365 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 366 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 367 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 368                                           PCIINTxRoutingNotifier notifier);
 369 void pci_device_reset(PCIDevice *dev);
 370 void pci_bus_reset(PCIBus *bus);
 371
 372 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 373                         const char *default_devaddr);
 374 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 375                                const char *default_devaddr);
 376
 377 PCIDevice *pci_vga_init(PCIBus *bus);
 378
 379 int pci_bus_num(PCIBus *s);
 380 void pci_for_each_device(PCIBus *bus, int bus_num,
 381                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 382                          void *opaque);
 383 PCIBus *pci_find_root_bus(int domain);
 384 int pci_find_domain(const PCIBus *bus);
 385 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 386 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 387 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 388
 389 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 390                      unsigned *slotp);
 391
 392 void pci_device_deassert_intx(PCIDevice *dev);
 393
 394 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int);
 395
 396 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque);
 397
 398 static inline void
 399 pci_set_byte(uint8_t *config, uint8_t val)
 400 {
 401     *config = val;
 402 }
 403
 404 static inline uint8_t
 405 pci_get_byte(const uint8_t *config)
 406 {
 407     return *config;
 408 }
 409
 410 static inline void
 411 pci_set_word(uint8_t *config, uint16_t val)
 412 {
 413     cpu_to_le16wu((uint16_t *)config, val);
 414 }
 415
 416 static inline uint16_t
 417 pci_get_word(const uint8_t *config)
 418 {
 419     return le16_to_cpupu((const uint16_t *)config);
 420 }
 421
 422 static inline void
 423 pci_set_long(uint8_t *config, uint32_t val)
 424 {
 425     cpu_to_le32wu((uint32_t *)config, val);
 426 }
 427
 428 static inline uint32_t
 429 pci_get_long(const uint8_t *config)
 430 {
 431     return le32_to_cpupu((const uint32_t *)config);
 432 }
 433
 434 static inline void
 435 pci_set_quad(uint8_t *config, uint64_t val)
 436 {
 437     cpu_to_le64w((uint64_t *)config, val);
 438 }
 439
 440 static inline uint64_t
 441 pci_get_quad(const uint8_t *config)
 442 {
 443     return le64_to_cpup((const uint64_t *)config);
 444 }
 445
 446 static inline void
 447 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 448 {
 449     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 450 }
 451
 452 static inline void
 453 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 454 {
 455     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 456 }
 457
 458 static inline void
 459 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 460 {
 461     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 462 }
 463
 464 static inline void
 465 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 466 {
 467     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 468 }
 469
 470 static inline void
 471 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 472 {
 473     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 474 }
 475
 476 static inline void
 477 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 478 {
 479     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 480 }
 481
 482 /*
 483  * helper functions to do bit mask operation on configuration space.
 484  * Just to set bit, use test-and-set and discard returned value.
 485  * Just to clear bit, use test-and-clear and discard returned value.
 486  * NOTE: They aren't atomic.
 487  */
 488 static inline uint8_t
 489 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 490 {
 491     uint8_t val = pci_get_byte(config);
 492     pci_set_byte(config, val & ~mask);
 493     return val & mask;
 494 }
 495
 496 static inline uint8_t
 497 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 498 {
 499     uint8_t val = pci_get_byte(config);
 500     pci_set_byte(config, val | mask);
 501     return val & mask;
 502 }
 503
 504 static inline uint16_t
 505 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 506 {
 507     uint16_t val = pci_get_word(config);
 508     pci_set_word(config, val & ~mask);
 509     return val & mask;
 510 }
 511
 512 static inline uint16_t
 513 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 514 {
 515     uint16_t val = pci_get_word(config);
 516     pci_set_word(config, val | mask);
 517     return val & mask;
 518 }
 519
 520 static inline uint32_t
 521 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 522 {
 523     uint32_t val = pci_get_long(config);
 524     pci_set_long(config, val & ~mask);
 525     return val & mask;
 526 }
 527
 528 static inline uint32_t
 529 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 530 {
 531     uint32_t val = pci_get_long(config);
 532     pci_set_long(config, val | mask);
 533     return val & mask;
 534 }
 535
 536 static inline uint64_t
 537 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 538 {
 539     uint64_t val = pci_get_quad(config);
 540     pci_set_quad(config, val & ~mask);
 541     return val & mask;
 542 }
 543
 544 static inline uint64_t
 545 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 546 {
 547     uint64_t val = pci_get_quad(config);
 548     pci_set_quad(config, val | mask);
 549     return val & mask;
 550 }
 551
 552 /* Access a register specified by a mask */
 553 static inline void
 554 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 555 {
 556     uint8_t val = pci_get_byte(config);
 557     uint8_t rval = reg << (ffs(mask) - 1);
 558     pci_set_byte(config, (~mask & val) | (mask & rval));
 559 }
 560
 561 static inline uint8_t
 562 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 563 {
 564     uint8_t val = pci_get_byte(config);
 565     return (val & mask) >> (ffs(mask) - 1);
 566 }
 567
 568 static inline void
 569 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 570 {
 571     uint16_t val = pci_get_word(config);
 572     uint16_t rval = reg << (ffs(mask) - 1);
 573     pci_set_word(config, (~mask & val) | (mask & rval));
 574 }
 575
 576 static inline uint16_t
 577 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 578 {
 579     uint16_t val = pci_get_word(config);
 580     return (val & mask) >> (ffs(mask) - 1);
 581 }
 582
 583 static inline void
 584 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 585 {
 586     uint32_t val = pci_get_long(config);
 587     uint32_t rval = reg << (ffs(mask) - 1);
 588     pci_set_long(config, (~mask & val) | (mask & rval));
 589 }
 590
 591 static inline uint32_t
 592 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 593 {
 594     uint32_t val = pci_get_long(config);
 595     return (val & mask) >> (ffs(mask) - 1);
 596 }
 597
 598 static inline void
 599 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 600 {
 601     uint64_t val = pci_get_quad(config);
 602     uint64_t rval = reg << (ffs(mask) - 1);
 603     pci_set_quad(config, (~mask & val) | (mask & rval));
 604 }
 605
 606 static inline uint64_t
 607 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 608 {
 609     uint64_t val = pci_get_quad(config);
 610     return (val & mask) >> (ffs(mask) - 1);
 611 }
 612
 613 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 614                                     const char *name);
 615 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 616                                            bool multifunction,
 617                                            const char *name);
 618 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 619 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 620
 621 static inline int pci_is_express(const PCIDevice *d)
 622 {
 623     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 624 }
 625
 626 static inline uint32_t pci_config_size(const PCIDevice *d)
 627 {
 628     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 629 }
 630
 631 /* DMA access functions */
 632 static inline DMAContext *pci_dma_context(PCIDevice *dev)
 633 {
 634     return dev->dma;
 635 }
 636
 637 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 638                              void *buf, dma_addr_t len, DMADirection dir)
 639 {
 640     dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir);
 641     return 0;
 642 }
 643
 644 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 645                                void *buf, dma_addr_t len)
 646 {
 647     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 648 }
 649
 650 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 651                                 const void *buf, dma_addr_t len)
 652 {
 653     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 654 }
 655
 656 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 657     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 658                                                    dma_addr_t addr)     \
 659     {                                                                   \
 660         return ld##_l##_dma(pci_dma_context(dev), addr);                \
 661     }                                                                   \
 662     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 663                                         dma_addr_t addr, uint##_bits##_t val) \
 664     {                                                                   \
 665         st##_s##_dma(pci_dma_context(dev), addr, val);                  \
 666     }
 667
 668 PCI_DMA_DEFINE_LDST(ub, b, 8);
 669 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 670 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 671 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 672 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 673 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 674 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 675
 676 #undef PCI_DMA_DEFINE_LDST
 677
 678 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 679                                 dma_addr_t *plen, DMADirection dir)
 680 {
 681     void *buf;
 682
 683     buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir);
 684     return buf;
 685 }
 686
 687 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 688                                  DMADirection dir, dma_addr_t access_len)
 689 {
 690     dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len);
 691 }
 692
 693 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 694                                        int alloc_hint)
 695 {
 696     qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev));
 697 }
 698
 699 extern const VMStateDescription vmstate_pci_device;
 700
 701 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 702     .name       = (stringify(_field)),                               \
 703     .size       = sizeof(PCIDevice),                                 \
 704     .vmsd       = &vmstate_pci_device,                               \
 705     .flags      = VMS_STRUCT,                                        \
 706     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 707 }
 708
 709 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 710     .name       = (stringify(_field)),                               \
 711     .size       = sizeof(PCIDevice),                                 \
 712     .vmsd       = &vmstate_pci_device,                               \
 713     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 714     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 715 }
 716
 717 #endif