2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "exec/memop.h"
30 #include "exec/tb-context.h"
31 #include "qemu/bitops.h"
32 #include "qemu/plugin.h"
33 #include "qemu/queue.h"
34 #include "tcg/tcg-mo.h"
35 #include "tcg-target.h"
36 #include "qemu/int128.h"
38 /* XXX: make safe guess about sizes */
39 #define MAX_OP_PER_INSTR 266
41 #if HOST_LONG_BITS == 32
42 #define MAX_OPC_PARAM_PER_ARG 2
44 #define MAX_OPC_PARAM_PER_ARG 1
46 #define MAX_OPC_PARAM_IARGS 6
47 #define MAX_OPC_PARAM_OARGS 1
48 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
50 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
51 * and up to 4 + N parameters on 64-bit archs
52 * (N = number of input arguments + output arguments). */
53 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
55 #define CPU_TEMP_BUF_NLONGS 128
57 /* Default target word size to pointer size. */
58 #ifndef TCG_TARGET_REG_BITS
59 # if UINTPTR_MAX == UINT32_MAX
60 # define TCG_TARGET_REG_BITS 32
61 # elif UINTPTR_MAX == UINT64_MAX
62 # define TCG_TARGET_REG_BITS 64
64 # error Unknown pointer size for tcg target
68 #if TCG_TARGET_REG_BITS == 32
69 typedef int32_t tcg_target_long
;
70 typedef uint32_t tcg_target_ulong
;
71 #define TCG_PRIlx PRIx32
72 #define TCG_PRIld PRId32
73 #elif TCG_TARGET_REG_BITS == 64
74 typedef int64_t tcg_target_long
;
75 typedef uint64_t tcg_target_ulong
;
76 #define TCG_PRIlx PRIx64
77 #define TCG_PRIld PRId64
82 /* Oversized TCG guests make things like MTTCG hard
83 * as we can't use atomics for cputlb updates.
85 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
86 #define TCG_OVERSIZED_GUEST 1
88 #define TCG_OVERSIZED_GUEST 0
91 #if TCG_TARGET_NB_REGS <= 32
92 typedef uint32_t TCGRegSet
;
93 #elif TCG_TARGET_NB_REGS <= 64
94 typedef uint64_t TCGRegSet
;
99 #if TCG_TARGET_REG_BITS == 32
100 /* Turn some undef macros into false macros. */
101 #define TCG_TARGET_HAS_extrl_i64_i32 0
102 #define TCG_TARGET_HAS_extrh_i64_i32 0
103 #define TCG_TARGET_HAS_div_i64 0
104 #define TCG_TARGET_HAS_rem_i64 0
105 #define TCG_TARGET_HAS_div2_i64 0
106 #define TCG_TARGET_HAS_rot_i64 0
107 #define TCG_TARGET_HAS_ext8s_i64 0
108 #define TCG_TARGET_HAS_ext16s_i64 0
109 #define TCG_TARGET_HAS_ext32s_i64 0
110 #define TCG_TARGET_HAS_ext8u_i64 0
111 #define TCG_TARGET_HAS_ext16u_i64 0
112 #define TCG_TARGET_HAS_ext32u_i64 0
113 #define TCG_TARGET_HAS_bswap16_i64 0
114 #define TCG_TARGET_HAS_bswap32_i64 0
115 #define TCG_TARGET_HAS_bswap64_i64 0
116 #define TCG_TARGET_HAS_neg_i64 0
117 #define TCG_TARGET_HAS_not_i64 0
118 #define TCG_TARGET_HAS_andc_i64 0
119 #define TCG_TARGET_HAS_orc_i64 0
120 #define TCG_TARGET_HAS_eqv_i64 0
121 #define TCG_TARGET_HAS_nand_i64 0
122 #define TCG_TARGET_HAS_nor_i64 0
123 #define TCG_TARGET_HAS_clz_i64 0
124 #define TCG_TARGET_HAS_ctz_i64 0
125 #define TCG_TARGET_HAS_ctpop_i64 0
126 #define TCG_TARGET_HAS_deposit_i64 0
127 #define TCG_TARGET_HAS_extract_i64 0
128 #define TCG_TARGET_HAS_sextract_i64 0
129 #define TCG_TARGET_HAS_extract2_i64 0
130 #define TCG_TARGET_HAS_movcond_i64 0
131 #define TCG_TARGET_HAS_add2_i64 0
132 #define TCG_TARGET_HAS_sub2_i64 0
133 #define TCG_TARGET_HAS_mulu2_i64 0
134 #define TCG_TARGET_HAS_muls2_i64 0
135 #define TCG_TARGET_HAS_muluh_i64 0
136 #define TCG_TARGET_HAS_mulsh_i64 0
137 /* Turn some undef macros into true macros. */
138 #define TCG_TARGET_HAS_add2_i32 1
139 #define TCG_TARGET_HAS_sub2_i32 1
142 #ifndef TCG_TARGET_deposit_i32_valid
143 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
145 #ifndef TCG_TARGET_deposit_i64_valid
146 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
148 #ifndef TCG_TARGET_extract_i32_valid
149 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
151 #ifndef TCG_TARGET_extract_i64_valid
152 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
155 /* Only one of DIV or DIV2 should be defined. */
156 #if defined(TCG_TARGET_HAS_div_i32)
157 #define TCG_TARGET_HAS_div2_i32 0
158 #elif defined(TCG_TARGET_HAS_div2_i32)
159 #define TCG_TARGET_HAS_div_i32 0
160 #define TCG_TARGET_HAS_rem_i32 0
162 #if defined(TCG_TARGET_HAS_div_i64)
163 #define TCG_TARGET_HAS_div2_i64 0
164 #elif defined(TCG_TARGET_HAS_div2_i64)
165 #define TCG_TARGET_HAS_div_i64 0
166 #define TCG_TARGET_HAS_rem_i64 0
169 /* For 32-bit targets, some sort of unsigned widening multiply is required. */
170 #if TCG_TARGET_REG_BITS == 32 \
171 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
172 || defined(TCG_TARGET_HAS_muluh_i32))
173 # error "Missing unsigned widening multiply"
176 #if !defined(TCG_TARGET_HAS_v64) \
177 && !defined(TCG_TARGET_HAS_v128) \
178 && !defined(TCG_TARGET_HAS_v256)
179 #define TCG_TARGET_MAYBE_vec 0
180 #define TCG_TARGET_HAS_abs_vec 0
181 #define TCG_TARGET_HAS_neg_vec 0
182 #define TCG_TARGET_HAS_not_vec 0
183 #define TCG_TARGET_HAS_andc_vec 0
184 #define TCG_TARGET_HAS_orc_vec 0
185 #define TCG_TARGET_HAS_roti_vec 0
186 #define TCG_TARGET_HAS_rots_vec 0
187 #define TCG_TARGET_HAS_rotv_vec 0
188 #define TCG_TARGET_HAS_shi_vec 0
189 #define TCG_TARGET_HAS_shs_vec 0
190 #define TCG_TARGET_HAS_shv_vec 0
191 #define TCG_TARGET_HAS_mul_vec 0
192 #define TCG_TARGET_HAS_sat_vec 0
193 #define TCG_TARGET_HAS_minmax_vec 0
194 #define TCG_TARGET_HAS_bitsel_vec 0
195 #define TCG_TARGET_HAS_cmpsel_vec 0
197 #define TCG_TARGET_MAYBE_vec 1
199 #ifndef TCG_TARGET_HAS_v64
200 #define TCG_TARGET_HAS_v64 0
202 #ifndef TCG_TARGET_HAS_v128
203 #define TCG_TARGET_HAS_v128 0
205 #ifndef TCG_TARGET_HAS_v256
206 #define TCG_TARGET_HAS_v256 0
209 #ifndef TARGET_INSN_START_EXTRA_WORDS
210 # define TARGET_INSN_START_WORDS 1
212 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
215 typedef enum TCGOpcode
{
216 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
217 #include "tcg/tcg-opc.h"
222 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r))
223 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
224 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
226 #ifndef TCG_TARGET_INSN_UNIT_SIZE
227 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
228 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
229 typedef uint8_t tcg_insn_unit
;
230 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
231 typedef uint16_t tcg_insn_unit
;
232 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
233 typedef uint32_t tcg_insn_unit
;
234 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
235 typedef uint64_t tcg_insn_unit
;
237 /* The port better have done this. */
241 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
242 # define tcg_debug_assert(X) do { assert(X); } while (0)
244 # define tcg_debug_assert(X) \
245 do { if (!(X)) { __builtin_unreachable(); } } while (0)
248 typedef struct TCGRelocation TCGRelocation
;
249 struct TCGRelocation
{
250 QSIMPLEQ_ENTRY(TCGRelocation
) next
;
256 typedef struct TCGLabel TCGLabel
;
258 unsigned present
: 1;
259 unsigned has_value
: 1;
264 const tcg_insn_unit
*value_ptr
;
266 QSIMPLEQ_HEAD(, TCGRelocation
) relocs
;
267 QSIMPLEQ_ENTRY(TCGLabel
) next
;
270 typedef struct TCGPool
{
271 struct TCGPool
*next
;
273 uint8_t data
[] __attribute__ ((aligned
));
276 #define TCG_POOL_CHUNK_SIZE 32768
278 #define TCG_MAX_TEMPS 512
279 #define TCG_MAX_INSNS 512
281 /* when the size of the arguments of a called function is smaller than
282 this value, they are statically allocated in the TB stack frame */
283 #define TCG_STATIC_CALL_ARGS_SIZE 128
285 typedef enum TCGType
{
293 TCG_TYPE_COUNT
, /* number of different types */
295 /* An alias for the size of the host register. */
296 #if TCG_TARGET_REG_BITS == 32
297 TCG_TYPE_REG
= TCG_TYPE_I32
,
299 TCG_TYPE_REG
= TCG_TYPE_I64
,
302 /* An alias for the size of the native pointer. */
303 #if UINTPTR_MAX == UINT32_MAX
304 TCG_TYPE_PTR
= TCG_TYPE_I32
,
306 TCG_TYPE_PTR
= TCG_TYPE_I64
,
309 /* An alias for the size of the target "long", aka register. */
310 #if TARGET_LONG_BITS == 64
311 TCG_TYPE_TL
= TCG_TYPE_I64
,
313 TCG_TYPE_TL
= TCG_TYPE_I32
,
319 * @memop: MemOp value
321 * Extract the alignment size from the memop.
323 static inline unsigned get_alignment_bits(MemOp memop
)
325 unsigned a
= memop
& MO_AMASK
;
328 /* No alignment required. */
330 } else if (a
== MO_ALIGN
) {
331 /* A natural alignment requirement. */
334 /* A specific alignment requirement. */
337 #if defined(CONFIG_SOFTMMU)
338 /* The requested alignment cannot overlap the TLB flags. */
339 tcg_debug_assert((TLB_FLAGS_MASK
& ((1 << a
) - 1)) == 0);
344 typedef tcg_target_ulong TCGArg
;
346 /* Define type and accessor macros for TCG variables.
348 TCG variables are the inputs and outputs of TCG ops, as described
349 in tcg/README. Target CPU front-end code uses these types to deal
350 with TCG variables as it emits TCG code via the tcg_gen_* functions.
351 They come in several flavours:
352 * TCGv_i32 : 32 bit integer type
353 * TCGv_i64 : 64 bit integer type
354 * TCGv_ptr : a host pointer type
355 * TCGv_vec : a host vector type; the exact size is not exposed
356 to the CPU front-end code.
357 * TCGv : an integer type the same size as target_ulong
358 (an alias for either TCGv_i32 or TCGv_i64)
359 The compiler's type checking will complain if you mix them
360 up and pass the wrong sized TCGv to a function.
362 Users of tcg_gen_* don't need to know about any of the internal
363 details of these, and should treat them as opaque types.
364 You won't be able to look inside them in a debugger either.
366 Internal implementation details follow:
368 Note that there is no definition of the structs TCGv_i32_d etc anywhere.
369 This is deliberate, because the values we store in variables of type
370 TCGv_i32 are not really pointers-to-structures. They're just small
371 integers, but keeping them in pointer types like this means that the
372 compiler will complain if you accidentally pass a TCGv_i32 to a
373 function which takes a TCGv_i64, and so on. Only the internals of
374 TCG need to care about the actual contents of the types. */
376 typedef struct TCGv_i32_d
*TCGv_i32
;
377 typedef struct TCGv_i64_d
*TCGv_i64
;
378 typedef struct TCGv_ptr_d
*TCGv_ptr
;
379 typedef struct TCGv_vec_d
*TCGv_vec
;
380 typedef TCGv_ptr TCGv_env
;
381 #if TARGET_LONG_BITS == 32
382 #define TCGv TCGv_i32
383 #elif TARGET_LONG_BITS == 64
384 #define TCGv TCGv_i64
386 #error Unhandled TARGET_LONG_BITS value
390 /* Helper does not read globals (either directly or through an exception). It
391 implies TCG_CALL_NO_WRITE_GLOBALS. */
392 #define TCG_CALL_NO_READ_GLOBALS 0x0001
393 /* Helper does not write globals */
394 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002
395 /* Helper can be safely suppressed if the return value is not used. */
396 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004
397 /* Helper is QEMU_NORETURN. */
398 #define TCG_CALL_NO_RETURN 0x0008
400 /* convenience version of most used call flags */
401 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
402 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
403 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
404 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
405 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
407 /* Used to align parameters. See the comment before tcgv_i32_temp. */
408 #define TCG_CALL_DUMMY_ARG ((TCGArg)0)
410 /* Conditions. Note that these are laid out for easy manipulation by
412 bit 0 is used for inverting;
415 bit 3 is used with bit 0 for swapping signed/unsigned. */
418 TCG_COND_NEVER
= 0 | 0 | 0 | 0,
419 TCG_COND_ALWAYS
= 0 | 0 | 0 | 1,
420 TCG_COND_EQ
= 8 | 0 | 0 | 0,
421 TCG_COND_NE
= 8 | 0 | 0 | 1,
423 TCG_COND_LT
= 0 | 0 | 2 | 0,
424 TCG_COND_GE
= 0 | 0 | 2 | 1,
425 TCG_COND_LE
= 8 | 0 | 2 | 0,
426 TCG_COND_GT
= 8 | 0 | 2 | 1,
428 TCG_COND_LTU
= 0 | 4 | 0 | 0,
429 TCG_COND_GEU
= 0 | 4 | 0 | 1,
430 TCG_COND_LEU
= 8 | 4 | 0 | 0,
431 TCG_COND_GTU
= 8 | 4 | 0 | 1,
434 /* Invert the sense of the comparison. */
435 static inline TCGCond
tcg_invert_cond(TCGCond c
)
437 return (TCGCond
)(c
^ 1);
440 /* Swap the operands in a comparison. */
441 static inline TCGCond
tcg_swap_cond(TCGCond c
)
443 return c
& 6 ? (TCGCond
)(c
^ 9) : c
;
446 /* Create an "unsigned" version of a "signed" comparison. */
447 static inline TCGCond
tcg_unsigned_cond(TCGCond c
)
449 return c
& 2 ? (TCGCond
)(c
^ 6) : c
;
452 /* Create a "signed" version of an "unsigned" comparison. */
453 static inline TCGCond
tcg_signed_cond(TCGCond c
)
455 return c
& 4 ? (TCGCond
)(c
^ 6) : c
;
458 /* Must a comparison be considered unsigned? */
459 static inline bool is_unsigned_cond(TCGCond c
)
464 /* Create a "high" version of a double-word comparison.
465 This removes equality from a LTE or GTE comparison. */
466 static inline TCGCond
tcg_high_cond(TCGCond c
)
473 return (TCGCond
)(c
^ 8);
479 typedef enum TCGTempVal
{
486 typedef enum TCGTempKind
{
487 /* Temp is dead at the end of all basic blocks. */
489 /* Temp is saved across basic blocks but dead at the end of TBs. */
491 /* Temp is saved across both basic blocks and translation blocks. */
493 /* Temp is in a fixed register. */
497 typedef struct TCGTemp
{
499 TCGTempVal val_type
:8;
503 unsigned int indirect_reg
:1;
504 unsigned int indirect_base
:1;
505 unsigned int mem_coherent
:1;
506 unsigned int mem_allocated
:1;
507 unsigned int temp_allocated
:1;
510 struct TCGTemp
*mem_base
;
514 /* Pass-specific information that can be stored for a temporary.
515 One word worth of integer data, and one pointer to data
516 allocated separately. */
521 typedef struct TCGContext TCGContext
;
523 typedef struct TCGTempSet
{
524 unsigned long l
[BITS_TO_LONGS(TCG_MAX_TEMPS
)];
527 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
528 this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
529 There are never more than 2 outputs, which means that we can store all
530 dead + sync data within 16 bits. */
533 typedef uint16_t TCGLifeData
;
535 /* The layout here is designed to avoid a bitfield crossing of
536 a 32-bit boundary, which would cause GCC to add extra padding. */
537 typedef struct TCGOp
{
538 TCGOpcode opc
: 8; /* 8 */
540 /* Parameters for this opcode. See below. */
541 unsigned param1
: 4; /* 12 */
542 unsigned param2
: 4; /* 16 */
544 /* Lifetime data of the operands. */
545 unsigned life
: 16; /* 32 */
547 /* Next and previous opcodes. */
548 QTAILQ_ENTRY(TCGOp
) link
;
550 QSIMPLEQ_ENTRY(TCGOp
) plugin_link
;
553 /* Arguments for the opcode. */
554 TCGArg args
[MAX_OPC_PARAM
];
556 /* Register preferences for the output(s). */
557 TCGRegSet output_pref
[2];
560 #define TCGOP_CALLI(X) (X)->param1
561 #define TCGOP_CALLO(X) (X)->param2
563 #define TCGOP_VECL(X) (X)->param1
564 #define TCGOP_VECE(X) (X)->param2
566 /* Make sure operands fit in the bitfields above. */
567 QEMU_BUILD_BUG_ON(NB_OPS
> (1 << 8));
569 typedef struct TCGProfile
{
570 int64_t cpu_exec_time
;
573 int64_t op_count
; /* total insn count */
574 int op_count_max
; /* max insn per TB */
577 int64_t del_op_count
;
579 int64_t code_out_len
;
580 int64_t search_out_len
;
585 int64_t restore_count
;
586 int64_t restore_time
;
587 int64_t table_op_count
[NB_OPS
];
591 uint8_t *pool_cur
, *pool_end
;
592 TCGPool
*pool_first
, *pool_current
, *pool_first_large
;
599 /* goto_tb support */
600 tcg_insn_unit
*code_buf
;
601 uint16_t *tb_jmp_reset_offset
; /* tb->jmp_reset_offset */
602 uintptr_t *tb_jmp_insn_offset
; /* tb->jmp_target_arg if direct_jump */
603 uintptr_t *tb_jmp_target_addr
; /* tb->jmp_target_arg if !direct_jump */
605 TCGRegSet reserved_regs
;
606 uint32_t tb_cflags
; /* cflags of the current TB */
607 intptr_t current_frame_offset
;
608 intptr_t frame_start
;
612 tcg_insn_unit
*code_ptr
;
614 #ifdef CONFIG_PROFILER
618 #ifdef CONFIG_DEBUG_TCG
620 int goto_tb_issue_mask
;
621 const TCGOpcode
*vecop_list
;
624 /* Code generation. Note that we specifically do not use tcg_insn_unit
625 here, because there's too much arithmetic throughout that relies
626 on addition and subtraction working on bytes. Rely on the GCC
627 extension that allows arithmetic on void*. */
628 void *code_gen_buffer
;
629 size_t code_gen_buffer_size
;
633 /* Threshold to flush the translated code buffer. */
634 void *code_gen_highwater
;
636 size_t tb_phys_invalidate_count
;
638 /* Track which vCPU triggers events */
639 CPUState
*cpu
; /* *_trans */
641 /* These structures are private to tcg-target.c.inc. */
642 #ifdef TCG_TARGET_NEED_LDST_LABELS
643 QSIMPLEQ_HEAD(, TCGLabelQemuLdst
) ldst_labels
;
645 #ifdef TCG_TARGET_NEED_POOL_LABELS
646 struct TCGLabelPoolData
*pool_labels
;
649 TCGLabel
*exitreq_label
;
653 * We keep one plugin_tb struct per TCGContext. Note that on every TB
654 * translation we clear but do not free its contents; this way we
655 * avoid a lot of malloc/free churn, since after a few TB's it's
656 * unlikely that we'll need to allocate either more instructions or more
657 * space for instructions (for variable-instruction-length ISAs).
659 struct qemu_plugin_tb
*plugin_tb
;
661 /* descriptor of the instruction being translated */
662 struct qemu_plugin_insn
*plugin_insn
;
664 /* list to quickly access the injected ops */
665 QSIMPLEQ_HEAD(, TCGOp
) plugin_ops
;
668 TCGTempSet free_temps
[TCG_TYPE_COUNT
* 2];
669 TCGTemp temps
[TCG_MAX_TEMPS
]; /* globals first, temps after */
671 QTAILQ_HEAD(, TCGOp
) ops
, free_ops
;
672 QSIMPLEQ_HEAD(, TCGLabel
) labels
;
674 /* Tells which temporary holds a given register.
675 It does not take into account fixed registers */
676 TCGTemp
*reg_to_temp
[TCG_TARGET_NB_REGS
];
678 uint16_t gen_insn_end_off
[TCG_MAX_INSNS
];
679 target_ulong gen_insn_data
[TCG_MAX_INSNS
][TARGET_INSN_START_WORDS
];
682 static inline bool temp_readonly(TCGTemp
*ts
)
684 return ts
->kind
== TEMP_FIXED
;
687 extern TCGContext tcg_init_ctx
;
688 extern __thread TCGContext
*tcg_ctx
;
689 extern const void *tcg_code_gen_epilogue
;
690 extern uintptr_t tcg_splitwx_diff
;
691 extern TCGv_env cpu_env
;
693 static inline bool in_code_gen_buffer(const void *p
)
695 const TCGContext
*s
= &tcg_init_ctx
;
697 * Much like it is valid to have a pointer to the byte past the
698 * end of an array (so long as you don't dereference it), allow
699 * a pointer to the byte past the end of the code gen buffer.
701 return (size_t)(p
- s
->code_gen_buffer
) <= s
->code_gen_buffer_size
;
704 #ifdef CONFIG_DEBUG_TCG
705 const void *tcg_splitwx_to_rx(void *rw
);
706 void *tcg_splitwx_to_rw(const void *rx
);
708 static inline const void *tcg_splitwx_to_rx(void *rw
)
710 return rw
? rw
+ tcg_splitwx_diff
: NULL
;
713 static inline void *tcg_splitwx_to_rw(const void *rx
)
715 return rx
? (void *)rx
- tcg_splitwx_diff
: NULL
;
719 static inline size_t temp_idx(TCGTemp
*ts
)
721 ptrdiff_t n
= ts
- tcg_ctx
->temps
;
722 tcg_debug_assert(n
>= 0 && n
< tcg_ctx
->nb_temps
);
726 static inline TCGArg
temp_arg(TCGTemp
*ts
)
728 return (uintptr_t)ts
;
731 static inline TCGTemp
*arg_temp(TCGArg a
)
733 return (TCGTemp
*)(uintptr_t)a
;
736 /* Using the offset of a temporary, relative to TCGContext, rather than
737 its index means that we don't use 0. That leaves offset 0 free for
738 a NULL representation without having to leave index 0 unused. */
739 static inline TCGTemp
*tcgv_i32_temp(TCGv_i32 v
)
741 uintptr_t o
= (uintptr_t)v
;
742 TCGTemp
*t
= (void *)tcg_ctx
+ o
;
743 tcg_debug_assert(offsetof(TCGContext
, temps
[temp_idx(t
)]) == o
);
747 static inline TCGTemp
*tcgv_i64_temp(TCGv_i64 v
)
749 return tcgv_i32_temp((TCGv_i32
)v
);
752 static inline TCGTemp
*tcgv_ptr_temp(TCGv_ptr v
)
754 return tcgv_i32_temp((TCGv_i32
)v
);
757 static inline TCGTemp
*tcgv_vec_temp(TCGv_vec v
)
759 return tcgv_i32_temp((TCGv_i32
)v
);
762 static inline TCGArg
tcgv_i32_arg(TCGv_i32 v
)
764 return temp_arg(tcgv_i32_temp(v
));
767 static inline TCGArg
tcgv_i64_arg(TCGv_i64 v
)
769 return temp_arg(tcgv_i64_temp(v
));
772 static inline TCGArg
tcgv_ptr_arg(TCGv_ptr v
)
774 return temp_arg(tcgv_ptr_temp(v
));
777 static inline TCGArg
tcgv_vec_arg(TCGv_vec v
)
779 return temp_arg(tcgv_vec_temp(v
));
782 static inline TCGv_i32
temp_tcgv_i32(TCGTemp
*t
)
784 (void)temp_idx(t
); /* trigger embedded assert */
785 return (TCGv_i32
)((void *)t
- (void *)tcg_ctx
);
788 static inline TCGv_i64
temp_tcgv_i64(TCGTemp
*t
)
790 return (TCGv_i64
)temp_tcgv_i32(t
);
793 static inline TCGv_ptr
temp_tcgv_ptr(TCGTemp
*t
)
795 return (TCGv_ptr
)temp_tcgv_i32(t
);
798 static inline TCGv_vec
temp_tcgv_vec(TCGTemp
*t
)
800 return (TCGv_vec
)temp_tcgv_i32(t
);
803 #if TCG_TARGET_REG_BITS == 32
804 static inline TCGv_i32
TCGV_LOW(TCGv_i64 t
)
806 return temp_tcgv_i32(tcgv_i64_temp(t
));
809 static inline TCGv_i32
TCGV_HIGH(TCGv_i64 t
)
811 return temp_tcgv_i32(tcgv_i64_temp(t
) + 1);
815 static inline TCGArg
tcg_get_insn_param(TCGOp
*op
, int arg
)
817 return op
->args
[arg
];
820 static inline void tcg_set_insn_param(TCGOp
*op
, int arg
, TCGArg v
)
825 static inline target_ulong
tcg_get_insn_start_param(TCGOp
*op
, int arg
)
827 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
828 return tcg_get_insn_param(op
, arg
);
830 return tcg_get_insn_param(op
, arg
* 2) |
831 ((uint64_t)tcg_get_insn_param(op
, arg
* 2 + 1) << 32);
835 static inline void tcg_set_insn_start_param(TCGOp
*op
, int arg
, target_ulong v
)
837 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
838 tcg_set_insn_param(op
, arg
, v
);
840 tcg_set_insn_param(op
, arg
* 2, v
);
841 tcg_set_insn_param(op
, arg
* 2 + 1, v
>> 32);
845 /* The last op that was emitted. */
846 static inline TCGOp
*tcg_last_op(void)
848 return QTAILQ_LAST(&tcg_ctx
->ops
);
851 /* Test for whether to terminate the TB for using too many opcodes. */
852 static inline bool tcg_op_buf_full(void)
854 /* This is not a hard limit, it merely stops translation when
855 * we have produced "enough" opcodes. We want to limit TB size
856 * such that a RISC host can reasonably use a 16-bit signed
857 * branch within the TB. We also need to be mindful of the
858 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
859 * and TCGContext.gen_insn_end_off[].
861 return tcg_ctx
->nb_ops
>= 4000;
864 /* pool based memory allocation */
866 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
867 void *tcg_malloc_internal(TCGContext
*s
, int size
);
868 void tcg_pool_reset(TCGContext
*s
);
869 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
);
871 void tcg_region_init(void);
872 void tb_destroy(TranslationBlock
*tb
);
873 void tcg_region_reset_all(void);
875 size_t tcg_code_size(void);
876 size_t tcg_code_capacity(void);
878 void tcg_tb_insert(TranslationBlock
*tb
);
879 void tcg_tb_remove(TranslationBlock
*tb
);
880 size_t tcg_tb_phys_invalidate_count(void);
881 TranslationBlock
*tcg_tb_lookup(uintptr_t tc_ptr
);
882 void tcg_tb_foreach(GTraverseFunc func
, gpointer user_data
);
883 size_t tcg_nb_tbs(void);
885 /* user-mode: Called with mmap_lock held. */
886 static inline void *tcg_malloc(int size
)
888 TCGContext
*s
= tcg_ctx
;
889 uint8_t *ptr
, *ptr_end
;
891 /* ??? This is a weak placeholder for minimum malloc alignment. */
892 size
= QEMU_ALIGN_UP(size
, 8);
895 ptr_end
= ptr
+ size
;
896 if (unlikely(ptr_end
> s
->pool_end
)) {
897 return tcg_malloc_internal(tcg_ctx
, size
);
899 s
->pool_cur
= ptr_end
;
904 void tcg_context_init(TCGContext
*s
);
905 void tcg_register_thread(void);
906 void tcg_prologue_init(TCGContext
*s
);
907 void tcg_func_start(TCGContext
*s
);
909 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
);
911 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
);
913 TCGTemp
*tcg_global_mem_new_internal(TCGType
, TCGv_ptr
,
914 intptr_t, const char *);
915 TCGTemp
*tcg_temp_new_internal(TCGType
, bool);
916 void tcg_temp_free_internal(TCGTemp
*);
917 TCGv_vec
tcg_temp_new_vec(TCGType type
);
918 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
);
920 static inline void tcg_temp_free_i32(TCGv_i32 arg
)
922 tcg_temp_free_internal(tcgv_i32_temp(arg
));
925 static inline void tcg_temp_free_i64(TCGv_i64 arg
)
927 tcg_temp_free_internal(tcgv_i64_temp(arg
));
930 static inline void tcg_temp_free_ptr(TCGv_ptr arg
)
932 tcg_temp_free_internal(tcgv_ptr_temp(arg
));
935 static inline void tcg_temp_free_vec(TCGv_vec arg
)
937 tcg_temp_free_internal(tcgv_vec_temp(arg
));
940 static inline TCGv_i32
tcg_global_mem_new_i32(TCGv_ptr reg
, intptr_t offset
,
943 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
944 return temp_tcgv_i32(t
);
947 static inline TCGv_i32
tcg_temp_new_i32(void)
949 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I32
, false);
950 return temp_tcgv_i32(t
);
953 static inline TCGv_i32
tcg_temp_local_new_i32(void)
955 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I32
, true);
956 return temp_tcgv_i32(t
);
959 static inline TCGv_i64
tcg_global_mem_new_i64(TCGv_ptr reg
, intptr_t offset
,
962 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
963 return temp_tcgv_i64(t
);
966 static inline TCGv_i64
tcg_temp_new_i64(void)
968 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I64
, false);
969 return temp_tcgv_i64(t
);
972 static inline TCGv_i64
tcg_temp_local_new_i64(void)
974 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I64
, true);
975 return temp_tcgv_i64(t
);
978 static inline TCGv_ptr
tcg_global_mem_new_ptr(TCGv_ptr reg
, intptr_t offset
,
981 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_PTR
, reg
, offset
, name
);
982 return temp_tcgv_ptr(t
);
985 static inline TCGv_ptr
tcg_temp_new_ptr(void)
987 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_PTR
, false);
988 return temp_tcgv_ptr(t
);
991 static inline TCGv_ptr
tcg_temp_local_new_ptr(void)
993 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_PTR
, true);
994 return temp_tcgv_ptr(t
);
997 #if defined(CONFIG_DEBUG_TCG)
998 /* If you call tcg_clear_temp_count() at the start of a section of
999 * code which is not supposed to leak any TCG temporaries, then
1000 * calling tcg_check_temp_count() at the end of the section will
1001 * return 1 if the section did in fact leak a temporary.
1003 void tcg_clear_temp_count(void);
1004 int tcg_check_temp_count(void);
1006 #define tcg_clear_temp_count() do { } while (0)
1007 #define tcg_check_temp_count() 0
1010 int64_t tcg_cpu_exec_time(void);
1011 void tcg_dump_info(void);
1012 void tcg_dump_op_count(void);
1014 #define TCG_CT_CONST 1 /* any constant of register size */
1016 typedef struct TCGArgConstraint
{
1018 unsigned alias_index
: 4;
1019 unsigned sort_index
: 4;
1026 #define TCG_MAX_OP_ARGS 16
1028 /* Bits for TCGOpDef->flags, 8 bits available, all used. */
1030 /* Instruction exits the translation block. */
1031 TCG_OPF_BB_EXIT
= 0x01,
1032 /* Instruction defines the end of a basic block. */
1033 TCG_OPF_BB_END
= 0x02,
1034 /* Instruction clobbers call registers and potentially update globals. */
1035 TCG_OPF_CALL_CLOBBER
= 0x04,
1036 /* Instruction has side effects: it cannot be removed if its outputs
1037 are not used, and might trigger exceptions. */
1038 TCG_OPF_SIDE_EFFECTS
= 0x08,
1039 /* Instruction operands are 64-bits (otherwise 32-bits). */
1040 TCG_OPF_64BIT
= 0x10,
1041 /* Instruction is optional and not implemented by the host, or insn
1042 is generic and should not be implemened by the host. */
1043 TCG_OPF_NOT_PRESENT
= 0x20,
1044 /* Instruction operands are vectors. */
1045 TCG_OPF_VECTOR
= 0x40,
1046 /* Instruction is a conditional branch. */
1047 TCG_OPF_COND_BRANCH
= 0x80
1050 typedef struct TCGOpDef
{
1052 uint8_t nb_oargs
, nb_iargs
, nb_cargs
, nb_args
;
1054 TCGArgConstraint
*args_ct
;
1057 extern TCGOpDef tcg_op_defs
[];
1058 extern const size_t tcg_op_defs_max
;
1060 typedef struct TCGTargetOpDef
{
1062 const char *args_ct_str
[TCG_MAX_OP_ARGS
];
1065 #define tcg_abort() \
1067 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1071 bool tcg_op_supported(TCGOpcode op
);
1073 void tcg_gen_callN(void *func
, TCGTemp
*ret
, int nargs
, TCGTemp
**args
);
1075 TCGOp
*tcg_emit_op(TCGOpcode opc
);
1076 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
);
1077 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
);
1078 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
);
1080 void tcg_optimize(TCGContext
*s
);
1082 TCGv_i32
tcg_const_i32(int32_t val
);
1083 TCGv_i64
tcg_const_i64(int64_t val
);
1084 TCGv_i32
tcg_const_local_i32(int32_t val
);
1085 TCGv_i64
tcg_const_local_i64(int64_t val
);
1086 TCGv_vec
tcg_const_zeros_vec(TCGType
);
1087 TCGv_vec
tcg_const_ones_vec(TCGType
);
1088 TCGv_vec
tcg_const_zeros_vec_matching(TCGv_vec
);
1089 TCGv_vec
tcg_const_ones_vec_matching(TCGv_vec
);
1091 #if UINTPTR_MAX == UINT32_MAX
1092 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1093 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1095 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1096 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1099 TCGLabel
*gen_new_label(void);
1105 * Encode a label for storage in the TCG opcode stream.
1108 static inline TCGArg
label_arg(TCGLabel
*l
)
1110 return (uintptr_t)l
;
1117 * The opposite of label_arg. Retrieve a label from the
1118 * encoding of the TCG opcode stream.
1121 static inline TCGLabel
*arg_label(TCGArg i
)
1123 return (TCGLabel
*)(uintptr_t)i
;
1128 * @a, @b: addresses to be differenced
1130 * There are many places within the TCG backends where we need a byte
1131 * difference between two pointers. While this can be accomplished
1132 * with local casting, it's easy to get wrong -- especially if one is
1133 * concerned with the signedness of the result.
1135 * This version relies on GCC's void pointer arithmetic to get the
1139 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a
, const void *b
)
1146 * @s: the tcg context
1147 * @target: address of the target
1149 * Produce a pc-relative difference, from the current code_ptr
1150 * to the destination address.
1153 static inline ptrdiff_t tcg_pcrel_diff(TCGContext
*s
, const void *target
)
1155 return tcg_ptr_byte_diff(target
, tcg_splitwx_to_rx(s
->code_ptr
));
1160 * @s: the tcg context
1161 * @target: address of the target
1163 * Produce a difference, from the beginning of the current TB code
1164 * to the destination address.
1166 static inline ptrdiff_t tcg_tbrel_diff(TCGContext
*s
, const void *target
)
1168 return tcg_ptr_byte_diff(target
, tcg_splitwx_to_rx(s
->code_buf
));
1172 * tcg_current_code_size
1173 * @s: the tcg context
1175 * Compute the current code size within the translation block.
1176 * This is used to fill in qemu's data structures for goto_tb.
1179 static inline size_t tcg_current_code_size(TCGContext
*s
)
1181 return tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
);
1184 /* Combine the MemOp and mmu_idx parameters into a single value. */
1185 typedef uint32_t TCGMemOpIdx
;
1189 * @op: memory operation
1192 * Encode these values into a single parameter.
1194 static inline TCGMemOpIdx
make_memop_idx(MemOp op
, unsigned idx
)
1196 tcg_debug_assert(idx
<= 15);
1197 return (op
<< 4) | idx
;
1202 * @oi: combined op/idx parameter
1204 * Extract the memory operation from the combined value.
1206 static inline MemOp
get_memop(TCGMemOpIdx oi
)
1213 * @oi: combined op/idx parameter
1215 * Extract the mmu index from the combined value.
1217 static inline unsigned get_mmuidx(TCGMemOpIdx oi
)
1224 * @env: pointer to CPUArchState for the CPU
1225 * @tb_ptr: address of generated code for the TB to execute
1227 * Start executing code from a given translation block.
1228 * Where translation blocks have been linked, execution
1229 * may proceed from the given TB into successive ones.
1230 * Control eventually returns only when some action is needed
1231 * from the top-level loop: either control must pass to a TB
1232 * which has not yet been directly linked, or an asynchronous
1233 * event such as an interrupt needs handling.
1235 * Return: The return value is the value passed to the corresponding
1236 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1237 * The value is either zero or a 4-byte aligned pointer to that TB combined
1238 * with additional information in its two least significant bits. The
1239 * additional information is encoded as follows:
1240 * 0, 1: the link between this TB and the next is via the specified
1241 * TB index (0 or 1). That is, we left the TB via (the equivalent
1242 * of) "goto_tb <index>". The main loop uses this to determine
1243 * how to link the TB just executed to the next.
1244 * 2: we are using instruction counting code generation, and we
1245 * did not start executing this TB because the instruction counter
1246 * would hit zero midway through it. In this case the pointer
1247 * returned is the TB we were about to execute, and the caller must
1248 * arrange to execute the remaining count of instructions.
1249 * 3: we stopped because the CPU's exit_request flag was set
1250 * (usually meaning that there is an interrupt that needs to be
1251 * handled). The pointer returned is the TB we were about to execute
1252 * when we noticed the pending exit request.
1254 * If the bottom two bits indicate an exit-via-index then the CPU
1255 * state is correctly synchronised and ready for execution of the next
1256 * TB (and in particular the guest PC is the address to execute next).
1257 * Otherwise, we gave up on execution of this TB before it started, and
1258 * the caller must fix up the CPU state by calling the CPU's
1259 * synchronize_from_tb() method with the TB pointer we return (falling
1260 * back to calling the CPU's set_pc method with tb->pb if no
1261 * synchronize_from_tb() method exists).
1263 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1264 * to this default (which just calls the prologue.code emitted by
1265 * tcg_target_qemu_prologue()).
1267 #define TB_EXIT_MASK 3
1268 #define TB_EXIT_IDX0 0
1269 #define TB_EXIT_IDX1 1
1270 #define TB_EXIT_IDXMAX 1
1271 #define TB_EXIT_REQUESTED 3
1273 #ifdef CONFIG_TCG_INTERPRETER
1274 uintptr_t tcg_qemu_tb_exec(CPUArchState
*env
, const void *tb_ptr
);
1276 typedef uintptr_t tcg_prologue_fn(CPUArchState
*env
, const void *tb_ptr
);
1277 extern tcg_prologue_fn
*tcg_qemu_tb_exec
;
1280 void tcg_register_jit(const void *buf
, size_t buf_size
);
1282 #if TCG_TARGET_MAYBE_vec
1283 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1284 return > 0 if it is directly supportable;
1285 return < 0 if we must call tcg_expand_vec_op. */
1286 int tcg_can_emit_vec_op(TCGOpcode
, TCGType
, unsigned);
1288 static inline int tcg_can_emit_vec_op(TCGOpcode o
, TCGType t
, unsigned ve
)
1294 /* Expand the tuple (opc, type, vece) on the given arguments. */
1295 void tcg_expand_vec_op(TCGOpcode
, TCGType
, unsigned, TCGArg
, ...);
1297 /* Replicate a constant C accoring to the log2 of the element size. */
1298 uint64_t dup_const(unsigned vece
, uint64_t c
);
1300 #define dup_const(VECE, C) \
1301 (__builtin_constant_p(VECE) \
1302 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
1303 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
1304 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
1305 : dup_const(VECE, C)) \
1306 : dup_const(VECE, C))
1310 * Memory helpers that will be used by TCG generated code.
1312 #ifdef CONFIG_SOFTMMU
1313 /* Value zero-extended to tcg register size. */
1314 tcg_target_ulong
helper_ret_ldub_mmu(CPUArchState
*env
, target_ulong addr
,
1315 TCGMemOpIdx oi
, uintptr_t retaddr
);
1316 tcg_target_ulong
helper_le_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1317 TCGMemOpIdx oi
, uintptr_t retaddr
);
1318 tcg_target_ulong
helper_le_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1319 TCGMemOpIdx oi
, uintptr_t retaddr
);
1320 uint64_t helper_le_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1321 TCGMemOpIdx oi
, uintptr_t retaddr
);
1322 tcg_target_ulong
helper_be_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1323 TCGMemOpIdx oi
, uintptr_t retaddr
);
1324 tcg_target_ulong
helper_be_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1325 TCGMemOpIdx oi
, uintptr_t retaddr
);
1326 uint64_t helper_be_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1327 TCGMemOpIdx oi
, uintptr_t retaddr
);
1329 /* Value sign-extended to tcg register size. */
1330 tcg_target_ulong
helper_ret_ldsb_mmu(CPUArchState
*env
, target_ulong addr
,
1331 TCGMemOpIdx oi
, uintptr_t retaddr
);
1332 tcg_target_ulong
helper_le_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1333 TCGMemOpIdx oi
, uintptr_t retaddr
);
1334 tcg_target_ulong
helper_le_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1335 TCGMemOpIdx oi
, uintptr_t retaddr
);
1336 tcg_target_ulong
helper_be_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1337 TCGMemOpIdx oi
, uintptr_t retaddr
);
1338 tcg_target_ulong
helper_be_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1339 TCGMemOpIdx oi
, uintptr_t retaddr
);
1341 void helper_ret_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint8_t val
,
1342 TCGMemOpIdx oi
, uintptr_t retaddr
);
1343 void helper_le_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1344 TCGMemOpIdx oi
, uintptr_t retaddr
);
1345 void helper_le_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1346 TCGMemOpIdx oi
, uintptr_t retaddr
);
1347 void helper_le_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1348 TCGMemOpIdx oi
, uintptr_t retaddr
);
1349 void helper_be_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1350 TCGMemOpIdx oi
, uintptr_t retaddr
);
1351 void helper_be_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1352 TCGMemOpIdx oi
, uintptr_t retaddr
);
1353 void helper_be_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1354 TCGMemOpIdx oi
, uintptr_t retaddr
);
1356 /* Temporary aliases until backends are converted. */
1357 #ifdef TARGET_WORDS_BIGENDIAN
1358 # define helper_ret_ldsw_mmu helper_be_ldsw_mmu
1359 # define helper_ret_lduw_mmu helper_be_lduw_mmu
1360 # define helper_ret_ldsl_mmu helper_be_ldsl_mmu
1361 # define helper_ret_ldul_mmu helper_be_ldul_mmu
1362 # define helper_ret_ldl_mmu helper_be_ldul_mmu
1363 # define helper_ret_ldq_mmu helper_be_ldq_mmu
1364 # define helper_ret_stw_mmu helper_be_stw_mmu
1365 # define helper_ret_stl_mmu helper_be_stl_mmu
1366 # define helper_ret_stq_mmu helper_be_stq_mmu
1368 # define helper_ret_ldsw_mmu helper_le_ldsw_mmu
1369 # define helper_ret_lduw_mmu helper_le_lduw_mmu
1370 # define helper_ret_ldsl_mmu helper_le_ldsl_mmu
1371 # define helper_ret_ldul_mmu helper_le_ldul_mmu
1372 # define helper_ret_ldl_mmu helper_le_ldul_mmu
1373 # define helper_ret_ldq_mmu helper_le_ldq_mmu
1374 # define helper_ret_stw_mmu helper_le_stw_mmu
1375 # define helper_ret_stl_mmu helper_le_stl_mmu
1376 # define helper_ret_stq_mmu helper_le_stq_mmu
1379 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState
*env
, target_ulong addr
,
1380 uint32_t cmpv
, uint32_t newv
,
1381 TCGMemOpIdx oi
, uintptr_t retaddr
);
1382 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState
*env
, target_ulong addr
,
1383 uint32_t cmpv
, uint32_t newv
,
1384 TCGMemOpIdx oi
, uintptr_t retaddr
);
1385 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState
*env
, target_ulong addr
,
1386 uint32_t cmpv
, uint32_t newv
,
1387 TCGMemOpIdx oi
, uintptr_t retaddr
);
1388 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState
*env
, target_ulong addr
,
1389 uint64_t cmpv
, uint64_t newv
,
1390 TCGMemOpIdx oi
, uintptr_t retaddr
);
1391 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState
*env
, target_ulong addr
,
1392 uint32_t cmpv
, uint32_t newv
,
1393 TCGMemOpIdx oi
, uintptr_t retaddr
);
1394 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState
*env
, target_ulong addr
,
1395 uint32_t cmpv
, uint32_t newv
,
1396 TCGMemOpIdx oi
, uintptr_t retaddr
);
1397 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState
*env
, target_ulong addr
,
1398 uint64_t cmpv
, uint64_t newv
,
1399 TCGMemOpIdx oi
, uintptr_t retaddr
);
1401 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
1402 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
1403 (CPUArchState *env, target_ulong addr, TYPE val, \
1404 TCGMemOpIdx oi, uintptr_t retaddr);
1406 #ifdef CONFIG_ATOMIC64
1407 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1408 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1409 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1410 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1411 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1412 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
1413 GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
1414 GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1416 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1417 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1418 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1419 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1420 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1421 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1424 GEN_ATOMIC_HELPER_ALL(fetch_add
)
1425 GEN_ATOMIC_HELPER_ALL(fetch_sub
)
1426 GEN_ATOMIC_HELPER_ALL(fetch_and
)
1427 GEN_ATOMIC_HELPER_ALL(fetch_or
)
1428 GEN_ATOMIC_HELPER_ALL(fetch_xor
)
1429 GEN_ATOMIC_HELPER_ALL(fetch_smin
)
1430 GEN_ATOMIC_HELPER_ALL(fetch_umin
)
1431 GEN_ATOMIC_HELPER_ALL(fetch_smax
)
1432 GEN_ATOMIC_HELPER_ALL(fetch_umax
)
1434 GEN_ATOMIC_HELPER_ALL(add_fetch
)
1435 GEN_ATOMIC_HELPER_ALL(sub_fetch
)
1436 GEN_ATOMIC_HELPER_ALL(and_fetch
)
1437 GEN_ATOMIC_HELPER_ALL(or_fetch
)
1438 GEN_ATOMIC_HELPER_ALL(xor_fetch
)
1439 GEN_ATOMIC_HELPER_ALL(smin_fetch
)
1440 GEN_ATOMIC_HELPER_ALL(umin_fetch
)
1441 GEN_ATOMIC_HELPER_ALL(smax_fetch
)
1442 GEN_ATOMIC_HELPER_ALL(umax_fetch
)
1444 GEN_ATOMIC_HELPER_ALL(xchg
)
1446 #undef GEN_ATOMIC_HELPER_ALL
1447 #undef GEN_ATOMIC_HELPER
1448 #endif /* CONFIG_SOFTMMU */
1451 * These aren't really a "proper" helpers because TCG cannot manage Int128.
1452 * However, use the same format as the others, for use by the backends.
1454 * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1455 * the ld/st functions are only defined if HAVE_ATOMIC128,
1456 * as defined by <qemu/atomic128.h>.
1458 Int128
helper_atomic_cmpxchgo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1459 Int128 cmpv
, Int128 newv
,
1460 TCGMemOpIdx oi
, uintptr_t retaddr
);
1461 Int128
helper_atomic_cmpxchgo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1462 Int128 cmpv
, Int128 newv
,
1463 TCGMemOpIdx oi
, uintptr_t retaddr
);
1465 Int128
helper_atomic_ldo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1466 TCGMemOpIdx oi
, uintptr_t retaddr
);
1467 Int128
helper_atomic_ldo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1468 TCGMemOpIdx oi
, uintptr_t retaddr
);
1469 void helper_atomic_sto_le_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1470 TCGMemOpIdx oi
, uintptr_t retaddr
);
1471 void helper_atomic_sto_be_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1472 TCGMemOpIdx oi
, uintptr_t retaddr
);
1474 #ifdef CONFIG_DEBUG_TCG
1475 void tcg_assert_listed_vecop(TCGOpcode
);
1477 static inline void tcg_assert_listed_vecop(TCGOpcode op
) { }
1480 static inline const TCGOpcode
*tcg_swap_vecop_list(const TCGOpcode
*n
)
1482 #ifdef CONFIG_DEBUG_TCG
1483 const TCGOpcode
*o
= tcg_ctx
->vecop_list
;
1484 tcg_ctx
->vecop_list
= n
;
1491 bool tcg_can_emit_vecop_list(const TCGOpcode
*, TCGType
, unsigned);