2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "sysemu/reset.h"
18 #include "hw/qdev-properties.h"
19 #include "migration/vmstate.h"
20 #include "monitor/monitor.h"
22 #include "hw/ppc/xive.h"
23 #include "hw/ppc/xive_regs.h"
26 * XIVE Thread Interrupt Management context
30 * Convert a priority number to an Interrupt Pending Buffer (IPB)
31 * register, which indicates a pending interrupt at the priority
32 * corresponding to the bit number
34 static uint8_t priority_to_ipb(uint8_t priority
)
36 return priority
> XIVE_PRIORITY_MAX
?
37 0 : 1 << (XIVE_PRIORITY_MAX
- priority
);
41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
42 * Interrupt Priority Register (PIPR), which contains the priority of
43 * the most favored pending notification.
45 static uint8_t ipb_to_pipr(uint8_t ibp
)
47 return ibp
? clz32((uint32_t)ibp
<< 24) : 0xff;
50 static void ipb_update(uint8_t *regs
, uint8_t priority
)
52 regs
[TM_IPB
] |= priority_to_ipb(priority
);
53 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
56 static uint8_t exception_mask(uint8_t ring
)
64 g_assert_not_reached();
68 static qemu_irq
xive_tctx_output(XiveTCTX
*tctx
, uint8_t ring
)
72 return 0; /* Not supported */
74 return tctx
->os_output
;
77 return tctx
->hv_output
;
83 static uint64_t xive_tctx_accept(XiveTCTX
*tctx
, uint8_t ring
)
85 uint8_t *regs
= &tctx
->regs
[ring
];
86 uint8_t nsr
= regs
[TM_NSR
];
87 uint8_t mask
= exception_mask(ring
);
89 qemu_irq_lower(xive_tctx_output(tctx
, ring
));
91 if (regs
[TM_NSR
] & mask
) {
92 uint8_t cppr
= regs
[TM_PIPR
];
96 /* Reset the pending buffer bit */
97 regs
[TM_IPB
] &= ~priority_to_ipb(cppr
);
98 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
100 /* Drop Exception bit */
101 regs
[TM_NSR
] &= ~mask
;
104 return (nsr
<< 8) | regs
[TM_CPPR
];
107 static void xive_tctx_notify(XiveTCTX
*tctx
, uint8_t ring
)
109 uint8_t *regs
= &tctx
->regs
[ring
];
111 if (regs
[TM_PIPR
] < regs
[TM_CPPR
]) {
114 regs
[TM_NSR
] |= TM_QW1_NSR_EO
;
117 regs
[TM_NSR
] |= (TM_QW3_NSR_HE_PHYS
<< 6);
120 g_assert_not_reached();
122 qemu_irq_raise(xive_tctx_output(tctx
, ring
));
126 static void xive_tctx_set_cppr(XiveTCTX
*tctx
, uint8_t ring
, uint8_t cppr
)
128 if (cppr
> XIVE_PRIORITY_MAX
) {
132 tctx
->regs
[ring
+ TM_CPPR
] = cppr
;
134 /* CPPR has changed, check if we need to raise a pending exception */
135 xive_tctx_notify(tctx
, ring
);
138 static inline uint32_t xive_tctx_word2(uint8_t *ring
)
140 return *((uint32_t *) &ring
[TM_WORD2
]);
144 * XIVE Thread Interrupt Management Area (TIMA)
147 static void xive_tm_set_hv_cppr(XiveTCTX
*tctx
, hwaddr offset
,
148 uint64_t value
, unsigned size
)
150 xive_tctx_set_cppr(tctx
, TM_QW3_HV_PHYS
, value
& 0xff);
153 static uint64_t xive_tm_ack_hv_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
155 return xive_tctx_accept(tctx
, TM_QW3_HV_PHYS
);
158 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX
*tctx
, hwaddr offset
,
161 uint32_t qw2w2_prev
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
164 qw2w2
= xive_set_field32(TM_QW2W2_VP
, qw2w2_prev
, 0);
165 memcpy(&tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
], &qw2w2
, 4);
169 static void xive_tm_vt_push(XiveTCTX
*tctx
, hwaddr offset
,
170 uint64_t value
, unsigned size
)
172 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] = value
& 0xff;
175 static uint64_t xive_tm_vt_poll(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
177 return tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] & 0xff;
181 * Define an access map for each page of the TIMA that we will use in
182 * the memory region ops to filter values when doing loads and stores
183 * of raw registers values
185 * Registers accessibility bits :
193 static const uint8_t xive_tm_hw_view
[] = {
194 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
195 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
196 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
197 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
200 static const uint8_t xive_tm_hv_view
[] = {
201 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
202 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
203 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
204 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
207 static const uint8_t xive_tm_os_view
[] = {
208 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
209 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
214 static const uint8_t xive_tm_user_view
[] = {
215 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
222 * Overall TIMA access map for the thread interrupt management context
225 static const uint8_t *xive_tm_views
[] = {
226 [XIVE_TM_HW_PAGE
] = xive_tm_hw_view
,
227 [XIVE_TM_HV_PAGE
] = xive_tm_hv_view
,
228 [XIVE_TM_OS_PAGE
] = xive_tm_os_view
,
229 [XIVE_TM_USER_PAGE
] = xive_tm_user_view
,
233 * Computes a register access mask for a given offset in the TIMA
235 static uint64_t xive_tm_mask(hwaddr offset
, unsigned size
, bool write
)
237 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
238 uint8_t reg_offset
= offset
& 0x3F;
239 uint8_t reg_mask
= write
? 0x1 : 0x2;
243 for (i
= 0; i
< size
; i
++) {
244 if (xive_tm_views
[page_offset
][reg_offset
+ i
] & reg_mask
) {
245 mask
|= (uint64_t) 0xff << (8 * (size
- i
- 1));
252 static void xive_tm_raw_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
255 uint8_t ring_offset
= offset
& 0x30;
256 uint8_t reg_offset
= offset
& 0x3F;
257 uint64_t mask
= xive_tm_mask(offset
, size
, true);
261 * Only 4 or 8 bytes stores are allowed and the User ring is
264 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
265 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA @%"
266 HWADDR_PRIx
"\n", offset
);
271 * Use the register offset for the raw values and filter out
274 for (i
= 0; i
< size
; i
++) {
275 uint8_t byte_mask
= (mask
>> (8 * (size
- i
- 1)));
277 tctx
->regs
[reg_offset
+ i
] = (value
>> (8 * (size
- i
- 1))) &
283 static uint64_t xive_tm_raw_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
285 uint8_t ring_offset
= offset
& 0x30;
286 uint8_t reg_offset
= offset
& 0x3F;
287 uint64_t mask
= xive_tm_mask(offset
, size
, false);
292 * Only 4 or 8 bytes loads are allowed and the User ring is
295 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
296 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access at TIMA @%"
297 HWADDR_PRIx
"\n", offset
);
301 /* Use the register offset for the raw values */
303 for (i
= 0; i
< size
; i
++) {
304 ret
|= (uint64_t) tctx
->regs
[reg_offset
+ i
] << (8 * (size
- i
- 1));
307 /* filter out reserved values */
312 * The TM context is mapped twice within each page. Stores and loads
313 * to the first mapping below 2K write and read the specified values
314 * without modification. The second mapping above 2K performs specific
315 * state changes (side effects) in addition to setting/returning the
316 * interrupt management area context of the processor thread.
318 static uint64_t xive_tm_ack_os_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
320 return xive_tctx_accept(tctx
, TM_QW1_OS
);
323 static void xive_tm_set_os_cppr(XiveTCTX
*tctx
, hwaddr offset
,
324 uint64_t value
, unsigned size
)
326 xive_tctx_set_cppr(tctx
, TM_QW1_OS
, value
& 0xff);
330 * Adjust the IPB to allow a CPU to process event queues of other
331 * priorities during one physical interrupt cycle.
333 static void xive_tm_set_os_pending(XiveTCTX
*tctx
, hwaddr offset
,
334 uint64_t value
, unsigned size
)
336 ipb_update(&tctx
->regs
[TM_QW1_OS
], value
& 0xff);
337 xive_tctx_notify(tctx
, TM_QW1_OS
);
341 * Define a mapping of "special" operations depending on the TIMA page
342 * offset and the size of the operation.
344 typedef struct XiveTmOp
{
348 void (*write_handler
)(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
350 uint64_t (*read_handler
)(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
);
353 static const XiveTmOp xive_tm_operations
[] = {
355 * MMIOs below 2K : raw values and special operations without side
358 { XIVE_TM_OS_PAGE
, TM_QW1_OS
+ TM_CPPR
, 1, xive_tm_set_os_cppr
, NULL
},
359 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_CPPR
, 1, xive_tm_set_hv_cppr
, NULL
},
360 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, xive_tm_vt_push
, NULL
},
361 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, NULL
, xive_tm_vt_poll
},
363 /* MMIOs above 2K : special operations with side effects */
364 { XIVE_TM_OS_PAGE
, TM_SPC_ACK_OS_REG
, 2, NULL
, xive_tm_ack_os_reg
},
365 { XIVE_TM_OS_PAGE
, TM_SPC_SET_OS_PENDING
, 1, xive_tm_set_os_pending
, NULL
},
366 { XIVE_TM_HV_PAGE
, TM_SPC_ACK_HV_REG
, 2, NULL
, xive_tm_ack_hv_reg
},
367 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 4, NULL
, xive_tm_pull_pool_ctx
},
368 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 8, NULL
, xive_tm_pull_pool_ctx
},
371 static const XiveTmOp
*xive_tm_find_op(hwaddr offset
, unsigned size
, bool write
)
373 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
374 uint32_t op_offset
= offset
& 0xFFF;
377 for (i
= 0; i
< ARRAY_SIZE(xive_tm_operations
); i
++) {
378 const XiveTmOp
*xto
= &xive_tm_operations
[i
];
380 /* Accesses done from a more privileged TIMA page is allowed */
381 if (xto
->page_offset
>= page_offset
&&
382 xto
->op_offset
== op_offset
&&
384 ((write
&& xto
->write_handler
) || (!write
&& xto
->read_handler
))) {
394 void xive_tctx_tm_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
400 * TODO: check V bit in Q[0-3]W2
404 * First, check for special operations in the 2K region
406 if (offset
& 0x800) {
407 xto
= xive_tm_find_op(offset
, size
, true);
409 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA"
410 "@%"HWADDR_PRIx
"\n", offset
);
412 xto
->write_handler(tctx
, offset
, value
, size
);
418 * Then, for special operations in the region below 2K.
420 xto
= xive_tm_find_op(offset
, size
, true);
422 xto
->write_handler(tctx
, offset
, value
, size
);
427 * Finish with raw access to the register values
429 xive_tm_raw_write(tctx
, offset
, value
, size
);
432 uint64_t xive_tctx_tm_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
437 * TODO: check V bit in Q[0-3]W2
441 * First, check for special operations in the 2K region
443 if (offset
& 0x800) {
444 xto
= xive_tm_find_op(offset
, size
, false);
446 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access to TIMA"
447 "@%"HWADDR_PRIx
"\n", offset
);
450 return xto
->read_handler(tctx
, offset
, size
);
454 * Then, for special operations in the region below 2K.
456 xto
= xive_tm_find_op(offset
, size
, false);
458 return xto
->read_handler(tctx
, offset
, size
);
462 * Finish with raw access to the register values
464 return xive_tm_raw_read(tctx
, offset
, size
);
467 static void xive_tm_write(void *opaque
, hwaddr offset
,
468 uint64_t value
, unsigned size
)
470 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
472 xive_tctx_tm_write(tctx
, offset
, value
, size
);
475 static uint64_t xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
477 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
479 return xive_tctx_tm_read(tctx
, offset
, size
);
482 const MemoryRegionOps xive_tm_ops
= {
483 .read
= xive_tm_read
,
484 .write
= xive_tm_write
,
485 .endianness
= DEVICE_BIG_ENDIAN
,
487 .min_access_size
= 1,
488 .max_access_size
= 8,
491 .min_access_size
= 1,
492 .max_access_size
= 8,
496 static char *xive_tctx_ring_print(uint8_t *ring
)
498 uint32_t w2
= xive_tctx_word2(ring
);
500 return g_strdup_printf("%02x %02x %02x %02x %02x "
501 "%02x %02x %02x %08x",
502 ring
[TM_NSR
], ring
[TM_CPPR
], ring
[TM_IPB
], ring
[TM_LSMFB
],
503 ring
[TM_ACK_CNT
], ring
[TM_INC
], ring
[TM_AGE
], ring
[TM_PIPR
],
507 static const char * const xive_tctx_ring_names
[] = {
508 "USER", "OS", "POOL", "PHYS",
511 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
)
513 int cpu_index
= tctx
->cs
? tctx
->cs
->cpu_index
: -1;
516 if (kvm_irqchip_in_kernel()) {
517 Error
*local_err
= NULL
;
519 kvmppc_xive_cpu_synchronize_state(tctx
, &local_err
);
521 error_report_err(local_err
);
526 monitor_printf(mon
, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
529 for (i
= 0; i
< XIVE_TM_RING_COUNT
; i
++) {
530 char *s
= xive_tctx_ring_print(&tctx
->regs
[i
* XIVE_TM_RING_SIZE
]);
531 monitor_printf(mon
, "CPU[%04x]: %4s %s\n", cpu_index
,
532 xive_tctx_ring_names
[i
], s
);
537 static void xive_tctx_reset(void *dev
)
539 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
541 memset(tctx
->regs
, 0, sizeof(tctx
->regs
));
543 /* Set some defaults */
544 tctx
->regs
[TM_QW1_OS
+ TM_LSMFB
] = 0xFF;
545 tctx
->regs
[TM_QW1_OS
+ TM_ACK_CNT
] = 0xFF;
546 tctx
->regs
[TM_QW1_OS
+ TM_AGE
] = 0xFF;
549 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
552 tctx
->regs
[TM_QW1_OS
+ TM_PIPR
] =
553 ipb_to_pipr(tctx
->regs
[TM_QW1_OS
+ TM_IPB
]);
554 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_PIPR
] =
555 ipb_to_pipr(tctx
->regs
[TM_QW3_HV_PHYS
+ TM_IPB
]);
558 static void xive_tctx_realize(DeviceState
*dev
, Error
**errp
)
560 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
564 Error
*local_err
= NULL
;
566 obj
= object_property_get_link(OBJECT(dev
), "cpu", &local_err
);
568 error_propagate(errp
, local_err
);
569 error_prepend(errp
, "required link 'cpu' not found: ");
573 cpu
= POWERPC_CPU(obj
);
577 switch (PPC_INPUT(env
)) {
578 case PPC_FLAGS_INPUT_POWER9
:
579 tctx
->hv_output
= env
->irq_inputs
[POWER9_INPUT_HINT
];
580 tctx
->os_output
= env
->irq_inputs
[POWER9_INPUT_INT
];
584 error_setg(errp
, "XIVE interrupt controller does not support "
585 "this CPU bus model");
589 /* Connect the presenter to the VCPU (required for CPU hotplug) */
590 if (kvm_irqchip_in_kernel()) {
591 kvmppc_xive_cpu_connect(tctx
, &local_err
);
593 error_propagate(errp
, local_err
);
598 qemu_register_reset(xive_tctx_reset
, dev
);
601 static void xive_tctx_unrealize(DeviceState
*dev
, Error
**errp
)
603 qemu_unregister_reset(xive_tctx_reset
, dev
);
606 static int vmstate_xive_tctx_pre_save(void *opaque
)
608 Error
*local_err
= NULL
;
610 if (kvm_irqchip_in_kernel()) {
611 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque
), &local_err
);
613 error_report_err(local_err
);
621 static int vmstate_xive_tctx_post_load(void *opaque
, int version_id
)
623 Error
*local_err
= NULL
;
625 if (kvm_irqchip_in_kernel()) {
627 * Required for hotplugged CPU, for which the state comes
628 * after all states of the machine.
630 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque
), &local_err
);
632 error_report_err(local_err
);
640 static const VMStateDescription vmstate_xive_tctx
= {
641 .name
= TYPE_XIVE_TCTX
,
643 .minimum_version_id
= 1,
644 .pre_save
= vmstate_xive_tctx_pre_save
,
645 .post_load
= vmstate_xive_tctx_post_load
,
646 .fields
= (VMStateField
[]) {
647 VMSTATE_BUFFER(regs
, XiveTCTX
),
648 VMSTATE_END_OF_LIST()
652 static void xive_tctx_class_init(ObjectClass
*klass
, void *data
)
654 DeviceClass
*dc
= DEVICE_CLASS(klass
);
656 dc
->desc
= "XIVE Interrupt Thread Context";
657 dc
->realize
= xive_tctx_realize
;
658 dc
->unrealize
= xive_tctx_unrealize
;
659 dc
->vmsd
= &vmstate_xive_tctx
;
662 static const TypeInfo xive_tctx_info
= {
663 .name
= TYPE_XIVE_TCTX
,
664 .parent
= TYPE_DEVICE
,
665 .instance_size
= sizeof(XiveTCTX
),
666 .class_init
= xive_tctx_class_init
,
669 Object
*xive_tctx_create(Object
*cpu
, XiveRouter
*xrtr
, Error
**errp
)
671 Error
*local_err
= NULL
;
674 obj
= object_new(TYPE_XIVE_TCTX
);
675 object_property_add_child(cpu
, TYPE_XIVE_TCTX
, obj
, &error_abort
);
677 object_property_add_const_link(obj
, "cpu", cpu
, &error_abort
);
678 object_property_set_bool(obj
, true, "realized", &local_err
);
686 object_unparent(obj
);
687 error_propagate(errp
, local_err
);
695 static uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
697 uint8_t old_pq
= *pq
& 0x3;
705 static bool xive_esb_trigger(uint8_t *pq
)
707 uint8_t old_pq
= *pq
& 0x3;
711 xive_esb_set(pq
, XIVE_ESB_PENDING
);
713 case XIVE_ESB_PENDING
:
714 case XIVE_ESB_QUEUED
:
715 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
718 xive_esb_set(pq
, XIVE_ESB_OFF
);
721 g_assert_not_reached();
725 static bool xive_esb_eoi(uint8_t *pq
)
727 uint8_t old_pq
= *pq
& 0x3;
731 case XIVE_ESB_PENDING
:
732 xive_esb_set(pq
, XIVE_ESB_RESET
);
734 case XIVE_ESB_QUEUED
:
735 xive_esb_set(pq
, XIVE_ESB_PENDING
);
738 xive_esb_set(pq
, XIVE_ESB_OFF
);
741 g_assert_not_reached();
746 * XIVE Interrupt Source (or IVSE)
749 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
751 assert(srcno
< xsrc
->nr_irqs
);
753 return xsrc
->status
[srcno
] & 0x3;
756 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
758 assert(srcno
< xsrc
->nr_irqs
);
760 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
764 * Returns whether the event notification should be forwarded.
766 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
768 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
770 xsrc
->status
[srcno
] |= XIVE_STATUS_ASSERTED
;
774 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
782 * Returns whether the event notification should be forwarded.
784 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
788 assert(srcno
< xsrc
->nr_irqs
);
790 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
792 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
793 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
794 qemu_log_mask(LOG_GUEST_ERROR
,
795 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
802 * Returns whether the event notification should be forwarded.
804 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
808 assert(srcno
< xsrc
->nr_irqs
);
810 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
813 * LSI sources do not set the Q bit but they can still be
814 * asserted, in which case we should forward a new event
817 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
818 xsrc
->status
[srcno
] & XIVE_STATUS_ASSERTED
) {
819 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
826 * Forward the source event notification to the Router
828 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
830 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
833 xnc
->notify(xsrc
->xive
, srcno
);
838 * In a two pages ESB MMIO setting, even page is the trigger page, odd
839 * page is for management
841 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
843 return !((addr
>> shift
) & 1);
846 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
848 return xive_source_esb_has_2page(xsrc
) &&
849 addr_is_even(addr
, xsrc
->esb_shift
- 1);
854 * Trigger page Management/EOI page
856 * ESB MMIO setting 2 pages 1 or 2 pages
858 * 0x000 .. 0x3FF -1 EOI and return 0|1
859 * 0x400 .. 0x7FF -1 EOI and return 0|1
860 * 0x800 .. 0xBFF -1 return PQ
861 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
862 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
863 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
864 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
866 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
868 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
869 uint32_t offset
= addr
& 0xFFF;
870 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
873 /* In a two pages ESB MMIO setting, trigger page should not be read */
874 if (xive_source_is_trigger_page(xsrc
, addr
)) {
875 qemu_log_mask(LOG_GUEST_ERROR
,
876 "XIVE: invalid load on IRQ %d trigger page at "
877 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
882 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
883 ret
= xive_source_esb_eoi(xsrc
, srcno
);
885 /* Forward the source event notification for routing */
887 xive_source_notify(xsrc
, srcno
);
891 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
892 ret
= xive_source_esb_get(xsrc
, srcno
);
895 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
896 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
897 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
898 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
899 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
902 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
911 * Trigger page Management/EOI page
913 * ESB MMIO setting 2 pages 1 or 2 pages
915 * 0x000 .. 0x3FF Trigger Trigger
916 * 0x400 .. 0x7FF Trigger EOI
917 * 0x800 .. 0xBFF Trigger undefined
918 * 0xC00 .. 0xCFF Trigger PQ=00
919 * 0xD00 .. 0xDFF Trigger PQ=01
920 * 0xE00 .. 0xDFF Trigger PQ=10
921 * 0xF00 .. 0xDFF Trigger PQ=11
923 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
924 uint64_t value
, unsigned size
)
926 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
927 uint32_t offset
= addr
& 0xFFF;
928 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
931 /* In a two pages ESB MMIO setting, trigger page only triggers */
932 if (xive_source_is_trigger_page(xsrc
, addr
)) {
933 notify
= xive_source_esb_trigger(xsrc
, srcno
);
939 notify
= xive_source_esb_trigger(xsrc
, srcno
);
942 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
943 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
944 qemu_log_mask(LOG_GUEST_ERROR
,
945 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
949 notify
= xive_source_esb_eoi(xsrc
, srcno
);
952 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
953 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
954 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
955 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
956 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
960 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
966 /* Forward the source event notification for routing */
968 xive_source_notify(xsrc
, srcno
);
972 static const MemoryRegionOps xive_source_esb_ops
= {
973 .read
= xive_source_esb_read
,
974 .write
= xive_source_esb_write
,
975 .endianness
= DEVICE_BIG_ENDIAN
,
977 .min_access_size
= 8,
978 .max_access_size
= 8,
981 .min_access_size
= 8,
982 .max_access_size
= 8,
986 void xive_source_set_irq(void *opaque
, int srcno
, int val
)
988 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
991 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
993 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
995 xsrc
->status
[srcno
] &= ~XIVE_STATUS_ASSERTED
;
999 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1003 /* Forward the source event notification for routing */
1005 xive_source_notify(xsrc
, srcno
);
1009 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
1013 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
1014 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
1016 if (pq
== XIVE_ESB_OFF
) {
1020 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
1021 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
1022 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1023 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1024 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ');
1028 static void xive_source_reset(void *dev
)
1030 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1032 /* Do not clear the LSI bitmap */
1034 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
1035 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
1038 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
1040 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1042 Error
*local_err
= NULL
;
1044 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1046 error_propagate(errp
, local_err
);
1047 error_prepend(errp
, "required link 'xive' not found: ");
1051 xsrc
->xive
= XIVE_NOTIFIER(obj
);
1053 if (!xsrc
->nr_irqs
) {
1054 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1058 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1059 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
1060 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
1061 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
1062 error_setg(errp
, "Invalid ESB shift setting");
1066 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
1067 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
1069 if (!kvm_irqchip_in_kernel()) {
1070 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1071 &xive_source_esb_ops
, xsrc
, "xive.esb",
1072 (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
);
1075 qemu_register_reset(xive_source_reset
, dev
);
1078 static const VMStateDescription vmstate_xive_source
= {
1079 .name
= TYPE_XIVE_SOURCE
,
1081 .minimum_version_id
= 1,
1082 .fields
= (VMStateField
[]) {
1083 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
1084 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
1085 VMSTATE_END_OF_LIST()
1090 * The default XIVE interrupt source setting for the ESB MMIOs is two
1091 * 64k pages without Store EOI, to be in sync with KVM.
1093 static Property xive_source_properties
[] = {
1094 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
1095 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
1096 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
1097 DEFINE_PROP_END_OF_LIST(),
1100 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
1102 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1104 dc
->desc
= "XIVE Interrupt Source";
1105 dc
->props
= xive_source_properties
;
1106 dc
->realize
= xive_source_realize
;
1107 dc
->vmsd
= &vmstate_xive_source
;
1110 static const TypeInfo xive_source_info
= {
1111 .name
= TYPE_XIVE_SOURCE
,
1112 .parent
= TYPE_DEVICE
,
1113 .instance_size
= sizeof(XiveSource
),
1114 .class_init
= xive_source_class_init
,
1121 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
1123 uint64_t qaddr_base
= xive_end_qaddr(end
);
1124 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1125 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1126 uint32_t qentries
= 1 << (qsize
+ 10);
1130 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1132 monitor_printf(mon
, " [ ");
1133 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
1134 for (i
= 0; i
< width
; i
++) {
1135 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1136 uint32_t qdata
= -1;
1138 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
1140 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
1141 HWADDR_PRIx
"\n", qaddr
);
1144 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
1145 be32_to_cpu(qdata
));
1146 qindex
= (qindex
+ 1) & (qentries
- 1);
1150 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
1152 uint64_t qaddr_base
= xive_end_qaddr(end
);
1153 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1154 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1155 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1156 uint32_t qentries
= 1 << (qsize
+ 10);
1158 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1159 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1161 if (!xive_end_is_valid(end
)) {
1165 monitor_printf(mon
, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64
1166 "% 6d/%5d ^%d", end_idx
,
1167 xive_end_is_valid(end
) ? 'v' : '-',
1168 xive_end_is_enqueue(end
) ? 'q' : '-',
1169 xive_end_is_notify(end
) ? 'n' : '-',
1170 xive_end_is_backlog(end
) ? 'b' : '-',
1171 xive_end_is_escalate(end
) ? 'e' : '-',
1172 priority
, nvt
, qaddr_base
, qindex
, qentries
, qgen
);
1174 xive_end_queue_pic_print_info(end
, 6, mon
);
1175 monitor_printf(mon
, "]\n");
1178 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
1180 uint64_t qaddr_base
= xive_end_qaddr(end
);
1181 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1182 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1183 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1185 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1186 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
1187 uint32_t qentries
= 1 << (qsize
+ 10);
1189 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
))) {
1190 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
1191 HWADDR_PRIx
"\n", qaddr
);
1195 qindex
= (qindex
+ 1) & (qentries
- 1);
1198 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
1200 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
1204 * XIVE Router (aka. Virtualization Controller or IVRE)
1207 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1210 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1212 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
1215 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1218 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1220 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
1223 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1224 XiveEND
*end
, uint8_t word_number
)
1226 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1228 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
1231 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1234 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1236 return xrc
->get_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
);
1239 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1240 XiveNVT
*nvt
, uint8_t word_number
)
1242 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1244 return xrc
->write_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
, word_number
);
1247 XiveTCTX
*xive_router_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
1249 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1251 return xrc
->get_tctx(xrtr
, cs
);
1255 * Encode the HW CAM line in the block group mode format :
1257 * chip << 19 | 0000000 0 0001 thread (7Bit)
1259 static uint32_t xive_tctx_hw_cam_line(XiveTCTX
*tctx
)
1261 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
1262 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
1264 return xive_nvt_cam_line((pir
>> 8) & 0xf, 1 << 7 | (pir
& 0x7f));
1268 * The thread context register words are in big-endian format.
1270 static int xive_presenter_tctx_match(XiveTCTX
*tctx
, uint8_t format
,
1271 uint8_t nvt_blk
, uint32_t nvt_idx
,
1272 bool cam_ignore
, uint32_t logic_serv
)
1274 uint32_t cam
= xive_nvt_cam_line(nvt_blk
, nvt_idx
);
1275 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
1276 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
1277 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
1278 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
1281 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1282 * identifier are ignored in the "CAM" match.
1286 if (cam_ignore
== true) {
1288 * F=0 & i=1: Logical server notification (bits ignored at
1289 * the end of the NVT identifier)
1291 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
1296 /* F=0 & i=0: Specific NVT notification */
1299 if ((be32_to_cpu(qw3w2
) & TM_QW3W2_VT
) &&
1300 cam
== xive_tctx_hw_cam_line(tctx
)) {
1301 return TM_QW3_HV_PHYS
;
1305 if ((be32_to_cpu(qw2w2
) & TM_QW2W2_VP
) &&
1306 cam
== xive_get_field32(TM_QW2W2_POOL_CAM
, qw2w2
)) {
1307 return TM_QW2_HV_POOL
;
1311 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1312 cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) {
1316 /* F=1 : User level Event-Based Branch (EBB) notification */
1319 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1320 (cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) &&
1321 (be32_to_cpu(qw0w2
) & TM_QW0W2_VU
) &&
1322 (logic_serv
== xive_get_field32(TM_QW0W2_LOGIC_SERV
, qw0w2
))) {
1329 typedef struct XiveTCTXMatch
{
1334 static bool xive_presenter_match(XiveRouter
*xrtr
, uint8_t format
,
1335 uint8_t nvt_blk
, uint32_t nvt_idx
,
1336 bool cam_ignore
, uint8_t priority
,
1337 uint32_t logic_serv
, XiveTCTXMatch
*match
)
1342 * TODO (PowerNV): handle chip_id overwrite of block field for
1343 * hardwired CAM compares
1347 XiveTCTX
*tctx
= xive_router_get_tctx(xrtr
, cs
);
1351 * HW checks that the CPU is enabled in the Physical Thread
1352 * Enable Register (PTER).
1356 * Check the thread context CAM lines and record matches. We
1357 * will handle CPU exception delivery later
1359 ring
= xive_presenter_tctx_match(tctx
, format
, nvt_blk
, nvt_idx
,
1360 cam_ignore
, logic_serv
);
1362 * Save the context and follow on to catch duplicates, that we
1363 * don't support yet.
1367 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a thread "
1368 "context NVT %x/%x\n", nvt_blk
, nvt_idx
);
1378 qemu_log_mask(LOG_UNIMP
, "XIVE: NVT %x/%x is not dispatched\n",
1387 * This is our simple Xive Presenter Engine model. It is merged in the
1388 * Router as it does not require an extra object.
1390 * It receives notification requests sent by the IVRE to find one
1391 * matching NVT (or more) dispatched on the processor threads. In case
1392 * of a single NVT notification, the process is abreviated and the
1393 * thread is signaled if a match is found. In case of a logical server
1394 * notification (bits ignored at the end of the NVT identifier), the
1395 * IVPE and IVRE select a winning thread using different filters. This
1396 * involves 2 or 3 exchanges on the PowerBus that the model does not
1399 * The parameters represent what is sent on the PowerBus
1401 static void xive_presenter_notify(XiveRouter
*xrtr
, uint8_t format
,
1402 uint8_t nvt_blk
, uint32_t nvt_idx
,
1403 bool cam_ignore
, uint8_t priority
,
1404 uint32_t logic_serv
)
1407 XiveTCTXMatch match
= { .tctx
= NULL
, .ring
= 0 };
1410 /* NVT cache lookup */
1411 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
1412 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVT %x/%x\n",
1417 if (!xive_nvt_is_valid(&nvt
)) {
1418 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is invalid\n",
1423 found
= xive_presenter_match(xrtr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1424 priority
, logic_serv
, &match
);
1426 ipb_update(&match
.tctx
->regs
[match
.ring
], priority
);
1427 xive_tctx_notify(match
.tctx
, match
.ring
);
1431 /* Record the IPB in the associated NVT structure */
1432 ipb_update((uint8_t *) &nvt
.w4
, priority
);
1433 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
1436 * If no matching NVT is dispatched on a HW thread :
1437 * - update the NVT structure if backlog is activated
1438 * - escalate (ESe PQ bits and EAS in w4-5) if escalation is
1444 * An END trigger can come from an event trigger (IPI or HW) or from
1445 * another chip. We don't model the PowerBus but the END trigger
1446 * message has the same parameters than in the function below.
1448 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1449 uint32_t end_idx
, uint32_t end_data
)
1455 /* END cache lookup */
1456 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
1457 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1462 if (!xive_end_is_valid(&end
)) {
1463 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1468 if (xive_end_is_enqueue(&end
)) {
1469 xive_end_enqueue(&end
, end_data
);
1470 /* Enqueuing event data modifies the EQ toggle and index */
1471 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1475 * The W7 format depends on the F bit in W6. It defines the type
1476 * of the notification :
1478 * F=0 : single or multiple NVT notification
1479 * F=1 : User level Event-Based Branch (EBB) notification, no
1482 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
1483 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
1485 /* The END is masked */
1486 if (format
== 0 && priority
== 0xff) {
1491 * Check the END ESn (Event State Buffer for notification) for
1492 * even futher coalescing in the Router
1494 if (!xive_end_is_notify(&end
)) {
1495 uint8_t pq
= xive_get_field32(END_W1_ESn
, end
.w1
);
1496 bool notify
= xive_esb_trigger(&pq
);
1498 if (pq
!= xive_get_field32(END_W1_ESn
, end
.w1
)) {
1499 end
.w1
= xive_set_field32(END_W1_ESn
, end
.w1
, pq
);
1500 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1503 /* ESn[Q]=1 : end of notification */
1510 * Follows IVPE notification
1512 xive_presenter_notify(xrtr
, format
,
1513 xive_get_field32(END_W6_NVT_BLOCK
, end
.w6
),
1514 xive_get_field32(END_W6_NVT_INDEX
, end
.w6
),
1515 xive_get_field32(END_W7_F0_IGNORE
, end
.w7
),
1517 xive_get_field32(END_W7_F1_LOG_SERVER_ID
, end
.w7
));
1519 /* TODO: Auto EOI. */
1522 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
)
1524 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
1525 uint8_t eas_blk
= XIVE_SRCNO_BLOCK(lisn
);
1526 uint32_t eas_idx
= XIVE_SRCNO_INDEX(lisn
);
1529 /* EAS cache lookup */
1530 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
1531 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
1536 * The IVRE checks the State Bit Cache at this point. We skip the
1537 * SBC lookup because the state bits of the sources are modeled
1538 * internally in QEMU.
1541 if (!xive_eas_is_valid(&eas
)) {
1542 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
1546 if (xive_eas_is_masked(&eas
)) {
1547 /* Notification completed */
1552 * The event trigger becomes an END trigger
1554 xive_router_end_notify(xrtr
,
1555 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
1556 xive_get_field64(EAS_END_INDEX
, eas
.w
),
1557 xive_get_field64(EAS_END_DATA
, eas
.w
));
1560 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
1562 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1563 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1565 dc
->desc
= "XIVE Router Engine";
1566 xnc
->notify
= xive_router_notify
;
1569 static const TypeInfo xive_router_info
= {
1570 .name
= TYPE_XIVE_ROUTER
,
1571 .parent
= TYPE_SYS_BUS_DEVICE
,
1573 .class_size
= sizeof(XiveRouterClass
),
1574 .class_init
= xive_router_class_init
,
1575 .interfaces
= (InterfaceInfo
[]) {
1576 { TYPE_XIVE_NOTIFIER
},
1581 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
1583 if (!xive_eas_is_valid(eas
)) {
1587 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
1588 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
1589 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1590 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1591 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1595 * END ESB MMIO loads
1597 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
1599 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
1600 uint32_t offset
= addr
& 0xFFF;
1604 uint32_t end_esmask
;
1608 end_blk
= xsrc
->block_id
;
1609 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
1611 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
1612 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1617 if (!xive_end_is_valid(&end
)) {
1618 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1623 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
1624 pq
= xive_get_field32(end_esmask
, end
.w1
);
1627 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1628 ret
= xive_esb_eoi(&pq
);
1630 /* Forward the source event notification for routing ?? */
1633 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1637 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1638 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1639 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1640 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1641 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
1644 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
1649 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
1650 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
1651 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
1658 * END ESB MMIO stores are invalid
1660 static void xive_end_source_write(void *opaque
, hwaddr addr
,
1661 uint64_t value
, unsigned size
)
1663 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
1664 HWADDR_PRIx
"\n", addr
);
1667 static const MemoryRegionOps xive_end_source_ops
= {
1668 .read
= xive_end_source_read
,
1669 .write
= xive_end_source_write
,
1670 .endianness
= DEVICE_BIG_ENDIAN
,
1672 .min_access_size
= 8,
1673 .max_access_size
= 8,
1676 .min_access_size
= 8,
1677 .max_access_size
= 8,
1681 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
1683 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
1685 Error
*local_err
= NULL
;
1687 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1689 error_propagate(errp
, local_err
);
1690 error_prepend(errp
, "required link 'xive' not found: ");
1694 xsrc
->xrtr
= XIVE_ROUTER(obj
);
1696 if (!xsrc
->nr_ends
) {
1697 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1701 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1702 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
1703 error_setg(errp
, "Invalid ESB shift setting");
1708 * Each END is assigned an even/odd pair of MMIO pages, the even page
1709 * manages the ESn field while the odd page manages the ESe field.
1711 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1712 &xive_end_source_ops
, xsrc
, "xive.end",
1713 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
1716 static Property xive_end_source_properties
[] = {
1717 DEFINE_PROP_UINT8("block-id", XiveENDSource
, block_id
, 0),
1718 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
1719 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
1720 DEFINE_PROP_END_OF_LIST(),
1723 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
1725 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1727 dc
->desc
= "XIVE END Source";
1728 dc
->props
= xive_end_source_properties
;
1729 dc
->realize
= xive_end_source_realize
;
1732 static const TypeInfo xive_end_source_info
= {
1733 .name
= TYPE_XIVE_END_SOURCE
,
1734 .parent
= TYPE_DEVICE
,
1735 .instance_size
= sizeof(XiveENDSource
),
1736 .class_init
= xive_end_source_class_init
,
1742 static const TypeInfo xive_notifier_info
= {
1743 .name
= TYPE_XIVE_NOTIFIER
,
1744 .parent
= TYPE_INTERFACE
,
1745 .class_size
= sizeof(XiveNotifierClass
),
1748 static void xive_register_types(void)
1750 type_register_static(&xive_source_info
);
1751 type_register_static(&xive_notifier_info
);
1752 type_register_static(&xive_router_info
);
1753 type_register_static(&xive_end_source_info
);
1754 type_register_static(&xive_tctx_info
);
1757 type_init(xive_register_types
)