2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "kvm-consts.h"
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
29 # define ELF_MACHINE EM_AARCH64
31 # define TARGET_LONG_BITS 32
32 # define ELF_MACHINE EM_ARM
35 #define CPUArchState struct CPUARMState
37 #include "qemu-common.h"
38 #include "exec/cpu-defs.h"
40 #include "fpu/softfloat.h"
42 #define TARGET_HAS_ICE 1
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
55 #define ARMV7M_EXCP_RESET 1
56 #define ARMV7M_EXCP_NMI 2
57 #define ARMV7M_EXCP_HARD 3
58 #define ARMV7M_EXCP_MEM 4
59 #define ARMV7M_EXCP_BUS 5
60 #define ARMV7M_EXCP_USAGE 6
61 #define ARMV7M_EXCP_SVC 11
62 #define ARMV7M_EXCP_DEBUG 12
63 #define ARMV7M_EXCP_PENDSV 14
64 #define ARMV7M_EXCP_SYSTICK 15
66 /* ARM-specific interrupt pending bits. */
67 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
69 /* The usual mapping for an AArch64 system register to its AArch32
70 * counterpart is for the 32 bit world to have access to the lower
71 * half only (with writes leaving the upper half untouched). It's
72 * therefore useful to be able to pass TCG the offset of the least
73 * significant half of a uint64_t struct member.
75 #ifdef HOST_WORDS_BIGENDIAN
76 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
77 #define offsetofhigh32(S, M) offsetof(S, M)
79 #define offsetoflow32(S, M) offsetof(S, M)
80 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
83 /* Meanings of the ARMCPU object's two inbound GPIO lines */
87 typedef void ARMWriteCPFunc(void *opaque
, int cp_info
,
88 int srcreg
, int operand
, uint32_t value
);
89 typedef uint32_t ARMReadCPFunc(void *opaque
, int cp_info
,
90 int dstreg
, int operand
);
94 #define NB_MMU_MODES 2
96 /* We currently assume float and double are IEEE single and double
97 precision respectively.
98 Doing runtime conversions is tricky because VFP registers may contain
99 integer values (eg. as the result of a FTOSI instruction).
100 s<2n> maps to the least significant half of d<n>
101 s<2n+1> maps to the most significant half of d<n>
104 /* CPU state for each instance of a generic timer (in cp15 c14) */
105 typedef struct ARMGenericTimer
{
106 uint64_t cval
; /* Timer CompareValue register */
107 uint64_t ctl
; /* Timer Control register */
110 #define GTIMER_PHYS 0
111 #define GTIMER_VIRT 1
112 #define NUM_GTIMERS 2
114 typedef struct CPUARMState
{
115 /* Regs for current mode. */
118 /* 32/64 switch only happens when taking and returning from
119 * exceptions so the overlap semantics are taken care of then
120 * instead of having a complicated union.
122 /* Regs for A64 mode. */
125 /* PSTATE isn't an architectural register for ARMv8. However, it is
126 * convenient for us to assemble the underlying state into a 32 bit format
127 * identical to the architectural format used for the SPSR. (This is also
128 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
129 * 'pstate' register are.) Of the PSTATE bits:
130 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
131 * semantics as for AArch32, as described in the comments on each field)
132 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
133 * DAIF (exception masks) are kept in env->daif
134 * all other bits are stored in their correct places in env->pstate
137 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
139 /* Frequently accessed CPSR bits are stored separately for efficiency.
140 This contains all the other bits. Use cpsr_{read,write} to access
142 uint32_t uncached_cpsr
;
145 /* Banked registers. */
146 uint64_t banked_spsr
[8];
147 uint32_t banked_r13
[6];
148 uint32_t banked_r14
[6];
150 /* These hold r8-r12. */
151 uint32_t usr_regs
[5];
152 uint32_t fiq_regs
[5];
154 /* cpsr flag cache for faster execution */
155 uint32_t CF
; /* 0 or 1 */
156 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
157 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
158 uint32_t ZF
; /* Z set if zero. */
159 uint32_t QF
; /* 0 or 1 */
160 uint32_t GE
; /* cpsr[19:16] */
161 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
162 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
163 uint64_t daif
; /* exception masks, in the bits they are in in PSTATE */
165 uint64_t elr_el
[4]; /* AArch64 exception link regs */
166 uint64_t sp_el
[4]; /* AArch64 banked stack pointers */
168 /* System control coprocessor (cp15) */
171 uint64_t c0_cssel
; /* Cache size selection. */
172 uint64_t c1_sys
; /* System control register. */
173 uint64_t c1_coproc
; /* Coprocessor access register. */
174 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
175 uint64_t ttbr0_el1
; /* MMU translation table base 0. */
176 uint64_t ttbr1_el1
; /* MMU translation table base 1. */
177 uint64_t c2_control
; /* MMU translation table base control. */
178 uint32_t c2_mask
; /* MMU translation table base selection mask. */
179 uint32_t c2_base_mask
; /* MMU translation table base 0 mask. */
180 uint32_t c2_data
; /* MPU data cachable bits. */
181 uint32_t c2_insn
; /* MPU instruction cachable bits. */
182 uint32_t c3
; /* MMU domain access control register
183 MPU write buffer control. */
184 uint32_t pmsav5_data_ap
; /* PMSAv5 MPU data access permissions */
185 uint32_t pmsav5_insn_ap
; /* PMSAv5 MPU insn access permissions */
186 uint64_t hcr_el2
; /* Hypervisor configuration register */
187 uint64_t scr_el3
; /* Secure configuration register. */
188 uint32_t ifsr_el2
; /* Fault status registers. */
190 uint32_t c6_region
[8]; /* MPU base/size registers. */
191 uint64_t far_el
[4]; /* Fault address registers. */
192 uint64_t par_el1
; /* Translation result. */
193 uint32_t c9_insn
; /* Cache lockdown registers. */
195 uint64_t c9_pmcr
; /* performance monitor control register */
196 uint64_t c9_pmcnten
; /* perf monitor counter enables */
197 uint32_t c9_pmovsr
; /* perf monitor overflow status */
198 uint32_t c9_pmxevtyper
; /* perf monitor event type */
199 uint32_t c9_pmuserenr
; /* perf monitor user enable */
200 uint32_t c9_pminten
; /* perf monitor interrupt enables */
202 uint64_t vbar_el
[4]; /* vector base address register */
203 uint32_t c13_fcse
; /* FCSE PID. */
204 uint64_t contextidr_el1
; /* Context ID. */
205 uint64_t tpidr_el0
; /* User RW Thread register. */
206 uint64_t tpidrro_el0
; /* User RO Thread register. */
207 uint64_t tpidr_el1
; /* Privileged Thread register. */
208 uint64_t c14_cntfrq
; /* Counter Frequency register */
209 uint64_t c14_cntkctl
; /* Timer Control register */
210 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
211 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
212 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
213 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
214 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
215 uint32_t c15_threadid
; /* TI debugger thread-ID. */
216 uint32_t c15_config_base_address
; /* SCU base address. */
217 uint32_t c15_diagnostic
; /* diagnostic register */
218 uint32_t c15_power_diagnostic
;
219 uint32_t c15_power_control
; /* power control */
220 uint64_t dbgbvr
[16]; /* breakpoint value registers */
221 uint64_t dbgbcr
[16]; /* breakpoint control registers */
222 uint64_t dbgwvr
[16]; /* watchpoint value registers */
223 uint64_t dbgwcr
[16]; /* watchpoint control registers */
225 /* If the counter is enabled, this stores the last time the counter
226 * was reset. Otherwise it stores the counter value
229 uint64_t pmccfiltr_el0
; /* Performance Monitor Filter Register */
239 int pending_exception
;
242 /* Information associated with an exception about to be taken:
243 * code which raises an exception must set cs->exception_index and
244 * the relevant parts of this structure; the cpu_do_interrupt function
245 * will then set the guest-visible registers as part of the exception
249 uint32_t syndrome
; /* AArch64 format syndrome register */
250 uint32_t fsr
; /* AArch32 format fault status register info */
251 uint64_t vaddress
; /* virtual addr associated with exception, if any */
252 /* If we implement EL2 we will also need to store information
253 * about the intermediate physical address for stage 2 faults.
257 /* Thumb-2 EE state. */
261 /* VFP coprocessor state. */
263 /* VFP/Neon register state. Note that the mapping between S, D and Q
264 * views of the register bank differs between AArch64 and AArch32:
266 * Qn = regs[2n+1]:regs[2n]
268 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
269 * (and regs[32] to regs[63] are inaccessible)
271 * Qn = regs[2n+1]:regs[2n]
273 * Sn = regs[2n] bits 31..0
274 * This corresponds to the architecturally defined mapping between
275 * the two execution states, and means we do not need to explicitly
276 * map these registers when changing states.
281 /* We store these fpcsr fields separately for convenience. */
285 /* scratch space when Tn are not sufficient. */
288 /* fp_status is the "normal" fp status. standard_fp_status retains
289 * values corresponding to the ARM "Standard FPSCR Value", ie
290 * default-NaN, flush-to-zero, round-to-nearest and is used by
291 * any operations (generally Neon) which the architecture defines
292 * as controlled by the standard FPSCR value rather than the FPSCR.
294 * To avoid having to transfer exception bits around, we simply
295 * say that the FPSCR cumulative exception flags are the logical
296 * OR of the flags in the two fp statuses. This relies on the
297 * only thing which needs to read the exception flags being
298 * an explicit FPSCR read.
300 float_status fp_status
;
301 float_status standard_fp_status
;
303 uint64_t exclusive_addr
;
304 uint64_t exclusive_val
;
305 uint64_t exclusive_high
;
306 #if defined(CONFIG_USER_ONLY)
307 uint64_t exclusive_test
;
308 uint32_t exclusive_info
;
311 /* iwMMXt coprocessor state. */
319 /* For mixed endian mode. */
322 #if defined(CONFIG_USER_ONLY)
323 /* For usermode syscall translation. */
327 struct CPUBreakpoint
*cpu_breakpoint
[16];
328 struct CPUWatchpoint
*cpu_watchpoint
[16];
332 /* These fields after the common ones so they are preserved on reset. */
334 /* Internal CPU feature flags. */
338 const struct arm_boot_info
*boot_info
;
343 ARMCPU
*cpu_arm_init(const char *cpu_model
);
344 int cpu_arm_exec(CPUARMState
*s
);
345 uint32_t do_arm_semihosting(CPUARMState
*env
);
347 static inline bool is_a64(CPUARMState
*env
)
352 /* you can call this signal handler from your SIGBUS and SIGSEGV
353 signal handlers to inform the virtual CPU of exceptions. non zero
354 is returned if the signal was handled by the virtual CPU. */
355 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
357 int arm_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
364 * Synchronises the counter in the PMCCNTR. This must always be called twice,
365 * once before any action that might affect the timer and again afterwards.
366 * The function is used to swap the state of the register if required.
367 * This only happens when not in user mode (!CONFIG_USER_ONLY)
369 void pmccntr_sync(CPUARMState
*env
);
371 /* SCTLR bit meanings. Several bits have been reused in newer
372 * versions of the architecture; in that case we define constants
373 * for both old and new bit meanings. Code which tests against those
374 * bits should probably check or otherwise arrange that the CPU
375 * is the architectural version it expects.
377 #define SCTLR_M (1U << 0)
378 #define SCTLR_A (1U << 1)
379 #define SCTLR_C (1U << 2)
380 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
381 #define SCTLR_SA (1U << 3)
382 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
383 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
384 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
385 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
386 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
387 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
388 #define SCTLR_ITD (1U << 7) /* v8 onward */
389 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
390 #define SCTLR_SED (1U << 8) /* v8 onward */
391 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
392 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
393 #define SCTLR_F (1U << 10) /* up to v6 */
394 #define SCTLR_SW (1U << 10) /* v7 onward */
395 #define SCTLR_Z (1U << 11)
396 #define SCTLR_I (1U << 12)
397 #define SCTLR_V (1U << 13)
398 #define SCTLR_RR (1U << 14) /* up to v7 */
399 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
400 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
401 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
402 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
403 #define SCTLR_nTWI (1U << 16) /* v8 onward */
404 #define SCTLR_HA (1U << 17)
405 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
406 #define SCTLR_nTWE (1U << 18) /* v8 onward */
407 #define SCTLR_WXN (1U << 19)
408 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
409 #define SCTLR_UWXN (1U << 20) /* v7 onward */
410 #define SCTLR_FI (1U << 21)
411 #define SCTLR_U (1U << 22)
412 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
413 #define SCTLR_VE (1U << 24) /* up to v7 */
414 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
415 #define SCTLR_EE (1U << 25)
416 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
417 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
418 #define SCTLR_NMFI (1U << 27)
419 #define SCTLR_TRE (1U << 28)
420 #define SCTLR_AFE (1U << 29)
421 #define SCTLR_TE (1U << 30)
423 #define CPSR_M (0x1fU)
424 #define CPSR_T (1U << 5)
425 #define CPSR_F (1U << 6)
426 #define CPSR_I (1U << 7)
427 #define CPSR_A (1U << 8)
428 #define CPSR_E (1U << 9)
429 #define CPSR_IT_2_7 (0xfc00U)
430 #define CPSR_GE (0xfU << 16)
431 #define CPSR_IL (1U << 20)
432 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
433 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
434 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
435 * where it is live state but not accessible to the AArch32 code.
437 #define CPSR_RESERVED (0x7U << 21)
438 #define CPSR_J (1U << 24)
439 #define CPSR_IT_0_1 (3U << 25)
440 #define CPSR_Q (1U << 27)
441 #define CPSR_V (1U << 28)
442 #define CPSR_C (1U << 29)
443 #define CPSR_Z (1U << 30)
444 #define CPSR_N (1U << 31)
445 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
446 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
448 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
449 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
451 /* Bits writable in user mode. */
452 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
453 /* Execution state bits. MRS read as zero, MSR writes ignored. */
454 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
455 /* Mask of bits which may be set by exception return copying them from SPSR */
456 #define CPSR_ERET_MASK (~CPSR_RESERVED)
458 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
459 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
460 #define TTBCR_PD0 (1U << 4)
461 #define TTBCR_PD1 (1U << 5)
462 #define TTBCR_EPD0 (1U << 7)
463 #define TTBCR_IRGN0 (3U << 8)
464 #define TTBCR_ORGN0 (3U << 10)
465 #define TTBCR_SH0 (3U << 12)
466 #define TTBCR_T1SZ (3U << 16)
467 #define TTBCR_A1 (1U << 22)
468 #define TTBCR_EPD1 (1U << 23)
469 #define TTBCR_IRGN1 (3U << 24)
470 #define TTBCR_ORGN1 (3U << 26)
471 #define TTBCR_SH1 (1U << 28)
472 #define TTBCR_EAE (1U << 31)
474 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
475 * Only these are valid when in AArch64 mode; in
476 * AArch32 mode SPSRs are basically CPSR-format.
478 #define PSTATE_SP (1U)
479 #define PSTATE_M (0xFU)
480 #define PSTATE_nRW (1U << 4)
481 #define PSTATE_F (1U << 6)
482 #define PSTATE_I (1U << 7)
483 #define PSTATE_A (1U << 8)
484 #define PSTATE_D (1U << 9)
485 #define PSTATE_IL (1U << 20)
486 #define PSTATE_SS (1U << 21)
487 #define PSTATE_V (1U << 28)
488 #define PSTATE_C (1U << 29)
489 #define PSTATE_Z (1U << 30)
490 #define PSTATE_N (1U << 31)
491 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
492 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
493 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
494 /* Mode values for AArch64 */
495 #define PSTATE_MODE_EL3h 13
496 #define PSTATE_MODE_EL3t 12
497 #define PSTATE_MODE_EL2h 9
498 #define PSTATE_MODE_EL2t 8
499 #define PSTATE_MODE_EL1h 5
500 #define PSTATE_MODE_EL1t 4
501 #define PSTATE_MODE_EL0t 0
503 /* Map EL and handler into a PSTATE_MODE. */
504 static inline unsigned int aarch64_pstate_mode(unsigned int el
, bool handler
)
506 return (el
<< 2) | handler
;
509 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
510 * interprocessing, so we don't attempt to sync with the cpsr state used by
511 * the 32 bit decoder.
513 static inline uint32_t pstate_read(CPUARMState
*env
)
518 return (env
->NF
& 0x80000000) | (ZF
<< 30)
519 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
520 | env
->pstate
| env
->daif
;
523 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
525 env
->ZF
= (~val
) & PSTATE_Z
;
527 env
->CF
= (val
>> 29) & 1;
528 env
->VF
= (val
<< 3) & 0x80000000;
529 env
->daif
= val
& PSTATE_DAIF
;
530 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
533 /* Return the current CPSR value. */
534 uint32_t cpsr_read(CPUARMState
*env
);
535 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
536 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
);
538 /* Return the current xPSR value. */
539 static inline uint32_t xpsr_read(CPUARMState
*env
)
543 return (env
->NF
& 0x80000000) | (ZF
<< 30)
544 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
545 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
546 | ((env
->condexec_bits
& 0xfc) << 8)
547 | env
->v7m
.exception
;
550 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
551 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
553 if (mask
& CPSR_NZCV
) {
554 env
->ZF
= (~val
) & CPSR_Z
;
556 env
->CF
= (val
>> 29) & 1;
557 env
->VF
= (val
<< 3) & 0x80000000;
560 env
->QF
= ((val
& CPSR_Q
) != 0);
561 if (mask
& (1 << 24))
562 env
->thumb
= ((val
& (1 << 24)) != 0);
563 if (mask
& CPSR_IT_0_1
) {
564 env
->condexec_bits
&= ~3;
565 env
->condexec_bits
|= (val
>> 25) & 3;
567 if (mask
& CPSR_IT_2_7
) {
568 env
->condexec_bits
&= 3;
569 env
->condexec_bits
|= (val
>> 8) & 0xfc;
572 env
->v7m
.exception
= val
& 0x1ff;
576 #define HCR_VM (1ULL << 0)
577 #define HCR_SWIO (1ULL << 1)
578 #define HCR_PTW (1ULL << 2)
579 #define HCR_FMO (1ULL << 3)
580 #define HCR_IMO (1ULL << 4)
581 #define HCR_AMO (1ULL << 5)
582 #define HCR_VF (1ULL << 6)
583 #define HCR_VI (1ULL << 7)
584 #define HCR_VSE (1ULL << 8)
585 #define HCR_FB (1ULL << 9)
586 #define HCR_BSU_MASK (3ULL << 10)
587 #define HCR_DC (1ULL << 12)
588 #define HCR_TWI (1ULL << 13)
589 #define HCR_TWE (1ULL << 14)
590 #define HCR_TID0 (1ULL << 15)
591 #define HCR_TID1 (1ULL << 16)
592 #define HCR_TID2 (1ULL << 17)
593 #define HCR_TID3 (1ULL << 18)
594 #define HCR_TSC (1ULL << 19)
595 #define HCR_TIDCP (1ULL << 20)
596 #define HCR_TACR (1ULL << 21)
597 #define HCR_TSW (1ULL << 22)
598 #define HCR_TPC (1ULL << 23)
599 #define HCR_TPU (1ULL << 24)
600 #define HCR_TTLB (1ULL << 25)
601 #define HCR_TVM (1ULL << 26)
602 #define HCR_TGE (1ULL << 27)
603 #define HCR_TDZ (1ULL << 28)
604 #define HCR_HCD (1ULL << 29)
605 #define HCR_TRVM (1ULL << 30)
606 #define HCR_RW (1ULL << 31)
607 #define HCR_CD (1ULL << 32)
608 #define HCR_ID (1ULL << 33)
609 #define HCR_MASK ((1ULL << 34) - 1)
611 #define SCR_NS (1U << 0)
612 #define SCR_IRQ (1U << 1)
613 #define SCR_FIQ (1U << 2)
614 #define SCR_EA (1U << 3)
615 #define SCR_FW (1U << 4)
616 #define SCR_AW (1U << 5)
617 #define SCR_NET (1U << 6)
618 #define SCR_SMD (1U << 7)
619 #define SCR_HCE (1U << 8)
620 #define SCR_SIF (1U << 9)
621 #define SCR_RW (1U << 10)
622 #define SCR_ST (1U << 11)
623 #define SCR_TWI (1U << 12)
624 #define SCR_TWE (1U << 13)
625 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
626 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
628 /* Return the current FPSCR value. */
629 uint32_t vfp_get_fpscr(CPUARMState
*env
);
630 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
632 /* For A64 the FPSCR is split into two logically distinct registers,
633 * FPCR and FPSR. However since they still use non-overlapping bits
634 * we store the underlying state in fpscr and just mask on read/write.
636 #define FPSR_MASK 0xf800009f
637 #define FPCR_MASK 0x07f79f00
638 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
640 return vfp_get_fpscr(env
) & FPSR_MASK
;
643 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
645 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
646 vfp_set_fpscr(env
, new_fpscr
);
649 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
651 return vfp_get_fpscr(env
) & FPCR_MASK
;
654 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
656 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
657 vfp_set_fpscr(env
, new_fpscr
);
661 ARM_CPU_MODE_USR
= 0x10,
662 ARM_CPU_MODE_FIQ
= 0x11,
663 ARM_CPU_MODE_IRQ
= 0x12,
664 ARM_CPU_MODE_SVC
= 0x13,
665 ARM_CPU_MODE_MON
= 0x16,
666 ARM_CPU_MODE_ABT
= 0x17,
667 ARM_CPU_MODE_HYP
= 0x1a,
668 ARM_CPU_MODE_UND
= 0x1b,
669 ARM_CPU_MODE_SYS
= 0x1f
672 /* VFP system registers. */
673 #define ARM_VFP_FPSID 0
674 #define ARM_VFP_FPSCR 1
675 #define ARM_VFP_MVFR2 5
676 #define ARM_VFP_MVFR1 6
677 #define ARM_VFP_MVFR0 7
678 #define ARM_VFP_FPEXC 8
679 #define ARM_VFP_FPINST 9
680 #define ARM_VFP_FPINST2 10
682 /* iwMMXt coprocessor control registers. */
683 #define ARM_IWMMXT_wCID 0
684 #define ARM_IWMMXT_wCon 1
685 #define ARM_IWMMXT_wCSSF 2
686 #define ARM_IWMMXT_wCASF 3
687 #define ARM_IWMMXT_wCGR0 8
688 #define ARM_IWMMXT_wCGR1 9
689 #define ARM_IWMMXT_wCGR2 10
690 #define ARM_IWMMXT_wCGR3 11
692 /* If adding a feature bit which corresponds to a Linux ELF
693 * HWCAP bit, remember to update the feature-bit-to-hwcap
694 * mapping in linux-user/elfload.c:get_elf_hwcap().
698 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
699 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
700 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
705 ARM_FEATURE_MPU
, /* Only has Memory Protection Unit, not full MMU. */
707 ARM_FEATURE_VFP_FP16
,
709 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
710 ARM_FEATURE_M
, /* Microcontroller profile. */
711 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
712 ARM_FEATURE_THUMB2EE
,
713 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
716 ARM_FEATURE_STRONGARM
,
717 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
718 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
719 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
720 ARM_FEATURE_GENERIC_TIMER
,
721 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
722 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
723 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
724 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
725 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
726 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
727 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
728 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
730 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
731 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
732 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
733 ARM_FEATURE_CRC
, /* ARMv8 CRC instructions */
734 ARM_FEATURE_CBAR_RO
, /* has cp15 CBAR and it is read-only */
735 ARM_FEATURE_EL2
, /* has EL2 Virtualization support */
736 ARM_FEATURE_EL3
, /* has EL3 Secure monitor support */
737 ARM_FEATURE_V8_SHA1
, /* implements SHA1 part of v8 Crypto Extensions */
738 ARM_FEATURE_V8_SHA256
, /* implements SHA256 part of v8 Crypto Extensions */
739 ARM_FEATURE_V8_PMULL
, /* implements PMULL part of v8 Crypto Extensions */
742 static inline int arm_feature(CPUARMState
*env
, int feature
)
744 return (env
->features
& (1ULL << feature
)) != 0;
747 /* Return true if the specified exception level is running in AArch64 state. */
748 static inline bool arm_el_is_aa64(CPUARMState
*env
, int el
)
750 /* We don't currently support EL2 or EL3, and this isn't valid for EL0
751 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
752 * then the state of EL0 isn't well defined.)
755 /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
756 * is a QEMU-imposed simplification which we may wish to change later.
757 * If we in future support EL2 and/or EL3, then the state of lower
758 * exception levels is controlled by the HCR.RW and SCR.RW bits.
760 return arm_feature(env
, ARM_FEATURE_AARCH64
);
763 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
764 unsigned int arm_excp_target_el(CPUState
*cs
, unsigned int excp_idx
);
766 /* Interface between CPU and Interrupt controller. */
767 void armv7m_nvic_set_pending(void *opaque
, int irq
);
768 int armv7m_nvic_acknowledge_irq(void *opaque
);
769 void armv7m_nvic_complete_irq(void *opaque
, int irq
);
771 /* Interface for defining coprocessor registers.
772 * Registers are defined in tables of arm_cp_reginfo structs
773 * which are passed to define_arm_cp_regs().
776 /* When looking up a coprocessor register we look for it
777 * via an integer which encodes all of:
779 * Crn, Crm, opc1, opc2 fields
780 * 32 or 64 bit register (ie is it accessed via MRC/MCR
782 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
783 * (In this case crn and opc2 should be zero.)
784 * For AArch64, there is no 32/64 bit size distinction;
785 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
786 * and 4 bit CRn and CRm. The encoding patterns are chosen
787 * to be easy to convert to and from the KVM encodings, and also
788 * so that the hashtable can contain both AArch32 and AArch64
789 * registers (to allow for interprocessing where we might run
790 * 32 bit code on a 64 bit core).
792 /* This bit is private to our hashtable cpreg; in KVM register
793 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
794 * in the upper bits of the 64 bit ID.
796 #define CP_REG_AA64_SHIFT 28
797 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
799 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \
800 (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \
801 ((crm) << 7) | ((opc1) << 3) | (opc2))
803 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
804 (CP_REG_AA64_MASK | \
805 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
806 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
807 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
808 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
809 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
810 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
812 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
813 * version used as a key for the coprocessor register hashtable
815 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
817 uint32_t cpregid
= kvmid
;
818 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
819 cpregid
|= CP_REG_AA64_MASK
;
820 } else if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
821 cpregid
|= (1 << 15);
826 /* Convert a truncated 32 bit hashtable key into the full
827 * 64 bit KVM register ID.
829 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
833 if (cpregid
& CP_REG_AA64_MASK
) {
834 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
835 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
837 kvmid
= cpregid
& ~(1 << 15);
838 if (cpregid
& (1 << 15)) {
839 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
841 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
847 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
848 * special-behaviour cp reg and bits [15..8] indicate what behaviour
849 * it has. Otherwise it is a simple cp reg, where CONST indicates that
850 * TCG can assume the value to be constant (ie load at translate time)
851 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
852 * indicates that the TB should not be ended after a write to this register
853 * (the default is that the TB ends after cp writes). OVERRIDE permits
854 * a register definition to override a previous definition for the
855 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
856 * old must have the OVERRIDE bit set.
857 * NO_MIGRATE indicates that this register should be ignored for migration;
858 * (eg because any state is accessed via some other coprocessor register).
859 * IO indicates that this register does I/O and therefore its accesses
860 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
861 * registers which implement clocks or timers require this.
863 #define ARM_CP_SPECIAL 1
864 #define ARM_CP_CONST 2
865 #define ARM_CP_64BIT 4
866 #define ARM_CP_SUPPRESS_TB_END 8
867 #define ARM_CP_OVERRIDE 16
868 #define ARM_CP_NO_MIGRATE 32
870 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
871 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
872 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
873 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
874 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
875 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
876 /* Used only as a terminator for ARMCPRegInfo lists */
877 #define ARM_CP_SENTINEL 0xffff
878 /* Mask of only the flag bits in a type field */
879 #define ARM_CP_FLAG_MASK 0x7f
881 /* Valid values for ARMCPRegInfo state field, indicating which of
882 * the AArch32 and AArch64 execution states this register is visible in.
883 * If the reginfo doesn't explicitly specify then it is AArch32 only.
884 * If the reginfo is declared to be visible in both states then a second
885 * reginfo is synthesised for the AArch32 view of the AArch64 register,
886 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
887 * Note that we rely on the values of these enums as we iterate through
888 * the various states in some places.
891 ARM_CP_STATE_AA32
= 0,
892 ARM_CP_STATE_AA64
= 1,
893 ARM_CP_STATE_BOTH
= 2,
896 /* Return true if cptype is a valid type field. This is used to try to
897 * catch errors where the sentinel has been accidentally left off the end
898 * of a list of registers.
900 static inline bool cptype_valid(int cptype
)
902 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
903 || ((cptype
& ARM_CP_SPECIAL
) &&
904 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
908 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
909 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
910 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
911 * (ie any of the privileged modes in Secure state, or Monitor mode).
912 * If a register is accessible in one privilege level it's always accessible
913 * in higher privilege levels too. Since "Secure PL1" also follows this rule
914 * (ie anything visible in PL2 is visible in S-PL1, some things are only
915 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
916 * terminology a little and call this PL3.
917 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
918 * with the ELx exception levels.
920 * If access permissions for a register are more complex than can be
921 * described with these bits, then use a laxer set of restrictions, and
922 * do the more restrictive/complex check inside a helper function.
926 #define PL2_R (0x20 | PL3_R)
927 #define PL2_W (0x10 | PL3_W)
928 #define PL1_R (0x08 | PL2_R)
929 #define PL1_W (0x04 | PL2_W)
930 #define PL0_R (0x02 | PL1_R)
931 #define PL0_W (0x01 | PL1_W)
933 #define PL3_RW (PL3_R | PL3_W)
934 #define PL2_RW (PL2_R | PL2_W)
935 #define PL1_RW (PL1_R | PL1_W)
936 #define PL0_RW (PL0_R | PL0_W)
938 static inline int arm_current_pl(CPUARMState
*env
)
941 return extract32(env
->pstate
, 2, 2);
944 if ((env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_USR
) {
947 /* We don't currently implement the Virtualization or TrustZone
948 * extensions, so PL2 and PL3 don't exist for us.
953 typedef struct ARMCPRegInfo ARMCPRegInfo
;
955 typedef enum CPAccessResult
{
956 /* Access is permitted */
958 /* Access fails due to a configurable trap or enable which would
959 * result in a categorized exception syndrome giving information about
960 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
964 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
965 * Note that this is not a catch-all case -- the set of cases which may
966 * result in this failure is specifically defined by the architecture.
968 CP_ACCESS_TRAP_UNCATEGORIZED
= 2,
971 /* Access functions for coprocessor registers. These cannot fail and
972 * may not raise exceptions.
974 typedef uint64_t CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
975 typedef void CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
977 /* Access permission check functions for coprocessor registers. */
978 typedef CPAccessResult
CPAccessFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
979 /* Hook function for register reset */
980 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
984 /* Definition of an ARM coprocessor register */
985 struct ARMCPRegInfo
{
986 /* Name of register (useful mainly for debugging, need not be unique) */
988 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
989 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
990 * 'wildcard' field -- any value of that field in the MRC/MCR insn
991 * will be decoded to this register. The register read and write
992 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
993 * used by the program, so it is possible to register a wildcard and
994 * then behave differently on read/write if necessary.
995 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
997 * For AArch64-visible registers, opc0 is also used.
998 * Since there are no "coprocessors" in AArch64, cp is purely used as a
999 * way to distinguish (for KVM's benefit) guest-visible system registers
1000 * from demuxed ones provided to preserve the "no side effects on
1001 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1002 * visible (to match KVM's encoding); cp==0 will be converted to
1003 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1011 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1013 /* Register type: ARM_CP_* bits/values */
1015 /* Access rights: PL*_[RW] */
1017 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1018 * this register was defined: can be used to hand data through to the
1019 * register read/write functions, since they are passed the ARMCPRegInfo*.
1022 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1023 * fieldoffset is non-zero, the reset value of the register.
1025 uint64_t resetvalue
;
1026 /* Offset of the field in CPUARMState for this register. This is not
1028 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1029 * 2. both readfn and writefn are specified
1031 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
1032 /* Function for making any access checks for this register in addition to
1033 * those specified by the 'access' permissions bits. If NULL, no extra
1034 * checks required. The access check is performed at runtime, not at
1037 CPAccessFn
*accessfn
;
1038 /* Function for handling reads of this register. If NULL, then reads
1039 * will be done by loading from the offset into CPUARMState specified
1043 /* Function for handling writes of this register. If NULL, then writes
1044 * will be done by writing to the offset into CPUARMState specified
1048 /* Function for doing a "raw" read; used when we need to copy
1049 * coprocessor state to the kernel for KVM or out for
1050 * migration. This only needs to be provided if there is also a
1051 * readfn and it has side effects (for instance clear-on-read bits).
1053 CPReadFn
*raw_readfn
;
1054 /* Function for doing a "raw" write; used when we need to copy KVM
1055 * kernel coprocessor state into userspace, or for inbound
1056 * migration. This only needs to be provided if there is also a
1057 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1058 * or similar behaviour.
1060 CPWriteFn
*raw_writefn
;
1061 /* Function for resetting the register. If NULL, then reset will be done
1062 * by writing resetvalue to the field specified in fieldoffset. If
1063 * fieldoffset is 0 then no reset will be done.
1068 /* Macros which are lvalues for the field in CPUARMState for the
1071 #define CPREG_FIELD32(env, ri) \
1072 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1073 #define CPREG_FIELD64(env, ri) \
1074 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1076 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1078 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1079 const ARMCPRegInfo
*regs
, void *opaque
);
1080 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1081 const ARMCPRegInfo
*regs
, void *opaque
);
1082 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1084 define_arm_cp_regs_with_opaque(cpu
, regs
, 0);
1086 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1088 define_one_arm_cp_reg_with_opaque(cpu
, regs
, 0);
1090 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
1092 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1093 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1095 /* CPReadFn that can be used for read-as-zero behaviour */
1096 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1098 /* CPResetFn that does nothing, for use if no reset is required even
1099 * if fieldoffset is non zero.
1101 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1103 /* Return true if this reginfo struct's field in the cpu state struct
1106 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo
*ri
)
1108 return (ri
->state
== ARM_CP_STATE_AA64
) || (ri
->type
& ARM_CP_64BIT
);
1111 static inline bool cp_access_ok(int current_pl
,
1112 const ARMCPRegInfo
*ri
, int isread
)
1114 return (ri
->access
>> ((current_pl
* 2) + isread
)) & 1;
1118 * write_list_to_cpustate
1121 * For each register listed in the ARMCPU cpreg_indexes list, write
1122 * its value from the cpreg_values list into the ARMCPUState structure.
1123 * This updates TCG's working data structures from KVM data or
1124 * from incoming migration state.
1126 * Returns: true if all register values were updated correctly,
1127 * false if some register was unknown or could not be written.
1128 * Note that we do not stop early on failure -- we will attempt
1129 * writing all registers in the list.
1131 bool write_list_to_cpustate(ARMCPU
*cpu
);
1134 * write_cpustate_to_list:
1137 * For each register listed in the ARMCPU cpreg_indexes list, write
1138 * its value from the ARMCPUState structure into the cpreg_values list.
1139 * This is used to copy info from TCG's working data structures into
1140 * KVM or for outbound migration.
1142 * Returns: true if all register values were read correctly,
1143 * false if some register was unknown or could not be read.
1144 * Note that we do not stop early on failure -- we will attempt
1145 * reading all registers in the list.
1147 bool write_cpustate_to_list(ARMCPU
*cpu
);
1149 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
1150 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1151 conventional cores (ie. Application or Realtime profile). */
1153 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1155 #define ARM_CPUID_TI915T 0x54029152
1156 #define ARM_CPUID_TI925T 0x54029252
1158 #if defined(CONFIG_USER_ONLY)
1159 #define TARGET_PAGE_BITS 12
1161 /* The ARM MMU allows 1k pages. */
1162 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1163 architecture revisions. Maybe a configure option to disable them. */
1164 #define TARGET_PAGE_BITS 10
1167 #if defined(TARGET_AARCH64)
1168 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1169 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1171 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1172 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1175 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
)
1177 CPUARMState
*env
= cs
->env_ptr
;
1178 unsigned int cur_el
= arm_current_pl(env
);
1179 unsigned int target_el
= arm_excp_target_el(cs
, excp_idx
);
1181 /* Don't take exceptions if they target a lower EL. */
1182 if (cur_el
> target_el
) {
1188 return !(env
->daif
& PSTATE_F
);
1190 return !(env
->daif
& PSTATE_I
)
1191 && (!IS_M(env
) || env
->regs
[15] < 0xfffffff0);
1193 g_assert_not_reached();
1197 static inline CPUARMState
*cpu_init(const char *cpu_model
)
1199 ARMCPU
*cpu
= cpu_arm_init(cpu_model
);
1206 #define cpu_exec cpu_arm_exec
1207 #define cpu_gen_code cpu_arm_gen_code
1208 #define cpu_signal_handler cpu_arm_signal_handler
1209 #define cpu_list arm_cpu_list
1211 /* MMU modes definitions */
1212 #define MMU_MODE0_SUFFIX _user
1213 #define MMU_MODE1_SUFFIX _kernel
1214 #define MMU_USER_IDX 0
1215 static inline int cpu_mmu_index (CPUARMState
*env
)
1217 return arm_current_pl(env
);
1220 /* Return the Exception Level targeted by debug exceptions;
1221 * currently always EL1 since we don't implement EL2 or EL3.
1223 static inline int arm_debug_target_el(CPUARMState
*env
)
1228 static inline bool aa64_generate_debug_exceptions(CPUARMState
*env
)
1230 if (arm_current_pl(env
) == arm_debug_target_el(env
)) {
1231 if ((extract32(env
->cp15
.mdscr_el1
, 13, 1) == 0)
1232 || (env
->daif
& PSTATE_D
)) {
1239 static inline bool aa32_generate_debug_exceptions(CPUARMState
*env
)
1241 if (arm_current_pl(env
) == 0 && arm_el_is_aa64(env
, 1)) {
1242 return aa64_generate_debug_exceptions(env
);
1244 return arm_current_pl(env
) != 2;
1247 /* Return true if debugging exceptions are currently enabled.
1248 * This corresponds to what in ARM ARM pseudocode would be
1249 * if UsingAArch32() then
1250 * return AArch32.GenerateDebugExceptions()
1252 * return AArch64.GenerateDebugExceptions()
1253 * We choose to push the if() down into this function for clarity,
1254 * since the pseudocode has it at all callsites except for the one in
1255 * CheckSoftwareStep(), where it is elided because both branches would
1256 * always return the same value.
1258 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
1259 * don't yet implement those exception levels or their associated trap bits.
1261 static inline bool arm_generate_debug_exceptions(CPUARMState
*env
)
1264 return aa64_generate_debug_exceptions(env
);
1266 return aa32_generate_debug_exceptions(env
);
1270 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
1271 * implicitly means this always returns false in pre-v8 CPUs.)
1273 static inline bool arm_singlestep_active(CPUARMState
*env
)
1275 return extract32(env
->cp15
.mdscr_el1
, 0, 1)
1276 && arm_el_is_aa64(env
, arm_debug_target_el(env
))
1277 && arm_generate_debug_exceptions(env
);
1280 #include "exec/cpu-all.h"
1282 /* Bit usage in the TB flags field: bit 31 indicates whether we are
1283 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
1285 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1286 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1288 /* Bit usage when in AArch32 state: */
1289 #define ARM_TBFLAG_THUMB_SHIFT 0
1290 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1291 #define ARM_TBFLAG_VECLEN_SHIFT 1
1292 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1293 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1294 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1295 #define ARM_TBFLAG_PRIV_SHIFT 6
1296 #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
1297 #define ARM_TBFLAG_VFPEN_SHIFT 7
1298 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1299 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
1300 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1301 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1302 #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1303 #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
1304 #define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
1305 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 18
1306 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1307 #define ARM_TBFLAG_PSTATE_SS_SHIFT 19
1308 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1309 /* We store the bottom two bits of the CPAR as TB flags and handle
1310 * checks on the other bits at runtime
1312 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
1313 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1315 /* Bit usage when in AArch64 state */
1316 #define ARM_TBFLAG_AA64_EL_SHIFT 0
1317 #define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
1318 #define ARM_TBFLAG_AA64_FPEN_SHIFT 2
1319 #define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
1320 #define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
1321 #define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1322 #define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4
1323 #define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1325 /* some convenience accessor macros */
1326 #define ARM_TBFLAG_AARCH64_STATE(F) \
1327 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1328 #define ARM_TBFLAG_THUMB(F) \
1329 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1330 #define ARM_TBFLAG_VECLEN(F) \
1331 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1332 #define ARM_TBFLAG_VECSTRIDE(F) \
1333 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1334 #define ARM_TBFLAG_PRIV(F) \
1335 (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
1336 #define ARM_TBFLAG_VFPEN(F) \
1337 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1338 #define ARM_TBFLAG_CONDEXEC(F) \
1339 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1340 #define ARM_TBFLAG_BSWAP_CODE(F) \
1341 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1342 #define ARM_TBFLAG_CPACR_FPEN(F) \
1343 (((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
1344 #define ARM_TBFLAG_SS_ACTIVE(F) \
1345 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1346 #define ARM_TBFLAG_PSTATE_SS(F) \
1347 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
1348 #define ARM_TBFLAG_XSCALE_CPAR(F) \
1349 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1350 #define ARM_TBFLAG_AA64_EL(F) \
1351 (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
1352 #define ARM_TBFLAG_AA64_FPEN(F) \
1353 (((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT)
1354 #define ARM_TBFLAG_AA64_SS_ACTIVE(F) \
1355 (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1356 #define ARM_TBFLAG_AA64_PSTATE_SS(F) \
1357 (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1359 static inline void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
1360 target_ulong
*cs_base
, int *flags
)
1364 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1365 fpen
= extract32(env
->cp15
.c1_coproc
, 20, 2);
1367 /* CPACR doesn't exist before v6, so VFP is always accessible */
1373 *flags
= ARM_TBFLAG_AARCH64_STATE_MASK
1374 | (arm_current_pl(env
) << ARM_TBFLAG_AA64_EL_SHIFT
);
1375 if (fpen
== 3 || (fpen
== 1 && arm_current_pl(env
) != 0)) {
1376 *flags
|= ARM_TBFLAG_AA64_FPEN_MASK
;
1378 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1379 * states defined in the ARM ARM for software singlestep:
1380 * SS_ACTIVE PSTATE.SS State
1381 * 0 x Inactive (the TB flag for SS is always 0)
1382 * 1 0 Active-pending
1383 * 1 1 Active-not-pending
1385 if (arm_singlestep_active(env
)) {
1386 *flags
|= ARM_TBFLAG_AA64_SS_ACTIVE_MASK
;
1387 if (env
->pstate
& PSTATE_SS
) {
1388 *flags
|= ARM_TBFLAG_AA64_PSTATE_SS_MASK
;
1393 *pc
= env
->regs
[15];
1394 *flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
1395 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
1396 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
1397 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
1398 | (env
->bswap_code
<< ARM_TBFLAG_BSWAP_CODE_SHIFT
);
1399 if (arm_feature(env
, ARM_FEATURE_M
)) {
1400 privmode
= !((env
->v7m
.exception
== 0) && (env
->v7m
.control
& 1));
1402 privmode
= (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
;
1405 *flags
|= ARM_TBFLAG_PRIV_MASK
;
1407 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
1408 || arm_el_is_aa64(env
, 1)) {
1409 *flags
|= ARM_TBFLAG_VFPEN_MASK
;
1411 if (fpen
== 3 || (fpen
== 1 && arm_current_pl(env
) != 0)) {
1412 *flags
|= ARM_TBFLAG_CPACR_FPEN_MASK
;
1414 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1415 * states defined in the ARM ARM for software singlestep:
1416 * SS_ACTIVE PSTATE.SS State
1417 * 0 x Inactive (the TB flag for SS is always 0)
1418 * 1 0 Active-pending
1419 * 1 1 Active-not-pending
1421 if (arm_singlestep_active(env
)) {
1422 *flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
1423 if (env
->uncached_cpsr
& PSTATE_SS
) {
1424 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
1427 *flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
1428 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
1434 #include "exec/exec-all.h"
1436 static inline void cpu_pc_from_tb(CPUARMState
*env
, TranslationBlock
*tb
)
1438 if (ARM_TBFLAG_AARCH64_STATE(tb
->flags
)) {
1441 env
->regs
[15] = tb
->pc
;