2 * QEMU RISC-V VirtIO Board
4 * Copyright (c) 2017 SiFive, Inc.
6 * RISC-V machine with 16550a UART and VirtIO MMIO
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
24 #include "qemu/error-report.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/riscv/riscv_hart.h"
33 #include "hw/riscv/sifive_plic.h"
34 #include "hw/riscv/sifive_clint.h"
35 #include "hw/riscv/sifive_test.h"
36 #include "hw/riscv/virt.h"
37 #include "hw/riscv/boot.h"
38 #include "chardev/char.h"
39 #include "sysemu/arch_init.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/sysemu.h"
42 #include "exec/address-spaces.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci-host/gpex.h"
48 #if defined(TARGET_RISCV32)
49 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
51 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
54 static const struct MemmapEntry
{
58 [VIRT_DEBUG
] = { 0x0, 0x100 },
59 [VIRT_MROM
] = { 0x1000, 0x11000 },
60 [VIRT_TEST
] = { 0x100000, 0x1000 },
61 [VIRT_RTC
] = { 0x101000, 0x1000 },
62 [VIRT_CLINT
] = { 0x2000000, 0x10000 },
63 [VIRT_PLIC
] = { 0xc000000, 0x4000000 },
64 [VIRT_UART0
] = { 0x10000000, 0x100 },
65 [VIRT_VIRTIO
] = { 0x10001000, 0x1000 },
66 [VIRT_FLASH
] = { 0x20000000, 0x4000000 },
67 [VIRT_DRAM
] = { 0x80000000, 0x0 },
68 [VIRT_PCIE_MMIO
] = { 0x40000000, 0x40000000 },
69 [VIRT_PCIE_PIO
] = { 0x03000000, 0x00010000 },
70 [VIRT_PCIE_ECAM
] = { 0x30000000, 0x10000000 },
73 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
75 static PFlashCFI01
*virt_flash_create1(RISCVVirtState
*s
,
77 const char *alias_prop_name
)
80 * Create a single flash device. We use the same parameters as
81 * the flash devices on the ARM virt board.
83 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
85 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
86 qdev_prop_set_uint8(dev
, "width", 4);
87 qdev_prop_set_uint8(dev
, "device-width", 2);
88 qdev_prop_set_bit(dev
, "big-endian", false);
89 qdev_prop_set_uint16(dev
, "id0", 0x89);
90 qdev_prop_set_uint16(dev
, "id1", 0x18);
91 qdev_prop_set_uint16(dev
, "id2", 0x00);
92 qdev_prop_set_uint16(dev
, "id3", 0x00);
93 qdev_prop_set_string(dev
, "name", name
);
95 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
));
96 object_property_add_alias(OBJECT(s
), alias_prop_name
,
97 OBJECT(dev
), "drive");
99 return PFLASH_CFI01(dev
);
102 static void virt_flash_create(RISCVVirtState
*s
)
104 s
->flash
[0] = virt_flash_create1(s
, "virt.flash0", "pflash0");
105 s
->flash
[1] = virt_flash_create1(s
, "virt.flash1", "pflash1");
108 static void virt_flash_map1(PFlashCFI01
*flash
,
109 hwaddr base
, hwaddr size
,
110 MemoryRegion
*sysmem
)
112 DeviceState
*dev
= DEVICE(flash
);
114 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
115 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
116 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
117 qdev_realize_and_unref(dev
, NULL
, &error_fatal
);
119 memory_region_add_subregion(sysmem
, base
,
120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
124 static void virt_flash_map(RISCVVirtState
*s
,
125 MemoryRegion
*sysmem
)
127 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
128 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
130 virt_flash_map1(s
->flash
[0], flashbase
, flashsize
,
132 virt_flash_map1(s
->flash
[1], flashbase
+ flashsize
, flashsize
,
136 static void create_pcie_irq_map(void *fdt
, char *nodename
,
137 uint32_t plic_phandle
)
141 full_irq_map
[GPEX_NUM_IRQS
* GPEX_NUM_IRQS
* FDT_INT_MAP_WIDTH
] = {};
142 uint32_t *irq_map
= full_irq_map
;
144 /* This code creates a standard swizzle of interrupts such that
145 * each device's first interrupt is based on it's PCI_SLOT number.
146 * (See pci_swizzle_map_irq_fn())
148 * We only need one entry per interrupt in the table (not one per
149 * possible slot) seeing the interrupt-map-mask will allow the table
150 * to wrap to any number of devices.
152 for (dev
= 0; dev
< GPEX_NUM_IRQS
; dev
++) {
153 int devfn
= dev
* 0x8;
155 for (pin
= 0; pin
< GPEX_NUM_IRQS
; pin
++) {
156 int irq_nr
= PCIE_IRQ
+ ((pin
+ PCI_SLOT(devfn
)) % GPEX_NUM_IRQS
);
159 irq_map
[i
] = cpu_to_be32(devfn
<< 8);
161 i
+= FDT_PCI_ADDR_CELLS
;
162 irq_map
[i
] = cpu_to_be32(pin
+ 1);
164 i
+= FDT_PCI_INT_CELLS
;
165 irq_map
[i
++] = cpu_to_be32(plic_phandle
);
167 i
+= FDT_PLIC_ADDR_CELLS
;
168 irq_map
[i
] = cpu_to_be32(irq_nr
);
170 irq_map
+= FDT_INT_MAP_WIDTH
;
174 qemu_fdt_setprop(fdt
, nodename
, "interrupt-map",
175 full_irq_map
, sizeof(full_irq_map
));
177 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-map-mask",
181 static void create_fdt(RISCVVirtState
*s
, const struct MemmapEntry
*memmap
,
182 uint64_t mem_size
, const char *cmdline
)
188 uint32_t plic_phandle
, test_phandle
, phandle
= 1;
189 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
190 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
192 fdt
= s
->fdt
= create_device_tree(&s
->fdt_size
);
194 error_report("create_device_tree() failed");
198 qemu_fdt_setprop_string(fdt
, "/", "model", "riscv-virtio,qemu");
199 qemu_fdt_setprop_string(fdt
, "/", "compatible", "riscv-virtio");
200 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
201 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
203 qemu_fdt_add_subnode(fdt
, "/soc");
204 qemu_fdt_setprop(fdt
, "/soc", "ranges", NULL
, 0);
205 qemu_fdt_setprop_string(fdt
, "/soc", "compatible", "simple-bus");
206 qemu_fdt_setprop_cell(fdt
, "/soc", "#size-cells", 0x2);
207 qemu_fdt_setprop_cell(fdt
, "/soc", "#address-cells", 0x2);
209 nodename
= g_strdup_printf("/memory@%lx",
210 (long)memmap
[VIRT_DRAM
].base
);
211 qemu_fdt_add_subnode(fdt
, nodename
);
212 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
213 memmap
[VIRT_DRAM
].base
>> 32, memmap
[VIRT_DRAM
].base
,
214 mem_size
>> 32, mem_size
);
215 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "memory");
218 qemu_fdt_add_subnode(fdt
, "/cpus");
219 qemu_fdt_setprop_cell(fdt
, "/cpus", "timebase-frequency",
220 SIFIVE_CLINT_TIMEBASE_FREQ
);
221 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0x0);
222 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 0x1);
224 for (cpu
= s
->soc
.num_harts
- 1; cpu
>= 0; cpu
--) {
225 int cpu_phandle
= phandle
++;
227 nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
228 char *intc
= g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
229 char *isa
= riscv_isa_string(&s
->soc
.harts
[cpu
]);
230 qemu_fdt_add_subnode(fdt
, nodename
);
231 #if defined(TARGET_RISCV32)
232 qemu_fdt_setprop_string(fdt
, nodename
, "mmu-type", "riscv,sv32");
234 qemu_fdt_setprop_string(fdt
, nodename
, "mmu-type", "riscv,sv48");
236 qemu_fdt_setprop_string(fdt
, nodename
, "riscv,isa", isa
);
237 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv");
238 qemu_fdt_setprop_string(fdt
, nodename
, "status", "okay");
239 qemu_fdt_setprop_cell(fdt
, nodename
, "reg", cpu
);
240 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "cpu");
241 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", cpu_phandle
);
242 intc_phandle
= phandle
++;
243 qemu_fdt_add_subnode(fdt
, intc
);
244 qemu_fdt_setprop_cell(fdt
, intc
, "phandle", intc_phandle
);
245 qemu_fdt_setprop_string(fdt
, intc
, "compatible", "riscv,cpu-intc");
246 qemu_fdt_setprop(fdt
, intc
, "interrupt-controller", NULL
, 0);
247 qemu_fdt_setprop_cell(fdt
, intc
, "#interrupt-cells", 1);
253 /* Add cpu-topology node */
254 qemu_fdt_add_subnode(fdt
, "/cpus/cpu-map");
255 qemu_fdt_add_subnode(fdt
, "/cpus/cpu-map/cluster0");
256 for (cpu
= s
->soc
.num_harts
- 1; cpu
>= 0; cpu
--) {
257 char *core_nodename
= g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
259 char *cpu_nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
260 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, cpu_nodename
);
261 qemu_fdt_add_subnode(fdt
, core_nodename
);
262 qemu_fdt_setprop_cell(fdt
, core_nodename
, "cpu", intc_phandle
);
263 g_free(core_nodename
);
264 g_free(cpu_nodename
);
267 cells
= g_new0(uint32_t, s
->soc
.num_harts
* 4);
268 for (cpu
= 0; cpu
< s
->soc
.num_harts
; cpu
++) {
270 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
271 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
272 cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
273 cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
274 cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
275 cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
278 nodename
= g_strdup_printf("/soc/clint@%lx",
279 (long)memmap
[VIRT_CLINT
].base
);
280 qemu_fdt_add_subnode(fdt
, nodename
);
281 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv,clint0");
282 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
283 0x0, memmap
[VIRT_CLINT
].base
,
284 0x0, memmap
[VIRT_CLINT
].size
);
285 qemu_fdt_setprop(fdt
, nodename
, "interrupts-extended",
286 cells
, s
->soc
.num_harts
* sizeof(uint32_t) * 4);
290 plic_phandle
= phandle
++;
291 cells
= g_new0(uint32_t, s
->soc
.num_harts
* 4);
292 for (cpu
= 0; cpu
< s
->soc
.num_harts
; cpu
++) {
294 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
295 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
296 cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
297 cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_EXT
);
298 cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
299 cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_S_EXT
);
302 nodename
= g_strdup_printf("/soc/interrupt-controller@%lx",
303 (long)memmap
[VIRT_PLIC
].base
);
304 qemu_fdt_add_subnode(fdt
, nodename
);
305 qemu_fdt_setprop_cell(fdt
, nodename
, "#address-cells",
306 FDT_PLIC_ADDR_CELLS
);
307 qemu_fdt_setprop_cell(fdt
, nodename
, "#interrupt-cells",
309 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv,plic0");
310 qemu_fdt_setprop(fdt
, nodename
, "interrupt-controller", NULL
, 0);
311 qemu_fdt_setprop(fdt
, nodename
, "interrupts-extended",
312 cells
, s
->soc
.num_harts
* sizeof(uint32_t) * 4);
313 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
314 0x0, memmap
[VIRT_PLIC
].base
,
315 0x0, memmap
[VIRT_PLIC
].size
);
316 qemu_fdt_setprop_cell(fdt
, nodename
, "riscv,ndev", VIRTIO_NDEV
);
317 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", plic_phandle
);
318 plic_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
322 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
323 nodename
= g_strdup_printf("/virtio_mmio@%lx",
324 (long)(memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
));
325 qemu_fdt_add_subnode(fdt
, nodename
);
326 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "virtio,mmio");
327 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
328 0x0, memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
329 0x0, memmap
[VIRT_VIRTIO
].size
);
330 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupt-parent", plic_phandle
);
331 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupts", VIRTIO_IRQ
+ i
);
335 nodename
= g_strdup_printf("/soc/pci@%lx",
336 (long) memmap
[VIRT_PCIE_ECAM
].base
);
337 qemu_fdt_add_subnode(fdt
, nodename
);
338 qemu_fdt_setprop_cell(fdt
, nodename
, "#address-cells",
340 qemu_fdt_setprop_cell(fdt
, nodename
, "#interrupt-cells",
342 qemu_fdt_setprop_cell(fdt
, nodename
, "#size-cells", 0x2);
343 qemu_fdt_setprop_string(fdt
, nodename
, "compatible",
344 "pci-host-ecam-generic");
345 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "pci");
346 qemu_fdt_setprop_cell(fdt
, nodename
, "linux,pci-domain", 0);
347 qemu_fdt_setprop_cells(fdt
, nodename
, "bus-range", 0,
348 memmap
[VIRT_PCIE_ECAM
].size
/
349 PCIE_MMCFG_SIZE_MIN
- 1);
350 qemu_fdt_setprop(fdt
, nodename
, "dma-coherent", NULL
, 0);
351 qemu_fdt_setprop_cells(fdt
, nodename
, "reg", 0, memmap
[VIRT_PCIE_ECAM
].base
,
352 0, memmap
[VIRT_PCIE_ECAM
].size
);
353 qemu_fdt_setprop_sized_cells(fdt
, nodename
, "ranges",
354 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
355 2, memmap
[VIRT_PCIE_PIO
].base
, 2, memmap
[VIRT_PCIE_PIO
].size
,
356 1, FDT_PCI_RANGE_MMIO
,
357 2, memmap
[VIRT_PCIE_MMIO
].base
,
358 2, memmap
[VIRT_PCIE_MMIO
].base
, 2, memmap
[VIRT_PCIE_MMIO
].size
);
359 create_pcie_irq_map(fdt
, nodename
, plic_phandle
);
362 test_phandle
= phandle
++;
363 nodename
= g_strdup_printf("/test@%lx",
364 (long)memmap
[VIRT_TEST
].base
);
365 qemu_fdt_add_subnode(fdt
, nodename
);
367 const char compat
[] = "sifive,test1\0sifive,test0\0syscon";
368 qemu_fdt_setprop(fdt
, nodename
, "compatible", compat
, sizeof(compat
));
370 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
371 0x0, memmap
[VIRT_TEST
].base
,
372 0x0, memmap
[VIRT_TEST
].size
);
373 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", test_phandle
);
374 test_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
377 nodename
= g_strdup_printf("/reboot");
378 qemu_fdt_add_subnode(fdt
, nodename
);
379 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "syscon-reboot");
380 qemu_fdt_setprop_cell(fdt
, nodename
, "regmap", test_phandle
);
381 qemu_fdt_setprop_cell(fdt
, nodename
, "offset", 0x0);
382 qemu_fdt_setprop_cell(fdt
, nodename
, "value", FINISHER_RESET
);
385 nodename
= g_strdup_printf("/poweroff");
386 qemu_fdt_add_subnode(fdt
, nodename
);
387 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "syscon-poweroff");
388 qemu_fdt_setprop_cell(fdt
, nodename
, "regmap", test_phandle
);
389 qemu_fdt_setprop_cell(fdt
, nodename
, "offset", 0x0);
390 qemu_fdt_setprop_cell(fdt
, nodename
, "value", FINISHER_PASS
);
393 nodename
= g_strdup_printf("/uart@%lx",
394 (long)memmap
[VIRT_UART0
].base
);
395 qemu_fdt_add_subnode(fdt
, nodename
);
396 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "ns16550a");
397 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
398 0x0, memmap
[VIRT_UART0
].base
,
399 0x0, memmap
[VIRT_UART0
].size
);
400 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency", 3686400);
401 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupt-parent", plic_phandle
);
402 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupts", UART0_IRQ
);
404 qemu_fdt_add_subnode(fdt
, "/chosen");
405 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", nodename
);
407 qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs", cmdline
);
411 nodename
= g_strdup_printf("/rtc@%lx",
412 (long)memmap
[VIRT_RTC
].base
);
413 qemu_fdt_add_subnode(fdt
, nodename
);
414 qemu_fdt_setprop_string(fdt
, nodename
, "compatible",
415 "google,goldfish-rtc");
416 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
417 0x0, memmap
[VIRT_RTC
].base
,
418 0x0, memmap
[VIRT_RTC
].size
);
419 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupt-parent", plic_phandle
);
420 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupts", RTC_IRQ
);
423 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
424 qemu_fdt_add_subnode(s
->fdt
, nodename
);
425 qemu_fdt_setprop_string(s
->fdt
, nodename
, "compatible", "cfi-flash");
426 qemu_fdt_setprop_sized_cells(s
->fdt
, nodename
, "reg",
427 2, flashbase
, 2, flashsize
,
428 2, flashbase
+ flashsize
, 2, flashsize
);
429 qemu_fdt_setprop_cell(s
->fdt
, nodename
, "bank-width", 4);
434 static inline DeviceState
*gpex_pcie_init(MemoryRegion
*sys_mem
,
435 hwaddr ecam_base
, hwaddr ecam_size
,
436 hwaddr mmio_base
, hwaddr mmio_size
,
438 DeviceState
*plic
, bool link_up
)
441 MemoryRegion
*ecam_alias
, *ecam_reg
;
442 MemoryRegion
*mmio_alias
, *mmio_reg
;
446 dev
= qdev_new(TYPE_GPEX_HOST
);
448 qdev_realize_and_unref(dev
, NULL
, &error_fatal
);
450 ecam_alias
= g_new0(MemoryRegion
, 1);
451 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
452 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
453 ecam_reg
, 0, ecam_size
);
454 memory_region_add_subregion(get_system_memory(), ecam_base
, ecam_alias
);
456 mmio_alias
= g_new0(MemoryRegion
, 1);
457 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
458 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
459 mmio_reg
, mmio_base
, mmio_size
);
460 memory_region_add_subregion(get_system_memory(), mmio_base
, mmio_alias
);
462 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, pio_base
);
464 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
465 irq
= qdev_get_gpio_in(plic
, PCIE_IRQ
+ i
);
467 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, irq
);
468 gpex_set_irq_num(GPEX_HOST(dev
), i
, PCIE_IRQ
+ i
);
474 static void virt_machine_init(MachineState
*machine
)
476 const struct MemmapEntry
*memmap
= virt_memmap
;
477 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(machine
);
478 MemoryRegion
*system_memory
= get_system_memory();
479 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
480 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
481 char *plic_hart_config
;
482 size_t plic_hart_config_len
;
483 target_ulong start_addr
= memmap
[VIRT_DRAM
].base
;
485 unsigned int smp_cpus
= machine
->smp
.cpus
;
488 sysbus_init_child_obj(OBJECT(machine
), "soc", &s
->soc
, sizeof(s
->soc
),
489 TYPE_RISCV_HART_ARRAY
);
490 object_property_set_str(OBJECT(&s
->soc
), machine
->cpu_type
, "cpu-type",
492 object_property_set_int(OBJECT(&s
->soc
), smp_cpus
, "num-harts",
494 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
497 /* register system main memory (actual RAM) */
498 memory_region_init_ram(main_mem
, NULL
, "riscv_virt_board.ram",
499 machine
->ram_size
, &error_fatal
);
500 memory_region_add_subregion(system_memory
, memmap
[VIRT_DRAM
].base
,
503 /* create device tree */
504 create_fdt(s
, memmap
, machine
->ram_size
, machine
->kernel_cmdline
);
507 memory_region_init_rom(mask_rom
, NULL
, "riscv_virt_board.mrom",
508 memmap
[VIRT_MROM
].size
, &error_fatal
);
509 memory_region_add_subregion(system_memory
, memmap
[VIRT_MROM
].base
,
512 riscv_find_and_load_firmware(machine
, BIOS_FILENAME
,
513 memmap
[VIRT_DRAM
].base
, NULL
);
515 if (machine
->kernel_filename
) {
516 uint64_t kernel_entry
= riscv_load_kernel(machine
->kernel_filename
,
519 if (machine
->initrd_filename
) {
521 hwaddr end
= riscv_load_initrd(machine
->initrd_filename
,
522 machine
->ram_size
, kernel_entry
,
524 qemu_fdt_setprop_cell(s
->fdt
, "/chosen",
525 "linux,initrd-start", start
);
526 qemu_fdt_setprop_cell(s
->fdt
, "/chosen", "linux,initrd-end",
531 if (drive_get(IF_PFLASH
, 0, 0)) {
533 * Pflash was supplied, let's overwrite the address we jump to after
534 * reset to the base of the flash.
536 start_addr
= virt_memmap
[VIRT_FLASH
].base
;
540 uint32_t reset_vec
[8] = {
541 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
542 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
543 0xf1402573, /* csrr a0, mhartid */
544 #if defined(TARGET_RISCV32)
545 0x0182a283, /* lw t0, 24(t0) */
546 #elif defined(TARGET_RISCV64)
547 0x0182b283, /* ld t0, 24(t0) */
549 0x00028067, /* jr t0 */
551 start_addr
, /* start: .dword */
556 /* copy in the reset vector in little_endian byte order */
557 for (i
= 0; i
< sizeof(reset_vec
) >> 2; i
++) {
558 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
560 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
561 memmap
[VIRT_MROM
].base
, &address_space_memory
);
563 /* copy in the device tree */
564 if (fdt_pack(s
->fdt
) || fdt_totalsize(s
->fdt
) >
565 memmap
[VIRT_MROM
].size
- sizeof(reset_vec
)) {
566 error_report("not enough space to store device-tree");
569 qemu_fdt_dumpdtb(s
->fdt
, fdt_totalsize(s
->fdt
));
570 rom_add_blob_fixed_as("mrom.fdt", s
->fdt
, fdt_totalsize(s
->fdt
),
571 memmap
[VIRT_MROM
].base
+ sizeof(reset_vec
),
572 &address_space_memory
);
574 /* create PLIC hart topology configuration string */
575 plic_hart_config_len
= (strlen(VIRT_PLIC_HART_CONFIG
) + 1) * smp_cpus
;
576 plic_hart_config
= g_malloc0(plic_hart_config_len
);
577 for (i
= 0; i
< smp_cpus
; i
++) {
579 strncat(plic_hart_config
, ",", plic_hart_config_len
);
581 strncat(plic_hart_config
, VIRT_PLIC_HART_CONFIG
, plic_hart_config_len
);
582 plic_hart_config_len
-= (strlen(VIRT_PLIC_HART_CONFIG
) + 1);
586 s
->plic
= sifive_plic_create(memmap
[VIRT_PLIC
].base
,
588 VIRT_PLIC_NUM_SOURCES
,
589 VIRT_PLIC_NUM_PRIORITIES
,
590 VIRT_PLIC_PRIORITY_BASE
,
591 VIRT_PLIC_PENDING_BASE
,
592 VIRT_PLIC_ENABLE_BASE
,
593 VIRT_PLIC_ENABLE_STRIDE
,
594 VIRT_PLIC_CONTEXT_BASE
,
595 VIRT_PLIC_CONTEXT_STRIDE
,
596 memmap
[VIRT_PLIC
].size
);
597 sifive_clint_create(memmap
[VIRT_CLINT
].base
,
598 memmap
[VIRT_CLINT
].size
, smp_cpus
,
599 SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
, true);
600 sifive_test_create(memmap
[VIRT_TEST
].base
);
602 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
603 sysbus_create_simple("virtio-mmio",
604 memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
605 qdev_get_gpio_in(DEVICE(s
->plic
), VIRTIO_IRQ
+ i
));
608 gpex_pcie_init(system_memory
,
609 memmap
[VIRT_PCIE_ECAM
].base
,
610 memmap
[VIRT_PCIE_ECAM
].size
,
611 memmap
[VIRT_PCIE_MMIO
].base
,
612 memmap
[VIRT_PCIE_MMIO
].size
,
613 memmap
[VIRT_PCIE_PIO
].base
,
614 DEVICE(s
->plic
), true);
616 serial_mm_init(system_memory
, memmap
[VIRT_UART0
].base
,
617 0, qdev_get_gpio_in(DEVICE(s
->plic
), UART0_IRQ
), 399193,
618 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
620 sysbus_create_simple("goldfish_rtc", memmap
[VIRT_RTC
].base
,
621 qdev_get_gpio_in(DEVICE(s
->plic
), RTC_IRQ
));
623 virt_flash_create(s
);
625 for (i
= 0; i
< ARRAY_SIZE(s
->flash
); i
++) {
626 /* Map legacy -drive if=pflash to machine properties */
627 pflash_cfi01_legacy_drive(s
->flash
[i
],
628 drive_get(IF_PFLASH
, 0, i
));
630 virt_flash_map(s
, system_memory
);
632 g_free(plic_hart_config
);
635 static void virt_machine_instance_init(Object
*obj
)
639 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
641 MachineClass
*mc
= MACHINE_CLASS(oc
);
643 mc
->desc
= "RISC-V VirtIO board";
644 mc
->init
= virt_machine_init
;
646 mc
->default_cpu_type
= VIRT_CPU
;
647 mc
->pci_allow_0_address
= true;
650 static const TypeInfo virt_machine_typeinfo
= {
651 .name
= MACHINE_TYPE_NAME("virt"),
652 .parent
= TYPE_MACHINE
,
653 .class_init
= virt_machine_class_init
,
654 .instance_init
= virt_machine_instance_init
,
655 .instance_size
= sizeof(RISCVVirtState
),
658 static void virt_machine_init_register_types(void)
660 type_register_static(&virt_machine_typeinfo
);
663 type_init(virt_machine_init_register_types
)