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piix4: don't reserve hw resources when hotplug is off globally
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob8d14e4667a0b678ce9276af7a82c8ee29689495e
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/rtc/mc146818rtc_regs.h"
49 #include "migration/vmstate.h"
50 #include "hw/mem/memory-device.h"
51 #include "hw/mem/nvdimm.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/reset.h"
54 #include "hw/hyperv/vmbus-bridge.h"
55
56 /* Supported chipsets: */
57 #include "hw/southbridge/piix.h"
58 #include "hw/acpi/pcihp.h"
59 #include "hw/i386/fw_cfg.h"
60 #include "hw/i386/ich9.h"
61 #include "hw/pci/pci_bus.h"
62 #include "hw/pci-host/q35.h"
63 #include "hw/i386/x86-iommu.h"
64
65 #include "hw/acpi/aml-build.h"
66 #include "hw/acpi/utils.h"
67 #include "hw/acpi/pci.h"
68
69 #include "qom/qom-qobject.h"
70 #include "hw/i386/amd_iommu.h"
71 #include "hw/i386/intel_iommu.h"
72
73 #include "hw/acpi/ipmi.h"
74 #include "hw/acpi/hmat.h"
75
76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
78 * a little bit, there should be plenty of free space since the DSDT
79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
80 */
81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
82 #define ACPI_BUILD_ALIGN_SIZE 0x1000
83
84 #define ACPI_BUILD_TABLE_SIZE 0x20000
85
86 /* #define DEBUG_ACPI_BUILD */
87 #ifdef DEBUG_ACPI_BUILD
88 #define ACPI_BUILD_DPRINTF(fmt, ...) \
89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
90 #else
91 #define ACPI_BUILD_DPRINTF(fmt, ...)
92 #endif
93
94 typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 bool smi_on_cpuhp;
99 bool pcihp_root_en;
100 uint8_t s4_val;
101 AcpiFadtData fadt;
102 uint16_t cpu_hp_io_base;
103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
105 } AcpiPmInfo;
106
107 typedef struct AcpiMiscInfo {
108 bool is_piix4;
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 typedef struct FwCfgTPMConfig {
125 uint32_t tpmppi_address;
126 uint8_t tpm_version;
127 uint8_t tpmppi_version;
128 } QEMU_PACKED FwCfgTPMConfig;
129
130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
131
132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
133 .space_id = AML_AS_SYSTEM_IO,
134 .address = NVDIMM_ACPI_IO_BASE,
135 .bit_width = NVDIMM_ACPI_IO_LEN << 3
136 };
137
138 static void init_common_fadt_data(MachineState *ms, Object *o,
139 AcpiFadtData *data)
140 {
141 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
142 AmlAddressSpace as = AML_AS_SYSTEM_IO;
143 AcpiFadtData fadt = {
144 .rev = 3,
145 .flags =
146 (1 << ACPI_FADT_F_WBINVD) |
147 (1 << ACPI_FADT_F_PROC_C1) |
148 (1 << ACPI_FADT_F_SLP_BUTTON) |
149 (1 << ACPI_FADT_F_RTC_S4) |
150 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
151 /* APIC destination mode ("Flat Logical") has an upper limit of 8
152 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
153 * used
154 */
155 ((ms->smp.max_cpus > 8) ?
156 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
157 .int_model = 1 /* Multiple APIC */,
158 .rtc_century = RTC_CENTURY,
159 .plvl2_lat = 0xfff /* C2 state not supported */,
160 .plvl3_lat = 0xfff /* C3 state not supported */,
161 .smi_cmd = ACPI_PORT_SMI_CMD,
162 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
163 .acpi_enable_cmd =
164 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
165 .acpi_disable_cmd =
166 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
167 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
168 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
169 .address = io + 0x04 },
170 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
171 .gpe0_blk = { .space_id = as, .bit_width =
172 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
173 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
174 },
175 };
176 *data = fadt;
177 }
178
179 static Object *object_resolve_type_unambiguous(const char *typename)
180 {
181 bool ambig;
182 Object *o = object_resolve_path_type("", typename, &ambig);
183
184 if (ambig || !o) {
185 return NULL;
186 }
187 return o;
188 }
189
190 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
191 {
192 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
193 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
194 Object *obj = piix ? piix : lpc;
195 QObject *o;
196 pm->cpu_hp_io_base = 0;
197 pm->pcihp_io_base = 0;
198 pm->pcihp_io_len = 0;
199 pm->smi_on_cpuhp = false;
200
201 assert(obj);
202 init_common_fadt_data(machine, obj, &pm->fadt);
203 if (piix) {
204 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
205 pm->fadt.rev = 1;
206 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
207 pm->pcihp_io_base =
208 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
209 pm->pcihp_io_len =
210 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
211 }
212 if (lpc) {
213 uint64_t smi_features = object_property_get_uint(lpc,
214 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
215 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
216 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
217 pm->fadt.reset_reg = r;
218 pm->fadt.reset_val = 0xf;
219 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
220 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
221 pm->smi_on_cpuhp =
222 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
223 }
224
225 /* The above need not be conditional on machine type because the reset port
226 * happens to be the same on PIIX (pc) and ICH9 (q35). */
227 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
228
229 /* Fill in optional s3/s4 related properties */
230 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
231 if (o) {
232 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
233 } else {
234 pm->s3_disabled = false;
235 }
236 qobject_unref(o);
237 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
238 if (o) {
239 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
240 } else {
241 pm->s4_disabled = false;
242 }
243 qobject_unref(o);
244 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
245 if (o) {
246 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
247 } else {
248 pm->s4_val = false;
249 }
250 qobject_unref(o);
251
252 pm->pcihp_bridge_en =
253 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
254 NULL);
255 pm->pcihp_root_en =
256 object_property_get_bool(obj, "acpi-root-pci-hotplug",
257 NULL);
258 }
259
260 static void acpi_get_misc_info(AcpiMiscInfo *info)
261 {
262 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
263 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
264 assert(!!piix != !!lpc);
265
266 if (piix) {
267 info->is_piix4 = true;
268 }
269 if (lpc) {
270 info->is_piix4 = false;
271 }
272
273 info->has_hpet = hpet_find();
274 info->tpm_version = tpm_get_version(tpm_find());
275 info->pvpanic_port = pvpanic_port();
276 info->applesmc_io_base = applesmc_port();
277 }
278
279 /*
280 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
281 * On i386 arch we only have two pci hosts, so we can look only for them.
282 */
283 static Object *acpi_get_i386_pci_host(void)
284 {
285 PCIHostState *host;
286
287 host = OBJECT_CHECK(PCIHostState,
288 object_resolve_path("/machine/i440fx", NULL),
289 TYPE_PCI_HOST_BRIDGE);
290 if (!host) {
291 host = OBJECT_CHECK(PCIHostState,
292 object_resolve_path("/machine/q35", NULL),
293 TYPE_PCI_HOST_BRIDGE);
294 }
295
296 return OBJECT(host);
297 }
298
299 static void acpi_get_pci_holes(Range *hole, Range *hole64)
300 {
301 Object *pci_host;
302
303 pci_host = acpi_get_i386_pci_host();
304 g_assert(pci_host);
305
306 range_set_bounds1(hole,
307 object_property_get_uint(pci_host,
308 PCI_HOST_PROP_PCI_HOLE_START,
309 NULL),
310 object_property_get_uint(pci_host,
311 PCI_HOST_PROP_PCI_HOLE_END,
312 NULL));
313 range_set_bounds1(hole64,
314 object_property_get_uint(pci_host,
315 PCI_HOST_PROP_PCI_HOLE64_START,
316 NULL),
317 object_property_get_uint(pci_host,
318 PCI_HOST_PROP_PCI_HOLE64_END,
319 NULL));
320 }
321
322 static void acpi_align_size(GArray *blob, unsigned align)
323 {
324 /* Align size to multiple of given size. This reduces the chance
325 * we need to change size in the future (breaking cross version migration).
326 */
327 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
328 }
329
330 /* FACS */
331 static void
332 build_facs(GArray *table_data)
333 {
334 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
335 memcpy(&facs->signature, "FACS", 4);
336 facs->length = cpu_to_le32(sizeof(*facs));
337 }
338
339 static void build_append_pcihp_notify_entry(Aml *method, int slot)
340 {
341 Aml *if_ctx;
342 int32_t devfn = PCI_DEVFN(slot, 0);
343
344 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
345 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
346 aml_append(method, if_ctx);
347 }
348
349 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
350 bool pcihp_bridge_en)
351 {
352 Aml *dev, *notify_method = NULL, *method;
353 QObject *bsel;
354 PCIBus *sec;
355 int i;
356
357 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
358 if (bsel) {
359 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
360
361 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
362 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
363 }
364
365 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
366 DeviceClass *dc;
367 PCIDeviceClass *pc;
368 PCIDevice *pdev = bus->devices[i];
369 int slot = PCI_SLOT(i);
370 bool hotplug_enabled_dev;
371 bool bridge_in_acpi;
372 bool cold_plugged_bridge;
373
374 if (!pdev) {
375 if (bsel) { /* add hotplug slots for non present devices */
376 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
377 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
378 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
379 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
380 aml_append(method,
381 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
382 );
383 aml_append(dev, method);
384 aml_append(parent_scope, dev);
385
386 build_append_pcihp_notify_entry(notify_method, slot);
387 }
388 continue;
389 }
390
391 pc = PCI_DEVICE_GET_CLASS(pdev);
392 dc = DEVICE_GET_CLASS(pdev);
393
394 /*
395 * Cold plugged bridges aren't themselves hot-pluggable.
396 * Hotplugged bridges *are* hot-pluggable.
397 */
398 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
399 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
400
401 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
402
403 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
404 continue;
405 }
406
407 /* start to compose PCI slot descriptor */
408 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
409 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
410
411 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
412 /* add VGA specific AML methods */
413 int s3d;
414
415 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
416 s3d = 3;
417 } else {
418 s3d = 0;
419 }
420
421 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
422 aml_append(method, aml_return(aml_int(0)));
423 aml_append(dev, method);
424
425 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
426 aml_append(method, aml_return(aml_int(0)));
427 aml_append(dev, method);
428
429 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
430 aml_append(method, aml_return(aml_int(s3d)));
431 aml_append(dev, method);
432 } else if (hotplug_enabled_dev) {
433 /* add _SUN/_EJ0 to make slot hotpluggable */
434 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
435
436 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
437 aml_append(method,
438 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
439 );
440 aml_append(dev, method);
441
442 if (bsel) {
443 build_append_pcihp_notify_entry(notify_method, slot);
444 }
445 } else if (bridge_in_acpi) {
446 /*
447 * device is coldplugged bridge,
448 * add child device descriptions into its scope
449 */
450 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
451
452 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
453 }
454 /* slot descriptor has been composed, add it into parent context */
455 aml_append(parent_scope, dev);
456 }
457
458 if (bsel) {
459 aml_append(parent_scope, notify_method);
460 }
461
462 /* Append PCNT method to notify about events on local and child buses.
463 * Add this method for root bus only when hotplug is enabled since DSDT
464 * expects it.
465 */
466 if (bsel || pcihp_bridge_en) {
467 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
468 }
469 /* If bus supports hotplug select it and notify about local events */
470 if (bsel) {
471 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
472
473 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
474 aml_append(method,
475 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
476 );
477 aml_append(method,
478 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
479 );
480 }
481
482 /* Notify about child bus events in any case */
483 if (pcihp_bridge_en) {
484 QLIST_FOREACH(sec, &bus->child, sibling) {
485 int32_t devfn = sec->parent_dev->devfn;
486
487 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
488 continue;
489 }
490
491 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
492 }
493 }
494
495 if (bsel || pcihp_bridge_en) {
496 aml_append(parent_scope, method);
497 }
498 qobject_unref(bsel);
499 }
500
501 /**
502 * build_prt_entry:
503 * @link_name: link name for PCI route entry
504 *
505 * build AML package containing a PCI route entry for @link_name
506 */
507 static Aml *build_prt_entry(const char *link_name)
508 {
509 Aml *a_zero = aml_int(0);
510 Aml *pkg = aml_package(4);
511 aml_append(pkg, a_zero);
512 aml_append(pkg, a_zero);
513 aml_append(pkg, aml_name("%s", link_name));
514 aml_append(pkg, a_zero);
515 return pkg;
516 }
517
518 /*
519 * initialize_route - Initialize the interrupt routing rule
520 * through a specific LINK:
521 * if (lnk_idx == idx)
522 * route using link 'link_name'
523 */
524 static Aml *initialize_route(Aml *route, const char *link_name,
525 Aml *lnk_idx, int idx)
526 {
527 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
528 Aml *pkg = build_prt_entry(link_name);
529
530 aml_append(if_ctx, aml_store(pkg, route));
531
532 return if_ctx;
533 }
534
535 /*
536 * build_prt - Define interrupt rounting rules
537 *
538 * Returns an array of 128 routes, one for each device,
539 * based on device location.
540 * The main goal is to equaly distribute the interrupts
541 * over the 4 existing ACPI links (works only for i440fx).
542 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
543 *
544 */
545 static Aml *build_prt(bool is_pci0_prt)
546 {
547 Aml *method, *while_ctx, *pin, *res;
548
549 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
550 res = aml_local(0);
551 pin = aml_local(1);
552 aml_append(method, aml_store(aml_package(128), res));
553 aml_append(method, aml_store(aml_int(0), pin));
554
555 /* while (pin < 128) */
556 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
557 {
558 Aml *slot = aml_local(2);
559 Aml *lnk_idx = aml_local(3);
560 Aml *route = aml_local(4);
561
562 /* slot = pin >> 2 */
563 aml_append(while_ctx,
564 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
565 /* lnk_idx = (slot + pin) & 3 */
566 aml_append(while_ctx,
567 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
568 lnk_idx));
569
570 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
571 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
572 if (is_pci0_prt) {
573 Aml *if_device_1, *if_pin_4, *else_pin_4;
574
575 /* device 1 is the power-management device, needs SCI */
576 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
577 {
578 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
579 {
580 aml_append(if_pin_4,
581 aml_store(build_prt_entry("LNKS"), route));
582 }
583 aml_append(if_device_1, if_pin_4);
584 else_pin_4 = aml_else();
585 {
586 aml_append(else_pin_4,
587 aml_store(build_prt_entry("LNKA"), route));
588 }
589 aml_append(if_device_1, else_pin_4);
590 }
591 aml_append(while_ctx, if_device_1);
592 } else {
593 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
594 }
595 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
596 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
597
598 /* route[0] = 0x[slot]FFFF */
599 aml_append(while_ctx,
600 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
601 NULL),
602 aml_index(route, aml_int(0))));
603 /* route[1] = pin & 3 */
604 aml_append(while_ctx,
605 aml_store(aml_and(pin, aml_int(3), NULL),
606 aml_index(route, aml_int(1))));
607 /* res[pin] = route */
608 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
609 /* pin++ */
610 aml_append(while_ctx, aml_increment(pin));
611 }
612 aml_append(method, while_ctx);
613 /* return res*/
614 aml_append(method, aml_return(res));
615
616 return method;
617 }
618
619 typedef struct CrsRangeEntry {
620 uint64_t base;
621 uint64_t limit;
622 } CrsRangeEntry;
623
624 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
625 {
626 CrsRangeEntry *entry;
627
628 entry = g_malloc(sizeof(*entry));
629 entry->base = base;
630 entry->limit = limit;
631
632 g_ptr_array_add(ranges, entry);
633 }
634
635 static void crs_range_free(gpointer data)
636 {
637 CrsRangeEntry *entry = (CrsRangeEntry *)data;
638 g_free(entry);
639 }
640
641 typedef struct CrsRangeSet {
642 GPtrArray *io_ranges;
643 GPtrArray *mem_ranges;
644 GPtrArray *mem_64bit_ranges;
645 } CrsRangeSet;
646
647 static void crs_range_set_init(CrsRangeSet *range_set)
648 {
649 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
650 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
651 range_set->mem_64bit_ranges =
652 g_ptr_array_new_with_free_func(crs_range_free);
653 }
654
655 static void crs_range_set_free(CrsRangeSet *range_set)
656 {
657 g_ptr_array_free(range_set->io_ranges, true);
658 g_ptr_array_free(range_set->mem_ranges, true);
659 g_ptr_array_free(range_set->mem_64bit_ranges, true);
660 }
661
662 static gint crs_range_compare(gconstpointer a, gconstpointer b)
663 {
664 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
665 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
666
667 if (entry_a->base < entry_b->base) {
668 return -1;
669 } else if (entry_a->base > entry_b->base) {
670 return 1;
671 } else {
672 return 0;
673 }
674 }
675
676 /*
677 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
678 * interval, computes the 'free' ranges from the same interval.
679 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
680 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
681 */
682 static void crs_replace_with_free_ranges(GPtrArray *ranges,
683 uint64_t start, uint64_t end)
684 {
685 GPtrArray *free_ranges = g_ptr_array_new();
686 uint64_t free_base = start;
687 int i;
688
689 g_ptr_array_sort(ranges, crs_range_compare);
690 for (i = 0; i < ranges->len; i++) {
691 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
692
693 if (free_base < used->base) {
694 crs_range_insert(free_ranges, free_base, used->base - 1);
695 }
696
697 free_base = used->limit + 1;
698 }
699
700 if (free_base < end) {
701 crs_range_insert(free_ranges, free_base, end);
702 }
703
704 g_ptr_array_set_size(ranges, 0);
705 for (i = 0; i < free_ranges->len; i++) {
706 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
707 }
708
709 g_ptr_array_free(free_ranges, true);
710 }
711
712 /*
713 * crs_range_merge - merges adjacent ranges in the given array.
714 * Array elements are deleted and replaced with the merged ranges.
715 */
716 static void crs_range_merge(GPtrArray *range)
717 {
718 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
719 CrsRangeEntry *entry;
720 uint64_t range_base, range_limit;
721 int i;
722
723 if (!range->len) {
724 return;
725 }
726
727 g_ptr_array_sort(range, crs_range_compare);
728
729 entry = g_ptr_array_index(range, 0);
730 range_base = entry->base;
731 range_limit = entry->limit;
732 for (i = 1; i < range->len; i++) {
733 entry = g_ptr_array_index(range, i);
734 if (entry->base - 1 == range_limit) {
735 range_limit = entry->limit;
736 } else {
737 crs_range_insert(tmp, range_base, range_limit);
738 range_base = entry->base;
739 range_limit = entry->limit;
740 }
741 }
742 crs_range_insert(tmp, range_base, range_limit);
743
744 g_ptr_array_set_size(range, 0);
745 for (i = 0; i < tmp->len; i++) {
746 entry = g_ptr_array_index(tmp, i);
747 crs_range_insert(range, entry->base, entry->limit);
748 }
749 g_ptr_array_free(tmp, true);
750 }
751
752 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
753 {
754 Aml *crs = aml_resource_template();
755 CrsRangeSet temp_range_set;
756 CrsRangeEntry *entry;
757 uint8_t max_bus = pci_bus_num(host->bus);
758 uint8_t type;
759 int devfn;
760 int i;
761
762 crs_range_set_init(&temp_range_set);
763 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
764 uint64_t range_base, range_limit;
765 PCIDevice *dev = host->bus->devices[devfn];
766
767 if (!dev) {
768 continue;
769 }
770
771 for (i = 0; i < PCI_NUM_REGIONS; i++) {
772 PCIIORegion *r = &dev->io_regions[i];
773
774 range_base = r->addr;
775 range_limit = r->addr + r->size - 1;
776
777 /*
778 * Work-around for old bioses
779 * that do not support multiple root buses
780 */
781 if (!range_base || range_base > range_limit) {
782 continue;
783 }
784
785 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
786 crs_range_insert(temp_range_set.io_ranges,
787 range_base, range_limit);
788 } else { /* "memory" */
789 crs_range_insert(temp_range_set.mem_ranges,
790 range_base, range_limit);
791 }
792 }
793
794 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
795 if (type == PCI_HEADER_TYPE_BRIDGE) {
796 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
797 if (subordinate > max_bus) {
798 max_bus = subordinate;
799 }
800
801 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
802 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
803
804 /*
805 * Work-around for old bioses
806 * that do not support multiple root buses
807 */
808 if (range_base && range_base <= range_limit) {
809 crs_range_insert(temp_range_set.io_ranges,
810 range_base, range_limit);
811 }
812
813 range_base =
814 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
815 range_limit =
816 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
817
818 /*
819 * Work-around for old bioses
820 * that do not support multiple root buses
821 */
822 if (range_base && range_base <= range_limit) {
823 uint64_t length = range_limit - range_base + 1;
824 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
825 crs_range_insert(temp_range_set.mem_ranges,
826 range_base, range_limit);
827 } else {
828 crs_range_insert(temp_range_set.mem_64bit_ranges,
829 range_base, range_limit);
830 }
831 }
832
833 range_base =
834 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
835 range_limit =
836 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
837
838 /*
839 * Work-around for old bioses
840 * that do not support multiple root buses
841 */
842 if (range_base && range_base <= range_limit) {
843 uint64_t length = range_limit - range_base + 1;
844 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
845 crs_range_insert(temp_range_set.mem_ranges,
846 range_base, range_limit);
847 } else {
848 crs_range_insert(temp_range_set.mem_64bit_ranges,
849 range_base, range_limit);
850 }
851 }
852 }
853 }
854
855 crs_range_merge(temp_range_set.io_ranges);
856 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
857 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
858 aml_append(crs,
859 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
860 AML_POS_DECODE, AML_ENTIRE_RANGE,
861 0, entry->base, entry->limit, 0,
862 entry->limit - entry->base + 1));
863 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
864 }
865
866 crs_range_merge(temp_range_set.mem_ranges);
867 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
868 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
869 aml_append(crs,
870 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
871 AML_MAX_FIXED, AML_NON_CACHEABLE,
872 AML_READ_WRITE,
873 0, entry->base, entry->limit, 0,
874 entry->limit - entry->base + 1));
875 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
876 }
877
878 crs_range_merge(temp_range_set.mem_64bit_ranges);
879 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
880 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
881 aml_append(crs,
882 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
883 AML_MAX_FIXED, AML_NON_CACHEABLE,
884 AML_READ_WRITE,
885 0, entry->base, entry->limit, 0,
886 entry->limit - entry->base + 1));
887 crs_range_insert(range_set->mem_64bit_ranges,
888 entry->base, entry->limit);
889 }
890
891 crs_range_set_free(&temp_range_set);
892
893 aml_append(crs,
894 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
895 0,
896 pci_bus_num(host->bus),
897 max_bus,
898 0,
899 max_bus - pci_bus_num(host->bus) + 1));
900
901 return crs;
902 }
903
904 static void build_hpet_aml(Aml *table)
905 {
906 Aml *crs;
907 Aml *field;
908 Aml *method;
909 Aml *if_ctx;
910 Aml *scope = aml_scope("_SB");
911 Aml *dev = aml_device("HPET");
912 Aml *zero = aml_int(0);
913 Aml *id = aml_local(0);
914 Aml *period = aml_local(1);
915
916 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
917 aml_append(dev, aml_name_decl("_UID", zero));
918
919 aml_append(dev,
920 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
921 HPET_LEN));
922 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
923 aml_append(field, aml_named_field("VEND", 32));
924 aml_append(field, aml_named_field("PRD", 32));
925 aml_append(dev, field);
926
927 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
928 aml_append(method, aml_store(aml_name("VEND"), id));
929 aml_append(method, aml_store(aml_name("PRD"), period));
930 aml_append(method, aml_shiftright(id, aml_int(16), id));
931 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
932 aml_equal(id, aml_int(0xffff))));
933 {
934 aml_append(if_ctx, aml_return(zero));
935 }
936 aml_append(method, if_ctx);
937
938 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
939 aml_lgreater(period, aml_int(100000000))));
940 {
941 aml_append(if_ctx, aml_return(zero));
942 }
943 aml_append(method, if_ctx);
944
945 aml_append(method, aml_return(aml_int(0x0F)));
946 aml_append(dev, method);
947
948 crs = aml_resource_template();
949 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
950 aml_append(dev, aml_name_decl("_CRS", crs));
951
952 aml_append(scope, dev);
953 aml_append(table, scope);
954 }
955
956 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
957 {
958 Aml *dev;
959 Aml *method;
960 Aml *crs;
961
962 dev = aml_device("VMBS");
963 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
964 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
965 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
966 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
967
968 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
969 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
970 aml_name("STA")));
971 aml_append(dev, method);
972
973 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
974 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
975 aml_name("STA")));
976 aml_append(dev, method);
977
978 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
979 aml_append(method, aml_return(aml_name("STA")));
980 aml_append(dev, method);
981
982 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
983
984 crs = aml_resource_template();
985 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
986 aml_append(dev, aml_name_decl("_CRS", crs));
987
988 return dev;
989 }
990
991 static void build_isa_devices_aml(Aml *table)
992 {
993 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
994 bool ambiguous;
995 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
996 Aml *scope;
997
998 assert(obj && !ambiguous);
999
1000 scope = aml_scope("_SB.PCI0.ISA");
1001 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
1002 isa_build_aml(ISA_BUS(obj), scope);
1003
1004 if (vmbus_bridge) {
1005 aml_append(scope, build_vmbus_device_aml(vmbus_bridge));
1006 }
1007
1008 aml_append(table, scope);
1009 }
1010
1011 static void build_dbg_aml(Aml *table)
1012 {
1013 Aml *field;
1014 Aml *method;
1015 Aml *while_ctx;
1016 Aml *scope = aml_scope("\\");
1017 Aml *buf = aml_local(0);
1018 Aml *len = aml_local(1);
1019 Aml *idx = aml_local(2);
1020
1021 aml_append(scope,
1022 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1023 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1024 aml_append(field, aml_named_field("DBGB", 8));
1025 aml_append(scope, field);
1026
1027 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1028
1029 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1030 aml_append(method, aml_to_buffer(buf, buf));
1031 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1032 aml_append(method, aml_store(aml_int(0), idx));
1033
1034 while_ctx = aml_while(aml_lless(idx, len));
1035 aml_append(while_ctx,
1036 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1037 aml_append(while_ctx, aml_increment(idx));
1038 aml_append(method, while_ctx);
1039
1040 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1041 aml_append(scope, method);
1042
1043 aml_append(table, scope);
1044 }
1045
1046 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1047 {
1048 Aml *dev;
1049 Aml *crs;
1050 Aml *method;
1051 uint32_t irqs[] = {5, 10, 11};
1052
1053 dev = aml_device("%s", name);
1054 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1055 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1056
1057 crs = aml_resource_template();
1058 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1059 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1060 aml_append(dev, aml_name_decl("_PRS", crs));
1061
1062 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1063 aml_append(method, aml_return(aml_call1("IQST", reg)));
1064 aml_append(dev, method);
1065
1066 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1067 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1068 aml_append(dev, method);
1069
1070 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1071 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1072 aml_append(dev, method);
1073
1074 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1075 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1076 aml_append(method, aml_store(aml_name("PRRI"), reg));
1077 aml_append(dev, method);
1078
1079 return dev;
1080 }
1081
1082 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1083 {
1084 Aml *dev;
1085 Aml *crs;
1086 Aml *method;
1087 uint32_t irqs;
1088
1089 dev = aml_device("%s", name);
1090 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1091 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1092
1093 crs = aml_resource_template();
1094 irqs = gsi;
1095 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1096 AML_SHARED, &irqs, 1));
1097 aml_append(dev, aml_name_decl("_PRS", crs));
1098
1099 aml_append(dev, aml_name_decl("_CRS", crs));
1100
1101 /*
1102 * _DIS can be no-op because the interrupt cannot be disabled.
1103 */
1104 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1105 aml_append(dev, method);
1106
1107 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1108 aml_append(dev, method);
1109
1110 return dev;
1111 }
1112
1113 /* _CRS method - get current settings */
1114 static Aml *build_iqcr_method(bool is_piix4)
1115 {
1116 Aml *if_ctx;
1117 uint32_t irqs;
1118 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1119 Aml *crs = aml_resource_template();
1120
1121 irqs = 0;
1122 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1123 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1124 aml_append(method, aml_name_decl("PRR0", crs));
1125
1126 aml_append(method,
1127 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1128
1129 if (is_piix4) {
1130 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1131 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1132 aml_append(method, if_ctx);
1133 } else {
1134 aml_append(method,
1135 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1136 aml_name("PRRI")));
1137 }
1138
1139 aml_append(method, aml_return(aml_name("PRR0")));
1140 return method;
1141 }
1142
1143 /* _STA method - get status */
1144 static Aml *build_irq_status_method(void)
1145 {
1146 Aml *if_ctx;
1147 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1148
1149 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1150 aml_append(if_ctx, aml_return(aml_int(0x09)));
1151 aml_append(method, if_ctx);
1152 aml_append(method, aml_return(aml_int(0x0B)));
1153 return method;
1154 }
1155
1156 static void build_piix4_pci0_int(Aml *table)
1157 {
1158 Aml *dev;
1159 Aml *crs;
1160 Aml *field;
1161 Aml *method;
1162 uint32_t irqs;
1163 Aml *sb_scope = aml_scope("_SB");
1164 Aml *pci0_scope = aml_scope("PCI0");
1165
1166 aml_append(pci0_scope, build_prt(true));
1167 aml_append(sb_scope, pci0_scope);
1168
1169 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1170 aml_append(field, aml_named_field("PRQ0", 8));
1171 aml_append(field, aml_named_field("PRQ1", 8));
1172 aml_append(field, aml_named_field("PRQ2", 8));
1173 aml_append(field, aml_named_field("PRQ3", 8));
1174 aml_append(sb_scope, field);
1175
1176 aml_append(sb_scope, build_irq_status_method());
1177 aml_append(sb_scope, build_iqcr_method(true));
1178
1179 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1180 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1181 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1182 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1183
1184 dev = aml_device("LNKS");
1185 {
1186 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1187 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1188
1189 crs = aml_resource_template();
1190 irqs = 9;
1191 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1192 AML_ACTIVE_HIGH, AML_SHARED,
1193 &irqs, 1));
1194 aml_append(dev, aml_name_decl("_PRS", crs));
1195
1196 /* The SCI cannot be disabled and is always attached to GSI 9,
1197 * so these are no-ops. We only need this link to override the
1198 * polarity to active high and match the content of the MADT.
1199 */
1200 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1201 aml_append(method, aml_return(aml_int(0x0b)));
1202 aml_append(dev, method);
1203
1204 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1205 aml_append(dev, method);
1206
1207 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1208 aml_append(method, aml_return(aml_name("_PRS")));
1209 aml_append(dev, method);
1210
1211 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1212 aml_append(dev, method);
1213 }
1214 aml_append(sb_scope, dev);
1215
1216 aml_append(table, sb_scope);
1217 }
1218
1219 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1220 {
1221 int i;
1222 int head;
1223 Aml *pkg;
1224 char base = name[3] < 'E' ? 'A' : 'E';
1225 char *s = g_strdup(name);
1226 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1227
1228 assert(strlen(s) == 4);
1229
1230 head = name[3] - base;
1231 for (i = 0; i < 4; i++) {
1232 if (head + i > 3) {
1233 head = i * -1;
1234 }
1235 s[3] = base + head + i;
1236 pkg = aml_package(4);
1237 aml_append(pkg, a_nr);
1238 aml_append(pkg, aml_int(i));
1239 aml_append(pkg, aml_name("%s", s));
1240 aml_append(pkg, aml_int(0));
1241 aml_append(ctx, pkg);
1242 }
1243 g_free(s);
1244 }
1245
1246 static Aml *build_q35_routing_table(const char *str)
1247 {
1248 int i;
1249 Aml *pkg;
1250 char *name = g_strdup_printf("%s ", str);
1251
1252 pkg = aml_package(128);
1253 for (i = 0; i < 0x18; i++) {
1254 name[3] = 'E' + (i & 0x3);
1255 append_q35_prt_entry(pkg, i, name);
1256 }
1257
1258 name[3] = 'E';
1259 append_q35_prt_entry(pkg, 0x18, name);
1260
1261 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1262 for (i = 0x0019; i < 0x1e; i++) {
1263 name[3] = 'A';
1264 append_q35_prt_entry(pkg, i, name);
1265 }
1266
1267 /* PCIe->PCI bridge. use PIRQ[E-H] */
1268 name[3] = 'E';
1269 append_q35_prt_entry(pkg, 0x1e, name);
1270 name[3] = 'A';
1271 append_q35_prt_entry(pkg, 0x1f, name);
1272
1273 g_free(name);
1274 return pkg;
1275 }
1276
1277 static void build_q35_pci0_int(Aml *table)
1278 {
1279 Aml *field;
1280 Aml *method;
1281 Aml *sb_scope = aml_scope("_SB");
1282 Aml *pci0_scope = aml_scope("PCI0");
1283
1284 /* Zero => PIC mode, One => APIC Mode */
1285 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1286 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1287 {
1288 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1289 }
1290 aml_append(table, method);
1291
1292 aml_append(pci0_scope,
1293 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1294 aml_append(pci0_scope,
1295 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1296
1297 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1298 {
1299 Aml *if_ctx;
1300 Aml *else_ctx;
1301
1302 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1303 section 6.2.8.1 */
1304 /* Note: we provide the same info as the PCI routing
1305 table of the Bochs BIOS */
1306 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1307 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1308 aml_append(method, if_ctx);
1309 else_ctx = aml_else();
1310 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1311 aml_append(method, else_ctx);
1312 }
1313 aml_append(pci0_scope, method);
1314 aml_append(sb_scope, pci0_scope);
1315
1316 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1317 aml_append(field, aml_named_field("PRQA", 8));
1318 aml_append(field, aml_named_field("PRQB", 8));
1319 aml_append(field, aml_named_field("PRQC", 8));
1320 aml_append(field, aml_named_field("PRQD", 8));
1321 aml_append(field, aml_reserved_field(0x20));
1322 aml_append(field, aml_named_field("PRQE", 8));
1323 aml_append(field, aml_named_field("PRQF", 8));
1324 aml_append(field, aml_named_field("PRQG", 8));
1325 aml_append(field, aml_named_field("PRQH", 8));
1326 aml_append(sb_scope, field);
1327
1328 aml_append(sb_scope, build_irq_status_method());
1329 aml_append(sb_scope, build_iqcr_method(false));
1330
1331 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1332 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1333 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1334 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1335 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1336 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1337 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1338 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1339
1340 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1341 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1342 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1343 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1344 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1345 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1346 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1347 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1348
1349 aml_append(table, sb_scope);
1350 }
1351
1352 static void build_q35_isa_bridge(Aml *table)
1353 {
1354 Aml *dev;
1355 Aml *scope;
1356
1357 scope = aml_scope("_SB.PCI0");
1358 dev = aml_device("ISA");
1359 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1360
1361 /* ICH9 PCI to ISA irq remapping */
1362 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1363 aml_int(0x60), 0x0C));
1364
1365 aml_append(scope, dev);
1366 aml_append(table, scope);
1367 }
1368
1369 static void build_piix4_isa_bridge(Aml *table)
1370 {
1371 Aml *dev;
1372 Aml *scope;
1373
1374 scope = aml_scope("_SB.PCI0");
1375 dev = aml_device("ISA");
1376 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1377
1378 /* PIIX PCI to ISA irq remapping */
1379 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1380 aml_int(0x60), 0x04));
1381
1382 aml_append(scope, dev);
1383 aml_append(table, scope);
1384 }
1385
1386 static void build_piix4_pci_hotplug(Aml *table)
1387 {
1388 Aml *scope;
1389 Aml *field;
1390 Aml *method;
1391
1392 scope = aml_scope("_SB.PCI0");
1393
1394 aml_append(scope,
1395 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1396 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1397 aml_append(field, aml_named_field("PCIU", 32));
1398 aml_append(field, aml_named_field("PCID", 32));
1399 aml_append(scope, field);
1400
1401 aml_append(scope,
1402 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1403 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1404 aml_append(field, aml_named_field("B0EJ", 32));
1405 aml_append(scope, field);
1406
1407 aml_append(scope,
1408 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1409 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1410 aml_append(field, aml_named_field("BNUM", 32));
1411 aml_append(scope, field);
1412
1413 aml_append(scope, aml_mutex("BLCK", 0));
1414
1415 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1416 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1417 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1418 aml_append(method,
1419 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1420 aml_append(method, aml_release(aml_name("BLCK")));
1421 aml_append(method, aml_return(aml_int(0)));
1422 aml_append(scope, method);
1423
1424 aml_append(table, scope);
1425 }
1426
1427 static Aml *build_q35_osc_method(void)
1428 {
1429 Aml *if_ctx;
1430 Aml *if_ctx2;
1431 Aml *else_ctx;
1432 Aml *method;
1433 Aml *a_cwd1 = aml_name("CDW1");
1434 Aml *a_ctrl = aml_local(0);
1435
1436 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1437 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1438
1439 if_ctx = aml_if(aml_equal(
1440 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1441 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1442 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1443
1444 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1445
1446 /*
1447 * Always allow native PME, AER (no dependencies)
1448 * Allow SHPC (PCI bridges can have SHPC controller)
1449 */
1450 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1451
1452 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1453 /* Unknown revision */
1454 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1455 aml_append(if_ctx, if_ctx2);
1456
1457 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1458 /* Capabilities bits were masked */
1459 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1460 aml_append(if_ctx, if_ctx2);
1461
1462 /* Update DWORD3 in the buffer */
1463 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1464 aml_append(method, if_ctx);
1465
1466 else_ctx = aml_else();
1467 /* Unrecognized UUID */
1468 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1469 aml_append(method, else_ctx);
1470
1471 aml_append(method, aml_return(aml_arg(3)));
1472 return method;
1473 }
1474
1475 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1476 {
1477 Aml *scope = aml_scope("_SB.PCI0");
1478 Aml *dev = aml_device("SMB0");
1479
1480 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1481 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1482 aml_append(scope, dev);
1483 aml_append(table, scope);
1484 }
1485
1486 static void
1487 build_dsdt(GArray *table_data, BIOSLinker *linker,
1488 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1489 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1490 {
1491 CrsRangeEntry *entry;
1492 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1493 CrsRangeSet crs_range_set;
1494 PCMachineState *pcms = PC_MACHINE(machine);
1495 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1496 X86MachineState *x86ms = X86_MACHINE(machine);
1497 AcpiMcfgInfo mcfg;
1498 uint32_t nr_mem = machine->ram_slots;
1499 int root_bus_limit = 0xFF;
1500 PCIBus *bus = NULL;
1501 TPMIf *tpm = tpm_find();
1502 int i;
1503
1504 dsdt = init_aml_allocator();
1505
1506 /* Reserve space for header */
1507 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1508
1509 build_dbg_aml(dsdt);
1510 if (misc->is_piix4) {
1511 sb_scope = aml_scope("_SB");
1512 dev = aml_device("PCI0");
1513 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1514 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1515 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1516 aml_append(sb_scope, dev);
1517 aml_append(dsdt, sb_scope);
1518
1519 build_hpet_aml(dsdt);
1520 build_piix4_isa_bridge(dsdt);
1521 build_isa_devices_aml(dsdt);
1522 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1523 build_piix4_pci_hotplug(dsdt);
1524 }
1525 build_piix4_pci0_int(dsdt);
1526 } else {
1527 sb_scope = aml_scope("_SB");
1528 dev = aml_device("PCI0");
1529 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1530 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1531 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1532 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1533 aml_append(dev, build_q35_osc_method());
1534 aml_append(sb_scope, dev);
1535
1536 if (pm->smi_on_cpuhp) {
1537 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1538 dev = aml_device("PCI0.SMI0");
1539 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1540 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1541 crs = aml_resource_template();
1542 aml_append(crs,
1543 aml_io(
1544 AML_DECODE16,
1545 ACPI_PORT_SMI_CMD,
1546 ACPI_PORT_SMI_CMD,
1547 1,
1548 2)
1549 );
1550 aml_append(dev, aml_name_decl("_CRS", crs));
1551 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1552 aml_int(ACPI_PORT_SMI_CMD), 2));
1553 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1554 AML_WRITE_AS_ZEROS);
1555 aml_append(field, aml_named_field("SMIC", 8));
1556 aml_append(field, aml_reserved_field(8));
1557 aml_append(dev, field);
1558 aml_append(sb_scope, dev);
1559 }
1560
1561 aml_append(dsdt, sb_scope);
1562
1563 build_hpet_aml(dsdt);
1564 build_q35_isa_bridge(dsdt);
1565 build_isa_devices_aml(dsdt);
1566 build_q35_pci0_int(dsdt);
1567 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1568 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1569 }
1570 }
1571
1572 if (pcmc->legacy_cpu_hotplug) {
1573 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1574 } else {
1575 CPUHotplugFeatures opts = {
1576 .acpi_1_compatible = true, .has_legacy_cphp = true,
1577 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1578 };
1579 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1580 "\\_SB.PCI0", "\\_GPE._E02");
1581 }
1582
1583 if (pcms->memhp_io_base && nr_mem) {
1584 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1585 "\\_GPE._E03", AML_SYSTEM_IO,
1586 pcms->memhp_io_base);
1587 }
1588
1589 scope = aml_scope("_GPE");
1590 {
1591 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1592
1593 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1594 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1595 aml_append(method,
1596 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1597 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1598 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1599 aml_append(scope, method);
1600 }
1601
1602 if (machine->nvdimms_state->is_enabled) {
1603 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1604 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1605 aml_int(0x80)));
1606 aml_append(scope, method);
1607 }
1608 }
1609 aml_append(dsdt, scope);
1610
1611 crs_range_set_init(&crs_range_set);
1612 bus = PC_MACHINE(machine)->bus;
1613 if (bus) {
1614 QLIST_FOREACH(bus, &bus->child, sibling) {
1615 uint8_t bus_num = pci_bus_num(bus);
1616 uint8_t numa_node = pci_bus_numa_node(bus);
1617
1618 /* look only for expander root buses */
1619 if (!pci_bus_is_root(bus)) {
1620 continue;
1621 }
1622
1623 if (bus_num < root_bus_limit) {
1624 root_bus_limit = bus_num - 1;
1625 }
1626
1627 scope = aml_scope("\\_SB");
1628 dev = aml_device("PC%.02X", bus_num);
1629 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1630 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1631 if (pci_bus_is_express(bus)) {
1632 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1633 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1634 aml_append(dev, build_q35_osc_method());
1635 } else {
1636 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1637 }
1638
1639 if (numa_node != NUMA_NODE_UNASSIGNED) {
1640 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1641 }
1642
1643 aml_append(dev, build_prt(false));
1644 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1645 aml_append(dev, aml_name_decl("_CRS", crs));
1646 aml_append(scope, dev);
1647 aml_append(dsdt, scope);
1648 }
1649 }
1650
1651 /*
1652 * At this point crs_range_set has all the ranges used by pci
1653 * busses *other* than PCI0. These ranges will be excluded from
1654 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1655 * too.
1656 */
1657 if (acpi_get_mcfg(&mcfg)) {
1658 crs_range_insert(crs_range_set.mem_ranges,
1659 mcfg.base, mcfg.base + mcfg.size - 1);
1660 }
1661
1662 scope = aml_scope("\\_SB.PCI0");
1663 /* build PCI0._CRS */
1664 crs = aml_resource_template();
1665 aml_append(crs,
1666 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1667 0x0000, 0x0, root_bus_limit,
1668 0x0000, root_bus_limit + 1));
1669 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1670
1671 aml_append(crs,
1672 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1673 AML_POS_DECODE, AML_ENTIRE_RANGE,
1674 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1675
1676 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1677 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1678 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1679 aml_append(crs,
1680 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1681 AML_POS_DECODE, AML_ENTIRE_RANGE,
1682 0x0000, entry->base, entry->limit,
1683 0x0000, entry->limit - entry->base + 1));
1684 }
1685
1686 aml_append(crs,
1687 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1688 AML_CACHEABLE, AML_READ_WRITE,
1689 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1690
1691 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1692 range_lob(pci_hole),
1693 range_upb(pci_hole));
1694 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1695 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1696 aml_append(crs,
1697 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1698 AML_NON_CACHEABLE, AML_READ_WRITE,
1699 0, entry->base, entry->limit,
1700 0, entry->limit - entry->base + 1));
1701 }
1702
1703 if (!range_is_empty(pci_hole64)) {
1704 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1705 range_lob(pci_hole64),
1706 range_upb(pci_hole64));
1707 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1708 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1709 aml_append(crs,
1710 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1711 AML_MAX_FIXED,
1712 AML_CACHEABLE, AML_READ_WRITE,
1713 0, entry->base, entry->limit,
1714 0, entry->limit - entry->base + 1));
1715 }
1716 }
1717
1718 if (TPM_IS_TIS_ISA(tpm_find())) {
1719 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1720 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1721 }
1722 aml_append(scope, aml_name_decl("_CRS", crs));
1723
1724 /* reserve GPE0 block resources */
1725 dev = aml_device("GPE0");
1726 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1727 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1728 /* device present, functioning, decoding, not shown in UI */
1729 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1730 crs = aml_resource_template();
1731 aml_append(crs,
1732 aml_io(
1733 AML_DECODE16,
1734 pm->fadt.gpe0_blk.address,
1735 pm->fadt.gpe0_blk.address,
1736 1,
1737 pm->fadt.gpe0_blk.bit_width / 8)
1738 );
1739 aml_append(dev, aml_name_decl("_CRS", crs));
1740 aml_append(scope, dev);
1741
1742 crs_range_set_free(&crs_range_set);
1743
1744 /* reserve PCIHP resources */
1745 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1746 dev = aml_device("PHPR");
1747 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1748 aml_append(dev,
1749 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1750 /* device present, functioning, decoding, not shown in UI */
1751 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1752 crs = aml_resource_template();
1753 aml_append(crs,
1754 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1755 pm->pcihp_io_len)
1756 );
1757 aml_append(dev, aml_name_decl("_CRS", crs));
1758 aml_append(scope, dev);
1759 }
1760 aml_append(dsdt, scope);
1761
1762 /* create S3_ / S4_ / S5_ packages if necessary */
1763 scope = aml_scope("\\");
1764 if (!pm->s3_disabled) {
1765 pkg = aml_package(4);
1766 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1767 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1768 aml_append(pkg, aml_int(0)); /* reserved */
1769 aml_append(pkg, aml_int(0)); /* reserved */
1770 aml_append(scope, aml_name_decl("_S3", pkg));
1771 }
1772
1773 if (!pm->s4_disabled) {
1774 pkg = aml_package(4);
1775 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1776 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1777 aml_append(pkg, aml_int(pm->s4_val));
1778 aml_append(pkg, aml_int(0)); /* reserved */
1779 aml_append(pkg, aml_int(0)); /* reserved */
1780 aml_append(scope, aml_name_decl("_S4", pkg));
1781 }
1782
1783 pkg = aml_package(4);
1784 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1785 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1786 aml_append(pkg, aml_int(0)); /* reserved */
1787 aml_append(pkg, aml_int(0)); /* reserved */
1788 aml_append(scope, aml_name_decl("_S5", pkg));
1789 aml_append(dsdt, scope);
1790
1791 /* create fw_cfg node, unconditionally */
1792 {
1793 scope = aml_scope("\\_SB.PCI0");
1794 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1795 aml_append(dsdt, scope);
1796 }
1797
1798 if (misc->applesmc_io_base) {
1799 scope = aml_scope("\\_SB.PCI0.ISA");
1800 dev = aml_device("SMC");
1801
1802 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1803 /* device present, functioning, decoding, not shown in UI */
1804 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1805
1806 crs = aml_resource_template();
1807 aml_append(crs,
1808 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1809 0x01, APPLESMC_MAX_DATA_LENGTH)
1810 );
1811 aml_append(crs, aml_irq_no_flags(6));
1812 aml_append(dev, aml_name_decl("_CRS", crs));
1813
1814 aml_append(scope, dev);
1815 aml_append(dsdt, scope);
1816 }
1817
1818 if (misc->pvpanic_port) {
1819 scope = aml_scope("\\_SB.PCI0.ISA");
1820
1821 dev = aml_device("PEVT");
1822 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1823
1824 crs = aml_resource_template();
1825 aml_append(crs,
1826 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1827 );
1828 aml_append(dev, aml_name_decl("_CRS", crs));
1829
1830 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1831 aml_int(misc->pvpanic_port), 1));
1832 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1833 aml_append(field, aml_named_field("PEPT", 8));
1834 aml_append(dev, field);
1835
1836 /* device present, functioning, decoding, shown in UI */
1837 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1838
1839 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1840 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1841 aml_append(method, aml_return(aml_local(0)));
1842 aml_append(dev, method);
1843
1844 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1845 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1846 aml_append(dev, method);
1847
1848 aml_append(scope, dev);
1849 aml_append(dsdt, scope);
1850 }
1851
1852 sb_scope = aml_scope("\\_SB");
1853 {
1854 Object *pci_host;
1855 PCIBus *bus = NULL;
1856
1857 pci_host = acpi_get_i386_pci_host();
1858 if (pci_host) {
1859 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1860 }
1861
1862 if (bus) {
1863 Aml *scope = aml_scope("PCI0");
1864 /* Scan all PCI buses. Generate tables to support hotplug. */
1865 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1866
1867 if (TPM_IS_TIS_ISA(tpm)) {
1868 if (misc->tpm_version == TPM_VERSION_2_0) {
1869 dev = aml_device("TPM");
1870 aml_append(dev, aml_name_decl("_HID",
1871 aml_string("MSFT0101")));
1872 } else {
1873 dev = aml_device("ISA.TPM");
1874 aml_append(dev, aml_name_decl("_HID",
1875 aml_eisaid("PNP0C31")));
1876 }
1877
1878 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1879 crs = aml_resource_template();
1880 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1881 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1882 /*
1883 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1884 Rewrite to take IRQ from TPM device model and
1885 fix default IRQ value there to use some unused IRQ
1886 */
1887 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1888 aml_append(dev, aml_name_decl("_CRS", crs));
1889
1890 tpm_build_ppi_acpi(tpm, dev);
1891
1892 aml_append(scope, dev);
1893 }
1894
1895 aml_append(sb_scope, scope);
1896 }
1897 }
1898
1899 if (TPM_IS_CRB(tpm)) {
1900 dev = aml_device("TPM");
1901 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1902 crs = aml_resource_template();
1903 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1904 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1905 aml_append(dev, aml_name_decl("_CRS", crs));
1906
1907 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1908
1909 tpm_build_ppi_acpi(tpm, dev);
1910
1911 aml_append(sb_scope, dev);
1912 }
1913
1914 aml_append(dsdt, sb_scope);
1915
1916 /* copy AML table into ACPI tables blob and patch header there */
1917 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1918 build_header(linker, table_data,
1919 (void *)(table_data->data + table_data->len - dsdt->buf->len),
1920 "DSDT", dsdt->buf->len, 1, NULL, NULL);
1921 free_aml_allocator();
1922 }
1923
1924 static void
1925 build_hpet(GArray *table_data, BIOSLinker *linker)
1926 {
1927 Acpi20Hpet *hpet;
1928
1929 hpet = acpi_data_push(table_data, sizeof(*hpet));
1930 /* Note timer_block_id value must be kept in sync with value advertised by
1931 * emulated hpet
1932 */
1933 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1934 hpet->addr.address = cpu_to_le64(HPET_BASE);
1935 build_header(linker, table_data,
1936 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
1937 }
1938
1939 static void
1940 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
1941 {
1942 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1943 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
1944 unsigned log_addr_offset =
1945 (char *)&tcpa->log_area_start_address - table_data->data;
1946
1947 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1948 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1949 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
1950
1951 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1952 false /* high memory */);
1953
1954 /* log area start address to be filled by Guest linker */
1955 bios_linker_loader_add_pointer(linker,
1956 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
1957 ACPI_BUILD_TPMLOG_FILE, 0);
1958
1959 build_header(linker, table_data,
1960 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
1961 }
1962
1963 #define HOLE_640K_START (640 * KiB)
1964 #define HOLE_640K_END (1 * MiB)
1965
1966 static void
1967 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1968 {
1969 AcpiSystemResourceAffinityTable *srat;
1970 AcpiSratMemoryAffinity *numamem;
1971
1972 int i;
1973 int srat_start, numa_start, slots;
1974 uint64_t mem_len, mem_base, next_base;
1975 MachineClass *mc = MACHINE_GET_CLASS(machine);
1976 X86MachineState *x86ms = X86_MACHINE(machine);
1977 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1978 PCMachineState *pcms = PC_MACHINE(machine);
1979 ram_addr_t hotplugabble_address_space_size =
1980 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1981 NULL);
1982
1983 srat_start = table_data->len;
1984
1985 srat = acpi_data_push(table_data, sizeof *srat);
1986 srat->reserved1 = cpu_to_le32(1);
1987
1988 for (i = 0; i < apic_ids->len; i++) {
1989 int node_id = apic_ids->cpus[i].props.node_id;
1990 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1991
1992 if (apic_id < 255) {
1993 AcpiSratProcessorAffinity *core;
1994
1995 core = acpi_data_push(table_data, sizeof *core);
1996 core->type = ACPI_SRAT_PROCESSOR_APIC;
1997 core->length = sizeof(*core);
1998 core->local_apic_id = apic_id;
1999 core->proximity_lo = node_id;
2000 memset(core->proximity_hi, 0, 3);
2001 core->local_sapic_eid = 0;
2002 core->flags = cpu_to_le32(1);
2003 } else {
2004 AcpiSratProcessorX2ApicAffinity *core;
2005
2006 core = acpi_data_push(table_data, sizeof *core);
2007 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2008 core->length = sizeof(*core);
2009 core->x2apic_id = cpu_to_le32(apic_id);
2010 core->proximity_domain = cpu_to_le32(node_id);
2011 core->flags = cpu_to_le32(1);
2012 }
2013 }
2014
2015
2016 /* the memory map is a bit tricky, it contains at least one hole
2017 * from 640k-1M and possibly another one from 3.5G-4G.
2018 */
2019 next_base = 0;
2020 numa_start = table_data->len;
2021
2022 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2023 mem_base = next_base;
2024 mem_len = pcms->node_mem[i - 1];
2025 next_base = mem_base + mem_len;
2026
2027 /* Cut out the 640K hole */
2028 if (mem_base <= HOLE_640K_START &&
2029 next_base > HOLE_640K_START) {
2030 mem_len -= next_base - HOLE_640K_START;
2031 if (mem_len > 0) {
2032 numamem = acpi_data_push(table_data, sizeof *numamem);
2033 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2034 MEM_AFFINITY_ENABLED);
2035 }
2036
2037 /* Check for the rare case: 640K < RAM < 1M */
2038 if (next_base <= HOLE_640K_END) {
2039 next_base = HOLE_640K_END;
2040 continue;
2041 }
2042 mem_base = HOLE_640K_END;
2043 mem_len = next_base - HOLE_640K_END;
2044 }
2045
2046 /* Cut out the ACPI_PCI hole */
2047 if (mem_base <= x86ms->below_4g_mem_size &&
2048 next_base > x86ms->below_4g_mem_size) {
2049 mem_len -= next_base - x86ms->below_4g_mem_size;
2050 if (mem_len > 0) {
2051 numamem = acpi_data_push(table_data, sizeof *numamem);
2052 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2053 MEM_AFFINITY_ENABLED);
2054 }
2055 mem_base = 1ULL << 32;
2056 mem_len = next_base - x86ms->below_4g_mem_size;
2057 next_base = mem_base + mem_len;
2058 }
2059
2060 if (mem_len > 0) {
2061 numamem = acpi_data_push(table_data, sizeof *numamem);
2062 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2063 MEM_AFFINITY_ENABLED);
2064 }
2065 }
2066
2067 if (machine->nvdimms_state->is_enabled) {
2068 nvdimm_build_srat(table_data);
2069 }
2070
2071 slots = (table_data->len - numa_start) / sizeof *numamem;
2072 for (; slots < pcms->numa_nodes + 2; slots++) {
2073 numamem = acpi_data_push(table_data, sizeof *numamem);
2074 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2075 }
2076
2077 /*
2078 * Entry is required for Windows to enable memory hotplug in OS
2079 * and for Linux to enable SWIOTLB when booted with less than
2080 * 4G of RAM. Windows works better if the entry sets proximity
2081 * to the highest NUMA node in the machine.
2082 * Memory devices may override proximity set by this entry,
2083 * providing _PXM method if necessary.
2084 */
2085 if (hotplugabble_address_space_size) {
2086 numamem = acpi_data_push(table_data, sizeof *numamem);
2087 build_srat_memory(numamem, machine->device_memory->base,
2088 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2089 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2090 }
2091
2092 build_header(linker, table_data,
2093 (void *)(table_data->data + srat_start),
2094 "SRAT",
2095 table_data->len - srat_start, 1, NULL, NULL);
2096 }
2097
2098 /*
2099 * VT-d spec 8.1 DMA Remapping Reporting Structure
2100 * (version Oct. 2014 or later)
2101 */
2102 static void
2103 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2104 {
2105 int dmar_start = table_data->len;
2106
2107 AcpiTableDmar *dmar;
2108 AcpiDmarHardwareUnit *drhd;
2109 AcpiDmarRootPortATS *atsr;
2110 uint8_t dmar_flags = 0;
2111 X86IOMMUState *iommu = x86_iommu_get_default();
2112 AcpiDmarDeviceScope *scope = NULL;
2113 /* Root complex IOAPIC use one path[0] only */
2114 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2115 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2116
2117 assert(iommu);
2118 if (x86_iommu_ir_supported(iommu)) {
2119 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2120 }
2121
2122 dmar = acpi_data_push(table_data, sizeof(*dmar));
2123 dmar->host_address_width = intel_iommu->aw_bits - 1;
2124 dmar->flags = dmar_flags;
2125
2126 /* DMAR Remapping Hardware Unit Definition structure */
2127 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2128 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2129 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2130 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2131 drhd->pci_segment = cpu_to_le16(0);
2132 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2133
2134 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2135 * 8.3.1 (version Oct. 2014 or later). */
2136 scope = &drhd->scope[0];
2137 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2138 scope->length = ioapic_scope_size;
2139 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2140 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2141 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2142 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2143
2144 if (iommu->dt_supported) {
2145 atsr = acpi_data_push(table_data, sizeof(*atsr));
2146 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2147 atsr->length = cpu_to_le16(sizeof(*atsr));
2148 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2149 atsr->pci_segment = cpu_to_le16(0);
2150 }
2151
2152 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2153 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2154 }
2155
2156 /*
2157 * Windows ACPI Emulated Devices Table
2158 * (Version 1.0 - April 6, 2009)
2159 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2160 *
2161 * Helpful to speedup Windows guests and ignored by others.
2162 */
2163 static void
2164 build_waet(GArray *table_data, BIOSLinker *linker)
2165 {
2166 int waet_start = table_data->len;
2167
2168 /* WAET header */
2169 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2170 /*
2171 * Set "ACPI PM timer good" flag.
2172 *
2173 * Tells Windows guests that our ACPI PM timer is reliable in the
2174 * sense that guest can read it only once to obtain a reliable value.
2175 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2176 */
2177 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2178
2179 build_header(linker, table_data, (void *)(table_data->data + waet_start),
2180 "WAET", table_data->len - waet_start, 1, NULL, NULL);
2181 }
2182
2183 /*
2184 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2185 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2186 */
2187 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2188
2189 /*
2190 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2191 * necessary for the PCI topology.
2192 */
2193 static void
2194 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2195 {
2196 GArray *table_data = opaque;
2197 uint32_t entry;
2198
2199 /* "Select" IVHD entry, type 0x2 */
2200 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2201 build_append_int_noprefix(table_data, entry, 4);
2202
2203 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2204 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2205 uint8_t sec = pci_bus_num(sec_bus);
2206 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2207
2208 if (pci_bus_is_express(sec_bus)) {
2209 /*
2210 * Walk the bus if there are subordinates, otherwise use a range
2211 * to cover an entire leaf bus. We could potentially also use a
2212 * range for traversed buses, but we'd need to take care not to
2213 * create both Select and Range entries covering the same device.
2214 * This is easier and potentially more compact.
2215 *
2216 * An example bare metal system seems to use Select entries for
2217 * root ports without a slot (ie. built-ins) and Range entries
2218 * when there is a slot. The same system also only hard-codes
2219 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2220 * making no effort to support nested bridges. We attempt to
2221 * be more thorough here.
2222 */
2223 if (sec == sub) { /* leaf bus */
2224 /* "Start of Range" IVHD entry, type 0x3 */
2225 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2226 build_append_int_noprefix(table_data, entry, 4);
2227 /* "End of Range" IVHD entry, type 0x4 */
2228 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2229 build_append_int_noprefix(table_data, entry, 4);
2230 } else {
2231 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2232 }
2233 } else {
2234 /*
2235 * If the secondary bus is conventional, then we need to create an
2236 * Alias range for everything downstream. The range covers the
2237 * first devfn on the secondary bus to the last devfn on the
2238 * subordinate bus. The alias target depends on legacy versus
2239 * express bridges, just as in pci_device_iommu_address_space().
2240 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2241 */
2242 uint16_t dev_id_a, dev_id_b;
2243
2244 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2245
2246 if (pci_is_express(dev) &&
2247 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2248 dev_id_b = dev_id_a;
2249 } else {
2250 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2251 }
2252
2253 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2254 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2255 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2256
2257 /* "End of Range" IVHD entry, type 0x4 */
2258 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2259 build_append_int_noprefix(table_data, entry, 4);
2260 }
2261 }
2262 }
2263
2264 /* For all PCI host bridges, walk and insert IVHD entries */
2265 static int
2266 ivrs_host_bridges(Object *obj, void *opaque)
2267 {
2268 GArray *ivhd_blob = opaque;
2269
2270 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2271 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2272
2273 if (bus) {
2274 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2275 }
2276 }
2277
2278 return 0;
2279 }
2280
2281 static void
2282 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2283 {
2284 int ivhd_table_len = 24;
2285 int iommu_start = table_data->len;
2286 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2287 GArray *ivhd_blob = g_array_new(false, true, 1);
2288
2289 /* IVRS header */
2290 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2291 /* IVinfo - IO virtualization information common to all
2292 * IOMMU units in a system
2293 */
2294 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2295 /* reserved */
2296 build_append_int_noprefix(table_data, 0, 8);
2297
2298 /* IVHD definition - type 10h */
2299 build_append_int_noprefix(table_data, 0x10, 1);
2300 /* virtualization flags */
2301 build_append_int_noprefix(table_data,
2302 (1UL << 0) | /* HtTunEn */
2303 (1UL << 4) | /* iotblSup */
2304 (1UL << 6) | /* PrefSup */
2305 (1UL << 7), /* PPRSup */
2306 1);
2307
2308 /*
2309 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2310 * complete set of IVHD entries. Do this into a separate blob so that we
2311 * can calculate the total IVRS table length here and then append the new
2312 * blob further below. Fall back to an entry covering all devices, which
2313 * is sufficient when no aliases are present.
2314 */
2315 object_child_foreach_recursive(object_get_root(),
2316 ivrs_host_bridges, ivhd_blob);
2317
2318 if (!ivhd_blob->len) {
2319 /*
2320 * Type 1 device entry reporting all devices
2321 * These are 4-byte device entries currently reporting the range of
2322 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2323 */
2324 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2325 }
2326
2327 ivhd_table_len += ivhd_blob->len;
2328
2329 /*
2330 * When interrupt remapping is supported, we add a special IVHD device
2331 * for type IO-APIC.
2332 */
2333 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2334 ivhd_table_len += 8;
2335 }
2336
2337 /* IVHD length */
2338 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2339 /* DeviceID */
2340 build_append_int_noprefix(table_data, s->devid, 2);
2341 /* Capability offset */
2342 build_append_int_noprefix(table_data, s->capab_offset, 2);
2343 /* IOMMU base address */
2344 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2345 /* PCI Segment Group */
2346 build_append_int_noprefix(table_data, 0, 2);
2347 /* IOMMU info */
2348 build_append_int_noprefix(table_data, 0, 2);
2349 /* IOMMU Feature Reporting */
2350 build_append_int_noprefix(table_data,
2351 (48UL << 30) | /* HATS */
2352 (48UL << 28) | /* GATS */
2353 (1UL << 2) | /* GTSup */
2354 (1UL << 6), /* GASup */
2355 4);
2356
2357 /* IVHD entries as found above */
2358 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2359 g_array_free(ivhd_blob, TRUE);
2360
2361 /*
2362 * Add a special IVHD device type.
2363 * Refer to spec - Table 95: IVHD device entry type codes
2364 *
2365 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2366 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2367 */
2368 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2369 build_append_int_noprefix(table_data,
2370 (0x1ull << 56) | /* type IOAPIC */
2371 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2372 0x48, /* special device */
2373 8);
2374 }
2375
2376 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2377 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2378 }
2379
2380 typedef
2381 struct AcpiBuildState {
2382 /* Copy of table in RAM (for patching). */
2383 MemoryRegion *table_mr;
2384 /* Is table patched? */
2385 uint8_t patched;
2386 void *rsdp;
2387 MemoryRegion *rsdp_mr;
2388 MemoryRegion *linker_mr;
2389 } AcpiBuildState;
2390
2391 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2392 {
2393 Object *pci_host;
2394 QObject *o;
2395
2396 pci_host = acpi_get_i386_pci_host();
2397 g_assert(pci_host);
2398
2399 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2400 if (!o) {
2401 return false;
2402 }
2403 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2404 qobject_unref(o);
2405 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2406 return false;
2407 }
2408
2409 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2410 assert(o);
2411 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2412 qobject_unref(o);
2413 return true;
2414 }
2415
2416 static
2417 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2418 {
2419 PCMachineState *pcms = PC_MACHINE(machine);
2420 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2421 X86MachineState *x86ms = X86_MACHINE(machine);
2422 GArray *table_offsets;
2423 unsigned facs, dsdt, rsdt, fadt;
2424 AcpiPmInfo pm;
2425 AcpiMiscInfo misc;
2426 AcpiMcfgInfo mcfg;
2427 Range pci_hole, pci_hole64;
2428 uint8_t *u;
2429 size_t aml_len = 0;
2430 GArray *tables_blob = tables->table_data;
2431 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2432 Object *vmgenid_dev;
2433
2434 acpi_get_pm_info(machine, &pm);
2435 acpi_get_misc_info(&misc);
2436 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2437 acpi_get_slic_oem(&slic_oem);
2438
2439 table_offsets = g_array_new(false, true /* clear */,
2440 sizeof(uint32_t));
2441 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2442
2443 bios_linker_loader_alloc(tables->linker,
2444 ACPI_BUILD_TABLE_FILE, tables_blob,
2445 64 /* Ensure FACS is aligned */,
2446 false /* high memory */);
2447
2448 /*
2449 * FACS is pointed to by FADT.
2450 * We place it first since it's the only table that has alignment
2451 * requirements.
2452 */
2453 facs = tables_blob->len;
2454 build_facs(tables_blob);
2455
2456 /* DSDT is pointed to by FADT */
2457 dsdt = tables_blob->len;
2458 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2459 &pci_hole, &pci_hole64, machine);
2460
2461 /* Count the size of the DSDT and SSDT, we will need it for legacy
2462 * sizing of ACPI tables.
2463 */
2464 aml_len += tables_blob->len - dsdt;
2465
2466 /* ACPI tables pointed to by RSDT */
2467 fadt = tables_blob->len;
2468 acpi_add_table(table_offsets, tables_blob);
2469 pm.fadt.facs_tbl_offset = &facs;
2470 pm.fadt.dsdt_tbl_offset = &dsdt;
2471 pm.fadt.xdsdt_tbl_offset = &dsdt;
2472 build_fadt(tables_blob, tables->linker, &pm.fadt,
2473 slic_oem.id, slic_oem.table_id);
2474 aml_len += tables_blob->len - fadt;
2475
2476 acpi_add_table(table_offsets, tables_blob);
2477 acpi_build_madt(tables_blob, tables->linker, x86ms,
2478 ACPI_DEVICE_IF(x86ms->acpi_dev), true);
2479
2480 vmgenid_dev = find_vmgenid_dev();
2481 if (vmgenid_dev) {
2482 acpi_add_table(table_offsets, tables_blob);
2483 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2484 tables->vmgenid, tables->linker);
2485 }
2486
2487 if (misc.has_hpet) {
2488 acpi_add_table(table_offsets, tables_blob);
2489 build_hpet(tables_blob, tables->linker);
2490 }
2491 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2492 if (misc.tpm_version == TPM_VERSION_1_2) {
2493 acpi_add_table(table_offsets, tables_blob);
2494 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2495 } else { /* TPM_VERSION_2_0 */
2496 acpi_add_table(table_offsets, tables_blob);
2497 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2498 }
2499 }
2500 if (pcms->numa_nodes) {
2501 acpi_add_table(table_offsets, tables_blob);
2502 build_srat(tables_blob, tables->linker, machine);
2503 if (machine->numa_state->have_numa_distance) {
2504 acpi_add_table(table_offsets, tables_blob);
2505 build_slit(tables_blob, tables->linker, machine);
2506 }
2507 if (machine->numa_state->hmat_enabled) {
2508 acpi_add_table(table_offsets, tables_blob);
2509 build_hmat(tables_blob, tables->linker, machine->numa_state);
2510 }
2511 }
2512 if (acpi_get_mcfg(&mcfg)) {
2513 acpi_add_table(table_offsets, tables_blob);
2514 build_mcfg(tables_blob, tables->linker, &mcfg);
2515 }
2516 if (x86_iommu_get_default()) {
2517 IommuType IOMMUType = x86_iommu_get_type();
2518 if (IOMMUType == TYPE_AMD) {
2519 acpi_add_table(table_offsets, tables_blob);
2520 build_amd_iommu(tables_blob, tables->linker);
2521 } else if (IOMMUType == TYPE_INTEL) {
2522 acpi_add_table(table_offsets, tables_blob);
2523 build_dmar_q35(tables_blob, tables->linker);
2524 }
2525 }
2526 if (machine->nvdimms_state->is_enabled) {
2527 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2528 machine->nvdimms_state, machine->ram_slots);
2529 }
2530
2531 acpi_add_table(table_offsets, tables_blob);
2532 build_waet(tables_blob, tables->linker);
2533
2534 /* Add tables supplied by user (if any) */
2535 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2536 unsigned len = acpi_table_len(u);
2537
2538 acpi_add_table(table_offsets, tables_blob);
2539 g_array_append_vals(tables_blob, u, len);
2540 }
2541
2542 /* RSDT is pointed to by RSDP */
2543 rsdt = tables_blob->len;
2544 build_rsdt(tables_blob, tables->linker, table_offsets,
2545 slic_oem.id, slic_oem.table_id);
2546
2547 /* RSDP is in FSEG memory, so allocate it separately */
2548 {
2549 AcpiRsdpData rsdp_data = {
2550 .revision = 0,
2551 .oem_id = ACPI_BUILD_APPNAME6,
2552 .xsdt_tbl_offset = NULL,
2553 .rsdt_tbl_offset = &rsdt,
2554 };
2555 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2556 if (!pcmc->rsdp_in_ram) {
2557 /* We used to allocate some extra space for RSDP revision 2 but
2558 * only used the RSDP revision 0 space. The extra bytes were
2559 * zeroed out and not used.
2560 * Here we continue wasting those extra 16 bytes to make sure we
2561 * don't break migration for machine types 2.2 and older due to
2562 * RSDP blob size mismatch.
2563 */
2564 build_append_int_noprefix(tables->rsdp, 0, 16);
2565 }
2566 }
2567
2568 /* We'll expose it all to Guest so we want to reduce
2569 * chance of size changes.
2570 *
2571 * We used to align the tables to 4k, but of course this would
2572 * too simple to be enough. 4k turned out to be too small an
2573 * alignment very soon, and in fact it is almost impossible to
2574 * keep the table size stable for all (max_cpus, max_memory_slots)
2575 * combinations. So the table size is always 64k for pc-i440fx-2.1
2576 * and we give an error if the table grows beyond that limit.
2577 *
2578 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2579 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2580 * than 2.0 and we can always pad the smaller tables with zeros. We can
2581 * then use the exact size of the 2.0 tables.
2582 *
2583 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2584 */
2585 if (pcmc->legacy_acpi_table_size) {
2586 /* Subtracting aml_len gives the size of fixed tables. Then add the
2587 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2588 */
2589 int legacy_aml_len =
2590 pcmc->legacy_acpi_table_size +
2591 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2592 int legacy_table_size =
2593 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2594 ACPI_BUILD_ALIGN_SIZE);
2595 if (tables_blob->len > legacy_table_size) {
2596 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2597 warn_report("ACPI table size %u exceeds %d bytes,"
2598 " migration may not work",
2599 tables_blob->len, legacy_table_size);
2600 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2601 " or PCI bridges.");
2602 }
2603 g_array_set_size(tables_blob, legacy_table_size);
2604 } else {
2605 /* Make sure we have a buffer in case we need to resize the tables. */
2606 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2607 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2608 warn_report("ACPI table size %u exceeds %d bytes,"
2609 " migration may not work",
2610 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2611 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2612 " or PCI bridges.");
2613 }
2614 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2615 }
2616
2617 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2618
2619 /* Cleanup memory that's no longer used. */
2620 g_array_free(table_offsets, true);
2621 }
2622
2623 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2624 {
2625 uint32_t size = acpi_data_len(data);
2626
2627 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2628 memory_region_ram_resize(mr, size, &error_abort);
2629
2630 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2631 memory_region_set_dirty(mr, 0, size);
2632 }
2633
2634 static void acpi_build_update(void *build_opaque)
2635 {
2636 AcpiBuildState *build_state = build_opaque;
2637 AcpiBuildTables tables;
2638
2639 /* No state to update or already patched? Nothing to do. */
2640 if (!build_state || build_state->patched) {
2641 return;
2642 }
2643 build_state->patched = 1;
2644
2645 acpi_build_tables_init(&tables);
2646
2647 acpi_build(&tables, MACHINE(qdev_get_machine()));
2648
2649 acpi_ram_update(build_state->table_mr, tables.table_data);
2650
2651 if (build_state->rsdp) {
2652 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2653 } else {
2654 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2655 }
2656
2657 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2658 acpi_build_tables_cleanup(&tables, true);
2659 }
2660
2661 static void acpi_build_reset(void *build_opaque)
2662 {
2663 AcpiBuildState *build_state = build_opaque;
2664 build_state->patched = 0;
2665 }
2666
2667 static const VMStateDescription vmstate_acpi_build = {
2668 .name = "acpi_build",
2669 .version_id = 1,
2670 .minimum_version_id = 1,
2671 .fields = (VMStateField[]) {
2672 VMSTATE_UINT8(patched, AcpiBuildState),
2673 VMSTATE_END_OF_LIST()
2674 },
2675 };
2676
2677 void acpi_setup(void)
2678 {
2679 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2680 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2681 X86MachineState *x86ms = X86_MACHINE(pcms);
2682 AcpiBuildTables tables;
2683 AcpiBuildState *build_state;
2684 Object *vmgenid_dev;
2685 TPMIf *tpm;
2686 static FwCfgTPMConfig tpm_config;
2687
2688 if (!x86ms->fw_cfg) {
2689 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2690 return;
2691 }
2692
2693 if (!pcms->acpi_build_enabled) {
2694 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2695 return;
2696 }
2697
2698 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2699 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2700 return;
2701 }
2702
2703 build_state = g_malloc0(sizeof *build_state);
2704
2705 acpi_build_tables_init(&tables);
2706 acpi_build(&tables, MACHINE(pcms));
2707
2708 /* Now expose it all to Guest */
2709 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2710 build_state, tables.table_data,
2711 ACPI_BUILD_TABLE_FILE,
2712 ACPI_BUILD_TABLE_MAX_SIZE);
2713 assert(build_state->table_mr != NULL);
2714
2715 build_state->linker_mr =
2716 acpi_add_rom_blob(acpi_build_update, build_state,
2717 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
2718
2719 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2720 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2721
2722 tpm = tpm_find();
2723 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2724 tpm_config = (FwCfgTPMConfig) {
2725 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2726 .tpm_version = tpm_get_version(tpm),
2727 .tpmppi_version = TPM_PPI_VERSION_1_30
2728 };
2729 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2730 &tpm_config, sizeof tpm_config);
2731 }
2732
2733 vmgenid_dev = find_vmgenid_dev();
2734 if (vmgenid_dev) {
2735 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2736 tables.vmgenid);
2737 }
2738
2739 if (!pcmc->rsdp_in_ram) {
2740 /*
2741 * Keep for compatibility with old machine types.
2742 * Though RSDP is small, its contents isn't immutable, so
2743 * we'll update it along with the rest of tables on guest access.
2744 */
2745 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2746
2747 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2748 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2749 acpi_build_update, NULL, build_state,
2750 build_state->rsdp, rsdp_size, true);
2751 build_state->rsdp_mr = NULL;
2752 } else {
2753 build_state->rsdp = NULL;
2754 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2755 build_state, tables.rsdp,
2756 ACPI_BUILD_RSDP_FILE, 0);
2757 }
2758
2759 qemu_register_reset(acpi_build_reset, build_state);
2760 acpi_build_reset(build_state);
2761 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2762
2763 /* Cleanup tables but don't free the memory: we track it
2764 * in build_state.
2765 */
2766 acpi_build_tables_cleanup(&tables, false);
2767 }
AR7 emulation for QEMU