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[qemu/ar7.git] / hw / timer / exynos4210_mct.c
bloba2ec3920f82ea5fef8b4bc35702d462b48071865
1 /*
2 * Samsung exynos4210 Multi Core timer
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 *
7 * Evgeny Voevodin <e.voevodin@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 /*
24 * Global Timer:
25 *
26 * Consists of two timers. First represents Free Running Counter and second
27 * is used to measure interval from FRC to nearest comparator.
28 *
29 * 0 UINT64_MAX
30 * | timer0 |
31 * | <-------------------------------------------------------------- |
32 * | --------------------------------------------frc---------------> |
33 * |______________________________________________|__________________|
34 * CMP0 CMP1 CMP2 | CMP3
35 * __| |_
36 * | timer1 |
37 * | -------------> |
38 * frc CMPx
39 *
40 * Problem: when implementing global timer as is, overflow arises.
41 * next_time = cur_time + period * count;
42 * period and count are 64 bits width.
43 * Lets arm timer for MCT_GT_COUNTER_STEP count and update internal G_CNT
44 * register during each event.
45 *
46 * Problem: both timers need to be implemented using MCT_XT_COUNTER_STEP because
47 * local timer contains two counters: TCNT and ICNT. TCNT == 0 -> ICNT--.
48 * IRQ is generated when ICNT riches zero. Implementation where TCNT == 0
49 * generates IRQs suffers from too frequently events. Better to have one
50 * uint64_t counter equal to TCNT*ICNT and arm ptimer.c for a minimum(TCNT*ICNT,
51 * MCT_GT_COUNTER_STEP); (yes, if target tunes ICNT * TCNT to be too low values,
52 * there is no way to avoid frequently events).
53 */
54
55 #include "qemu/osdep.h"
56 #include "qemu/log.h"
57 #include "hw/sysbus.h"
58 #include "qemu/timer.h"
59 #include "qemu/main-loop.h"
60 #include "qemu-common.h"
61 #include "hw/ptimer.h"
62
63 #include "hw/arm/exynos4210.h"
64
65 //#define DEBUG_MCT
66
67 #ifdef DEBUG_MCT
68 #define DPRINTF(fmt, ...) \
69 do { fprintf(stdout, "MCT: [%24s:%5d] " fmt, __func__, __LINE__, \
70 ## __VA_ARGS__); } while (0)
71 #else
72 #define DPRINTF(fmt, ...) do {} while (0)
73 #endif
74
75 #define MCT_CFG 0x000
76 #define G_CNT_L 0x100
77 #define G_CNT_U 0x104
78 #define G_CNT_WSTAT 0x110
79 #define G_COMP0_L 0x200
80 #define G_COMP0_U 0x204
81 #define G_COMP0_ADD_INCR 0x208
82 #define G_COMP1_L 0x210
83 #define G_COMP1_U 0x214
84 #define G_COMP1_ADD_INCR 0x218
85 #define G_COMP2_L 0x220
86 #define G_COMP2_U 0x224
87 #define G_COMP2_ADD_INCR 0x228
88 #define G_COMP3_L 0x230
89 #define G_COMP3_U 0x234
90 #define G_COMP3_ADD_INCR 0x238
91 #define G_TCON 0x240
92 #define G_INT_CSTAT 0x244
93 #define G_INT_ENB 0x248
94 #define G_WSTAT 0x24C
95 #define L0_TCNTB 0x300
96 #define L0_TCNTO 0x304
97 #define L0_ICNTB 0x308
98 #define L0_ICNTO 0x30C
99 #define L0_FRCNTB 0x310
100 #define L0_FRCNTO 0x314
101 #define L0_TCON 0x320
102 #define L0_INT_CSTAT 0x330
103 #define L0_INT_ENB 0x334
104 #define L0_WSTAT 0x340
105 #define L1_TCNTB 0x400
106 #define L1_TCNTO 0x404
107 #define L1_ICNTB 0x408
108 #define L1_ICNTO 0x40C
109 #define L1_FRCNTB 0x410
110 #define L1_FRCNTO 0x414
111 #define L1_TCON 0x420
112 #define L1_INT_CSTAT 0x430
113 #define L1_INT_ENB 0x434
114 #define L1_WSTAT 0x440
115
116 #define MCT_CFG_GET_PRESCALER(x) ((x) & 0xFF)
117 #define MCT_CFG_GET_DIVIDER(x) (1 << ((x) >> 8 & 7))
118
119 #define GET_G_COMP_IDX(offset) (((offset) - G_COMP0_L) / 0x10)
120 #define GET_G_COMP_ADD_INCR_IDX(offset) (((offset) - G_COMP0_ADD_INCR) / 0x10)
121
122 #define G_COMP_L(x) (G_COMP0_L + (x) * 0x10)
123 #define G_COMP_U(x) (G_COMP0_U + (x) * 0x10)
124
125 #define G_COMP_ADD_INCR(x) (G_COMP0_ADD_INCR + (x) * 0x10)
126
127 /* MCT bits */
128 #define G_TCON_COMP_ENABLE(x) (1 << 2 * (x))
129 #define G_TCON_AUTO_ICREMENT(x) (1 << (2 * (x) + 1))
130 #define G_TCON_TIMER_ENABLE (1 << 8)
131
132 #define G_INT_ENABLE(x) (1 << (x))
133 #define G_INT_CSTAT_COMP(x) (1 << (x))
134
135 #define G_CNT_WSTAT_L 1
136 #define G_CNT_WSTAT_U 2
137
138 #define G_WSTAT_COMP_L(x) (1 << 4 * (x))
139 #define G_WSTAT_COMP_U(x) (1 << ((4 * (x)) + 1))
140 #define G_WSTAT_COMP_ADDINCR(x) (1 << ((4 * (x)) + 2))
141 #define G_WSTAT_TCON_WRITE (1 << 16)
142
143 #define GET_L_TIMER_IDX(offset) ((((offset) & 0xF00) - L0_TCNTB) / 0x100)
144 #define GET_L_TIMER_CNT_REG_IDX(offset, lt_i) \
145 (((offset) - (L0_TCNTB + 0x100 * (lt_i))) >> 2)
146
147 #define L_ICNTB_MANUAL_UPDATE (1 << 31)
148
149 #define L_TCON_TICK_START (1)
150 #define L_TCON_INT_START (1 << 1)
151 #define L_TCON_INTERVAL_MODE (1 << 2)
152 #define L_TCON_FRC_START (1 << 3)
153
154 #define L_INT_CSTAT_INTCNT (1 << 0)
155 #define L_INT_CSTAT_FRCCNT (1 << 1)
156
157 #define L_INT_INTENB_ICNTEIE (1 << 0)
158 #define L_INT_INTENB_FRCEIE (1 << 1)
159
160 #define L_WSTAT_TCNTB_WRITE (1 << 0)
161 #define L_WSTAT_ICNTB_WRITE (1 << 1)
162 #define L_WSTAT_FRCCNTB_WRITE (1 << 2)
163 #define L_WSTAT_TCON_WRITE (1 << 3)
164
165 enum LocalTimerRegCntIndexes {
166 L_REG_CNT_TCNTB,
167 L_REG_CNT_TCNTO,
168 L_REG_CNT_ICNTB,
169 L_REG_CNT_ICNTO,
170 L_REG_CNT_FRCCNTB,
171 L_REG_CNT_FRCCNTO,
172
173 L_REG_CNT_AMOUNT
174 };
175
176 #define MCT_NIRQ 6
177 #define MCT_SFR_SIZE 0x444
178
179 #define MCT_GT_CMP_NUM 4
180
181 #define MCT_GT_MAX_VAL UINT64_MAX
182
183 #define MCT_GT_COUNTER_STEP 0x100000000ULL
184 #define MCT_LT_COUNTER_STEP 0x100000000ULL
185 #define MCT_LT_CNT_LOW_LIMIT 0x100
186
187 /* global timer */
188 typedef struct {
189 qemu_irq irq[MCT_GT_CMP_NUM];
190
191 struct gregs {
192 uint64_t cnt;
193 uint32_t cnt_wstat;
194 uint32_t tcon;
195 uint32_t int_cstat;
196 uint32_t int_enb;
197 uint32_t wstat;
198 uint64_t comp[MCT_GT_CMP_NUM];
199 uint32_t comp_add_incr[MCT_GT_CMP_NUM];
200 } reg;
201
202 uint64_t count; /* Value FRC was armed with */
203 int32_t curr_comp; /* Current comparator FRC is running to */
204
205 ptimer_state *ptimer_frc; /* FRC timer */
206
207 } Exynos4210MCTGT;
208
209 /* local timer */
210 typedef struct {
211 int id; /* timer id */
212 qemu_irq irq; /* local timer irq */
213
214 struct tick_timer {
215 uint32_t cnt_run; /* cnt timer is running */
216 uint32_t int_run; /* int timer is running */
217
218 uint32_t last_icnto;
219 uint32_t last_tcnto;
220 uint32_t tcntb; /* initial value for TCNTB */
221 uint32_t icntb; /* initial value for ICNTB */
222
223 /* for step mode */
224 uint64_t distance; /* distance to count to the next event */
225 uint64_t progress; /* progress when counting by steps */
226 uint64_t count; /* count to arm timer with */
227
228 ptimer_state *ptimer_tick; /* timer for tick counter */
229 } tick_timer;
230
231 /* use ptimer.c to represent count down timer */
232
233 ptimer_state *ptimer_frc; /* timer for free running counter */
234
235 /* registers */
236 struct lregs {
237 uint32_t cnt[L_REG_CNT_AMOUNT];
238 uint32_t tcon;
239 uint32_t int_cstat;
240 uint32_t int_enb;
241 uint32_t wstat;
242 } reg;
243
244 } Exynos4210MCTLT;
245
246 #define TYPE_EXYNOS4210_MCT "exynos4210.mct"
247 #define EXYNOS4210_MCT(obj) \
248 OBJECT_CHECK(Exynos4210MCTState, (obj), TYPE_EXYNOS4210_MCT)
249
250 typedef struct Exynos4210MCTState {
251 SysBusDevice parent_obj;
252
253 MemoryRegion iomem;
254
255 /* Registers */
256 uint32_t reg_mct_cfg;
257
258 Exynos4210MCTLT l_timer[2];
259 Exynos4210MCTGT g_timer;
260
261 uint32_t freq; /* all timers tick frequency, TCLK */
262 } Exynos4210MCTState;
263
264 /*** VMState ***/
265 static const VMStateDescription vmstate_tick_timer = {
266 .name = "exynos4210.mct.tick_timer",
267 .version_id = 1,
268 .minimum_version_id = 1,
269 .fields = (VMStateField[]) {
270 VMSTATE_UINT32(cnt_run, struct tick_timer),
271 VMSTATE_UINT32(int_run, struct tick_timer),
272 VMSTATE_UINT32(last_icnto, struct tick_timer),
273 VMSTATE_UINT32(last_tcnto, struct tick_timer),
274 VMSTATE_UINT32(tcntb, struct tick_timer),
275 VMSTATE_UINT32(icntb, struct tick_timer),
276 VMSTATE_UINT64(distance, struct tick_timer),
277 VMSTATE_UINT64(progress, struct tick_timer),
278 VMSTATE_UINT64(count, struct tick_timer),
279 VMSTATE_PTIMER(ptimer_tick, struct tick_timer),
280 VMSTATE_END_OF_LIST()
281 }
282 };
283
284 static const VMStateDescription vmstate_lregs = {
285 .name = "exynos4210.mct.lregs",
286 .version_id = 1,
287 .minimum_version_id = 1,
288 .fields = (VMStateField[]) {
289 VMSTATE_UINT32_ARRAY(cnt, struct lregs, L_REG_CNT_AMOUNT),
290 VMSTATE_UINT32(tcon, struct lregs),
291 VMSTATE_UINT32(int_cstat, struct lregs),
292 VMSTATE_UINT32(int_enb, struct lregs),
293 VMSTATE_UINT32(wstat, struct lregs),
294 VMSTATE_END_OF_LIST()
295 }
296 };
297
298 static const VMStateDescription vmstate_exynos4210_mct_lt = {
299 .name = "exynos4210.mct.lt",
300 .version_id = 1,
301 .minimum_version_id = 1,
302 .fields = (VMStateField[]) {
303 VMSTATE_INT32(id, Exynos4210MCTLT),
304 VMSTATE_STRUCT(tick_timer, Exynos4210MCTLT, 0,
305 vmstate_tick_timer,
306 struct tick_timer),
307 VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTLT),
308 VMSTATE_STRUCT(reg, Exynos4210MCTLT, 0,
309 vmstate_lregs,
310 struct lregs),
311 VMSTATE_END_OF_LIST()
312 }
313 };
314
315 static const VMStateDescription vmstate_gregs = {
316 .name = "exynos4210.mct.lregs",
317 .version_id = 1,
318 .minimum_version_id = 1,
319 .fields = (VMStateField[]) {
320 VMSTATE_UINT64(cnt, struct gregs),
321 VMSTATE_UINT32(cnt_wstat, struct gregs),
322 VMSTATE_UINT32(tcon, struct gregs),
323 VMSTATE_UINT32(int_cstat, struct gregs),
324 VMSTATE_UINT32(int_enb, struct gregs),
325 VMSTATE_UINT32(wstat, struct gregs),
326 VMSTATE_UINT64_ARRAY(comp, struct gregs, MCT_GT_CMP_NUM),
327 VMSTATE_UINT32_ARRAY(comp_add_incr, struct gregs,
328 MCT_GT_CMP_NUM),
329 VMSTATE_END_OF_LIST()
330 }
331 };
332
333 static const VMStateDescription vmstate_exynos4210_mct_gt = {
334 .name = "exynos4210.mct.lt",
335 .version_id = 1,
336 .minimum_version_id = 1,
337 .fields = (VMStateField[]) {
338 VMSTATE_STRUCT(reg, Exynos4210MCTGT, 0, vmstate_gregs,
339 struct gregs),
340 VMSTATE_UINT64(count, Exynos4210MCTGT),
341 VMSTATE_INT32(curr_comp, Exynos4210MCTGT),
342 VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTGT),
343 VMSTATE_END_OF_LIST()
344 }
345 };
346
347 static const VMStateDescription vmstate_exynos4210_mct_state = {
348 .name = "exynos4210.mct",
349 .version_id = 1,
350 .minimum_version_id = 1,
351 .fields = (VMStateField[]) {
352 VMSTATE_UINT32(reg_mct_cfg, Exynos4210MCTState),
353 VMSTATE_STRUCT_ARRAY(l_timer, Exynos4210MCTState, 2, 0,
354 vmstate_exynos4210_mct_lt, Exynos4210MCTLT),
355 VMSTATE_STRUCT(g_timer, Exynos4210MCTState, 0,
356 vmstate_exynos4210_mct_gt, Exynos4210MCTGT),
357 VMSTATE_UINT32(freq, Exynos4210MCTState),
358 VMSTATE_END_OF_LIST()
359 }
360 };
361
362 static void exynos4210_mct_update_freq(Exynos4210MCTState *s);
363
364 /*
365 * Set counter of FRC global timer.
366 */
367 static void exynos4210_gfrc_set_count(Exynos4210MCTGT *s, uint64_t count)
368 {
369 s->count = count;
370 DPRINTF("global timer frc set count 0x%llx\n", count);
371 ptimer_set_count(s->ptimer_frc, count);
372 }
373
374 /*
375 * Get counter of FRC global timer.
376 */
377 static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT *s)
378 {
379 uint64_t count = 0;
380 count = ptimer_get_count(s->ptimer_frc);
381 count = s->count - count;
382 return s->reg.cnt + count;
383 }
384
385 /*
386 * Stop global FRC timer
387 */
388 static void exynos4210_gfrc_stop(Exynos4210MCTGT *s)
389 {
390 DPRINTF("global timer frc stop\n");
391
392 ptimer_stop(s->ptimer_frc);
393 }
394
395 /*
396 * Start global FRC timer
397 */
398 static void exynos4210_gfrc_start(Exynos4210MCTGT *s)
399 {
400 DPRINTF("global timer frc start\n");
401
402 ptimer_run(s->ptimer_frc, 1);
403 }
404
405 /*
406 * Find next nearest Comparator. If current Comparator value equals to other
407 * Comparator value, skip them both
408 */
409 static int32_t exynos4210_gcomp_find(Exynos4210MCTState *s)
410 {
411 int res;
412 int i;
413 int enabled;
414 uint64_t min;
415 int min_comp_i;
416 uint64_t gfrc;
417 uint64_t distance;
418 uint64_t distance_min;
419 int comp_i;
420
421 /* get gfrc count */
422 gfrc = exynos4210_gfrc_get_count(&s->g_timer);
423
424 min = UINT64_MAX;
425 distance_min = UINT64_MAX;
426 comp_i = MCT_GT_CMP_NUM;
427 min_comp_i = MCT_GT_CMP_NUM;
428 enabled = 0;
429
430 /* lookup for nearest comparator */
431 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
432
433 if (s->g_timer.reg.tcon & G_TCON_COMP_ENABLE(i)) {
434
435 enabled = 1;
436
437 if (s->g_timer.reg.comp[i] > gfrc) {
438 /* Comparator is upper then FRC */
439 distance = s->g_timer.reg.comp[i] - gfrc;
440
441 if (distance <= distance_min) {
442 distance_min = distance;
443 comp_i = i;
444 }
445 } else {
446 /* Comparator is below FRC, find the smallest */
447
448 if (s->g_timer.reg.comp[i] <= min) {
449 min = s->g_timer.reg.comp[i];
450 min_comp_i = i;
451 }
452 }
453 }
454 }
455
456 if (!enabled) {
457 /* All Comparators disabled */
458 res = -1;
459 } else if (comp_i < MCT_GT_CMP_NUM) {
460 /* Found upper Comparator */
461 res = comp_i;
462 } else {
463 /* All Comparators are below or equal to FRC */
464 res = min_comp_i;
465 }
466
467 DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
468 res,
469 s->g_timer.reg.comp[res],
470 distance_min,
471 gfrc);
472
473 return res;
474 }
475
476 /*
477 * Get distance to nearest Comparator
478 */
479 static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState *s, int32_t id)
480 {
481 if (id == -1) {
482 /* no enabled Comparators, choose max distance */
483 return MCT_GT_COUNTER_STEP;
484 }
485 if (s->g_timer.reg.comp[id] - s->g_timer.reg.cnt < MCT_GT_COUNTER_STEP) {
486 return s->g_timer.reg.comp[id] - s->g_timer.reg.cnt;
487 } else {
488 return MCT_GT_COUNTER_STEP;
489 }
490 }
491
492 /*
493 * Restart global FRC timer
494 */
495 static void exynos4210_gfrc_restart(Exynos4210MCTState *s)
496 {
497 uint64_t distance;
498
499 exynos4210_gfrc_stop(&s->g_timer);
500
501 s->g_timer.curr_comp = exynos4210_gcomp_find(s);
502
503 distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp);
504
505 if (distance > MCT_GT_COUNTER_STEP || !distance) {
506 distance = MCT_GT_COUNTER_STEP;
507 }
508
509 exynos4210_gfrc_set_count(&s->g_timer, distance);
510 exynos4210_gfrc_start(&s->g_timer);
511 }
512
513 /*
514 * Raise global timer CMP IRQ
515 */
516 static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
517 {
518 Exynos4210MCTGT *s = opaque;
519
520 /* If CSTAT is pending and IRQ is enabled */
521 if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
522 (s->reg.int_enb & G_INT_ENABLE(id))) {
523 DPRINTF("gcmp timer[%d] IRQ\n", id);
524 qemu_irq_raise(s->irq[id]);
525 }
526 }
527
528 /*
529 * Lower global timer CMP IRQ
530 */
531 static void exynos4210_gcomp_lower_irq(void *opaque, uint32_t id)
532 {
533 Exynos4210MCTGT *s = opaque;
534 qemu_irq_lower(s->irq[id]);
535 }
536
537 /*
538 * Global timer FRC event handler.
539 * Each event occurs when internal counter reaches counter + MCT_GT_COUNTER_STEP
540 * Every time we arm global FRC timer to count for MCT_GT_COUNTER_STEP value
541 */
542 static void exynos4210_gfrc_event(void *opaque)
543 {
544 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
545 int i;
546 uint64_t distance;
547
548 DPRINTF("\n");
549
550 s->g_timer.reg.cnt += s->g_timer.count;
551
552 /* Process all comparators */
553 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
554
555 if (s->g_timer.reg.cnt == s->g_timer.reg.comp[i]) {
556 /* reached nearest comparator */
557
558 s->g_timer.reg.int_cstat |= G_INT_CSTAT_COMP(i);
559
560 /* Auto increment */
561 if (s->g_timer.reg.tcon & G_TCON_AUTO_ICREMENT(i)) {
562 s->g_timer.reg.comp[i] += s->g_timer.reg.comp_add_incr[i];
563 }
564
565 /* IRQ */
566 exynos4210_gcomp_raise_irq(&s->g_timer, i);
567 }
568 }
569
570 /* Reload FRC to reach nearest comparator */
571 s->g_timer.curr_comp = exynos4210_gcomp_find(s);
572 distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp);
573 if (distance > MCT_GT_COUNTER_STEP || !distance) {
574 distance = MCT_GT_COUNTER_STEP;
575 }
576 exynos4210_gfrc_set_count(&s->g_timer, distance);
577
578 exynos4210_gfrc_start(&s->g_timer);
579 }
580
581 /*
582 * Get counter of FRC local timer.
583 */
584 static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT *s)
585 {
586 return ptimer_get_count(s->ptimer_frc);
587 }
588
589 /*
590 * Set counter of FRC local timer.
591 */
592 static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s)
593 {
594 if (!s->reg.cnt[L_REG_CNT_FRCCNTB]) {
595 ptimer_set_count(s->ptimer_frc, MCT_LT_COUNTER_STEP);
596 } else {
597 ptimer_set_count(s->ptimer_frc, s->reg.cnt[L_REG_CNT_FRCCNTB]);
598 }
599 }
600
601 /*
602 * Start local FRC timer
603 */
604 static void exynos4210_lfrc_start(Exynos4210MCTLT *s)
605 {
606 ptimer_run(s->ptimer_frc, 1);
607 }
608
609 /*
610 * Stop local FRC timer
611 */
612 static void exynos4210_lfrc_stop(Exynos4210MCTLT *s)
613 {
614 ptimer_stop(s->ptimer_frc);
615 }
616
617 /*
618 * Local timer free running counter tick handler
619 */
620 static void exynos4210_lfrc_event(void *opaque)
621 {
622 Exynos4210MCTLT * s = (Exynos4210MCTLT *)opaque;
623
624 /* local frc expired */
625
626 DPRINTF("\n");
627
628 s->reg.int_cstat |= L_INT_CSTAT_FRCCNT;
629
630 /* update frc counter */
631 exynos4210_lfrc_update_count(s);
632
633 /* raise irq */
634 if (s->reg.int_enb & L_INT_INTENB_FRCEIE) {
635 qemu_irq_raise(s->irq);
636 }
637
638 /* we reached here, this means that timer is enabled */
639 exynos4210_lfrc_start(s);
640 }
641
642 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s);
643 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s);
644 static void exynos4210_ltick_recalc_count(struct tick_timer *s);
645
646 /*
647 * Action on enabling local tick int timer
648 */
649 static void exynos4210_ltick_int_start(struct tick_timer *s)
650 {
651 if (!s->int_run) {
652 s->int_run = 1;
653 }
654 }
655
656 /*
657 * Action on disabling local tick int timer
658 */
659 static void exynos4210_ltick_int_stop(struct tick_timer *s)
660 {
661 if (s->int_run) {
662 s->last_icnto = exynos4210_ltick_int_get_cnto(s);
663 s->int_run = 0;
664 }
665 }
666
667 /*
668 * Get count for INT timer
669 */
670 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s)
671 {
672 uint32_t icnto;
673 uint64_t remain;
674 uint64_t count;
675 uint64_t counted;
676 uint64_t cur_progress;
677
678 count = ptimer_get_count(s->ptimer_tick);
679 if (count) {
680 /* timer is still counting, called not from event */
681 counted = s->count - ptimer_get_count(s->ptimer_tick);
682 cur_progress = s->progress + counted;
683 } else {
684 /* timer expired earlier */
685 cur_progress = s->progress;
686 }
687
688 remain = s->distance - cur_progress;
689
690 if (!s->int_run) {
691 /* INT is stopped. */
692 icnto = s->last_icnto;
693 } else {
694 /* Both are counting */
695 icnto = remain / s->tcntb;
696 }
697
698 return icnto;
699 }
700
701 /*
702 * Start local tick cnt timer.
703 */
704 static void exynos4210_ltick_cnt_start(struct tick_timer *s)
705 {
706 if (!s->cnt_run) {
707
708 exynos4210_ltick_recalc_count(s);
709 ptimer_set_count(s->ptimer_tick, s->count);
710 ptimer_run(s->ptimer_tick, 1);
711
712 s->cnt_run = 1;
713 }
714 }
715
716 /*
717 * Stop local tick cnt timer.
718 */
719 static void exynos4210_ltick_cnt_stop(struct tick_timer *s)
720 {
721 if (s->cnt_run) {
722
723 s->last_tcnto = exynos4210_ltick_cnt_get_cnto(s);
724
725 if (s->int_run) {
726 exynos4210_ltick_int_stop(s);
727 }
728
729 ptimer_stop(s->ptimer_tick);
730
731 s->cnt_run = 0;
732 }
733 }
734
735 /*
736 * Get counter for CNT timer
737 */
738 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s)
739 {
740 uint32_t tcnto;
741 uint32_t icnto;
742 uint64_t remain;
743 uint64_t counted;
744 uint64_t count;
745 uint64_t cur_progress;
746
747 count = ptimer_get_count(s->ptimer_tick);
748 if (count) {
749 /* timer is still counting, called not from event */
750 counted = s->count - ptimer_get_count(s->ptimer_tick);
751 cur_progress = s->progress + counted;
752 } else {
753 /* timer expired earlier */
754 cur_progress = s->progress;
755 }
756
757 remain = s->distance - cur_progress;
758
759 if (!s->cnt_run) {
760 /* Both are stopped. */
761 tcnto = s->last_tcnto;
762 } else if (!s->int_run) {
763 /* INT counter is stopped, progress is by CNT timer */
764 tcnto = remain % s->tcntb;
765 } else {
766 /* Both are counting */
767 icnto = remain / s->tcntb;
768 if (icnto) {
769 tcnto = remain % (icnto * s->tcntb);
770 } else {
771 tcnto = remain % s->tcntb;
772 }
773 }
774
775 return tcnto;
776 }
777
778 /*
779 * Set new values of counters for CNT and INT timers
780 */
781 static void exynos4210_ltick_set_cntb(struct tick_timer *s, uint32_t new_cnt,
782 uint32_t new_int)
783 {
784 uint32_t cnt_stopped = 0;
785 uint32_t int_stopped = 0;
786
787 if (s->cnt_run) {
788 exynos4210_ltick_cnt_stop(s);
789 cnt_stopped = 1;
790 }
791
792 if (s->int_run) {
793 exynos4210_ltick_int_stop(s);
794 int_stopped = 1;
795 }
796
797 s->tcntb = new_cnt + 1;
798 s->icntb = new_int + 1;
799
800 if (cnt_stopped) {
801 exynos4210_ltick_cnt_start(s);
802 }
803 if (int_stopped) {
804 exynos4210_ltick_int_start(s);
805 }
806
807 }
808
809 /*
810 * Calculate new counter value for tick timer
811 */
812 static void exynos4210_ltick_recalc_count(struct tick_timer *s)
813 {
814 uint64_t to_count;
815
816 if ((s->cnt_run && s->last_tcnto) || (s->int_run && s->last_icnto)) {
817 /*
818 * one or both timers run and not counted to the end;
819 * distance is not passed, recalculate with last_tcnto * last_icnto
820 */
821
822 if (s->last_tcnto) {
823 to_count = (uint64_t)s->last_tcnto * s->last_icnto;
824 } else {
825 to_count = s->last_icnto;
826 }
827 } else {
828 /* distance is passed, recalculate with tcnto * icnto */
829 if (s->icntb) {
830 s->distance = (uint64_t)s->tcntb * s->icntb;
831 } else {
832 s->distance = s->tcntb;
833 }
834
835 to_count = s->distance;
836 s->progress = 0;
837 }
838
839 if (to_count > MCT_LT_COUNTER_STEP) {
840 /* count by step */
841 s->count = MCT_LT_COUNTER_STEP;
842 } else {
843 s->count = to_count;
844 }
845 }
846
847 /*
848 * Initialize tick_timer
849 */
850 static void exynos4210_ltick_timer_init(struct tick_timer *s)
851 {
852 exynos4210_ltick_int_stop(s);
853 exynos4210_ltick_cnt_stop(s);
854
855 s->count = 0;
856 s->distance = 0;
857 s->progress = 0;
858 s->icntb = 0;
859 s->tcntb = 0;
860 }
861
862 /*
863 * tick_timer event.
864 * Raises when abstract tick_timer expires.
865 */
866 static void exynos4210_ltick_timer_event(struct tick_timer *s)
867 {
868 s->progress += s->count;
869 }
870
871 /*
872 * Local timer tick counter handler.
873 * Don't use reloaded timers. If timer counter = zero
874 * then handler called but after handler finished no
875 * timer reload occurs.
876 */
877 static void exynos4210_ltick_event(void *opaque)
878 {
879 Exynos4210MCTLT * s = (Exynos4210MCTLT *)opaque;
880 uint32_t tcnto;
881 uint32_t icnto;
882 #ifdef DEBUG_MCT
883 static uint64_t time1[2] = {0};
884 static uint64_t time2[2] = {0};
885 #endif
886
887 /* Call tick_timer event handler, it will update its tcntb and icntb. */
888 exynos4210_ltick_timer_event(&s->tick_timer);
889
890 /* get tick_timer cnt */
891 tcnto = exynos4210_ltick_cnt_get_cnto(&s->tick_timer);
892
893 /* get tick_timer int */
894 icnto = exynos4210_ltick_int_get_cnto(&s->tick_timer);
895
896 /* raise IRQ if needed */
897 if (!icnto && s->reg.tcon & L_TCON_INT_START) {
898 /* INT counter enabled and expired */
899
900 s->reg.int_cstat |= L_INT_CSTAT_INTCNT;
901
902 /* raise interrupt if enabled */
903 if (s->reg.int_enb & L_INT_INTENB_ICNTEIE) {
904 #ifdef DEBUG_MCT
905 time2[s->id] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
906 DPRINTF("local timer[%d] IRQ: %llx\n", s->id,
907 time2[s->id] - time1[s->id]);
908 time1[s->id] = time2[s->id];
909 #endif
910 qemu_irq_raise(s->irq);
911 }
912
913 /* reload ICNTB */
914 if (s->reg.tcon & L_TCON_INTERVAL_MODE) {
915 exynos4210_ltick_set_cntb(&s->tick_timer,
916 s->reg.cnt[L_REG_CNT_TCNTB],
917 s->reg.cnt[L_REG_CNT_ICNTB]);
918 }
919 } else {
920 /* reload TCNTB */
921 if (!tcnto) {
922 exynos4210_ltick_set_cntb(&s->tick_timer,
923 s->reg.cnt[L_REG_CNT_TCNTB],
924 icnto);
925 }
926 }
927
928 /* start tick_timer cnt */
929 exynos4210_ltick_cnt_start(&s->tick_timer);
930
931 /* start tick_timer int */
932 exynos4210_ltick_int_start(&s->tick_timer);
933 }
934
935 /* update timer frequency */
936 static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
937 {
938 uint32_t freq = s->freq;
939 s->freq = 24000000 /
940 ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) *
941 MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
942
943 if (freq != s->freq) {
944 DPRINTF("freq=%dHz\n", s->freq);
945
946 /* global timer */
947 ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
948
949 /* local timer */
950 ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq);
951 ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq);
952 ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq);
953 ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq);
954 }
955 }
956
957 /* set defaul_timer values for all fields */
958 static void exynos4210_mct_reset(DeviceState *d)
959 {
960 Exynos4210MCTState *s = EXYNOS4210_MCT(d);
961 uint32_t i;
962
963 s->reg_mct_cfg = 0;
964
965 /* global timer */
966 memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg));
967 exynos4210_gfrc_stop(&s->g_timer);
968
969 /* local timer */
970 memset(s->l_timer[0].reg.cnt, 0, sizeof(s->l_timer[0].reg.cnt));
971 memset(s->l_timer[1].reg.cnt, 0, sizeof(s->l_timer[1].reg.cnt));
972 for (i = 0; i < 2; i++) {
973 s->l_timer[i].reg.int_cstat = 0;
974 s->l_timer[i].reg.int_enb = 0;
975 s->l_timer[i].reg.tcon = 0;
976 s->l_timer[i].reg.wstat = 0;
977 s->l_timer[i].tick_timer.count = 0;
978 s->l_timer[i].tick_timer.distance = 0;
979 s->l_timer[i].tick_timer.progress = 0;
980 ptimer_stop(s->l_timer[i].ptimer_frc);
981
982 exynos4210_ltick_timer_init(&s->l_timer[i].tick_timer);
983 }
984
985 exynos4210_mct_update_freq(s);
986
987 }
988
989 /* Multi Core Timer read */
990 static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
991 unsigned size)
992 {
993 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
994 int index;
995 int shift;
996 uint64_t count;
997 uint32_t value;
998 int lt_i;
999
1000 switch (offset) {
1001
1002 case MCT_CFG:
1003 value = s->reg_mct_cfg;
1004 break;
1005
1006 case G_CNT_L: case G_CNT_U:
1007 shift = 8 * (offset & 0x4);
1008 count = exynos4210_gfrc_get_count(&s->g_timer);
1009 value = UINT32_MAX & (count >> shift);
1010 DPRINTF("read FRC=0x%llx\n", count);
1011 break;
1012
1013 case G_CNT_WSTAT:
1014 value = s->g_timer.reg.cnt_wstat;
1015 break;
1016
1017 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1018 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1019 index = GET_G_COMP_IDX(offset);
1020 shift = 8 * (offset & 0x4);
1021 value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
1022 break;
1023
1024 case G_TCON:
1025 value = s->g_timer.reg.tcon;
1026 break;
1027
1028 case G_INT_CSTAT:
1029 value = s->g_timer.reg.int_cstat;
1030 break;
1031
1032 case G_INT_ENB:
1033 value = s->g_timer.reg.int_enb;
1034 break;
1035 case G_WSTAT:
1036 value = s->g_timer.reg.wstat;
1037 break;
1038
1039 case G_COMP0_ADD_INCR: case G_COMP1_ADD_INCR:
1040 case G_COMP2_ADD_INCR: case G_COMP3_ADD_INCR:
1041 value = s->g_timer.reg.comp_add_incr[GET_G_COMP_ADD_INCR_IDX(offset)];
1042 break;
1043
1044 /* Local timers */
1045 case L0_TCNTB: case L0_ICNTB: case L0_FRCNTB:
1046 case L1_TCNTB: case L1_ICNTB: case L1_FRCNTB:
1047 lt_i = GET_L_TIMER_IDX(offset);
1048 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1049 value = s->l_timer[lt_i].reg.cnt[index];
1050 break;
1051
1052 case L0_TCNTO: case L1_TCNTO:
1053 lt_i = GET_L_TIMER_IDX(offset);
1054
1055 value = exynos4210_ltick_cnt_get_cnto(&s->l_timer[lt_i].tick_timer);
1056 DPRINTF("local timer[%d] read TCNTO %x\n", lt_i, value);
1057 break;
1058
1059 case L0_ICNTO: case L1_ICNTO:
1060 lt_i = GET_L_TIMER_IDX(offset);
1061
1062 value = exynos4210_ltick_int_get_cnto(&s->l_timer[lt_i].tick_timer);
1063 DPRINTF("local timer[%d] read ICNTO %x\n", lt_i, value);
1064 break;
1065
1066 case L0_FRCNTO: case L1_FRCNTO:
1067 lt_i = GET_L_TIMER_IDX(offset);
1068
1069 value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);
1070
1071 break;
1072
1073 case L0_TCON: case L1_TCON:
1074 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1075 value = s->l_timer[lt_i].reg.tcon;
1076 break;
1077
1078 case L0_INT_CSTAT: case L1_INT_CSTAT:
1079 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1080 value = s->l_timer[lt_i].reg.int_cstat;
1081 break;
1082
1083 case L0_INT_ENB: case L1_INT_ENB:
1084 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1085 value = s->l_timer[lt_i].reg.int_enb;
1086 break;
1087
1088 case L0_WSTAT: case L1_WSTAT:
1089 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1090 value = s->l_timer[lt_i].reg.wstat;
1091 break;
1092
1093 default:
1094 hw_error("exynos4210.mct: bad read offset "
1095 TARGET_FMT_plx "\n", offset);
1096 break;
1097 }
1098 return value;
1099 }
1100
1101 /* MCT write */
1102 static void exynos4210_mct_write(void *opaque, hwaddr offset,
1103 uint64_t value, unsigned size)
1104 {
1105 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
1106 int index; /* index in buffer which represents register set */
1107 int shift;
1108 int lt_i;
1109 uint64_t new_frc;
1110 uint32_t i;
1111 uint32_t old_val;
1112 #ifdef DEBUG_MCT
1113 static uint32_t icntb_max[2] = {0};
1114 static uint32_t icntb_min[2] = {UINT32_MAX, UINT32_MAX};
1115 static uint32_t tcntb_max[2] = {0};
1116 static uint32_t tcntb_min[2] = {UINT32_MAX, UINT32_MAX};
1117 #endif
1118
1119 new_frc = s->g_timer.reg.cnt;
1120
1121 switch (offset) {
1122
1123 case MCT_CFG:
1124 s->reg_mct_cfg = value;
1125 exynos4210_mct_update_freq(s);
1126 break;
1127
1128 case G_CNT_L:
1129 case G_CNT_U:
1130 if (offset == G_CNT_L) {
1131
1132 DPRINTF("global timer write to reg.cntl %llx\n", value);
1133
1134 new_frc = (s->g_timer.reg.cnt & (uint64_t)UINT32_MAX << 32) + value;
1135 s->g_timer.reg.cnt_wstat |= G_CNT_WSTAT_L;
1136 }
1137 if (offset == G_CNT_U) {
1138
1139 DPRINTF("global timer write to reg.cntu %llx\n", value);
1140
1141 new_frc = (s->g_timer.reg.cnt & UINT32_MAX) +
1142 ((uint64_t)value << 32);
1143 s->g_timer.reg.cnt_wstat |= G_CNT_WSTAT_U;
1144 }
1145
1146 s->g_timer.reg.cnt = new_frc;
1147 exynos4210_gfrc_restart(s);
1148 break;
1149
1150 case G_CNT_WSTAT:
1151 s->g_timer.reg.cnt_wstat &= ~(value);
1152 break;
1153
1154 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1155 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1156 index = GET_G_COMP_IDX(offset);
1157 shift = 8 * (offset & 0x4);
1158 s->g_timer.reg.comp[index] =
1159 (s->g_timer.reg.comp[index] &
1160 (((uint64_t)UINT32_MAX << 32) >> shift)) +
1161 (value << shift);
1162
1163 DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
1164
1165 if (offset&0x4) {
1166 s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
1167 } else {
1168 s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
1169 }
1170
1171 exynos4210_gfrc_restart(s);
1172 break;
1173
1174 case G_TCON:
1175 old_val = s->g_timer.reg.tcon;
1176 s->g_timer.reg.tcon = value;
1177 s->g_timer.reg.wstat |= G_WSTAT_TCON_WRITE;
1178
1179 DPRINTF("global timer write to reg.g_tcon %llx\n", value);
1180
1181 /* Start FRC if transition from disabled to enabled */
1182 if ((value & G_TCON_TIMER_ENABLE) > (old_val &
1183 G_TCON_TIMER_ENABLE)) {
1184 exynos4210_gfrc_start(&s->g_timer);
1185 }
1186 if ((value & G_TCON_TIMER_ENABLE) < (old_val &
1187 G_TCON_TIMER_ENABLE)) {
1188 exynos4210_gfrc_stop(&s->g_timer);
1189 }
1190
1191 /* Start CMP if transition from disabled to enabled */
1192 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1193 if ((value & G_TCON_COMP_ENABLE(i)) != (old_val &
1194 G_TCON_COMP_ENABLE(i))) {
1195 exynos4210_gfrc_restart(s);
1196 }
1197 }
1198 break;
1199
1200 case G_INT_CSTAT:
1201 s->g_timer.reg.int_cstat &= ~(value);
1202 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1203 if (value & G_INT_CSTAT_COMP(i)) {
1204 exynos4210_gcomp_lower_irq(&s->g_timer, i);
1205 }
1206 }
1207 break;
1208
1209 case G_INT_ENB:
1210
1211 /* Raise IRQ if transition from disabled to enabled and CSTAT pending */
1212 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1213 if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &
1214 G_INT_ENABLE(i))) {
1215 if (s->g_timer.reg.int_cstat & G_INT_CSTAT_COMP(i)) {
1216 exynos4210_gcomp_raise_irq(&s->g_timer, i);
1217 }
1218 }
1219
1220 if ((value & G_INT_ENABLE(i)) < (s->g_timer.reg.tcon &
1221 G_INT_ENABLE(i))) {
1222 exynos4210_gcomp_lower_irq(&s->g_timer, i);
1223 }
1224 }
1225
1226 DPRINTF("global timer INT enable %llx\n", value);
1227 s->g_timer.reg.int_enb = value;
1228 break;
1229
1230 case G_WSTAT:
1231 s->g_timer.reg.wstat &= ~(value);
1232 break;
1233
1234 case G_COMP0_ADD_INCR: case G_COMP1_ADD_INCR:
1235 case G_COMP2_ADD_INCR: case G_COMP3_ADD_INCR:
1236 index = GET_G_COMP_ADD_INCR_IDX(offset);
1237 s->g_timer.reg.comp_add_incr[index] = value;
1238 s->g_timer.reg.wstat |= G_WSTAT_COMP_ADDINCR(index);
1239 break;
1240
1241 /* Local timers */
1242 case L0_TCON: case L1_TCON:
1243 lt_i = GET_L_TIMER_IDX(offset);
1244 old_val = s->l_timer[lt_i].reg.tcon;
1245
1246 s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCON_WRITE;
1247 s->l_timer[lt_i].reg.tcon = value;
1248
1249 /* Stop local CNT */
1250 if ((value & L_TCON_TICK_START) <
1251 (old_val & L_TCON_TICK_START)) {
1252 DPRINTF("local timer[%d] stop cnt\n", lt_i);
1253 exynos4210_ltick_cnt_stop(&s->l_timer[lt_i].tick_timer);
1254 }
1255
1256 /* Stop local INT */
1257 if ((value & L_TCON_INT_START) <
1258 (old_val & L_TCON_INT_START)) {
1259 DPRINTF("local timer[%d] stop int\n", lt_i);
1260 exynos4210_ltick_int_stop(&s->l_timer[lt_i].tick_timer);
1261 }
1262
1263 /* Start local CNT */
1264 if ((value & L_TCON_TICK_START) >
1265 (old_val & L_TCON_TICK_START)) {
1266 DPRINTF("local timer[%d] start cnt\n", lt_i);
1267 exynos4210_ltick_cnt_start(&s->l_timer[lt_i].tick_timer);
1268 }
1269
1270 /* Start local INT */
1271 if ((value & L_TCON_INT_START) >
1272 (old_val & L_TCON_INT_START)) {
1273 DPRINTF("local timer[%d] start int\n", lt_i);
1274 exynos4210_ltick_int_start(&s->l_timer[lt_i].tick_timer);
1275 }
1276
1277 /* Start or Stop local FRC if TCON changed */
1278 if ((value & L_TCON_FRC_START) >
1279 (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) {
1280 DPRINTF("local timer[%d] start frc\n", lt_i);
1281 exynos4210_lfrc_start(&s->l_timer[lt_i]);
1282 }
1283 if ((value & L_TCON_FRC_START) <
1284 (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) {
1285 DPRINTF("local timer[%d] stop frc\n", lt_i);
1286 exynos4210_lfrc_stop(&s->l_timer[lt_i]);
1287 }
1288 break;
1289
1290 case L0_TCNTB: case L1_TCNTB:
1291
1292 lt_i = GET_L_TIMER_IDX(offset);
1293 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1294
1295 /*
1296 * TCNTB is updated to internal register only after CNT expired.
1297 * Due to this we should reload timer to nearest moment when CNT is
1298 * expired and then in event handler update tcntb to new TCNTB value.
1299 */
1300 exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, value,
1301 s->l_timer[lt_i].tick_timer.icntb);
1302
1303 s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCNTB_WRITE;
1304 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] = value;
1305
1306 #ifdef DEBUG_MCT
1307 if (tcntb_min[lt_i] > value) {
1308 tcntb_min[lt_i] = value;
1309 }
1310 if (tcntb_max[lt_i] < value) {
1311 tcntb_max[lt_i] = value;
1312 }
1313 DPRINTF("local timer[%d] TCNTB write %llx; max=%x, min=%x\n",
1314 lt_i, value, tcntb_max[lt_i], tcntb_min[lt_i]);
1315 #endif
1316 break;
1317
1318 case L0_ICNTB: case L1_ICNTB:
1319
1320 lt_i = GET_L_TIMER_IDX(offset);
1321 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1322
1323 s->l_timer[lt_i].reg.wstat |= L_WSTAT_ICNTB_WRITE;
1324 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] = value &
1325 ~L_ICNTB_MANUAL_UPDATE;
1326
1327 /*
1328 * We need to avoid too small values for TCNTB*ICNTB. If not, IRQ event
1329 * could raise too fast disallowing QEMU to execute target code.
1330 */
1331 if (s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] *
1332 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] < MCT_LT_CNT_LOW_LIMIT) {
1333 if (!s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB]) {
1334 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] =
1335 MCT_LT_CNT_LOW_LIMIT;
1336 } else {
1337 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] =
1338 MCT_LT_CNT_LOW_LIMIT /
1339 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB];
1340 }
1341 }
1342
1343 if (value & L_ICNTB_MANUAL_UPDATE) {
1344 exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer,
1345 s->l_timer[lt_i].tick_timer.tcntb,
1346 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB]);
1347 }
1348
1349 #ifdef DEBUG_MCT
1350 if (icntb_min[lt_i] > value) {
1351 icntb_min[lt_i] = value;
1352 }
1353 if (icntb_max[lt_i] < value) {
1354 icntb_max[lt_i] = value;
1355 }
1356 DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
1357 lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
1358 #endif
1359 break;
1360
1361 case L0_FRCNTB: case L1_FRCNTB:
1362
1363 lt_i = GET_L_TIMER_IDX(offset);
1364 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1365
1366 DPRINTF("local timer[%d] FRCNTB write %llx\n", lt_i, value);
1367
1368 s->l_timer[lt_i].reg.wstat |= L_WSTAT_FRCCNTB_WRITE;
1369 s->l_timer[lt_i].reg.cnt[L_REG_CNT_FRCCNTB] = value;
1370
1371 break;
1372
1373 case L0_TCNTO: case L1_TCNTO:
1374 case L0_ICNTO: case L1_ICNTO:
1375 case L0_FRCNTO: case L1_FRCNTO:
1376 qemu_log_mask(LOG_GUEST_ERROR,
1377 "exynos4210.mct: write to RO register " TARGET_FMT_plx,
1378 offset);
1379 break;
1380
1381 case L0_INT_CSTAT: case L1_INT_CSTAT:
1382 lt_i = GET_L_TIMER_IDX(offset);
1383
1384 DPRINTF("local timer[%d] CSTAT write %llx\n", lt_i, value);
1385
1386 s->l_timer[lt_i].reg.int_cstat &= ~value;
1387 if (!s->l_timer[lt_i].reg.int_cstat) {
1388 qemu_irq_lower(s->l_timer[lt_i].irq);
1389 }
1390 break;
1391
1392 case L0_INT_ENB: case L1_INT_ENB:
1393 lt_i = GET_L_TIMER_IDX(offset);
1394 old_val = s->l_timer[lt_i].reg.int_enb;
1395
1396 /* Raise Local timer IRQ if cstat is pending */
1397 if ((value & L_INT_INTENB_ICNTEIE) > (old_val & L_INT_INTENB_ICNTEIE)) {
1398 if (s->l_timer[lt_i].reg.int_cstat & L_INT_CSTAT_INTCNT) {
1399 qemu_irq_raise(s->l_timer[lt_i].irq);
1400 }
1401 }
1402
1403 s->l_timer[lt_i].reg.int_enb = value;
1404
1405 break;
1406
1407 case L0_WSTAT: case L1_WSTAT:
1408 lt_i = GET_L_TIMER_IDX(offset);
1409
1410 s->l_timer[lt_i].reg.wstat &= ~value;
1411 break;
1412
1413 default:
1414 hw_error("exynos4210.mct: bad write offset "
1415 TARGET_FMT_plx "\n", offset);
1416 break;
1417 }
1418 }
1419
1420 static const MemoryRegionOps exynos4210_mct_ops = {
1421 .read = exynos4210_mct_read,
1422 .write = exynos4210_mct_write,
1423 .endianness = DEVICE_NATIVE_ENDIAN,
1424 };
1425
1426 /* MCT init */
1427 static void exynos4210_mct_init(Object *obj)
1428 {
1429 int i;
1430 Exynos4210MCTState *s = EXYNOS4210_MCT(obj);
1431 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1432 QEMUBH *bh[2];
1433
1434 /* Global timer */
1435 bh[0] = qemu_bh_new(exynos4210_gfrc_event, s);
1436 s->g_timer.ptimer_frc = ptimer_init(bh[0], PTIMER_POLICY_DEFAULT);
1437 memset(&s->g_timer.reg, 0, sizeof(struct gregs));
1438
1439 /* Local timers */
1440 for (i = 0; i < 2; i++) {
1441 bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]);
1442 bh[1] = qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]);
1443 s->l_timer[i].tick_timer.ptimer_tick =
1444 ptimer_init(bh[0], PTIMER_POLICY_DEFAULT);
1445 s->l_timer[i].ptimer_frc = ptimer_init(bh[1], PTIMER_POLICY_DEFAULT);
1446 s->l_timer[i].id = i;
1447 }
1448
1449 /* IRQs */
1450 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1451 sysbus_init_irq(dev, &s->g_timer.irq[i]);
1452 }
1453 for (i = 0; i < 2; i++) {
1454 sysbus_init_irq(dev, &s->l_timer[i].irq);
1455 }
1456
1457 memory_region_init_io(&s->iomem, obj, &exynos4210_mct_ops, s,
1458 "exynos4210-mct", MCT_SFR_SIZE);
1459 sysbus_init_mmio(dev, &s->iomem);
1460 }
1461
1462 static void exynos4210_mct_class_init(ObjectClass *klass, void *data)
1463 {
1464 DeviceClass *dc = DEVICE_CLASS(klass);
1465
1466 dc->reset = exynos4210_mct_reset;
1467 dc->vmsd = &vmstate_exynos4210_mct_state;
1468 }
1469
1470 static const TypeInfo exynos4210_mct_info = {
1471 .name = TYPE_EXYNOS4210_MCT,
1472 .parent = TYPE_SYS_BUS_DEVICE,
1473 .instance_size = sizeof(Exynos4210MCTState),
1474 .instance_init = exynos4210_mct_init,
1475 .class_init = exynos4210_mct_class_init,
1476 };
1477
1478 static void exynos4210_mct_register_types(void)
1479 {
1480 type_register_static(&exynos4210_mct_info);
1481 }
1482
1483 type_init(exynos4210_mct_register_types)
AR7 emulation for QEMU