2 * Samsung exynos4210 Multi Core timer
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
7 * Evgeny Voevodin <e.voevodin@samsung.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Consists of two timers. First represents Free Running Counter and second
27 * is used to measure interval from FRC to nearest comparator.
31 * | <-------------------------------------------------------------- |
32 * | --------------------------------------------frc---------------> |
33 * |______________________________________________|__________________|
34 * CMP0 CMP1 CMP2 | CMP3
40 * Problem: when implementing global timer as is, overflow arises.
41 * next_time = cur_time + period * count;
42 * period and count are 64 bits width.
43 * Lets arm timer for MCT_GT_COUNTER_STEP count and update internal G_CNT
44 * register during each event.
46 * Problem: both timers need to be implemented using MCT_XT_COUNTER_STEP because
47 * local timer contains two counters: TCNT and ICNT. TCNT == 0 -> ICNT--.
48 * IRQ is generated when ICNT riches zero. Implementation where TCNT == 0
49 * generates IRQs suffers from too frequently events. Better to have one
50 * uint64_t counter equal to TCNT*ICNT and arm ptimer.c for a minimum(TCNT*ICNT,
51 * MCT_GT_COUNTER_STEP); (yes, if target tunes ICNT * TCNT to be too low values,
52 * there is no way to avoid frequently events).
55 #include "qemu/osdep.h"
57 #include "hw/sysbus.h"
58 #include "qemu/timer.h"
59 #include "qemu/main-loop.h"
60 #include "qemu-common.h"
61 #include "hw/ptimer.h"
63 #include "hw/arm/exynos4210.h"
68 #define DPRINTF(fmt, ...) \
69 do { fprintf(stdout, "MCT: [%24s:%5d] " fmt, __func__, __LINE__, \
70 ## __VA_ARGS__); } while (0)
72 #define DPRINTF(fmt, ...) do {} while (0)
78 #define G_CNT_WSTAT 0x110
79 #define G_COMP0_L 0x200
80 #define G_COMP0_U 0x204
81 #define G_COMP0_ADD_INCR 0x208
82 #define G_COMP1_L 0x210
83 #define G_COMP1_U 0x214
84 #define G_COMP1_ADD_INCR 0x218
85 #define G_COMP2_L 0x220
86 #define G_COMP2_U 0x224
87 #define G_COMP2_ADD_INCR 0x228
88 #define G_COMP3_L 0x230
89 #define G_COMP3_U 0x234
90 #define G_COMP3_ADD_INCR 0x238
92 #define G_INT_CSTAT 0x244
93 #define G_INT_ENB 0x248
95 #define L0_TCNTB 0x300
96 #define L0_TCNTO 0x304
97 #define L0_ICNTB 0x308
98 #define L0_ICNTO 0x30C
99 #define L0_FRCNTB 0x310
100 #define L0_FRCNTO 0x314
101 #define L0_TCON 0x320
102 #define L0_INT_CSTAT 0x330
103 #define L0_INT_ENB 0x334
104 #define L0_WSTAT 0x340
105 #define L1_TCNTB 0x400
106 #define L1_TCNTO 0x404
107 #define L1_ICNTB 0x408
108 #define L1_ICNTO 0x40C
109 #define L1_FRCNTB 0x410
110 #define L1_FRCNTO 0x414
111 #define L1_TCON 0x420
112 #define L1_INT_CSTAT 0x430
113 #define L1_INT_ENB 0x434
114 #define L1_WSTAT 0x440
116 #define MCT_CFG_GET_PRESCALER(x) ((x) & 0xFF)
117 #define MCT_CFG_GET_DIVIDER(x) (1 << ((x) >> 8 & 7))
119 #define GET_G_COMP_IDX(offset) (((offset) - G_COMP0_L) / 0x10)
120 #define GET_G_COMP_ADD_INCR_IDX(offset) (((offset) - G_COMP0_ADD_INCR) / 0x10)
122 #define G_COMP_L(x) (G_COMP0_L + (x) * 0x10)
123 #define G_COMP_U(x) (G_COMP0_U + (x) * 0x10)
125 #define G_COMP_ADD_INCR(x) (G_COMP0_ADD_INCR + (x) * 0x10)
128 #define G_TCON_COMP_ENABLE(x) (1 << 2 * (x))
129 #define G_TCON_AUTO_ICREMENT(x) (1 << (2 * (x) + 1))
130 #define G_TCON_TIMER_ENABLE (1 << 8)
132 #define G_INT_ENABLE(x) (1 << (x))
133 #define G_INT_CSTAT_COMP(x) (1 << (x))
135 #define G_CNT_WSTAT_L 1
136 #define G_CNT_WSTAT_U 2
138 #define G_WSTAT_COMP_L(x) (1 << 4 * (x))
139 #define G_WSTAT_COMP_U(x) (1 << ((4 * (x)) + 1))
140 #define G_WSTAT_COMP_ADDINCR(x) (1 << ((4 * (x)) + 2))
141 #define G_WSTAT_TCON_WRITE (1 << 16)
143 #define GET_L_TIMER_IDX(offset) ((((offset) & 0xF00) - L0_TCNTB) / 0x100)
144 #define GET_L_TIMER_CNT_REG_IDX(offset, lt_i) \
145 (((offset) - (L0_TCNTB + 0x100 * (lt_i))) >> 2)
147 #define L_ICNTB_MANUAL_UPDATE (1 << 31)
149 #define L_TCON_TICK_START (1)
150 #define L_TCON_INT_START (1 << 1)
151 #define L_TCON_INTERVAL_MODE (1 << 2)
152 #define L_TCON_FRC_START (1 << 3)
154 #define L_INT_CSTAT_INTCNT (1 << 0)
155 #define L_INT_CSTAT_FRCCNT (1 << 1)
157 #define L_INT_INTENB_ICNTEIE (1 << 0)
158 #define L_INT_INTENB_FRCEIE (1 << 1)
160 #define L_WSTAT_TCNTB_WRITE (1 << 0)
161 #define L_WSTAT_ICNTB_WRITE (1 << 1)
162 #define L_WSTAT_FRCCNTB_WRITE (1 << 2)
163 #define L_WSTAT_TCON_WRITE (1 << 3)
165 enum LocalTimerRegCntIndexes
{
177 #define MCT_SFR_SIZE 0x444
179 #define MCT_GT_CMP_NUM 4
181 #define MCT_GT_MAX_VAL UINT64_MAX
183 #define MCT_GT_COUNTER_STEP 0x100000000ULL
184 #define MCT_LT_COUNTER_STEP 0x100000000ULL
185 #define MCT_LT_CNT_LOW_LIMIT 0x100
189 qemu_irq irq
[MCT_GT_CMP_NUM
];
198 uint64_t comp
[MCT_GT_CMP_NUM
];
199 uint32_t comp_add_incr
[MCT_GT_CMP_NUM
];
202 uint64_t count
; /* Value FRC was armed with */
203 int32_t curr_comp
; /* Current comparator FRC is running to */
205 ptimer_state
*ptimer_frc
; /* FRC timer */
211 int id
; /* timer id */
212 qemu_irq irq
; /* local timer irq */
215 uint32_t cnt_run
; /* cnt timer is running */
216 uint32_t int_run
; /* int timer is running */
220 uint32_t tcntb
; /* initial value for TCNTB */
221 uint32_t icntb
; /* initial value for ICNTB */
224 uint64_t distance
; /* distance to count to the next event */
225 uint64_t progress
; /* progress when counting by steps */
226 uint64_t count
; /* count to arm timer with */
228 ptimer_state
*ptimer_tick
; /* timer for tick counter */
231 /* use ptimer.c to represent count down timer */
233 ptimer_state
*ptimer_frc
; /* timer for free running counter */
237 uint32_t cnt
[L_REG_CNT_AMOUNT
];
246 #define TYPE_EXYNOS4210_MCT "exynos4210.mct"
247 #define EXYNOS4210_MCT(obj) \
248 OBJECT_CHECK(Exynos4210MCTState, (obj), TYPE_EXYNOS4210_MCT)
250 typedef struct Exynos4210MCTState
{
251 SysBusDevice parent_obj
;
256 uint32_t reg_mct_cfg
;
258 Exynos4210MCTLT l_timer
[2];
259 Exynos4210MCTGT g_timer
;
261 uint32_t freq
; /* all timers tick frequency, TCLK */
262 } Exynos4210MCTState
;
265 static const VMStateDescription vmstate_tick_timer
= {
266 .name
= "exynos4210.mct.tick_timer",
268 .minimum_version_id
= 1,
269 .fields
= (VMStateField
[]) {
270 VMSTATE_UINT32(cnt_run
, struct tick_timer
),
271 VMSTATE_UINT32(int_run
, struct tick_timer
),
272 VMSTATE_UINT32(last_icnto
, struct tick_timer
),
273 VMSTATE_UINT32(last_tcnto
, struct tick_timer
),
274 VMSTATE_UINT32(tcntb
, struct tick_timer
),
275 VMSTATE_UINT32(icntb
, struct tick_timer
),
276 VMSTATE_UINT64(distance
, struct tick_timer
),
277 VMSTATE_UINT64(progress
, struct tick_timer
),
278 VMSTATE_UINT64(count
, struct tick_timer
),
279 VMSTATE_PTIMER(ptimer_tick
, struct tick_timer
),
280 VMSTATE_END_OF_LIST()
284 static const VMStateDescription vmstate_lregs
= {
285 .name
= "exynos4210.mct.lregs",
287 .minimum_version_id
= 1,
288 .fields
= (VMStateField
[]) {
289 VMSTATE_UINT32_ARRAY(cnt
, struct lregs
, L_REG_CNT_AMOUNT
),
290 VMSTATE_UINT32(tcon
, struct lregs
),
291 VMSTATE_UINT32(int_cstat
, struct lregs
),
292 VMSTATE_UINT32(int_enb
, struct lregs
),
293 VMSTATE_UINT32(wstat
, struct lregs
),
294 VMSTATE_END_OF_LIST()
298 static const VMStateDescription vmstate_exynos4210_mct_lt
= {
299 .name
= "exynos4210.mct.lt",
301 .minimum_version_id
= 1,
302 .fields
= (VMStateField
[]) {
303 VMSTATE_INT32(id
, Exynos4210MCTLT
),
304 VMSTATE_STRUCT(tick_timer
, Exynos4210MCTLT
, 0,
307 VMSTATE_PTIMER(ptimer_frc
, Exynos4210MCTLT
),
308 VMSTATE_STRUCT(reg
, Exynos4210MCTLT
, 0,
311 VMSTATE_END_OF_LIST()
315 static const VMStateDescription vmstate_gregs
= {
316 .name
= "exynos4210.mct.lregs",
318 .minimum_version_id
= 1,
319 .fields
= (VMStateField
[]) {
320 VMSTATE_UINT64(cnt
, struct gregs
),
321 VMSTATE_UINT32(cnt_wstat
, struct gregs
),
322 VMSTATE_UINT32(tcon
, struct gregs
),
323 VMSTATE_UINT32(int_cstat
, struct gregs
),
324 VMSTATE_UINT32(int_enb
, struct gregs
),
325 VMSTATE_UINT32(wstat
, struct gregs
),
326 VMSTATE_UINT64_ARRAY(comp
, struct gregs
, MCT_GT_CMP_NUM
),
327 VMSTATE_UINT32_ARRAY(comp_add_incr
, struct gregs
,
329 VMSTATE_END_OF_LIST()
333 static const VMStateDescription vmstate_exynos4210_mct_gt
= {
334 .name
= "exynos4210.mct.lt",
336 .minimum_version_id
= 1,
337 .fields
= (VMStateField
[]) {
338 VMSTATE_STRUCT(reg
, Exynos4210MCTGT
, 0, vmstate_gregs
,
340 VMSTATE_UINT64(count
, Exynos4210MCTGT
),
341 VMSTATE_INT32(curr_comp
, Exynos4210MCTGT
),
342 VMSTATE_PTIMER(ptimer_frc
, Exynos4210MCTGT
),
343 VMSTATE_END_OF_LIST()
347 static const VMStateDescription vmstate_exynos4210_mct_state
= {
348 .name
= "exynos4210.mct",
350 .minimum_version_id
= 1,
351 .fields
= (VMStateField
[]) {
352 VMSTATE_UINT32(reg_mct_cfg
, Exynos4210MCTState
),
353 VMSTATE_STRUCT_ARRAY(l_timer
, Exynos4210MCTState
, 2, 0,
354 vmstate_exynos4210_mct_lt
, Exynos4210MCTLT
),
355 VMSTATE_STRUCT(g_timer
, Exynos4210MCTState
, 0,
356 vmstate_exynos4210_mct_gt
, Exynos4210MCTGT
),
357 VMSTATE_UINT32(freq
, Exynos4210MCTState
),
358 VMSTATE_END_OF_LIST()
362 static void exynos4210_mct_update_freq(Exynos4210MCTState
*s
);
365 * Set counter of FRC global timer.
367 static void exynos4210_gfrc_set_count(Exynos4210MCTGT
*s
, uint64_t count
)
370 DPRINTF("global timer frc set count 0x%llx\n", count
);
371 ptimer_set_count(s
->ptimer_frc
, count
);
375 * Get counter of FRC global timer.
377 static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT
*s
)
380 count
= ptimer_get_count(s
->ptimer_frc
);
381 count
= s
->count
- count
;
382 return s
->reg
.cnt
+ count
;
386 * Stop global FRC timer
388 static void exynos4210_gfrc_stop(Exynos4210MCTGT
*s
)
390 DPRINTF("global timer frc stop\n");
392 ptimer_stop(s
->ptimer_frc
);
396 * Start global FRC timer
398 static void exynos4210_gfrc_start(Exynos4210MCTGT
*s
)
400 DPRINTF("global timer frc start\n");
402 ptimer_run(s
->ptimer_frc
, 1);
406 * Find next nearest Comparator. If current Comparator value equals to other
407 * Comparator value, skip them both
409 static int32_t exynos4210_gcomp_find(Exynos4210MCTState
*s
)
418 uint64_t distance_min
;
422 gfrc
= exynos4210_gfrc_get_count(&s
->g_timer
);
425 distance_min
= UINT64_MAX
;
426 comp_i
= MCT_GT_CMP_NUM
;
427 min_comp_i
= MCT_GT_CMP_NUM
;
430 /* lookup for nearest comparator */
431 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
433 if (s
->g_timer
.reg
.tcon
& G_TCON_COMP_ENABLE(i
)) {
437 if (s
->g_timer
.reg
.comp
[i
] > gfrc
) {
438 /* Comparator is upper then FRC */
439 distance
= s
->g_timer
.reg
.comp
[i
] - gfrc
;
441 if (distance
<= distance_min
) {
442 distance_min
= distance
;
446 /* Comparator is below FRC, find the smallest */
448 if (s
->g_timer
.reg
.comp
[i
] <= min
) {
449 min
= s
->g_timer
.reg
.comp
[i
];
457 /* All Comparators disabled */
459 } else if (comp_i
< MCT_GT_CMP_NUM
) {
460 /* Found upper Comparator */
463 /* All Comparators are below or equal to FRC */
467 DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
469 s
->g_timer
.reg
.comp
[res
],
477 * Get distance to nearest Comparator
479 static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState
*s
, int32_t id
)
482 /* no enabled Comparators, choose max distance */
483 return MCT_GT_COUNTER_STEP
;
485 if (s
->g_timer
.reg
.comp
[id
] - s
->g_timer
.reg
.cnt
< MCT_GT_COUNTER_STEP
) {
486 return s
->g_timer
.reg
.comp
[id
] - s
->g_timer
.reg
.cnt
;
488 return MCT_GT_COUNTER_STEP
;
493 * Restart global FRC timer
495 static void exynos4210_gfrc_restart(Exynos4210MCTState
*s
)
499 exynos4210_gfrc_stop(&s
->g_timer
);
501 s
->g_timer
.curr_comp
= exynos4210_gcomp_find(s
);
503 distance
= exynos4210_gcomp_get_distance(s
, s
->g_timer
.curr_comp
);
505 if (distance
> MCT_GT_COUNTER_STEP
|| !distance
) {
506 distance
= MCT_GT_COUNTER_STEP
;
509 exynos4210_gfrc_set_count(&s
->g_timer
, distance
);
510 exynos4210_gfrc_start(&s
->g_timer
);
514 * Raise global timer CMP IRQ
516 static void exynos4210_gcomp_raise_irq(void *opaque
, uint32_t id
)
518 Exynos4210MCTGT
*s
= opaque
;
520 /* If CSTAT is pending and IRQ is enabled */
521 if ((s
->reg
.int_cstat
& G_INT_CSTAT_COMP(id
)) &&
522 (s
->reg
.int_enb
& G_INT_ENABLE(id
))) {
523 DPRINTF("gcmp timer[%d] IRQ\n", id
);
524 qemu_irq_raise(s
->irq
[id
]);
529 * Lower global timer CMP IRQ
531 static void exynos4210_gcomp_lower_irq(void *opaque
, uint32_t id
)
533 Exynos4210MCTGT
*s
= opaque
;
534 qemu_irq_lower(s
->irq
[id
]);
538 * Global timer FRC event handler.
539 * Each event occurs when internal counter reaches counter + MCT_GT_COUNTER_STEP
540 * Every time we arm global FRC timer to count for MCT_GT_COUNTER_STEP value
542 static void exynos4210_gfrc_event(void *opaque
)
544 Exynos4210MCTState
*s
= (Exynos4210MCTState
*)opaque
;
550 s
->g_timer
.reg
.cnt
+= s
->g_timer
.count
;
552 /* Process all comparators */
553 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
555 if (s
->g_timer
.reg
.cnt
== s
->g_timer
.reg
.comp
[i
]) {
556 /* reached nearest comparator */
558 s
->g_timer
.reg
.int_cstat
|= G_INT_CSTAT_COMP(i
);
561 if (s
->g_timer
.reg
.tcon
& G_TCON_AUTO_ICREMENT(i
)) {
562 s
->g_timer
.reg
.comp
[i
] += s
->g_timer
.reg
.comp_add_incr
[i
];
566 exynos4210_gcomp_raise_irq(&s
->g_timer
, i
);
570 /* Reload FRC to reach nearest comparator */
571 s
->g_timer
.curr_comp
= exynos4210_gcomp_find(s
);
572 distance
= exynos4210_gcomp_get_distance(s
, s
->g_timer
.curr_comp
);
573 if (distance
> MCT_GT_COUNTER_STEP
|| !distance
) {
574 distance
= MCT_GT_COUNTER_STEP
;
576 exynos4210_gfrc_set_count(&s
->g_timer
, distance
);
578 exynos4210_gfrc_start(&s
->g_timer
);
582 * Get counter of FRC local timer.
584 static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT
*s
)
586 return ptimer_get_count(s
->ptimer_frc
);
590 * Set counter of FRC local timer.
592 static void exynos4210_lfrc_update_count(Exynos4210MCTLT
*s
)
594 if (!s
->reg
.cnt
[L_REG_CNT_FRCCNTB
]) {
595 ptimer_set_count(s
->ptimer_frc
, MCT_LT_COUNTER_STEP
);
597 ptimer_set_count(s
->ptimer_frc
, s
->reg
.cnt
[L_REG_CNT_FRCCNTB
]);
602 * Start local FRC timer
604 static void exynos4210_lfrc_start(Exynos4210MCTLT
*s
)
606 ptimer_run(s
->ptimer_frc
, 1);
610 * Stop local FRC timer
612 static void exynos4210_lfrc_stop(Exynos4210MCTLT
*s
)
614 ptimer_stop(s
->ptimer_frc
);
618 * Local timer free running counter tick handler
620 static void exynos4210_lfrc_event(void *opaque
)
622 Exynos4210MCTLT
* s
= (Exynos4210MCTLT
*)opaque
;
624 /* local frc expired */
628 s
->reg
.int_cstat
|= L_INT_CSTAT_FRCCNT
;
630 /* update frc counter */
631 exynos4210_lfrc_update_count(s
);
634 if (s
->reg
.int_enb
& L_INT_INTENB_FRCEIE
) {
635 qemu_irq_raise(s
->irq
);
638 /* we reached here, this means that timer is enabled */
639 exynos4210_lfrc_start(s
);
642 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer
*s
);
643 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer
*s
);
644 static void exynos4210_ltick_recalc_count(struct tick_timer
*s
);
647 * Action on enabling local tick int timer
649 static void exynos4210_ltick_int_start(struct tick_timer
*s
)
657 * Action on disabling local tick int timer
659 static void exynos4210_ltick_int_stop(struct tick_timer
*s
)
662 s
->last_icnto
= exynos4210_ltick_int_get_cnto(s
);
668 * Get count for INT timer
670 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer
*s
)
676 uint64_t cur_progress
;
678 count
= ptimer_get_count(s
->ptimer_tick
);
680 /* timer is still counting, called not from event */
681 counted
= s
->count
- ptimer_get_count(s
->ptimer_tick
);
682 cur_progress
= s
->progress
+ counted
;
684 /* timer expired earlier */
685 cur_progress
= s
->progress
;
688 remain
= s
->distance
- cur_progress
;
691 /* INT is stopped. */
692 icnto
= s
->last_icnto
;
694 /* Both are counting */
695 icnto
= remain
/ s
->tcntb
;
702 * Start local tick cnt timer.
704 static void exynos4210_ltick_cnt_start(struct tick_timer
*s
)
708 exynos4210_ltick_recalc_count(s
);
709 ptimer_set_count(s
->ptimer_tick
, s
->count
);
710 ptimer_run(s
->ptimer_tick
, 1);
717 * Stop local tick cnt timer.
719 static void exynos4210_ltick_cnt_stop(struct tick_timer
*s
)
723 s
->last_tcnto
= exynos4210_ltick_cnt_get_cnto(s
);
726 exynos4210_ltick_int_stop(s
);
729 ptimer_stop(s
->ptimer_tick
);
736 * Get counter for CNT timer
738 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer
*s
)
745 uint64_t cur_progress
;
747 count
= ptimer_get_count(s
->ptimer_tick
);
749 /* timer is still counting, called not from event */
750 counted
= s
->count
- ptimer_get_count(s
->ptimer_tick
);
751 cur_progress
= s
->progress
+ counted
;
753 /* timer expired earlier */
754 cur_progress
= s
->progress
;
757 remain
= s
->distance
- cur_progress
;
760 /* Both are stopped. */
761 tcnto
= s
->last_tcnto
;
762 } else if (!s
->int_run
) {
763 /* INT counter is stopped, progress is by CNT timer */
764 tcnto
= remain
% s
->tcntb
;
766 /* Both are counting */
767 icnto
= remain
/ s
->tcntb
;
769 tcnto
= remain
% (icnto
* s
->tcntb
);
771 tcnto
= remain
% s
->tcntb
;
779 * Set new values of counters for CNT and INT timers
781 static void exynos4210_ltick_set_cntb(struct tick_timer
*s
, uint32_t new_cnt
,
784 uint32_t cnt_stopped
= 0;
785 uint32_t int_stopped
= 0;
788 exynos4210_ltick_cnt_stop(s
);
793 exynos4210_ltick_int_stop(s
);
797 s
->tcntb
= new_cnt
+ 1;
798 s
->icntb
= new_int
+ 1;
801 exynos4210_ltick_cnt_start(s
);
804 exynos4210_ltick_int_start(s
);
810 * Calculate new counter value for tick timer
812 static void exynos4210_ltick_recalc_count(struct tick_timer
*s
)
816 if ((s
->cnt_run
&& s
->last_tcnto
) || (s
->int_run
&& s
->last_icnto
)) {
818 * one or both timers run and not counted to the end;
819 * distance is not passed, recalculate with last_tcnto * last_icnto
823 to_count
= (uint64_t)s
->last_tcnto
* s
->last_icnto
;
825 to_count
= s
->last_icnto
;
828 /* distance is passed, recalculate with tcnto * icnto */
830 s
->distance
= (uint64_t)s
->tcntb
* s
->icntb
;
832 s
->distance
= s
->tcntb
;
835 to_count
= s
->distance
;
839 if (to_count
> MCT_LT_COUNTER_STEP
) {
841 s
->count
= MCT_LT_COUNTER_STEP
;
848 * Initialize tick_timer
850 static void exynos4210_ltick_timer_init(struct tick_timer
*s
)
852 exynos4210_ltick_int_stop(s
);
853 exynos4210_ltick_cnt_stop(s
);
864 * Raises when abstract tick_timer expires.
866 static void exynos4210_ltick_timer_event(struct tick_timer
*s
)
868 s
->progress
+= s
->count
;
872 * Local timer tick counter handler.
873 * Don't use reloaded timers. If timer counter = zero
874 * then handler called but after handler finished no
875 * timer reload occurs.
877 static void exynos4210_ltick_event(void *opaque
)
879 Exynos4210MCTLT
* s
= (Exynos4210MCTLT
*)opaque
;
883 static uint64_t time1
[2] = {0};
884 static uint64_t time2
[2] = {0};
887 /* Call tick_timer event handler, it will update its tcntb and icntb. */
888 exynos4210_ltick_timer_event(&s
->tick_timer
);
890 /* get tick_timer cnt */
891 tcnto
= exynos4210_ltick_cnt_get_cnto(&s
->tick_timer
);
893 /* get tick_timer int */
894 icnto
= exynos4210_ltick_int_get_cnto(&s
->tick_timer
);
896 /* raise IRQ if needed */
897 if (!icnto
&& s
->reg
.tcon
& L_TCON_INT_START
) {
898 /* INT counter enabled and expired */
900 s
->reg
.int_cstat
|= L_INT_CSTAT_INTCNT
;
902 /* raise interrupt if enabled */
903 if (s
->reg
.int_enb
& L_INT_INTENB_ICNTEIE
) {
905 time2
[s
->id
] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
906 DPRINTF("local timer[%d] IRQ: %llx\n", s
->id
,
907 time2
[s
->id
] - time1
[s
->id
]);
908 time1
[s
->id
] = time2
[s
->id
];
910 qemu_irq_raise(s
->irq
);
914 if (s
->reg
.tcon
& L_TCON_INTERVAL_MODE
) {
915 exynos4210_ltick_set_cntb(&s
->tick_timer
,
916 s
->reg
.cnt
[L_REG_CNT_TCNTB
],
917 s
->reg
.cnt
[L_REG_CNT_ICNTB
]);
922 exynos4210_ltick_set_cntb(&s
->tick_timer
,
923 s
->reg
.cnt
[L_REG_CNT_TCNTB
],
928 /* start tick_timer cnt */
929 exynos4210_ltick_cnt_start(&s
->tick_timer
);
931 /* start tick_timer int */
932 exynos4210_ltick_int_start(&s
->tick_timer
);
935 /* update timer frequency */
936 static void exynos4210_mct_update_freq(Exynos4210MCTState
*s
)
938 uint32_t freq
= s
->freq
;
940 ((MCT_CFG_GET_PRESCALER(s
->reg_mct_cfg
)+1) *
941 MCT_CFG_GET_DIVIDER(s
->reg_mct_cfg
));
943 if (freq
!= s
->freq
) {
944 DPRINTF("freq=%dHz\n", s
->freq
);
947 ptimer_set_freq(s
->g_timer
.ptimer_frc
, s
->freq
);
950 ptimer_set_freq(s
->l_timer
[0].tick_timer
.ptimer_tick
, s
->freq
);
951 ptimer_set_freq(s
->l_timer
[0].ptimer_frc
, s
->freq
);
952 ptimer_set_freq(s
->l_timer
[1].tick_timer
.ptimer_tick
, s
->freq
);
953 ptimer_set_freq(s
->l_timer
[1].ptimer_frc
, s
->freq
);
957 /* set defaul_timer values for all fields */
958 static void exynos4210_mct_reset(DeviceState
*d
)
960 Exynos4210MCTState
*s
= EXYNOS4210_MCT(d
);
966 memset(&s
->g_timer
.reg
, 0, sizeof(s
->g_timer
.reg
));
967 exynos4210_gfrc_stop(&s
->g_timer
);
970 memset(s
->l_timer
[0].reg
.cnt
, 0, sizeof(s
->l_timer
[0].reg
.cnt
));
971 memset(s
->l_timer
[1].reg
.cnt
, 0, sizeof(s
->l_timer
[1].reg
.cnt
));
972 for (i
= 0; i
< 2; i
++) {
973 s
->l_timer
[i
].reg
.int_cstat
= 0;
974 s
->l_timer
[i
].reg
.int_enb
= 0;
975 s
->l_timer
[i
].reg
.tcon
= 0;
976 s
->l_timer
[i
].reg
.wstat
= 0;
977 s
->l_timer
[i
].tick_timer
.count
= 0;
978 s
->l_timer
[i
].tick_timer
.distance
= 0;
979 s
->l_timer
[i
].tick_timer
.progress
= 0;
980 ptimer_stop(s
->l_timer
[i
].ptimer_frc
);
982 exynos4210_ltick_timer_init(&s
->l_timer
[i
].tick_timer
);
985 exynos4210_mct_update_freq(s
);
989 /* Multi Core Timer read */
990 static uint64_t exynos4210_mct_read(void *opaque
, hwaddr offset
,
993 Exynos4210MCTState
*s
= (Exynos4210MCTState
*)opaque
;
1003 value
= s
->reg_mct_cfg
;
1006 case G_CNT_L
: case G_CNT_U
:
1007 shift
= 8 * (offset
& 0x4);
1008 count
= exynos4210_gfrc_get_count(&s
->g_timer
);
1009 value
= UINT32_MAX
& (count
>> shift
);
1010 DPRINTF("read FRC=0x%llx\n", count
);
1014 value
= s
->g_timer
.reg
.cnt_wstat
;
1017 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1018 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1019 index
= GET_G_COMP_IDX(offset
);
1020 shift
= 8 * (offset
& 0x4);
1021 value
= UINT32_MAX
& (s
->g_timer
.reg
.comp
[index
] >> shift
);
1025 value
= s
->g_timer
.reg
.tcon
;
1029 value
= s
->g_timer
.reg
.int_cstat
;
1033 value
= s
->g_timer
.reg
.int_enb
;
1036 value
= s
->g_timer
.reg
.wstat
;
1039 case G_COMP0_ADD_INCR
: case G_COMP1_ADD_INCR
:
1040 case G_COMP2_ADD_INCR
: case G_COMP3_ADD_INCR
:
1041 value
= s
->g_timer
.reg
.comp_add_incr
[GET_G_COMP_ADD_INCR_IDX(offset
)];
1045 case L0_TCNTB
: case L0_ICNTB
: case L0_FRCNTB
:
1046 case L1_TCNTB
: case L1_ICNTB
: case L1_FRCNTB
:
1047 lt_i
= GET_L_TIMER_IDX(offset
);
1048 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1049 value
= s
->l_timer
[lt_i
].reg
.cnt
[index
];
1052 case L0_TCNTO
: case L1_TCNTO
:
1053 lt_i
= GET_L_TIMER_IDX(offset
);
1055 value
= exynos4210_ltick_cnt_get_cnto(&s
->l_timer
[lt_i
].tick_timer
);
1056 DPRINTF("local timer[%d] read TCNTO %x\n", lt_i
, value
);
1059 case L0_ICNTO
: case L1_ICNTO
:
1060 lt_i
= GET_L_TIMER_IDX(offset
);
1062 value
= exynos4210_ltick_int_get_cnto(&s
->l_timer
[lt_i
].tick_timer
);
1063 DPRINTF("local timer[%d] read ICNTO %x\n", lt_i
, value
);
1066 case L0_FRCNTO
: case L1_FRCNTO
:
1067 lt_i
= GET_L_TIMER_IDX(offset
);
1069 value
= exynos4210_lfrc_get_count(&s
->l_timer
[lt_i
]);
1073 case L0_TCON
: case L1_TCON
:
1074 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1075 value
= s
->l_timer
[lt_i
].reg
.tcon
;
1078 case L0_INT_CSTAT
: case L1_INT_CSTAT
:
1079 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1080 value
= s
->l_timer
[lt_i
].reg
.int_cstat
;
1083 case L0_INT_ENB
: case L1_INT_ENB
:
1084 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1085 value
= s
->l_timer
[lt_i
].reg
.int_enb
;
1088 case L0_WSTAT
: case L1_WSTAT
:
1089 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1090 value
= s
->l_timer
[lt_i
].reg
.wstat
;
1094 hw_error("exynos4210.mct: bad read offset "
1095 TARGET_FMT_plx
"\n", offset
);
1102 static void exynos4210_mct_write(void *opaque
, hwaddr offset
,
1103 uint64_t value
, unsigned size
)
1105 Exynos4210MCTState
*s
= (Exynos4210MCTState
*)opaque
;
1106 int index
; /* index in buffer which represents register set */
1113 static uint32_t icntb_max
[2] = {0};
1114 static uint32_t icntb_min
[2] = {UINT32_MAX
, UINT32_MAX
};
1115 static uint32_t tcntb_max
[2] = {0};
1116 static uint32_t tcntb_min
[2] = {UINT32_MAX
, UINT32_MAX
};
1119 new_frc
= s
->g_timer
.reg
.cnt
;
1124 s
->reg_mct_cfg
= value
;
1125 exynos4210_mct_update_freq(s
);
1130 if (offset
== G_CNT_L
) {
1132 DPRINTF("global timer write to reg.cntl %llx\n", value
);
1134 new_frc
= (s
->g_timer
.reg
.cnt
& (uint64_t)UINT32_MAX
<< 32) + value
;
1135 s
->g_timer
.reg
.cnt_wstat
|= G_CNT_WSTAT_L
;
1137 if (offset
== G_CNT_U
) {
1139 DPRINTF("global timer write to reg.cntu %llx\n", value
);
1141 new_frc
= (s
->g_timer
.reg
.cnt
& UINT32_MAX
) +
1142 ((uint64_t)value
<< 32);
1143 s
->g_timer
.reg
.cnt_wstat
|= G_CNT_WSTAT_U
;
1146 s
->g_timer
.reg
.cnt
= new_frc
;
1147 exynos4210_gfrc_restart(s
);
1151 s
->g_timer
.reg
.cnt_wstat
&= ~(value
);
1154 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1155 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1156 index
= GET_G_COMP_IDX(offset
);
1157 shift
= 8 * (offset
& 0x4);
1158 s
->g_timer
.reg
.comp
[index
] =
1159 (s
->g_timer
.reg
.comp
[index
] &
1160 (((uint64_t)UINT32_MAX
<< 32) >> shift
)) +
1163 DPRINTF("comparator %d write 0x%llx val << %d\n", index
, value
, shift
);
1166 s
->g_timer
.reg
.wstat
|= G_WSTAT_COMP_U(index
);
1168 s
->g_timer
.reg
.wstat
|= G_WSTAT_COMP_L(index
);
1171 exynos4210_gfrc_restart(s
);
1175 old_val
= s
->g_timer
.reg
.tcon
;
1176 s
->g_timer
.reg
.tcon
= value
;
1177 s
->g_timer
.reg
.wstat
|= G_WSTAT_TCON_WRITE
;
1179 DPRINTF("global timer write to reg.g_tcon %llx\n", value
);
1181 /* Start FRC if transition from disabled to enabled */
1182 if ((value
& G_TCON_TIMER_ENABLE
) > (old_val
&
1183 G_TCON_TIMER_ENABLE
)) {
1184 exynos4210_gfrc_start(&s
->g_timer
);
1186 if ((value
& G_TCON_TIMER_ENABLE
) < (old_val
&
1187 G_TCON_TIMER_ENABLE
)) {
1188 exynos4210_gfrc_stop(&s
->g_timer
);
1191 /* Start CMP if transition from disabled to enabled */
1192 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1193 if ((value
& G_TCON_COMP_ENABLE(i
)) != (old_val
&
1194 G_TCON_COMP_ENABLE(i
))) {
1195 exynos4210_gfrc_restart(s
);
1201 s
->g_timer
.reg
.int_cstat
&= ~(value
);
1202 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1203 if (value
& G_INT_CSTAT_COMP(i
)) {
1204 exynos4210_gcomp_lower_irq(&s
->g_timer
, i
);
1211 /* Raise IRQ if transition from disabled to enabled and CSTAT pending */
1212 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1213 if ((value
& G_INT_ENABLE(i
)) > (s
->g_timer
.reg
.tcon
&
1215 if (s
->g_timer
.reg
.int_cstat
& G_INT_CSTAT_COMP(i
)) {
1216 exynos4210_gcomp_raise_irq(&s
->g_timer
, i
);
1220 if ((value
& G_INT_ENABLE(i
)) < (s
->g_timer
.reg
.tcon
&
1222 exynos4210_gcomp_lower_irq(&s
->g_timer
, i
);
1226 DPRINTF("global timer INT enable %llx\n", value
);
1227 s
->g_timer
.reg
.int_enb
= value
;
1231 s
->g_timer
.reg
.wstat
&= ~(value
);
1234 case G_COMP0_ADD_INCR
: case G_COMP1_ADD_INCR
:
1235 case G_COMP2_ADD_INCR
: case G_COMP3_ADD_INCR
:
1236 index
= GET_G_COMP_ADD_INCR_IDX(offset
);
1237 s
->g_timer
.reg
.comp_add_incr
[index
] = value
;
1238 s
->g_timer
.reg
.wstat
|= G_WSTAT_COMP_ADDINCR(index
);
1242 case L0_TCON
: case L1_TCON
:
1243 lt_i
= GET_L_TIMER_IDX(offset
);
1244 old_val
= s
->l_timer
[lt_i
].reg
.tcon
;
1246 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_TCON_WRITE
;
1247 s
->l_timer
[lt_i
].reg
.tcon
= value
;
1249 /* Stop local CNT */
1250 if ((value
& L_TCON_TICK_START
) <
1251 (old_val
& L_TCON_TICK_START
)) {
1252 DPRINTF("local timer[%d] stop cnt\n", lt_i
);
1253 exynos4210_ltick_cnt_stop(&s
->l_timer
[lt_i
].tick_timer
);
1256 /* Stop local INT */
1257 if ((value
& L_TCON_INT_START
) <
1258 (old_val
& L_TCON_INT_START
)) {
1259 DPRINTF("local timer[%d] stop int\n", lt_i
);
1260 exynos4210_ltick_int_stop(&s
->l_timer
[lt_i
].tick_timer
);
1263 /* Start local CNT */
1264 if ((value
& L_TCON_TICK_START
) >
1265 (old_val
& L_TCON_TICK_START
)) {
1266 DPRINTF("local timer[%d] start cnt\n", lt_i
);
1267 exynos4210_ltick_cnt_start(&s
->l_timer
[lt_i
].tick_timer
);
1270 /* Start local INT */
1271 if ((value
& L_TCON_INT_START
) >
1272 (old_val
& L_TCON_INT_START
)) {
1273 DPRINTF("local timer[%d] start int\n", lt_i
);
1274 exynos4210_ltick_int_start(&s
->l_timer
[lt_i
].tick_timer
);
1277 /* Start or Stop local FRC if TCON changed */
1278 if ((value
& L_TCON_FRC_START
) >
1279 (s
->l_timer
[lt_i
].reg
.tcon
& L_TCON_FRC_START
)) {
1280 DPRINTF("local timer[%d] start frc\n", lt_i
);
1281 exynos4210_lfrc_start(&s
->l_timer
[lt_i
]);
1283 if ((value
& L_TCON_FRC_START
) <
1284 (s
->l_timer
[lt_i
].reg
.tcon
& L_TCON_FRC_START
)) {
1285 DPRINTF("local timer[%d] stop frc\n", lt_i
);
1286 exynos4210_lfrc_stop(&s
->l_timer
[lt_i
]);
1290 case L0_TCNTB
: case L1_TCNTB
:
1292 lt_i
= GET_L_TIMER_IDX(offset
);
1293 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1296 * TCNTB is updated to internal register only after CNT expired.
1297 * Due to this we should reload timer to nearest moment when CNT is
1298 * expired and then in event handler update tcntb to new TCNTB value.
1300 exynos4210_ltick_set_cntb(&s
->l_timer
[lt_i
].tick_timer
, value
,
1301 s
->l_timer
[lt_i
].tick_timer
.icntb
);
1303 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_TCNTB_WRITE
;
1304 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
] = value
;
1307 if (tcntb_min
[lt_i
] > value
) {
1308 tcntb_min
[lt_i
] = value
;
1310 if (tcntb_max
[lt_i
] < value
) {
1311 tcntb_max
[lt_i
] = value
;
1313 DPRINTF("local timer[%d] TCNTB write %llx; max=%x, min=%x\n",
1314 lt_i
, value
, tcntb_max
[lt_i
], tcntb_min
[lt_i
]);
1318 case L0_ICNTB
: case L1_ICNTB
:
1320 lt_i
= GET_L_TIMER_IDX(offset
);
1321 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1323 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_ICNTB_WRITE
;
1324 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] = value
&
1325 ~L_ICNTB_MANUAL_UPDATE
;
1328 * We need to avoid too small values for TCNTB*ICNTB. If not, IRQ event
1329 * could raise too fast disallowing QEMU to execute target code.
1331 if (s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] *
1332 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
] < MCT_LT_CNT_LOW_LIMIT
) {
1333 if (!s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
]) {
1334 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] =
1335 MCT_LT_CNT_LOW_LIMIT
;
1337 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] =
1338 MCT_LT_CNT_LOW_LIMIT
/
1339 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
];
1343 if (value
& L_ICNTB_MANUAL_UPDATE
) {
1344 exynos4210_ltick_set_cntb(&s
->l_timer
[lt_i
].tick_timer
,
1345 s
->l_timer
[lt_i
].tick_timer
.tcntb
,
1346 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
]);
1350 if (icntb_min
[lt_i
] > value
) {
1351 icntb_min
[lt_i
] = value
;
1353 if (icntb_max
[lt_i
] < value
) {
1354 icntb_max
[lt_i
] = value
;
1356 DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
1357 lt_i
, value
, icntb_max
[lt_i
], icntb_min
[lt_i
]);
1361 case L0_FRCNTB
: case L1_FRCNTB
:
1363 lt_i
= GET_L_TIMER_IDX(offset
);
1364 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1366 DPRINTF("local timer[%d] FRCNTB write %llx\n", lt_i
, value
);
1368 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_FRCCNTB_WRITE
;
1369 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_FRCCNTB
] = value
;
1373 case L0_TCNTO
: case L1_TCNTO
:
1374 case L0_ICNTO
: case L1_ICNTO
:
1375 case L0_FRCNTO
: case L1_FRCNTO
:
1376 qemu_log_mask(LOG_GUEST_ERROR
,
1377 "exynos4210.mct: write to RO register " TARGET_FMT_plx
,
1381 case L0_INT_CSTAT
: case L1_INT_CSTAT
:
1382 lt_i
= GET_L_TIMER_IDX(offset
);
1384 DPRINTF("local timer[%d] CSTAT write %llx\n", lt_i
, value
);
1386 s
->l_timer
[lt_i
].reg
.int_cstat
&= ~value
;
1387 if (!s
->l_timer
[lt_i
].reg
.int_cstat
) {
1388 qemu_irq_lower(s
->l_timer
[lt_i
].irq
);
1392 case L0_INT_ENB
: case L1_INT_ENB
:
1393 lt_i
= GET_L_TIMER_IDX(offset
);
1394 old_val
= s
->l_timer
[lt_i
].reg
.int_enb
;
1396 /* Raise Local timer IRQ if cstat is pending */
1397 if ((value
& L_INT_INTENB_ICNTEIE
) > (old_val
& L_INT_INTENB_ICNTEIE
)) {
1398 if (s
->l_timer
[lt_i
].reg
.int_cstat
& L_INT_CSTAT_INTCNT
) {
1399 qemu_irq_raise(s
->l_timer
[lt_i
].irq
);
1403 s
->l_timer
[lt_i
].reg
.int_enb
= value
;
1407 case L0_WSTAT
: case L1_WSTAT
:
1408 lt_i
= GET_L_TIMER_IDX(offset
);
1410 s
->l_timer
[lt_i
].reg
.wstat
&= ~value
;
1414 hw_error("exynos4210.mct: bad write offset "
1415 TARGET_FMT_plx
"\n", offset
);
1420 static const MemoryRegionOps exynos4210_mct_ops
= {
1421 .read
= exynos4210_mct_read
,
1422 .write
= exynos4210_mct_write
,
1423 .endianness
= DEVICE_NATIVE_ENDIAN
,
1427 static void exynos4210_mct_init(Object
*obj
)
1430 Exynos4210MCTState
*s
= EXYNOS4210_MCT(obj
);
1431 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1435 bh
[0] = qemu_bh_new(exynos4210_gfrc_event
, s
);
1436 s
->g_timer
.ptimer_frc
= ptimer_init(bh
[0], PTIMER_POLICY_DEFAULT
);
1437 memset(&s
->g_timer
.reg
, 0, sizeof(struct gregs
));
1440 for (i
= 0; i
< 2; i
++) {
1441 bh
[0] = qemu_bh_new(exynos4210_ltick_event
, &s
->l_timer
[i
]);
1442 bh
[1] = qemu_bh_new(exynos4210_lfrc_event
, &s
->l_timer
[i
]);
1443 s
->l_timer
[i
].tick_timer
.ptimer_tick
=
1444 ptimer_init(bh
[0], PTIMER_POLICY_DEFAULT
);
1445 s
->l_timer
[i
].ptimer_frc
= ptimer_init(bh
[1], PTIMER_POLICY_DEFAULT
);
1446 s
->l_timer
[i
].id
= i
;
1450 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1451 sysbus_init_irq(dev
, &s
->g_timer
.irq
[i
]);
1453 for (i
= 0; i
< 2; i
++) {
1454 sysbus_init_irq(dev
, &s
->l_timer
[i
].irq
);
1457 memory_region_init_io(&s
->iomem
, obj
, &exynos4210_mct_ops
, s
,
1458 "exynos4210-mct", MCT_SFR_SIZE
);
1459 sysbus_init_mmio(dev
, &s
->iomem
);
1462 static void exynos4210_mct_class_init(ObjectClass
*klass
, void *data
)
1464 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1466 dc
->reset
= exynos4210_mct_reset
;
1467 dc
->vmsd
= &vmstate_exynos4210_mct_state
;
1470 static const TypeInfo exynos4210_mct_info
= {
1471 .name
= TYPE_EXYNOS4210_MCT
,
1472 .parent
= TYPE_SYS_BUS_DEVICE
,
1473 .instance_size
= sizeof(Exynos4210MCTState
),
1474 .instance_init
= exynos4210_mct_init
,
1475 .class_init
= exynos4210_mct_class_init
,
1478 static void exynos4210_mct_register_types(void)
1480 type_register_static(&exynos4210_mct_info
);
1483 type_init(exynos4210_mct_register_types
)